MONOLITHIC INTEGRATION OF HIGH AND LOW-SIDE GaN FETS WITH SCREENING BACK GATING EFFECT

Abstract

To provide an electronic device for mitigating the back gating effect of transistors, and a manufacturing method for the same.SOLUTION: An electronic device 100 includes: one of aluminum gallium nitride, aluminum nitride, indium aluminum nitride, or indium aluminum gallium nitride back barrier layer 116 over a buffer structure; a gallium nitride layer 118 over the back barrier layer; a hetero-epitaxy structure 120, 121 over the gallium nitride layer; first and second transistors 101, 102 over the hetero-epitaxy structure; and a hole injector 126 having a doped gallium nitride structure 124 over the hetero-epitaxy structure and a conductive structure partially over the doped gallium nitride structure. The hole injector injects holes to form a hole layer proximate an interface of the back barrier layer and the buffer structure to mitigate vertical electric field back gating effects for the first transistor.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] Monolithic integration of high-side and low-side gallium nitride (GaN) field-effect transistors (FETs) facilitates increased switching frequency with lower parasitic inductance and also reduces overall area compared to using silicon-based transistors. However, unlike silicon-based implementations, GaN FET devices do not have p- or n-wells in the GaN buffer or common silicon substrate for monolithic integration, and back-gate effects can reduce the on-state resistance (e.g., drain-source on-state resistance or RDSON) of the high-side GaN FET, especially for high-voltage switching applications. A reduction in RDSON leads to reduced efficiency. Summary of the Invention

[0002] In one aspect, an electronic device includes a buffer structure over a substrate, a back barrier layer over the buffer structure that is or includes aluminum gallium nitride, a gallium nitride layer over the back barrier layer, a heteroepitaxy structure over the gallium nitride layer, first and second transistors, and a hole injector structure. The first transistor has a first drain, a first gate, and a first source. The first drain is partially within the heteroepitaxy structure, and the first gate is over the heteroepitaxy structure and spaced apart from the first drain. The first source is partially within the heteroepitaxy structure and spaced apart from the first gate. The second transistor has a second drain, a second gate, and a second source. The second drain is partially within the heteroepitaxy structure and coupled to the first source. The second gate is over the heteroepitaxy structure and spaced apart from the second drain. The second source is partially within the heteroepitaxy structure and spaced from the second gate. The hole injector structure includes a doped gallium nitride structure and a conductive structure. The doped gallium nitride structure extends over the heteroepitaxy structure and partially over the doped gallium nitride structure.

[0003] In another aspect, an electronic device includes a semiconductor die, conductive leads, and a package structure enclosing the semiconductor die and portions of the conductive leads. The semiconductor die has a substrate, a buffer structure, a back barrier layer, a gallium nitride layer, a first transistor, a second transistor, and a hole injector structure. The buffer structure is over the substrate, and the back barrier layer is over the buffer structure, the back barrier layer comprising aluminum gallium nitride. The gallium nitride layer is over the back barrier layer, and a heteroepitaxy structure is over the gallium nitride layer. The first transistor is coupled to one of the conductive leads and has a first drain, a first gate, and a first source. The first drain is partially within the heteroepitaxy structure, and the first gate is over the heteroepitaxy structure and spaced apart from the first drain. The first source is partially within the heteroepitaxy structure and spaced apart from the first gate. The second transistor is coupled to another of the conductive leads and has a second drain, a second gate, and a second source. The second drain is partially within the heteroepitaxy structure and is coupled to the first source. The second gate is on the heteroepitaxy structure and spaced apart from the second drain. The second source is partially within the heteroepitaxy structure and spaced apart from the second gate. The hole injector structure has a doped gallium nitride structure and a conductive structure. The doped gallium nitride structure extends over the heteroepitaxy structure, and the conductive structure is partially on the doped gallium nitride structure.

[0004] In a further aspect, a method for fabricating an electronic device includes forming a buffer structure on a substrate, forming an aluminum gallium nitride back barrier layer on the buffer structure, forming a gallium nitride layer on the back barrier layer, forming a heteroepitaxy structure on the gallium nitride layer, and forming a doped gallium nitride structure of a hole injector structure on the heteroepitaxy structure. The method also includes forming a conductive structure including, in part, the conductive structure of the hole injector structure on the doped gallium nitride structure, conductive drain and source contacts of respective first and second transistors in the heteroepitaxy structure, and conductive gate contacts of the respective first and second transistors on the heteroepitaxy structure. [Brief explanation of the drawings]

[0005] [Figure 1] FIG. 1 is a partial cross-sectional side elevation view of an electronic device comprising first and second depletion-mode gallium nitride transistors with an aluminum gallium nitride back barrier layer between a buffer structure and a gallium nitride layer, and a hole injector structure overlying the heteroepitaxy structure and engaging the drain contact of the first transistor.

[0006] [Figure 2] FIG. 1 is a partial cross-sectional side elevation view of another electronic device comprising first and second enhancement mode gallium nitride transistors with an aluminum gallium nitride back barrier layer between a buffer structure and a gallium nitride layer, and a hole injector structure overlying the heteroepitaxy structure and engaging the drain contact of the first transistor.

[0007] [Figure 3]FIG. 1 is a partial cross-sectional side elevation view of an electronic device comprising first and second depletion-mode gallium nitride transistors with an aluminum gallium nitride back barrier layer between a buffer structure and a gallium nitride layer, and a hole injector structure spaced laterally outward from the drain contact of the first transistor and overlying the heteroepitaxy structure.

[0008] [Figure 4] FIG. 1 is a partial cross-sectional side elevation view of an electronic device comprising first and second enhancement mode gallium nitride transistors comprising an aluminum gallium nitride back barrier layer between a buffer structure and a gallium nitride layer, and a hole injector structure spaced laterally outward from the drain contact of the first transistor and overlying the heteroepitaxy structure.

[0009] [Figure 5] FIG. 1 is a partial cross-sectional side elevation view of an electronic device comprising first and second depletion-mode gallium nitride transistors with an aluminum gallium nitride back barrier layer between a buffer structure and a gallium nitride layer, and a hole injector structure laterally spaced apart from, between, and overlying the heteroepitaxy structure the drain contact and gate of the first transistor.

[0010] [Figure 6] FIG. 1 is a partial cross-sectional side elevation view of an electronic device comprising first and second enhancement mode gallium nitride transistors with an aluminum gallium nitride back barrier layer between a buffer structure and a gallium nitride layer, and a hole injector structure laterally spaced apart from, between, and overlying the heteroepitaxy structure the drain contact and gate of the first transistor.

[0011] [Figure 7]FIG. 1 is a partial cross-sectional side elevation view of an electronic device comprising first and second depletion-mode gallium nitride transistors with an aluminum gallium nitride back barrier layer between a buffer structure and a gallium nitride layer, and a hole injector structure laterally spaced apart from and between the gate and source contacts of the first transistor and overlying the heteroepitaxy structure.

[0012] [Figure 8] FIG. 1 is a partial cross-sectional side elevation view of an electronic device comprising first and second enhancement mode gallium nitride transistors with an aluminum gallium nitride back barrier layer between a buffer structure and a gallium nitride layer, and a hole injector structure laterally spaced apart from and between the gate and source contacts of the first transistor and overlying the heteroepitaxy structure.

[0013] [Figure 9] 1 is a flowchart of a method for making an electronic device.

[0014] [Figure 10] 10 is a partial cross-sectional side elevational view of the electronic device of FIG. 1 that has undergone a manufacturing process in accordance with FIG. 9. [Figure 11] 10 is a partial cross-sectional side elevational view of the electronic device of FIG. 1 that has undergone a manufacturing process in accordance with FIG. 9. [Figure 12] 10 is a partial cross-sectional side elevational view of the electronic device of FIG. 1 that has undergone a manufacturing process in accordance with FIG. 9. [Figure 13] 10 is a partial cross-sectional side elevational view of the electronic device of FIG. 1 that has undergone a manufacturing process in accordance with FIG. 9. [Figure 14] 10 is a partial cross-sectional side elevational view of the electronic device of FIG. 1 that has undergone a manufacturing process in accordance with FIG. 9. [Figure 15] 10 is a partial cross-sectional side elevational view of the electronic device of FIG. 1 that has undergone a manufacturing process in accordance with FIG. 9. [Figure 16] 10 is a partial cross-sectional side elevational view of the electronic device of FIG. 1 that has undergone a manufacturing process in accordance with FIG. 9. [Figure 17]10 is a partial cross-sectional side elevational view of the electronic device of FIG. 1 that has undergone a manufacturing process in accordance with FIG. 9. [Figure 18] 10 is a partial cross-sectional side elevational view of the electronic device of FIG. 1 that has undergone a manufacturing process in accordance with FIG. 9. [Figure 19] 10 is a partial cross-sectional side elevational view of the electronic device of FIG. 1 that has undergone a manufacturing process in accordance with FIG. 9. [Figure 20] 10 is a partial cross-sectional side elevational view of the electronic device of FIG. 1 that has undergone a manufacturing process in accordance with FIG. 9.

[0015] [Figure 21] FIG. 1 is a perspective view of a packaged electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0016] In the drawings, like reference numerals refer to like elements throughout, and various features are not necessarily drawn to scale. One or more operational characteristics of various circuits, systems, and / or components are described below, in some cases, in the context of the function that results from the configuration and / or interconnection of the various structures when the circuit is powered and operating.

[0017] FIG. 1 illustrates a portion of a semiconductor die of an electronic device 100, such as a packaged integrated circuit. The electronic device 100 includes first and second depletion-mode gallium nitride transistors 101 and 102, respectively. The illustrated portion of the device 100 is first fabricated in wafer form along with other semiconductor dies that are processed and then separated by a dicing process, and then separately packaged into a completed integrated circuit product, also referred to as a packaged electronic device. The illustrated example provides monolithic integration of the first and second GaN transistors 101 and 102 in a single product for improved performance in high-voltage switching power supply systems or other fields of application. In some exemplary high-voltage switching applications, as shown schematically in FIG. 1, the first GaN transistor 101 operates as a high-side switch coupled between a high-voltage supply (e.g., labeled "HV") and a switching node (e.g., labeled "SW"). The second GaN transistor 102 operates as a low-side switch coupled between the switch node SW and a low-voltage node (e.g., labeled "LV").

[0018] In one example, an inductor (not shown) is connected between a switch node SW and a load, and high-side and low-side switches are alternately operated to form a buck DC-DC converter. In the illustrated configuration, a first (high-side) transistor 101 has a first drain D1 coupled to a high-voltage supply HV, a first source S1 coupled to the switch node SW, and a first gate G1. A second (low-side) transistor 102 has a second drain D2 coupled to the switch node SW, a second source S2 coupled to a low-voltage node LV, and a second gate G2. The first drain D1 in this example is coupled to a high voltage, such as several hundred or several thousand volts higher than the potential of the low-voltage node LV.

[0019] In one example, the electronic device 100 includes a semiconductor substrate 104, such as silicon, electrically coupled to a second source S2 and a low-voltage node LV. When the high-side first transistor 101 is turned on, the first source S1 and first drain D1 are at or near the potential of a high-voltage supply HV, creating a large electric field between the low voltage of the substrate 104 and the high voltage of the first source S1 and first drain D1. The electronic device 100 includes a hole injector structure and a back barrier that injects holes to form a hole layer proximate the interface between the back barrier and the buffer structure to mitigate a vertical field back-gate effect on the first transistor 101. This configuration helps to avoid or mitigate the back-gate effect associated with this high electric field and helps to avoid or mitigate a reduced RDSON of the first transistor 101 during operation of the electronic device 100. The back gate effect increases the RDSON in the first source S1 to a higher value, and the hole injection suppresses the RDSON increase of the first source S1 by blocking the vertical electric field.

[0020] As best seen in the partial cross-sectional side elevation view of FIG. 1 , electronic device 100 includes a stack of epitaxially grown layers, including a buffer stack, formed on a semiconductor substrate 104. Individual layers of the stack structure are described herein as aluminum nitride, aluminum gallium nitride, gallium nitride, etc., and the individual layers may be of any suitable stoichiometry, being or including the designated constituent material alone or with the additional presence of small amounts of impurities, artifacts, or other materials, such as materials that may remain after individual processing steps associated with the manufacture of semiconductor products. An exemplary stack includes an aluminum nitride (AlN) layer 106 on top of substrate 104. In one example, aluminum nitride layer 106 extends directly onto and contacts the upper or top side of substrate 104. In another example, other materials, such as impurities, artifacts, or residual materials from manufacturing processes, may be present between aluminum nitride layer 106 and substrate 104. In one example, aluminum nitride layer 106 has a thickness of 300-600 nm.

[0021] A multi-layer, compositionally graded aluminum gallium nitride (AlGaN) buffer stack 108 extends over the aluminum nitride layer 106. The buffer stack 108 includes three layers, in this example, that are or include aluminum gallium nitride. In other examples, a different number of two or more compositionally graded aluminum gallium nitride buffer stack layers can be used. In different examples, different buffer stack configurations can be used, such as single or dual superlattice buffer structures (not shown). In the example of FIG. 1, the buffer stack 108 includes a first aluminum gallium nitride layer 111 on the aluminum nitride layer 106. In one example, the first aluminum gallium nitride layer 111 extends directly onto and contacts the upper or top side of the aluminum nitride layer 106. In another example, other materials, such as impurities or artifacts or residual materials from the manufacturing process, can be present between the first aluminum gallium nitride layer 111 and the aluminum nitride layer 106. The compositionally graded AlGaN buffer stack 108 also includes a second aluminum gallium nitride layer 112 on the first aluminum gallium nitride layer 111. In one example, the second aluminum gallium nitride layer 112 extends directly onto and contacts the upper or top side of the first aluminum gallium nitride layer 111. In another example, other materials, such as impurities or artifacts or residual materials from manufacturing processes, may be present between the second aluminum gallium nitride layer 112 and the first aluminum gallium nitride layer 111. A third aluminum gallium nitride layer 113 extends onto the second aluminum gallium nitride layer 112. In one example, the third aluminum gallium nitride layer 113 extends directly onto and contacts the upper or top side of the second aluminum gallium nitride layer 112. In another example, other materials, such as impurities or artifacts or residual materials from manufacturing processes, may be present between the third aluminum gallium nitride layer 113 and the second aluminum gallium nitride layer 112.

[0022] In one example, the multilayer compositionally graded aluminum gallium nitride stack 108 includes a first aluminum gallium nitride sublayer 111 having a first aluminum concentration on the aluminum nitride layer 106, a second aluminum gallium nitride sublayer 112 on the first aluminum gallium nitride sublayer 111 having a second aluminum concentration less than the first aluminum concentration, and a third aluminum gallium nitride sublayer 113 on the second aluminum gallium nitride sublayer 112 having a third aluminum concentration less than the second aluminum concentration. In one example, the first aluminum concentration is 60-70%, the second aluminum concentration is 40-50%, and the third aluminum concentration is 20-30%. In one example, the first aluminum gallium nitride layer 111 has a thickness of 300 to 600 nm, the second aluminum gallium nitride layer 112 has a thickness of 1.4 to 1.8 μm, and the third aluminum gallium nitride layer 113 has a thickness of 1.4 to 2.0 μm.

[0023] The electronic device 100 further includes a gallium nitride layer 114 over the multilayer, compositionally-graded aluminum gallium nitride stack 108. In one example, the gallium nitride layer 114 has a thickness of 0.5-2.0 μm. In this or another example, the gallium nitride layer 114 has a thickness of 0.1-1.0 μm. In one implementation, the gallium nitride layer 114 includes carbon. In one example, the gallium nitride layer 114 extends directly onto and contacts the upper or top side of the third aluminum gallium nitride layer 113. In another example, other materials, such as impurities or artifacts or residual materials from the manufacturing process, may be present between the gallium nitride layer 114 and the third aluminum gallium nitride layer 113.

[0024] The electronic device 100 also includes a back barrier layer 116 on the buffer structure. The back barrier layer 116, in one example, is or includes aluminum gallium nitride of any suitable stoichiometry. In one example, the back barrier layer 116 extends directly onto and contacts the upper or top side of the gallium nitride layer 114 at an interface 115 between the top side of the gallium nitride layer 114 and the bottom side of the back barrier layer 116. In another example, other materials, such as impurities, artifacts, or residual materials from manufacturing processes, may be present between the back barrier layer 116 and the gallium nitride layer 114. The back barrier layer 116 has a thickness 117 of tens of nanometers to several micrometers, such as 20 nm to 5 μm. In another example, the back barrier layer 116 is or includes aluminum nitride (AlN), indium aluminum nitride (InAlN), or indium aluminum gallium nitride (InAlGaN) of any suitable stoichiometry.

[0025] An upper gallium nitride layer 118 extends over the back barrier layer 116. Layer 118 is or includes gallium nitride of any suitable stoichiometry. In one example, gallium nitride layer 118 has a thickness 119 of 1.0 μm. In one implementation, gallium nitride layer 118 includes carbon. In one example, gallium nitride layer 118 extends directly over and contacts the upper or top side of back barrier layer 116. In another example, other materials, such as impurities or artifacts or residual materials from manufacturing processes, may be present between gallium nitride layer 118 and back barrier layer 116.

[0026] Electronic device 100 also includes a heteroepitaxy structure having an aluminum nitride layer 120 on gallium nitride layer 118 and an aluminum gallium nitride layer 121 on aluminum nitride layer 120. In one example, layer 120 is or includes aluminum nitride of any suitable stoichiometry. In one example, aluminum nitride layer 120 extends directly onto and contacts the upper or top side of gallium nitride layer 118. In another example, other materials, such as impurities or artifacts or residual materials from manufacturing processes, may be present between aluminum nitride layer 120 and gallium nitride layer 118. In this or another example, layer 121 is or includes aluminum gallium nitride of any suitable stoichiometry. In one example, aluminum gallium nitride layer 121 extends directly onto and contacts the upper or top side of aluminum nitride layer 120. In another example, other materials, such as impurities or artifacts or residual materials from the manufacturing process, may be present between aluminum gallium nitride layer 121 and aluminum nitride layer 120. The heterojunction at the interface between aluminum gallium nitride layer 121 and aluminum nitride layer 120 forms a two-dimensional electron gas region 122 (e.g., designated "2DEG"). In one example, the heteroepitaxy structure including layers 120 and 121 has a total thickness 123 of 10-30 nm. Electronic device 100 also includes one or more transistors, including, in the illustrated implementation, a depletion-mode high-side first transistor 101 and a depletion-mode low-side second transistor 102.

[0027] The various buffer layers and layers of the heteroepitaxy structure are fabricated, in one example, to a total thickness of about 5.1 μm using an epitaxial growth deposition process, e.g., a continuous epitaxial deposition process in which the variables and materials forming the constituent layers are varied throughout, and / or two or more sequential epitaxial deposition processes. In depletion-mode transistor 101, the heteroepitaxy structure including layers 120 and 121 has a total thickness of about 10-30 nm, and in enhancement-mode transistor 102, the heteroepitaxy structure has a total thickness of about 10-20 nm. In one example, aluminum nitride layer 120 has a thickness of about 10 Å (1 nm), and aluminum gallium nitride layer 121 has a thickness of about 20 nm. In the illustrated example, gallium nitride layer 118 has a thickness of about 0.1-1.0 μm. In one example, aluminum gallium nitride layer 121 has an aluminum concentration of about 26%.

[0028] The electronic device 100 includes a hole injector structure 126 having a doped gallium nitride structure 124 on the aluminum gallium nitride layer 121. The hole injector structure 126 also includes a conductive structure partially overlying and in contact with the doped gallium nitride structure 124. In one example, the doped gallium nitride structure 124 is or includes gallium nitride of any suitable stoichiometry doped with p-type impurities (e.g., p-GaN containing magnesium or other p-type impurities). In one example, the doped gallium nitride structure 124 extends directly onto and contacts the upper or top side of the aluminum gallium nitride layer 121. In another example, other materials, such as impurities or artifacts or residual materials from the manufacturing process, may be present between the doped gallium nitride structure 124 and the aluminum gallium nitride layer 121. In one example, the p-doped gallium nitride layer 124 includes a magnesium dopant and has a thickness of 50 to 200 nm, such as about 70 nm in one implementation.

[0029] The conductive structure in this case is a conductive first drain contact that is or includes tungsten, copper, aluminum, or other conductive metal. Electronic device 100 further includes an insulating structure 128, such as silicon dioxide of any suitable stoichiometry, between transistors 101 and 102 that extends down through aluminum gallium nitride layer 121, aluminum nitride layer 120, gallium nitride layer 118, and back barrier layer 116 and partially into gallium nitride layer 114. In this or another example, isolation between transistors 101 and 102 is achieved by implantation (not shown).

[0030] The electronic device 100 also includes a metallization structure having a first pre-metal dielectric (e.g., PMD) layer 130, comprising, for example, silicon nitride or silicon dioxide, in which various conductive metal structures are formed, including a first drain contact or electrode 131 of the first transistor 101 that at least partially covers the doped gallium nitride structure 124. In one example, the conductive structure 131 extends directly over and contacts at least a portion of the upper or top side of the doped gallium nitride structure 124. In another example, other materials, such as impurities or artifacts or residual materials from the manufacturing process, may be present between the conductive structure 131 and the doped gallium nitride structure 124.

[0031] The PMD layer or level also includes a first source contact or electrode 132 of the first transistor 101 and a first gate contact or electrode 134 of the first transistor 101. The PMD layer or level also includes a second drain contact or electrode 135 of the second transistor 102, a second source contact or electrode 136 of the second transistor 102, a second gate contact or electrode 138 of the second transistor 102, and one or more conductive contacts or vias 139 that extend through the PMD layer 130 and provide electrical interconnection of the various transistor terminals for routing in a second metallization structure level. The conductive drain and source contacts 131, 135, 132, 136 of the respective first and second transistors 101 and 102 extend partially into the heteroepitaxy structures 120, 121, and the conductive gate contacts 134 and 138 of the respective first and second transistors 101 and 102 extend onto and contact the heteroepitaxy structures 120, 121.

[0032] The electronic device 100 in FIG. 1 further includes a second metallization structure level comprising a dielectric layer 150 (e.g., silicon nitride or silicon dioxide) having one or more conductive routing features 151 (e.g., aluminum, copper, etc.), for providing, for example, drain, source, and gate connections and associated signal routing to each other and / or to conductive bond pads or other externally exposed conductive features, so that the transistors 101 and 102 can be electrically interconnected with other circuit elements using bond wires or lead frame electrical connections to integrated circuit leads, such as pins or pads within a packaged electronic device, as shown below in the exemplary packaged electronic device of FIG. 21.

[0033] The first transistor 101 in this example has a first drain terminal or lead 161 (D1), a first gate terminal or lead 162 (G1), and a first source terminal or lead 163 (S1). The second transistor 102 has a second drain terminal or lead 164 (D2), a second gate terminal or lead 165 (G2), and a second source terminal or lead 166 (S2), the terminals being electrically coupled to conductive leads of the finished electronic device 100 after packaging, in one example, as shown in Figure 21. The transistor terminals may be referred to herein as drain, gate, source, etc., with reference to associated conductive contacts, vias, conductive contact routing features, and / or their conductive contact leads.

[0034] In the illustrated example, a first drain 161, D1 extends partially into the heteroepitaxy structures 120, 121, and a first gate 162, G1 extends over the heteroepitaxy structures 120, 121 and is laterally spaced apart from the first drain 161, D1 along a first direction (e.g., the "X" direction in the figures). A first source 163, S1 extends partially into the heteroepitaxy structures 120, 121 and is laterally spaced apart from the first gate 162, G1 along the first direction X. A second drain 164, D2 extends partially into the heteroepitaxy structures 120, 121 and is coupled to the first source 163, S1 by a conductive routing feature 151 in FIG. 1 to form a switching node SW. The second gate 165, G2 extends over the heteroepitaxy structures 120, 121 and is laterally spaced apart from the second drain 164, D2 along the first direction X. The second source 166, S2 extends partially within the heteroepitaxy structures 120, 121 and is laterally spaced apart from the second gate 165, G2 along the first direction X.

[0035] 1, the first and second transistors 101 and 102 are depletion-mode transistors, and the first and second gates 162 and 165 (G1 and G2) include respective gate contact structures 134 and 138 that extend onto and contact the AlGaN layer 121 of the heteroepitaxy structures 120 and 121. Additionally, in this example, the conductive structure 131 of the hole injector structure 126 is coupled to the first drain 161 (D1). In this example, the hole injector structure 126 is adjacent to and contacts the first drain 161 (D1), and the metallization structure includes a conductive routing feature 151 that electrically couples the first source 163 (S1) to the second drain 164 (D2). In operation, when the first drain 161, D1, is at a high voltage relative to the substrate 104 and the first gate 162, G1, is at a voltage above the threshold voltage of the first transistor 101, electrons are formed in the channel region at and near the top surface of the gallium nitride layer 118, as shown at 170 in FIG. 1 . A high drain voltage at the conductive structure 131 of the hole injector structure 126 causes holes to be injected from the p-doped gallium nitride structure 124. The injected holes form a hole layer in the buffer at or near the bottom side of the gallium nitride layer 118 adjacent the interface 115 of the back barrier layer 116, as shown at 172 in FIG. 1 , to mitigate the vertical field back gate effect for the first transistor 101.

[0036] 2 shows a partial cross-sectional side elevation view of another electronic device 200 comprising first and second enhancement-mode gallium nitride transistors 201 and 202 having an aluminum gallium nitride back barrier layer between a buffer structure and a gallium nitride layer, and a hole injector structure overlying the heteroepitaxy structure and engaging the drain contact of the first transistor. The electronic device 200 includes the hole injector structure and the back barrier that injects holes to form a hole layer proximate the interface between the back barrier and the buffer structure to mitigate vertical field back-gating effect for the first transistor 201. The electronic device 200 includes an epitaxially grown stack of layers including a buffer stack formed over a semiconductor substrate 204. The individual layers of the stack structure are described herein as aluminum nitride, aluminum gallium nitride, gallium nitride, etc., and the individual layers may be of any suitable stoichiometry, being or including the specified constituent material alone or with the additional presence of small amounts of impurities, artifacts, or other materials, such as materials that may remain after individual processing steps associated with the manufacture of semiconductor products. An exemplary stack includes an aluminum nitride layer 206 on a substrate 204. In one example, the aluminum nitride layer 206 extends directly onto and contacts the upper or top side of the substrate 204. In another example, other materials, such as impurities, artifacts, or residual materials from manufacturing processes, may be present between the aluminum nitride layer 206 and the substrate 204. In one example, the aluminum nitride layer 206 has a thickness of 300-600 nm.

[0037] A multi-layer graded aluminum gallium nitride buffer stack 208 extends over the aluminum nitride layer 206. The buffer stack 208 includes three layers, in this example, that are or include aluminum gallium nitride. In other examples, a different number of two or more compositionally graded aluminum gallium nitride buffer stack layers can be used. In different examples, different buffer stack configurations can be used, such as single or double superlattice buffer structures (not shown). In the example of FIG. 2, the buffer stack 208 includes a first aluminum gallium nitride layer 211 over the aluminum nitride layer 206. In one example, the first aluminum gallium nitride layer 211 extends directly over and contacts the upper or top side of the aluminum nitride layer 206. In another example, other materials, such as impurities or artifacts or residual materials from the manufacturing process, can be present between the first aluminum gallium nitride layer 211 and the aluminum nitride layer 206. The compositionally graded AlGaN buffer stack 208 also includes a second aluminum gallium nitride layer 212 on the first aluminum gallium nitride layer 211. In one example, the second aluminum gallium nitride layer 212 extends directly onto and contacts the upper or top side of the first aluminum gallium nitride layer 211. In another example, other materials, such as impurities or artifacts or residual materials from the manufacturing process, may be present between the second aluminum gallium nitride layer 212 and the first aluminum gallium nitride layer 211. A third aluminum gallium nitride layer 213 extends on the second aluminum gallium nitride layer 212. In one example, the third aluminum gallium nitride layer 213 extends directly onto and contacts the upper or top side of the second aluminum gallium nitride layer 212. In another example, other materials, such as impurities or artifacts or residual materials from the manufacturing process, may be present between the third aluminum gallium nitride layer 213 and the second aluminum gallium nitride layer 212 .

[0038] In one example, the multilayer compositionally graded aluminum gallium nitride stack 208 includes a first aluminum gallium nitride sublayer 211 having a first aluminum concentration over the aluminum nitride layer 206, a second aluminum gallium nitride sublayer 212 having a second aluminum concentration over the first aluminum gallium nitride sublayer 211 that is less than the first aluminum concentration, and a third aluminum gallium nitride sublayer 213 having a third aluminum concentration over the second aluminum gallium nitride sublayer 212 that is less than the second aluminum concentration. In one example, the first aluminum concentration is 60-70%, the second aluminum concentration is 40-50%, and the third aluminum concentration is 20-30%. In one example, the first aluminum gallium nitride layer 211 has a thickness of 300 to 600 nm, the second aluminum gallium nitride layer 212 has a thickness of 1.4 to 1.8 μm, and the third aluminum gallium nitride layer 213 has a thickness of 1.4 to 2.0 μm.

[0039] The electronic device 200 further includes a gallium nitride layer 214 over the multilayer, compositionally-graded aluminum gallium nitride stack 208. In one example, the gallium nitride layer 214 has a thickness of 0.5-2.0 μm. In this or another example, the gallium nitride layer 214 has a thickness of 0.1-1.0 μm. In one implementation, the gallium nitride layer 214 includes carbon. In one example, the gallium nitride layer 214 extends directly onto and contacts the upper or top side of the third aluminum gallium nitride layer 213. In another example, other materials, such as impurities or artifacts or residual materials from the manufacturing process, may be present between the gallium nitride layer 214 and the third aluminum gallium nitride layer 213.

[0040] The electronic device 200 also includes a back barrier layer 216 over the buffer structure. The back barrier layer 216, in one example, is or includes aluminum gallium nitride of any suitable stoichiometry. In one example, the back barrier layer 216 extends directly onto and contacts the upper or top side of the gallium nitride layer 214 at an interface 215 between the top side of the gallium nitride layer 214 and the bottom side of the back barrier layer 216. In another example, other materials, such as impurities, artifacts, or residual materials from manufacturing processes, may be present between the back barrier layer 216 and the gallium nitride layer 214. The back barrier layer 216 has a thickness 217 of tens of nanometers to several micrometers, such as 20 nm to 5 μm. In another example, the back barrier layer 216 is or includes aluminum nitride, indium aluminum nitride, or indium aluminum gallium nitride of any suitable stoichiometry.

[0041] An upper gallium nitride layer 218 extends over the back barrier layer 216. Layer 218 is or includes gallium nitride of any suitable stoichiometry. In one example, gallium nitride layer 218 has a thickness 219 of 0.1-1.0 μm. In one implementation, gallium nitride layer 218 includes carbon. In one example, gallium nitride layer 218 extends directly over and contacts the upper or top side of back barrier layer 216. In another example, other materials, such as impurities or artifacts or residual materials from manufacturing processes, may be present between gallium nitride layer 218 and back barrier layer 216.

[0042] Electronic device 200 also includes a heteroepitaxy structure having an aluminum nitride layer 220 on gallium nitride layer 218 and an aluminum gallium nitride layer 221 on aluminum nitride layer 220. In one example, layer 220 is or includes aluminum nitride of any suitable stoichiometry. In one example, aluminum nitride layer 220 extends directly onto and contacts the upper or top side of gallium nitride layer 218. In another example, other materials, such as impurities or artifacts or residual materials from manufacturing processes, may be present between aluminum nitride layer 220 and gallium nitride layer 218. In this or another example, layer 221 is or includes aluminum gallium nitride of any suitable stoichiometry. In one example, aluminum gallium nitride layer 221 extends directly onto and contacts the upper or top side of aluminum nitride layer 220. In another example, other materials, such as impurities or artifacts or residual material from the manufacturing process, may be present between aluminum gallium nitride layer 221 and aluminum nitride layer 220. A heterojunction at the interface between aluminum gallium nitride layer 221 and aluminum nitride layer 220 forms a two-dimensional electron gas region 222. In one example, the heteroepitaxy structure including layers 220 and 221 has a total thickness 223 of 10 to 30 nm. Electronic device 200 also includes one or more transistors, which in the illustrated implementation include an enhancement-mode high-side first transistor 201 and an enhancement-mode low-side second transistor 202.

[0043] The various buffer layers and layers of the heteroepitaxy structure are fabricated, in one example, to a total thickness of about 5.1 μm using an epitaxial growth deposition process, e.g., a continuous epitaxial deposition process in which the variables and materials forming the constituent layers are varied throughout, and / or two or more sequential epitaxial deposition processes. In enhancement-mode transistor 201, the heteroepitaxy structure including layers 220 and 221 has a total thickness of about 10-30 nm, and in enhancement-mode transistor 202, the heteroepitaxy structure has a total thickness of about 10-20 nm. In one example, aluminum nitride layer 220 has a thickness of about 10 Å (1 nm), and aluminum gallium nitride layer 221 has a thickness of about 20 nm. In the illustrated example, gallium nitride layer 218 has a thickness of about 0.1-1.0 μm. In one example, aluminum gallium nitride layer 221 has an aluminum concentration of about 26%.

[0044] The electronic device 200 includes a hole injector structure 226 having a doped gallium nitride structure 224 on an aluminum gallium nitride layer 221. The hole injector structure 226 also includes a conductive structure partially overlying and in contact with the doped gallium nitride structure 224. In one example, the doped gallium nitride structure 224 is or includes gallium nitride of any suitable stoichiometry doped with p-type impurities (e.g., p-GaN containing magnesium or other p-type impurities). In one example, the doped gallium nitride structure 224 extends directly over and in contact with the upper or top side of the aluminum gallium nitride layer 221. In another example, other materials, such as impurities or artifacts or residual materials from manufacturing processes, may be present between the doped gallium nitride structure 224 and the aluminum gallium nitride layer 221. In one example, the p-doped gallium nitride layer 224 includes a magnesium dopant and has a thickness of 50-200 nm, such as about 70 nm in one implementation.

[0045] The conductive structure in this case is a conductive first drain contact that is or includes tungsten, copper, aluminum, or other conductive metal. Electronic device 200 further includes an insulating structure 228, such as silicon dioxide of any suitable stoichiometry, between transistors 201 and 202 that extends down through aluminum gallium nitride layer 221, aluminum nitride layer 220, gallium nitride layer 218, and back barrier layer 216 and partially into gallium nitride layer 214. In this or another example, isolation between transistors 201 and 202 is achieved by implantation (not shown).

[0046] The electronic device 200 also includes a metallization structure having a first pre-metal dielectric (e.g., PMD) layer 230, comprising, for example, silicon nitride or silicon dioxide, in which various conductive metal structures are formed, including a first drain contact or electrode 231 of the first transistor 201 that at least partially covers the doped gallium nitride structure 224. In one example, the conductive structure 231 extends directly over and contacts at least a portion of the upper or top side of the doped gallium nitride structure 224. In another example, other materials, such as impurities or artifacts or residual materials from the manufacturing process, may be present between the conductive structure 231 and the doped gallium nitride structure 224.

[0047] The PMD layer or level also includes a first source contact or electrode 232 of the first transistor 201 and a first gate contact or electrode 234 of the first transistor 201. The PMD layer or level also includes a second drain contact or electrode 235 of the second transistor 202, a second source contact or electrode 236 of the second transistor 202, a second gate contact or electrode 238 of the second transistor 202, and one or more conductive contacts or vias 239 that extend through the PMD layer 230 and provide electrical interconnection of the various transistor terminals for routing in a second metallization structure level. The conductive drain and source contacts 231, 235, 232, 236 of the respective first and second transistors 201 and 202 extend partially into the heteroepitaxy structures 220, 221, and the conductive gate contacts 234 and 238 of the respective first and second transistors 201 and 202 extend onto and contact the heteroepitaxy structures 220, 221.

[0048] 2, the first and second transistors 201, 202 are enhancement-mode transistors. The first gate 262, G1 includes a first doped gallium nitride gate structure 224 (e.g., p-doped GaN) extending over and in contact with the aluminum gallium nitride layer 221 of the heteroepitaxy structures 220, 221, and a first conductive gate contact structure 234 extends over the first doped gallium nitride gate structure 224. The second gate 265, G2 includes a second doped gallium nitride gate structure 224 (e.g., p-doped GaN) extending over and in contact with the aluminum gallium nitride layer 221 of the heteroepitaxy structures 220, 221, and a second conductive gate contact structure 284 extending over the second doped gallium nitride gate structure 224.

[0049] Electronic device 200 in FIG. 2 further includes a second metallization structure level comprising a dielectric layer 250 (e.g., silicon nitride or silicon dioxide) having one or more conductive routing features 251 (e.g., aluminum, copper, etc.), for providing, for example, drain, source, and gate connections and associated signal routing to each other and / or to conductive bond pads or other externally exposed conductive features, so that transistors 201 and 202 can be electrically interconnected with other circuit elements, for example, using bond wires or lead frame electrical connections to integrated circuit leads, such as pins or pads in a packaged electronic device.

[0050] The first transistor 201 in this example has a first drain terminal or lead 261 (D1), a first gate terminal or lead 262 (G1), and a first source terminal or lead 263 (S1). The second transistor 202 has a second drain terminal or lead 264 (D2), a second gate terminal or lead 265 (G2), and a second source terminal or lead 266 (S2), the terminals being electrically coupled to conductive leads of the completed electronic device 200 after packaging in one example. The transistor terminals may be referred to herein as drain, gate, source, etc., with reference to associated conductive contacts, vias, conductive contact routing features, and / or their conductive contact leads.

[0051] In the illustrated example, a first drain 261, D1 extends partially into the heteroepitaxy structures 220, 221, and a first gate 262, G1 extends over the heteroepitaxy structures 220, 221 and is laterally spaced apart from the first drain 261, D1 along a first direction (e.g., the "X" direction in the figures). A first source 263, S1 extends partially into the heteroepitaxy structures 220, 221 and is laterally spaced apart from the first gate 262, G1 along the first direction X. A second drain 264, D2 extends partially into the heteroepitaxy structures 220, 221 and is coupled to the first source 263, S1 by a conductive routing feature 251 in FIG. 2 to form a switching node SW. The second gate 265, G2 extends over the heteroepitaxy structures 220, 221 and is laterally spaced apart from the second drain 264, D2 along the first direction X. The second source 266, S2 extends partially within the heteroepitaxy structures 220, 221 and is laterally spaced apart from the second gate 265, G2 along the first direction X.

[0052] 2, the first and second transistors 201 and 202 are enhancement-mode transistors, and the first and second gates 262 and 265 (G1 and G2) include respective gate contact structures 234 and 238 that extend onto and contact the respective p-doped GaN structures 224 over the AlGaN layer 221 of the heteroepitaxy structures 220 and 221. Additionally, in this example, the conductive structure 231 of the hole injector structure 226 is coupled to the first drain 261 (D1). In this example, the hole injector structure 226 is adjacent to and contacts the first drain 261 (D1), and the metallization structure includes a conductive routing feature 251 that electrically couples the first source 263 (S1) to the second drain 264 (D2). In operation, when the first drain 261, D1, is at a high voltage relative to the substrate 204 and the first gate 262, G1, a voltage above the threshold voltage of the first transistor 201, electrons are formed in the channel region at and near the top surface of the gallium nitride layer 218, shown at 270 in FIG. 2. The high drain voltage at the conductive structure 231 of the hole injector structure 226 causes injection of holes from the p-doped gallium nitride structure 224. The injected holes form a hole layer in the buffer at or near the bottom side of the gallium nitride layer 218 adjacent the interface 215 of the back barrier layer 216, shown at 272 in FIG. 2, to mitigate the vertical field back gate effect for the first transistor 201.

[0053] 3 illustrates a partial cross-sectional side elevation view of another exemplary electronic device 300 having first and second (e.g., high-side and low-side) depletion-mode gallium nitride field effect transistors 301 and 302 with an aluminum gallium nitride back barrier layer between the buffer structure and the gallium nitride layer, and a hole injector structure disposed on the heteroepitaxy structure and spaced laterally outward from the drain contact of the first transistor. The electronic device 300 includes a semiconductor substrate 304, such as silicon. The hole injector structure injects holes to form a hole layer proximate the interface between the back barrier and the buffer structure to mitigate vertical-field back-gate effects on the first transistor 301. This configuration helps to avoid or mitigate the back-gate effects associated with this high electric field, and thus helps to avoid or mitigate a reduced RDSON of the first transistor 301 during operation of the electronic device 300.

[0054] The electronic device 300 includes a stack of epitaxially grown layers, including a buffer stack, formed on a semiconductor substrate 304. The individual layers of the stack structure are described herein as aluminum nitride, aluminum gallium nitride, gallium nitride, etc., and the individual layers may be of any suitable stoichiometry, either alone or including the specified constituent material, with the further presence of small amounts of impurities, artifacts, or other materials that may remain after individual processing steps associated with, for example, the manufacture of semiconductor products. The exemplary stack includes an aluminum nitride layer 306 on a substrate 304. In one example, the aluminum nitride layer 306 extends directly onto and contacts the upper or top side of the substrate 304. In another example, other materials, such as impurities, artifacts, or residual materials from manufacturing processes, may be present between the aluminum nitride layer 306 and the substrate 304. In one example, the aluminum nitride layer 306 has a thickness of 300-600 nm.

[0055] A multi-layer, compositionally-graded aluminum gallium nitride buffer stack 308 extends over the aluminum nitride layer 306. The buffer stack 308 includes three layers, which in this example are or include aluminum gallium nitride. In other examples, a different number of two or more compositionally-graded aluminum gallium nitride buffer stack layers can be used. In different examples, different buffer stack configurations can be used, such as single or double superlattice buffer structures (not shown). In the example of FIG. 3, the buffer stack 308 includes a first aluminum gallium nitride layer 311 over the aluminum nitride layer 306. In one example, the first aluminum gallium nitride 311 extends directly over and contacts the upper or top side of the aluminum nitride 306. In another example, other materials, such as impurities or artifacts or residual materials from manufacturing processes, can be present between the first aluminum gallium nitride layer 311 and the aluminum nitride layer 306. The compositionally-graded AlGaN buffer stack 308 also includes a second aluminum gallium nitride layer 312 over the first aluminum gallium nitride layer 311. In one example, the second aluminum gallium nitride layer 312 extends directly onto and contacts the upper or top side of the first aluminum gallium nitride layer 311. In another example, other materials, such as impurities or artifacts or residual materials from manufacturing processes, may be present between the second aluminum gallium nitride layer 312 and the first aluminum gallium nitride layer 311. The third aluminum gallium nitride layer 313 extends over the second aluminum gallium nitride layer 312. In one example, the third aluminum gallium nitride layer 313 extends directly onto and contacts the upper or top side of the second aluminum gallium nitride layer 312. In another example, other materials, such as impurities or artifacts or residual materials from manufacturing processes, may be present between the third aluminum gallium nitride layer 313 and the second aluminum gallium nitride layer 312.

[0056] In one example, the multilayer compositionally graded aluminum gallium nitride stack 308 includes a first aluminum gallium nitride sublayer 311 having a first aluminum concentration on the aluminum nitride layer 306, a second aluminum gallium nitride sublayer 312 having a second aluminum concentration on the first aluminum gallium nitride sublayer 311 that is less than the first aluminum concentration, and a third aluminum gallium nitride sublayer 313 having a third aluminum concentration on the second aluminum gallium nitride sublayer 312 that is less than the second aluminum concentration. In one example, the first aluminum concentration is 60-70%, the second aluminum concentration is 40-50%, and the third aluminum concentration is 20-30%. In one example, the first aluminum gallium nitride layer 311 has a thickness of 300 to 600 nm, the second aluminum gallium nitride layer 312 has a thickness of 1.4 to 1.8 μm, and the third aluminum gallium nitride layer 313 has a thickness of 1.4 to 2.0 μm.

[0057] The electronic device 300 further includes a gallium nitride layer 314 over the multilayer, compositionally-graded aluminum gallium nitride stack 308. In one example, the gallium nitride layer 314 has a thickness of 0.5-2.0 μm. In this or another example, the gallium nitride layer 314 has a thickness of 0.1-1.0 μm. In one implementation, the gallium nitride layer 314 includes carbon. In one example, the gallium nitride layer 314 extends directly onto and contacts the upper or top side of the third aluminum gallium nitride layer 313. In another example, other materials, such as impurities or artifacts or residual materials from the manufacturing process, may be present between the gallium nitride layer 314 and the third aluminum gallium nitride layer 313.

[0058] The electronic device 300 also includes a back barrier layer 316 over the buffer structure. The back barrier layer 316, in one example, is or includes aluminum gallium nitride of any suitable stoichiometry. In one example, the back barrier layer 316 extends directly onto and contacts the upper or top side of the gallium nitride layer 314 at an interface 315 between the top side of the gallium nitride layer 314 and the bottom side of the back barrier layer 316. In another example, other materials, such as impurities, artifacts, or residual materials from manufacturing processes, may be present between the back barrier layer 316 and the gallium nitride layer 314. The back barrier layer 316 has a thickness 317 of tens of nanometers to several micrometers, such as 20 nm to 5 μm. In another example, the back barrier layer 316 is or includes aluminum nitride (AlN), indium aluminum nitride (InAlN), or indium aluminum gallium nitride (InAlGaN) of any suitable stoichiometry.

[0059] An upper gallium nitride layer 318 extends over the back barrier layer 316. Layer 318 is or includes gallium nitride of any suitable stoichiometry. In one example, gallium nitride layer 318 has a thickness 319 of 0.1 to 1.0 μm. In one implementation, gallium nitride layer 318 includes carbon. In one example, gallium nitride layer 318 extends directly over and contacts the upper or top side of back barrier layer 316. In another example, other materials, such as impurities or artifacts or residual materials from manufacturing processes, may be present between gallium nitride layer 318 and back barrier layer 316.

[0060] Electronic device 300 also includes a heteroepitaxy structure having an aluminum nitride layer 320 on gallium nitride layer 318 and an aluminum gallium nitride layer 321 on aluminum nitride layer 320. In one example, layer 320 is or includes aluminum nitride of any suitable stoichiometry. In one example, aluminum nitride layer 320 extends directly onto and contacts the upper or top side of gallium nitride layer 318. In another example, other materials, such as impurities or artifacts or residual materials from manufacturing processes, may be present between aluminum nitride layer 320 and gallium nitride layer 318. In this or another example, layer 321 is or includes aluminum gallium nitride of any suitable stoichiometry. In one example, aluminum gallium nitride layer 321 extends directly onto and contacts the upper or top side of aluminum nitride layer 320. In another example, other materials, such as impurities or artifacts or residual material from the manufacturing process, may be present between aluminum gallium nitride layer 321 and aluminum nitride layer 320. A heterojunction at the interface between aluminum gallium nitride layer 321 and aluminum nitride layer 320 forms a two-dimensional electron gas region 322. In one example, the heteroepitaxy structure including layers 320 and 321 has a total thickness 323 of 10 to 30 nm. Electronic device 300 also includes one or more transistors, which in the illustrated implementation include a depletion-mode high-side first transistor 301 and a depletion-mode low-side second transistor 302.

[0061] The various buffer layers and layers of the heteroepitaxy structure are fabricated, in one example, to a total thickness of about 5.1 μm using an epitaxial growth deposition process, e.g., a continuous epitaxial deposition process in which the variables and materials forming the constituent layers are varied throughout, and / or two or more sequential epitaxial deposition processes. In depletion-mode transistor 301, the heteroepitaxy structure including layers 320 and 321 has a total thickness of about 10-30 nm, and in enhancement-mode transistor 302, the heteroepitaxy structure has a total thickness of about 10-20 nm. In one example, aluminum nitride layer 320 has a thickness of about 10 Å (1 nm), and aluminum gallium nitride layer 321 has a thickness of about 20 nm. In the illustrated example, gallium nitride layer 318 has a thickness of about 0.1-1.0 μm. In one example, aluminum gallium nitride layer 321 has an aluminum concentration of about 26%.

[0062] The electronic device 300 includes a hole injector structure 326 having a doped gallium nitride structure 324 on an aluminum gallium nitride layer 321. The hole injector structure 326 also includes a conductive structure 325 formed as a contact or via that partially overlies and abuts the doped gallium nitride structure 324. In one example, the doped gallium nitride structure 324 is or includes gallium nitride of any suitable stoichiometry doped with p-type impurities (including magnesium or other p-type impurities, such as p-GaN). In one example, the doped gallium nitride structure 324 extends directly onto and abuts the upper or top side of the aluminum gallium nitride layer 321. In another example, other materials, such as impurities or artifacts or residual materials from the manufacturing process, may be present between the doped gallium nitride structure 324 and the aluminum gallium nitride layer 321. In one example, p-doped gallium nitride layer 324 includes a magnesium dopant and has a thickness of 50-200 nm, such as about 70 nm in one implementation. Conductive structure 325 is or includes tungsten, copper, aluminum, or another conductive metal. Electronic device 300 further includes an insulating structure 328, such as silicon dioxide of any suitable stoichiometry, between transistors 301 and 302, extending down through aluminum gallium nitride layer 321, aluminum nitride layer 320, gallium nitride layer 318, and back barrier layer 316, and partially into gallium nitride layer 314. In this or another example, isolation between transistors 301 and 302 is achieved by implantation (not shown).

[0063] Electronic device 300 also includes a metallization structure having a first pre-metal dielectric (e.g., PMD) layer 330, comprising, for example, silicon nitride or silicon dioxide, in which various conductive metal structures, including conductive structure 325, are formed. In one example, conductive structure 325 extends directly over and contacts at least a portion of the upper or top side of doped gallium nitride structure 324. In another example, other materials, such as impurities or artifacts or residual materials from manufacturing processes, may be present between conductive structure 325 and doped gallium nitride structure 324.

[0064] The PMD layer or level also includes a first drain contact or electrode 331 of the first transistor 301, a first source contact or electrode 332 of the first transistor 301, and a first gate contact or electrode 334 of the first transistor 301. The PMD layer or level further includes a second drain contact or electrode 335 of the second transistor 302, a second source contact or electrode 336 of the second transistor 302, and a second gate contact or electrode 338 of the second transistor 302, as well as one or more conductive contacts or vias 339 that extend through the PMD layer 330 and provide electrical interconnection of the various transistor terminals for routing in a second metallization structure level. The conductive drain and source contacts 331, 335, 332, 336 of the respective first and second transistors 301 and 302 extend partially into the heteroepitaxy structures 320, 321, and the conductive gate contacts 334 and 338 of the respective first and second transistors 301 and 302 extend onto and contact the heteroepitaxy structures 320, 321.

[0065] The electronic device 300 in FIG. 3 further includes a second metallization structure level comprising a dielectric layer 350 having one or more conductive routing features 351 (e.g., aluminum, copper, etc.), for providing, for example, routing of drain, source, and gate connections and associated signals to each other and / or to conductive bond pads or other externally exposed conductive features, so that the transistors 301 and 302 can be electrically interconnected with other circuit elements, for example, using bond wires or lead frame electrical connections to integrated circuit leads, such as pins or pads in a packaged electronic device.

[0066] The first transistor 301 in this example has a first drain terminal or lead 361 (D1), a first gate terminal or lead 362 (G1), and a first source terminal or lead 363 (S1). The second transistor 302 has a second drain terminal or lead 364 (D2), a second gate terminal or lead 365 (G2), and a second source terminal or lead 366 (S2), which, in one example, are electrically coupled to conductive leads of the completed electronic device 300 after packaging. In the illustrated example, the first drain 361, D1, extends partially within the heteroepitaxy structures 320, 321, and the first gate 362, G1, extends over the heteroepitaxy structures 320, 321 and is laterally spaced apart from the first drain 361, D1 along a first direction (e.g., the "X" direction in the figure). The first source 363, S1 extends partially into the heteroepitaxy structures 320, 321 and is laterally spaced apart from the first gate 362, G1 along the first direction X. The second drain 364, D2 extends partially into the heteroepitaxy structures 320, 321 and is coupled to the first source 363, S1 by the conductive routing feature 351 in FIG. 3 to form the switching node SW. The second gate 365, G2 extends over the heteroepitaxy structures 320, 321 and is laterally spaced apart from the second drain 364, D2 along the first direction X. The second source 366, S2 extends partially into the heteroepitaxy structures 320, 321 and is laterally spaced apart from the second gate 365, G2 along the first direction X.

[0067] Further, in this example, the hole injector structure 326 is laterally spaced from the first drain 361 (D1), which is laterally spaced along the first direction X between the hole injector structure 326 and the first gate 362 (G1). Further, the metallization structure in this example electrically couples the hole injector structure 326 to the first gate 362 (G1). In operation, when the first transistor 301 is turned on, the hole injector structure 326 operates to inject holes downward into the GaN layer 318. In another implementation, the conductive structure 325 of the hole injector structure 326 is coupled to a control voltage node (not shown) to selectively provide a positive voltage signal to the hole injector structure 326, for example, when the first gate 362 (G1) is powered to turn on the first transistor 301.

[0068] 3, first and second transistors 301 and 302 are depletion-mode transistors, and first and second gates 362 and 365 (G1 and G2) include respective gate contact structures 334 and 338 that extend over and contact the AlGaN layer 321 of the heteroepitaxy structures 320, 321. Additionally, in this example, the conductive structure 325 of the hole injector structure 326 is coupled to the first gate 362 (G1). In this example, the metallization structure includes a conductive routing feature 351 that electrically couples the first source 363 (S1) to the second drain 364 (D2). In operation, when the first transistor 301 is turned on and the first drain D1 is at a high voltage relative to the substrate 304 and the first gate 362, G1, which is greater than the threshold voltage of the first transistor 301, electrons are formed in the channel region at and near the top surface of the gallium nitride layer 318, as shown at 370 in FIG. 3. A voltage on the conductive structure 325 of the hole injector structure 326 causes injection of holes from the p-doped gallium nitride structure 324. The injected holes form a hole layer in the buffer at or near the bottom side of the gallium nitride layer 318 adjacent the interface 315 of the back barrier layer 316, as shown at 372 in FIG. 3, to mitigate the vertical field back gate effect for the first transistor 301.

[0069] FIG. 4 shows a partial cross-sectional side elevation view of another electronic device 400 having first and second enhancement-mode gallium nitride transistors 401 and 402, with an aluminum gallium nitride back barrier layer between the buffer structure and the gallium nitride layer, and a hole injector structure spaced laterally outward from the drain contact of the first transistor and overlying the heteroepitaxy structure. The electronic device 400 includes a stack of epitaxially grown layers, including a buffer stack, formed on a semiconductor substrate 404. Individual layers of the stack structure are described herein as aluminum nitride, aluminum gallium nitride, gallium nitride, etc., and the individual layers may be of any suitable stoichiometry, being or including the specified constituent materials, alone or with the additional presence of small amounts of impurities, artifacts, or other materials, such as materials that may remain after individual processing steps associated with semiconductor product manufacturers. The exemplary stack includes an aluminum nitride layer 406 on the substrate 404. In one example, aluminum nitride layer 406 extends directly onto and contacts the upper or top side of substrate 404. In another example, other materials, such as impurities or artifacts or residual materials from the manufacturing process, may be present between aluminum nitride layer 406 and substrate 404. In one example, aluminum nitride layer 406 has a thickness of 300-600 nm.

[0070] A multi-layer, compositionally-graded aluminum gallium nitride buffer stack 408 extends over the aluminum nitride layer 406. The buffer stack 408 includes three layers, which in this example are or include aluminum gallium nitride. In other examples, a different number of two or more compositionally-graded aluminum gallium nitride buffer stack layers can be used. In different examples, different buffer stack configurations can be used, such as a single or dual superlattice buffer structure (not shown). In the example of FIG. 4, the buffer stack 408 includes a first aluminum gallium nitride layer 411 over the aluminum nitride layer 406. In one example, the first aluminum gallium nitride 411 extends directly over and contacts the upper or top side of the aluminum nitride 406. In another example, other materials, such as impurities or artifacts or residual materials from the manufacturing process, can be present between the first aluminum gallium nitride layer 411 and the aluminum nitride layer 406. The compositionally-graded AlGaN buffer stack 408 also includes a second aluminum gallium nitride layer 412 over the first aluminum gallium nitride layer 411. In one example, the second aluminum gallium nitride layer 412 extends directly onto and contacts the upper or top side of the first aluminum gallium nitride layer 411. In another example, other materials, such as impurities or artifacts or residual materials from manufacturing processes, may be present between the second aluminum gallium nitride layer 412 and the first aluminum gallium nitride layer 411. The third aluminum gallium nitride layer 413 extends onto the second aluminum gallium nitride layer 412. In one example, the third aluminum gallium nitride layer 413 extends directly onto and contacts the upper or top side of the second aluminum gallium nitride layer 412. In another example, other materials, such as impurities or artifacts or residual materials from manufacturing processes, may be present between the third aluminum gallium nitride layer 413 and the second aluminum gallium nitride layer 412.

[0071] In one example, the multilayer compositionally graded aluminum gallium nitride stack 408 includes a first aluminum gallium nitride sublayer 411 having a first aluminum concentration over the aluminum nitride layer 406, a second aluminum gallium nitride sublayer 412 having a second aluminum concentration over the first aluminum gallium nitride sublayer 411 that is less than the first aluminum concentration, and a third aluminum gallium nitride sublayer 413 having a third aluminum concentration over the second aluminum gallium nitride sublayer 412 that is less than the second aluminum concentration. In one example, the first aluminum concentration is 60-70%, the second aluminum concentration is 40-50%, and the third aluminum concentration is 20-30%. In one example, first aluminum gallium nitride layer 411 has a thickness of 300 to 600 nm, second aluminum gallium nitride layer 412 has a thickness of 1.4 to 1.8 μm, and third aluminum gallium nitride layer 413 has a thickness of 1.4 to 2.0 μm.

[0072] The electronic device 400 further includes a gallium nitride layer 414 over the multilayer, compositionally-graded aluminum gallium nitride stack 408. In one example, the gallium nitride layer 414 has a thickness of 0.5-2.0 μm. In this or another example, the gallium nitride layer 414 has a thickness of 0.1-1.0 μm. In one implementation, the gallium nitride layer 414 includes carbon. In one example, the gallium nitride layer 414 extends directly onto and contacts the upper or top side of the third aluminum gallium nitride layer 413. In another example, other materials, such as impurities or artifacts or residual materials from the manufacturing process, may be present between the gallium nitride layer 414 and the third aluminum gallium nitride layer 413.

[0073] The electronic device 400 also includes a back barrier layer 416 over the buffer structure. The back barrier layer 416, in one example, is or includes aluminum gallium nitride of any suitable stoichiometry. In one example, the back barrier layer 416 extends directly onto and contacts the upper or top side of the gallium nitride layer 414 at an interface 415 between the top side of the gallium nitride layer 414 and the bottom side of the back barrier layer 416. In another example, other materials, such as impurities, artifacts, or residual materials from manufacturing processes, may be present between the back barrier layer 416 and the gallium nitride layer 414. The back barrier layer 416 has a thickness 417 of tens of nanometers to several micrometers, such as 20 nm to 5 μm. In another example, the back barrier layer 416 is or includes aluminum nitride, indium aluminum nitride, or indium aluminum gallium nitride of any suitable stoichiometry.

[0074] An upper gallium nitride layer 418 extends over the back barrier layer 416. Layer 418 is or includes gallium nitride of any suitable stoichiometry. In one example, gallium nitride layer 418 has a thickness 419 of 0.1 to 1.0 μm. In one implementation, gallium nitride layer 418 includes carbon. In one example, gallium nitride layer 418 extends directly over and contacts the upper or top side of back barrier layer 416. In another example, other materials, such as impurities or artifacts or residual materials from manufacturing processes, may be present between gallium nitride layer 418 and back barrier layer 416.

[0075] Electronic device 400 also includes a heteroepitaxy structure having an aluminum nitride layer 420 on gallium nitride layer 418 and an aluminum gallium nitride layer 421 on aluminum nitride layer 420. In one example, layer 420 is or includes aluminum nitride of any suitable stoichiometry. In one example, aluminum nitride layer 420 extends directly onto and contacts the upper or top side of gallium nitride layer 418. In another example, other materials, such as impurities or artifacts or residual materials from manufacturing processes, may be present between aluminum nitride layer 420 and gallium nitride layer 418. In this or another example, layer 421 is or includes aluminum gallium nitride of any suitable stoichiometry. In one example, aluminum gallium nitride layer 421 extends directly onto and contacts the upper or top side of aluminum nitride layer 420. In another example, other materials, such as impurities or artifacts or residual material from the manufacturing process, may be present between aluminum gallium nitride layer 421 and aluminum nitride layer 420. A heterojunction at the interface between aluminum gallium nitride layer 421 and aluminum nitride layer 420 forms a two-dimensional electron gas region 422. In one example, the heteroepitaxy structure including layers 420 and 421 has a total thickness 423 of 10 to 30 nm. Electronic device 400 also includes one or more transistors, which in the illustrated implementation include a depletion-mode high-side first transistor 401 and a depletion-mode low-side second transistor 402.

[0076] The various buffer layers and layers of the heteroepitaxy structure are fabricated, in one example, to a total thickness of about 5.1 μm using an epitaxial growth deposition process, e.g., a continuous epitaxial deposition process in which the variables and materials forming the constituent layers are varied throughout, and / or two or more sequential epitaxial deposition processes. In depletion-mode transistor 401, the heteroepitaxy structure including layers 420 and 421 has a total thickness of about 10-30 nm, and in enhancement-mode transistor 402, the heteroepitaxy structure has a total thickness of about 10-20 nm. In one example, aluminum nitride layer 420 has a thickness of about 10 Å (1 nm), and aluminum gallium nitride layer 421 has a thickness of about 20 nm. In the illustrated example, gallium nitride layer 418 has a thickness of about 0.1-1.0 μm. In one example, aluminum gallium nitride layer 421 has an aluminum concentration of about 26%.

[0077] The electronic device 400 includes a hole injector structure 426 having a doped gallium nitride structure 424 on an aluminum gallium nitride layer 421. The hole injector structure 426 also includes a conductive structure 425 formed as a contact or via that partially overlies and contacts the doped gallium nitride structure 424. In one example, the doped gallium nitride structure 424 is or includes gallium nitride of any suitable stoichiometry doped with p-type impurities (e.g., p-GaN, including magnesium or other p-type impurities). In one example, the doped gallium nitride structure 424 extends directly onto and contacts the upper or top side of the aluminum gallium nitride layer 421. In another example, other materials, such as impurities or artifacts or residual materials from the manufacturing process, may be present between the doped gallium nitride structure 424 and the aluminum gallium nitride layer 421. In one example, p-doped gallium nitride layer 424 includes a magnesium dopant and has a thickness of 50-200 nm, such as about 70 nm in one implementation. Conductive structure 425 is or includes tungsten, copper, aluminum, or another conductive metal. Electronic device 400 further includes insulating structure 428, such as silicon dioxide of any suitable stoichiometry, between transistors 401 and 402, extending down through aluminum gallium nitride layer 421, aluminum nitride layer 420, gallium nitride layer 418, and back barrier layer 416 and partially into gallium nitride layer 414. In this or another example, isolation between transistors 401 and 402 is achieved by implantation (not shown).

[0078] Electronic device 400 also includes a metallization structure having a first pre-metal dielectric (e.g., PMD) layer 430, comprising, for example, silicon nitride or silicon dioxide, in which various conductive metal structures, including conductive structure 425, are formed. In one example, conductive structure 425 extends directly over and contacts at least a portion of the upper or top side of doped gallium nitride structure 424. In another example, other materials, such as impurities or artifacts or residual material from the manufacturing process, may be present between conductive structure 425 and doped gallium nitride structure 424.

[0079] The PMD layer or level also includes a first drain contact or electrode 431 of the first transistor 401, a first source contact or electrode 432 of the first transistor 401, and a first gate contact or electrode 434 of the first transistor 401. The PMD layer or level further includes a second drain contact or electrode 435 of the second transistor 402, a second source contact or electrode 436 of the second transistor 402, and a second gate contact or electrode 438 of the second transistor 402, as well as one or more conductive contacts or vias 439 that extend through the PMD layer 430 and provide electrical interconnection of the various transistor terminals for routing in a second metallization structure level. The conductive drain and source contacts 431, 435, 432, 436 of the respective first and second transistors 401 and 402 extend partially into the heteroepitaxy structures 420, 421, and the conductive gate contacts 434 and 438 of the respective first and second transistors 401 and 402 extend onto and contact the heteroepitaxy structures 420, 421.

[0080] The electronic device 400 in FIG. 4 further includes a second metallization structure level comprising a dielectric layer 450 (e.g., silicon nitride or silicon dioxide) having one or more conductive routing features 451 (e.g., aluminum, copper, etc.), for providing, for example, routing of drain, source, and gate connections and associated signals to each other and / or to conductive bond pads or other externally exposed conductive features, so that the transistors 401 and 402 can be electrically interconnected with other circuit elements, for example, using bond wires or lead frame electrical connections to integrated circuit leads, such as pins or pads in a packaged electronic device.

[0081] The first transistor 401 in this example has a first drain terminal or lead 461 (D1), a first gate terminal or lead 462 (G1), and a first source terminal or lead 463 (S1). The second transistor 402 has a second drain terminal or lead 464 (D2), a second gate terminal or lead 465 (G2), and a second source terminal or lead 466 (S2), which in one example are electrically coupled to conductive leads of the completed electronic device 400 after packaging. In the electronic device 400 of FIG. 4, the first and second transistors 401 and 402 are enhancement-mode transistors, and the first and second gates 462 and 465 (G1 and G2) include respective gate contact structures 434 and 438 that extend onto and contact respective p-doped GaN structures 424 on the AlGaN layer 421 of the heteroepitaxy structures 420, 421.

[0082] In the illustrated example, a first drain 461, D1 extends partially into the heteroepitaxy structures 420, 421, and a first gate 462, G1 extends on and contacts the respective p-doped GaN structures 424 above the heteroepitaxy structures 420, 421 and is laterally spaced apart from the first drain 461, D1 along a first direction (e.g., the "X" direction in the figures). A first source 463, S1 extends partially into the heteroepitaxy structures 420, 421 and is laterally spaced apart from the first gate 462, G1 along the first direction X. A second drain 464, D2 extends partially into the heteroepitaxy structures 420, 421 and is coupled to the first source 463, S1 by a conductive routing mechanism 451 in FIG. 4 to form a switching node SW. A second gate 465, G2 extends over and contacts the respective p-doped GaN structure 424 on the heteroepitaxy structures 420, 421 and is laterally spaced apart from the second drain 464, D2 along the first direction X. A second source 466, S2 extends partially within the heteroepitaxy structures 420, 421 and is laterally spaced apart from the second gate 465, G2 along the first direction X.

[0083] Also in this example, the hole injector structure 426 is spaced laterally and laterally outward from the first drain 461 (D1), which is spaced laterally along the first direction X between the hole injector structure 426 and the first gate 462 (G1). Also, in this example, the metallization structure electrically couples the hole injector structure 426 to the first gate 462 (G1). In operation, when the first transistor 401 is turned on, the hole injector structure 426 operates to inject holes downward into the GaN layer 418. In another example, the conductive structure 425 of the hole injector structure 426 is coupled to a control voltage node (not shown) to selectively provide a positive voltage signal to the hole injector structure 426, for example, when the first gate 462 (G1) is powered to turn on the first transistor 401.

[0084] In the electronic device 400 of FIG. 4 , the conductive structure 425 of the hole injector structure 426 is coupled to the first gate 462 (G1). In this example, the metallization structure includes a conductive routing feature 451 that electrically couples the first source 463 (S1) to the second drain 464 (D2). In operation, when the first transistor 401 is turned on and the first drain D1 is at a high voltage relative to the substrate 404 and the first gate 462, G1 is at a voltage higher than the threshold voltage of the first transistor 401, and electrons are formed in a channel region at and near the top surface of the gallium nitride layer 418, as shown at 470 in FIG. 4 . The voltage on the conductive structure 425 of the hole injector structure 426 causes holes to be injected from the p-doped gallium nitride structure 424. The injected holes form a hole layer in the buffer at or near the bottom side of the gallium nitride layer 418 adjacent to the interface 415 of the back barrier layer 416, shown as 472 in FIG. 4, to mitigate the vertical field back gate effect on the first transistor 401.

[0085] 5 shows a partial cross-sectional side elevation view of another electronic device 500 having first and second depletion-mode gallium nitride transistors 501 and 502 with an aluminum gallium nitride back barrier layer between a buffer structure and a gallium nitride layer, and a hole injector structure laterally spaced apart from and between the drain contact and gate of the first transistor and overlying the heteroepitaxy structure. The electronic device 500 includes a semiconductor substrate 504, such as silicon. The hole injector structure injects holes to form a hole layer proximate the interface between the back barrier and the buffer structure to mitigate vertical field back-gate effects on the first transistor 501. This configuration helps to avoid or mitigate this high electric field-related back-gate effect and thus helps to avoid or mitigate a reduced RDSON of the first transistor 501 during operation of the electronic device 500.

[0086] The electronic device 500 includes a stack of epitaxially grown layers, including a buffer stack, formed on a semiconductor substrate 504. The individual layers of the stack structure are described herein as aluminum nitride, aluminum gallium nitride, gallium nitride, etc., and the individual layers may be of any suitable stoichiometry, being or including the specified constituent material alone or with the additional presence of small amounts of impurities, artifacts, or other materials, such as materials that may remain after individual processing steps associated with the manufacture of semiconductor products. An example stack includes an aluminum nitride layer 506 on a substrate 504. In one example, the aluminum nitride layer 506 extends directly onto and contacts the upper or top side of the substrate 504. In another example, other materials, such as impurities, artifacts, or residual materials from manufacturing processes, may be present between the aluminum nitride layer 506 and the substrate 504. In one example, the aluminum nitride layer 506 has a thickness of 300-600 nm.

[0087] A multi-layer, compositionally-graded aluminum gallium nitride buffer stack 508 extends over the aluminum nitride layer 506. The buffer stack 508 includes three layers, in this example, that are or include aluminum gallium nitride. In other examples, a different number of two or more compositionally-graded aluminum gallium nitride buffer stack layers can be used. In different examples, different buffer stack configurations can be used, such as single or double superlattice buffer structures (not shown). In the example of FIG. 5, the buffer stack 508 includes a first aluminum gallium nitride layer 511 over the aluminum nitride layer 506. In one example, the first aluminum gallium nitride layer 511 extends directly over and contacts the upper or top side of the aluminum nitride layer 506. In another example, other materials, such as impurities or artifacts or residual materials from the manufacturing process, can be present between the first aluminum gallium nitride layer 511 and the aluminum nitride layer 506. The compositionally graded AlGaN buffer stack 508 also includes a second aluminum gallium nitride layer 512 on the first aluminum gallium nitride layer 511. In one example, the second aluminum gallium nitride layer 512 extends directly onto and contacts the upper or top side of the first aluminum gallium nitride layer 511. In another example, other materials, such as impurities or artifacts or residual materials from the manufacturing process, may be present between the second aluminum gallium nitride layer 512 and the first aluminum gallium nitride layer 511. A third aluminum gallium nitride layer 513 extends on the second aluminum gallium nitride layer 512. In one example, the third aluminum gallium nitride layer 513 extends directly onto and contacts the upper or top side of the second aluminum gallium nitride layer 512. In another example, other materials, such as impurities or artifacts or residual materials from the manufacturing process, may be present between the third aluminum gallium nitride layer 513 and the second aluminum gallium nitride layer 512 .

[0088] In one example, the multilayer compositionally graded aluminum gallium nitride stack 508 includes a first aluminum gallium nitride sublayer 511 having a first aluminum concentration over the aluminum nitride layer 506, a second aluminum gallium nitride sublayer 512 having a second aluminum concentration over the first aluminum gallium nitride sublayer 511 that is less than the first aluminum concentration, and a third aluminum gallium nitride sublayer 513 having a third aluminum concentration over the second aluminum gallium nitride sublayer 512 that is less than the second aluminum concentration. In one example, the first aluminum concentration is 60-70%, the second aluminum concentration is 40-50%, and the third aluminum concentration is 20-30%. In one example, the first aluminum gallium nitride layer 511 has a thickness of 300 to 600 nm, the second aluminum gallium nitride layer 512 has a thickness of 1.4 to 1.8 μm, and the third aluminum gallium nitride layer 513 has a thickness of 1.4 to 2.0 μm.

[0089] The electronic device 500 further includes a gallium nitride layer 514 over the multilayer, compositionally-graded aluminum gallium nitride stack 508. In one example, the gallium nitride layer 514 has a thickness of 0.5-2.0 μm. In this or another example, the gallium nitride layer 514 has a thickness of 0.1-1.0 μm. In one implementation, the gallium nitride layer 514 includes carbon. In one example, the gallium nitride layer 514 extends directly onto and contacts the upper or top side of the third aluminum gallium nitride layer 513. In another example, other materials, such as impurities or artifacts or residual materials from the manufacturing process, may be present between the gallium nitride layer 514 and the third aluminum gallium nitride layer 513.

[0090] The electronic device 500 also includes a back barrier layer 516 over the buffer structure. The back barrier layer 516, in one example, is or includes aluminum gallium nitride of any suitable stoichiometry. In one example, the back barrier layer 516 extends directly onto and contacts the upper or top side of the gallium nitride layer 514 at an interface 515 between the top side of the gallium nitride layer 514 and the bottom side of the back barrier layer 516. In another example, other materials, such as impurities, artifacts, or residual materials from manufacturing processes, may be present between the back barrier layer 516 and the gallium nitride layer 514. The back barrier layer 516 has a thickness 517 of tens of nanometers to several micrometers, such as 20 nm to 5 μm. In another example, the back barrier layer 516 is or includes aluminum nitride, indium aluminum nitride, or indium aluminum gallium nitride of any suitable stoichiometry.

[0091] An upper gallium nitride layer 518 extends over the back barrier layer 516. Layer 518 is or includes gallium nitride of any suitable stoichiometry. In one example, gallium nitride layer 518 has a thickness 519 of 0.1 to 1.0 μm. In one implementation, gallium nitride layer 518 includes carbon. In one example, gallium nitride layer 518 extends directly over and contacts the upper or top side of back barrier layer 516. In another example, other materials, such as impurities or artifacts or residual materials from manufacturing processes, may be present between gallium nitride layer 518 and back barrier layer 516.

[0092] Electronic device 500 also includes a heteroepitaxy structure having an aluminum nitride layer 520 on gallium nitride layer 518 and an aluminum gallium nitride layer 521 on aluminum nitride layer 520. In one example, layer 520 is or includes aluminum nitride of any suitable stoichiometry. In one example, aluminum nitride layer 520 extends directly onto and contacts the upper or top side of gallium nitride layer 518. In another example, other materials, such as impurities or artifacts or residual materials from manufacturing processes, may be present between aluminum nitride layer 520 and gallium nitride layer 518. In this or another example, layer 521 is or includes aluminum gallium nitride of any suitable stoichiometry. In one example, aluminum gallium nitride layer 521 extends directly onto and contacts the upper or top side of aluminum nitride layer 520. In another example, other materials, such as impurities or artifacts or residual material from the manufacturing process, may be present between aluminum gallium nitride layer 521 and aluminum nitride layer 520. A heterojunction at the interface between aluminum gallium nitride layer 521 and aluminum nitride layer 520 forms a two-dimensional electron gas region 522. In one example, the heteroepitaxy structure including layers 520 and 521 has a total thickness 523 of 10 to 30 nm. Electronic device 500 also includes one or more transistors, which in the illustrated implementation include a depletion-mode high-side first transistor 501 and a depletion-mode low-side second transistor 502.

[0093] The various buffer layers and layers of the heteroepitaxy structure are fabricated, in one example, to a total thickness of about 5.1 μm using an epitaxial growth deposition process, e.g., a continuous epitaxial deposition process in which the variables and materials forming the constituent layers are varied throughout, and / or two or more sequential epitaxial deposition processes. In depletion-mode transistor 501, the heteroepitaxy structure including layers 520 and 521 has a total thickness of about 10-30 nm, and in enhancement-mode transistor 502, the heteroepitaxy structure has a total thickness of about 10-20 nm. In one example, aluminum nitride layer 520 has a thickness of about 10 Å (1 nm), and aluminum gallium nitride layer 521 has a thickness of about 20 nm. In the illustrated example, gallium nitride layer 518 has a thickness of about 0.1-1.0 μm. In one example, aluminum gallium nitride layer 521 has an aluminum concentration of about 26%.

[0094] The electronic device 500 includes a hole injector structure 526 having a doped gallium nitride structure 524 on an aluminum gallium nitride layer 521. The hole injector structure 526 also includes a conductive structure 525 formed as a contact or via that partially overlies and contacts the doped gallium nitride structure 524. In one example, the doped gallium nitride structure 524 is or includes gallium nitride of any suitable stoichiometry doped with p-type impurities (p-GaN, including magnesium or other p-type impurities). In one example, the doped gallium nitride structure 524 extends directly onto and contacts the upper or top side of the aluminum gallium nitride layer 521. In another example, other materials, such as impurities or artifacts or residual materials from the manufacturing process, may be present between the doped gallium nitride structure 524 and the aluminum gallium nitride layer 521. In one example, p-doped gallium nitride layer 524 includes a magnesium dopant and has a thickness of 50-200 nm, such as about 70 nm in one implementation. Conductive structure 525 is or includes tungsten, copper, aluminum, or another conductive metal. Electronic device 500 further includes insulating structure 528, such as silicon dioxide of any suitable stoichiometry, between transistors 501 and 502, extending down through aluminum gallium nitride layer 521, aluminum nitride layer 520, gallium nitride layer 518, and back barrier layer 516, and partially into gallium nitride layer 514. In this or another example, isolation between transistors 501 and 502 is achieved by implantation (not shown).

[0095] The electronic device 500 also includes a metallization structure having a first pre-metal dielectric (e.g., PMD) layer 530, comprising, for example, silicon nitride or silicon dioxide, in which various conductive metal structures, including the conductive structure 525, are formed. In one example, the conductive structure 525 extends directly over and contacts at least a portion of the upper or top side of the doped gallium nitride structure 524. In another example, other materials, such as impurities or artifacts or residual materials from the manufacturing process, may be present between the conductive structure 525 and the doped gallium nitride structure 524.

[0096] The PMD layer or level also includes a first drain contact or electrode 531 of the first transistor 501, a first source contact or electrode 532 of the first transistor 501, and a first gate contact or electrode 534 of the first transistor 501. The PMD layer or level further includes a second drain contact or electrode 535 of the second transistor 502, a second source contact or electrode 536 of the second transistor 502, and a second gate contact or electrode 538 of the second transistor 502, as well as one or more conductive contacts or vias 539 that extend through the PMD layer 530 and provide electrical interconnection of the various transistor terminals for routing in a second metallization structure level. The conductive drain and source contacts 531, 535, 532, 536 of the respective first and second transistors 501 and 502 extend partially into the heteroepitaxy structures 520, 521, and the conductive gate contacts 534 and 538 of the respective first and second transistors 501 and 502 extend onto and contact the heteroepitaxy structures 520, 521.

[0097] The electronic device 500 in FIG. 5 further includes a second metallization structure level comprising a dielectric layer 550 (e.g., silicon nitride or silicon dioxide) having one or more conductive routing features 551 (e.g., aluminum, copper, etc.), for providing, for example, routing of drain, source, and gate connections and associated signals to each other and / or to conductive bond pads or other externally exposed conductive features, so that the transistors 501 and 502 can be electrically interconnected with other circuit elements, for example, using bond wires or lead frame electrical connections to integrated circuit leads, such as pins or pads in a packaged electronic device.

[0098] The first transistor 501 in this example has a first drain terminal or lead 561 (D1), a first gate terminal or lead 562 (G1), and a first source terminal or lead 563 (S1). The second transistor 502 has a second drain terminal or lead 564 (D2), a second gate terminal or lead 565 (G2), and a second source terminal or lead 566 (S2), which in one example are electrically coupled to conductive leads of the completed electronic device 500 after packaging. In the illustrated example, the first drain 561, D1, extends partially into the heteroepitaxy structures 520, 521, and the first gate 562, G1, extends over the heteroepitaxy structures 520, 521 and is laterally spaced apart from the first drain 561, D1 along the first direction X. The first source 563, S1 extends partially into the heteroepitaxy structures 520, 521 and is laterally spaced apart from the first gate 562, G1 along the first direction X. The second drain 564, D2 extends partially into the heteroepitaxy structures 520, 521 and is coupled to the first source 563, S1 by a conductive routing feature 551 in FIG. 5 to form a switching node SW. The second gate 565, G2 extends over the heteroepitaxy structures 520, 521 and is laterally spaced apart from the second drain 564, D2 along the first direction X. The second source 566, S2 extends partially into the heteroepitaxy structures 520, 521 and is laterally spaced apart from the second gate 565, G2 along the first direction X.

[0099] In this example, the hole injector structure 526 is between and laterally spaced apart from the first drain 561 (D1) and the first gate 562 (G1) along the first direction X. Furthermore, the metallization structure in this example electrically couples the hole injector structure 526 to the first gate 562 (G1). In operation, when the first transistor 501 is turned on, the hole injector structure 526 operates to inject holes downward into the GaN layer 518. In another implementation, the conductive structure 525 of the hole injector structure 526 is coupled to a control voltage node (not shown) to selectively provide a positive voltage signal to the hole injector structure 526, for example, when the first gate 562 (G1) is powered to turn on the first transistor 501. The first and second transistors 501 and 502 in this example are depletion-mode transistors, and the first and second gates 562 and 565 (G1 and G2) include respective gate contact structures 534 and 538 that extend over and contact the AlGaN layer 521 of the heteroepitaxy structures 520, 521. In this example, the conductive structure 525 of the hole injector structure 526 is coupled to the first gate 562 (G1). The metallization structure includes a conductive routing feature 551 that electrically couples the first source 563 (S1) to the second drain 564 (D2). In operation, when the first transistor 501 is turned on and the first drain D1 is at a high voltage relative to the substrate 504 and the first gate 562, G1, which is greater than the threshold voltage of the first transistor 501, electrons are formed in the channel region at and near the top surface of the gallium nitride layer 518, as shown at 570 in FIG. 5. A voltage on the conductive structure 525 of the hole injector structure 526 causes injection of holes from the p-doped gallium nitride structure 524. The injected holes form a hole layer in the buffer at or near the bottom side of the gallium nitride layer 518 adjacent the interface 515 of the back barrier layer 516, as shown at 572 in FIG. 5, to mitigate the vertical field back gate effect for the first transistor 501.

[0100] 6 shows a partial cross-sectional side elevation view of another electronic device 600 comprising first and second enhancement-mode gallium nitride transistors 601 and 602 with an aluminum gallium nitride back barrier layer between a buffer structure and a gallium nitride layer, and a hole injector structure between and spaced laterally from the drain contact and gate of the first transistor and overlying the heteroepitaxy structure. The electronic device 600 includes a semiconductor substrate 604, such as silicon. The hole injector structure injects holes to form a hole layer proximate the interface between the back barrier and the buffer structure to mitigate vertical-field back-gate effects on the first transistor 601. This configuration helps to avoid or mitigate the back-gate effects associated with this high electric field, and thus helps to avoid or mitigate a reduced RDSON of the first transistor 601 during operation of the electronic device 600.

[0101] The electronic device 600 includes a stack of epitaxially grown layers, including a buffer stack, formed on a semiconductor substrate 604. The individual layers of the stack structure are described herein as aluminum nitride, aluminum gallium nitride, gallium nitride, etc., and the individual layers may be of any suitable stoichiometry, being or including the specified constituent material alone or with the additional presence of small amounts of impurities, artifacts, or other materials, such as materials that may remain after individual processing steps associated with the manufacture of semiconductor products. An example stack includes an aluminum nitride layer 606 on a substrate 604. In one example, the aluminum nitride layer 606 extends directly onto and contacts the upper or top side of the substrate 604. In another example, other materials, such as impurities, artifacts, or residual materials from manufacturing processes, may be present between the aluminum nitride layer 606 and the substrate 604. In one example, the aluminum nitride layer 606 has a thickness of 300-600 nm.

[0102] A multi-layer, compositionally-graded aluminum gallium nitride buffer stack 608 extends over the aluminum nitride layer 606. The buffer stack 608 includes three layers, in this example, that are or include aluminum gallium nitride. In other examples, a different number of two or more compositionally-graded aluminum gallium nitride buffer stack layers can be used. In different examples, different buffer stack configurations can be used, such as single or double superlattice buffer structures (not shown). In the example of FIG. 6, the buffer stack 608 includes a first aluminum gallium nitride layer 611 over the aluminum nitride layer 606. In one example, the first aluminum gallium nitride 611 extends directly over and contacts the upper or top side of the aluminum nitride 606. In another example, other materials, such as impurities or artifacts or residual materials from the manufacturing process, can be present between the first aluminum gallium nitride layer 611 and the aluminum nitride layer 606. The compositionally graded AlGaN buffer stack 608 also includes a second aluminum gallium nitride layer 612 on the first aluminum gallium nitride layer 611. In one example, the second aluminum gallium nitride layer 612 extends directly onto and contacts the upper or top side of the first aluminum gallium nitride layer 611. In another example, other materials, such as impurities or artifacts or residual materials from the manufacturing process, may be present between the second aluminum gallium nitride layer 612 and the first aluminum gallium nitride layer 611. A third aluminum gallium nitride layer 613 extends on the second aluminum gallium nitride layer 612. In one example, the third aluminum gallium nitride layer 613 extends directly onto and contacts the upper or top side of the second aluminum gallium nitride layer 612. In another example, other materials, such as impurities or artifacts or residual materials from the manufacturing process, may be present between the third aluminum gallium nitride layer 613 and the second aluminum gallium nitride layer 612 .

[0103] In one example, the multilayer compositionally graded aluminum gallium nitride stack 608 includes a first aluminum gallium nitride sublayer 611 having a first aluminum concentration over the aluminum nitride layer 606, a second aluminum gallium nitride sublayer 612 having a second aluminum concentration less than the first aluminum concentration over the first aluminum gallium nitride sublayer 611, and a third aluminum gallium nitride sublayer 613 having a third aluminum concentration less than the second aluminum concentration over the second aluminum gallium nitride sublayer 612. In one example, the first aluminum concentration is 60-70%, the second aluminum concentration is 40-50%, and the third aluminum concentration is 20-30%. In one example, the first aluminum gallium nitride layer 611 has a thickness of 300 to 600 nm, the second aluminum gallium nitride layer 612 has a thickness of 1.4 to 1.8 μm, and the third aluminum gallium nitride layer 613 has a thickness of 1.4 to 2.0 μm.

[0104] Electronic device 600 further includes a gallium nitride layer 614 over multilayer compositionally graded aluminum gallium nitride stack 608. In one example, gallium nitride layer 614 has a thickness of 0.5-2.0 μm. In this or another example, gallium nitride layer 614 has a thickness of 0.1-1.0 μm. In one implementation, gallium nitride layer 614 includes carbon. In one example, gallium nitride layer 614 extends directly onto and contacts the upper or top side of third aluminum gallium nitride layer 613. In another example, other materials, such as impurities or artifacts or residual materials from manufacturing processes, may be present between gallium nitride layer 614 and third aluminum gallium nitride layer 613.

[0105] The electronic device 600 also includes a back barrier layer 616 over the buffer structure. The back barrier layer 616, in one example, is or includes aluminum gallium nitride of any suitable stoichiometry. In one example, the back barrier layer 616 extends directly onto and contacts the upper or top side of the gallium nitride layer 614 at an interface 615 between the top side of the gallium nitride layer 614 and the bottom side of the back barrier layer 616. In another example, other materials, such as impurities, artifacts, or residual materials from manufacturing processes, may be present between the back barrier layer 616 and the gallium nitride layer 614. The back barrier layer 616 has a thickness 617 of tens of nanometers to several micrometers, such as 20 nm to 5 μm. In another example, the back barrier layer 616 is or includes aluminum nitride, indium aluminum nitride, or indium aluminum gallium nitride of any suitable stoichiometry.

[0106] An upper gallium nitride layer 618 extends over the back barrier layer 616. Layer 618 is or includes gallium nitride of any suitable stoichiometry. In one example, gallium nitride layer 618 has a thickness 619 of 0.1-1.0 μm. In one implementation, gallium nitride layer 618 includes carbon. In one example, gallium nitride layer 618 extends directly over and contacts the upper or top side of back barrier layer 616. In another example, other materials, such as impurities or artifacts or residual materials from manufacturing processes, may be present between gallium nitride layer 618 and back barrier layer 616.

[0107] Electronic device 600 also includes a heteroepitaxy structure having an aluminum nitride layer 620 on gallium nitride layer 618 and an aluminum gallium nitride layer 621 on aluminum nitride layer 620. In one example, layer 620 is or includes aluminum nitride of any suitable stoichiometry. In one example, aluminum nitride layer 620 extends directly onto and contacts the upper or top side of gallium nitride layer 618. In another example, other materials, such as impurities or artifacts or residual materials from manufacturing processes, may be present between aluminum nitride layer 620 and gallium nitride layer 618. In this or another example, layer 621 is or includes aluminum gallium nitride of any suitable stoichiometry. In one example, aluminum gallium nitride layer 621 extends directly onto and contacts the upper or top side of aluminum nitride layer 620. In another example, other materials, such as impurities or artifacts or residual material from the manufacturing process, may be present between aluminum gallium nitride layer 621 and aluminum nitride layer 620. A heterojunction at the interface between aluminum gallium nitride layer 621 and aluminum nitride layer 620 forms a two-dimensional electron gas region 622. In one example, the heteroepitaxy structure including layers 620 and 621 has a total thickness 623 of 10 to 30 nm. Electronic device 600 also includes one or more transistors, which in the illustrated implementation include an enhancement-mode high-side first transistor 601 and an enhancement-mode low-side second transistor 602.

[0108] The various buffer layers and layers of the heteroepitaxy structure are fabricated, in one example, to a total thickness of about 5.1 μm using an epitaxial growth deposition process, e.g., a continuous epitaxial deposition process in which the variables and materials forming the constituent layers are varied throughout, and / or two or more sequential epitaxial deposition processes. In enhancement-mode transistor 601, the heteroepitaxy structure including layers 620 and 621 has a total thickness of about 10-30 nm, and in enhancement-mode transistor 602, the heteroepitaxy structure has a total thickness of about 10-20 nm. In one example, aluminum nitride layer 620 has a thickness of about 10 Å (1 nm), and aluminum gallium nitride layer 621 has a thickness of about 20 nm. In the illustrated example, gallium nitride layer 618 has a thickness of about 0.1-1.0 μm. In one example, aluminum gallium nitride layer 621 has an aluminum concentration of about 26%.

[0109] The electronic device 600 includes a hole injector structure 626 having a doped gallium nitride structure 624 on an aluminum gallium nitride layer 621. The hole injector structure 626 also includes a conductive structure 625 formed as a contact or via that partially overlies and contacts the doped gallium nitride structure 624. In one example, the doped gallium nitride structure 624 is or includes gallium nitride of any suitable stoichiometry doped with p-type impurities (e.g., p-GaN, including magnesium or other p-type impurities). In one example, the doped gallium nitride structure 624 extends directly onto and contacts the upper or top side of the aluminum gallium nitride layer 621. In another example, other materials, such as impurities or artifacts or residual materials from the manufacturing process, may be present between the doped gallium nitride structure 624 and the aluminum gallium nitride layer 621. In one example, p-doped gallium nitride layer 624 includes a magnesium dopant and has a thickness of 50-200 nm, such as about 70 nm in one implementation. Conductive structure 625 is or includes tungsten, copper, aluminum, or another conductive metal. Electronic device 600 further includes insulating structure 628, such as silicon dioxide of any suitable stoichiometry, between transistors 601 and 602, extending down through aluminum gallium nitride layer 621, aluminum nitride layer 620, gallium nitride layer 618, and back barrier layer 616 and partially into gallium nitride layer 614. In this or another example, isolation between transistors 601 and 602 is achieved by implantation (not shown).

[0110] Electronic device 600 also includes a metallization structure having a first pre-metal dielectric (e.g., PMD) layer 630, comprising, for example, silicon nitride or silicon dioxide, in which various conductive metal structures, including conductive structure 625, are formed. In one example, conductive structure 625 extends directly over and contacts at least a portion of the upper or top side of doped gallium nitride structure 624. In another example, other materials, such as impurities or artifacts or residual material from the manufacturing process, may be present between conductive structure 625 and doped gallium nitride structure 624.

[0111] The PMD layer or level also includes a first drain contact or electrode 631 of the first transistor 601, a first source contact or electrode 632 of the first transistor 601, and a first gate contact or electrode 634 of the first transistor 601. The PMD layer or level further includes a second drain contact or electrode 635 of the second transistor 602, a second source contact or electrode 636 of the second transistor 602, and a second gate contact or electrode 638 of the second transistor 602, as well as one or more conductive contacts or vias 639 that extend through the PMD layer 630 and provide electrical interconnection of the various transistor terminals for routing in a second metallization structure level. Conductive drain and source contacts 631, 635, 632, 636 of the respective first and second transistors 601 and 602 extend partially into the heteroepitaxy structures 620, 621, and conductive gate contacts 634 and 638 of the respective first and second transistors 601 and 602 extend onto and contact the heteroepitaxy structures 620, 621.

[0112] Electronic device 600 in FIG. 6 further includes a second metallization structure level comprising a dielectric layer 650 (e.g., silicon nitride or silicon dioxide) having one or more conductive routing features 651 (e.g., aluminum, copper, etc.), for providing, for example, routing of drain, source, and gate connections and associated signals to each other and / or to conductive bond pads or other externally exposed conductive features, so that transistors 601 and 602 can be electrically interconnected with other circuit elements, for example, using bond wires or lead frame electrical connections to integrated circuit leads, such as pins or pads in a packaged electronic device.

[0113] The first transistor 601 in this example has a first drain terminal or lead 661 (D1), a first gate terminal or lead 662 (G1), and a first source terminal or lead 663 (S1). The second transistor 602 has a second drain terminal or lead 664 (D2), a second gate terminal or lead 665 (G2), and a second source terminal or lead 666 (S2), which in one example are electrically coupled to conductive leads of the completed electronic device 600 after packaging. In the electronic device 600 of FIG. 6, the first and second transistors 601 and 602 are enhancement-mode transistors, and the first and second gates 662 and 665 (G1 and G2) include respective gate contact structures 634 and 638 that extend onto and contact respective p-doped GaN structures 624 on the AlGaN layer 621 of the heteroepitaxy structures 620, 621.

[0114] In the illustrated example, a first drain 661, D1 extends partially into the heteroepitaxy structures 620, 621, and a first gate 662, G1 extends above the heteroepitaxy structures 620, 621 onto and abuts the respective p-doped GaN structures 624 and is laterally spaced apart from the first drain 661, D1 along a first direction (e.g., the "X" direction in the figures). A first source 663, S1 extends partially into the heteroepitaxy structures 620, 621 and is laterally spaced apart from the first gate 662, G1 along the first direction X. A second drain 664, D2 extends partially into the heteroepitaxy structures 620, 621 and is coupled to the first source 663, S1 by a conductive routing feature 651 in FIG. 6 to form a switching node SW. The second gate 665, G2 extends on and contacts the respective p-doped GaN structure 624 on the heteroepitaxy structures 620, 621 and is laterally spaced apart from the second drain 664, D2 along the first direction X. The second source 666, S2 extends partially into the heteroepitaxy structures 620, 621 and is laterally spaced apart from the second gate 665, G2 along the first direction X.

[0115] In this example, the hole injector structure 626 is located between and laterally spaced apart from the first drain 661 (D1) and the first gate 662 (G1) along the first direction X. Additionally, the metallization structure in this example electrically couples the hole injector structure 626 to the first gate 662 (G1). In operation, when the first transistor 601 is turned on, the hole injector structure 626 operates to inject holes downward into the GaN layer 618. In another implementation, the conductive structure 625 of the hole injector structure 626 is coupled to a control voltage node (not shown) to selectively provide a positive voltage signal to the hole injector structure 626, for example, when the first gate 662 (G1) is powered to turn on the first transistor 601. The first and second transistors 601 and 602 in this example are enhancement-mode transistors, and the first and second gates 662 and 665 (G1 and G2) include respective gate contact structures 634 and 638 that extend over and contact the AlGaN layer 621 of the heteroepitaxy structures 620, 621. In this example, the conductive structure 625 of the hole injector structure 626 is coupled to the first gate 662 (G1). The metallization structure includes a conductive routing feature 651 that electrically couples the first source 663 (S1) to the second drain 664 (D2). In operation, when the first transistor 601 is turned on and the first drain D1 is at a high voltage relative to the substrate 604 and the first gate 662, G1, which is greater than the threshold voltage of the first transistor 601, electrons are formed in the channel region at and near the top surface of the gallium nitride layer 618, as shown at 670 in FIG. 6. A voltage on the conductive structure 625 of the hole injector structure 626 causes injection of holes from the p-doped gallium nitride structure 624. The injected holes form a hole layer in the buffer at or near the bottom side of the gallium nitride layer 618 adjacent the interface 615 of the back barrier layer 616, as shown at 672 in FIG. 6, to mitigate the vertical field back gate effect for the first transistor 601.

[0116] 7 shows a partial cross-sectional side elevation view of another electronic device 700 having first and second depletion-mode gallium nitride transistors 701 and 702 with an aluminum gallium nitride back barrier layer between the buffer structure and the gallium nitride layer, and a hole injector structure located laterally between and spaced apart from the gate and source contacts of the first transistor and overlying the heteroepitaxy structure. The electronic device 700 includes a semiconductor substrate 704, such as silicon. The hole injector structure injects holes to form a hole layer proximate the interface between the back barrier and the buffer structure to mitigate vertical field back-gate effects on the first transistor 701. This configuration helps to avoid or mitigate the back-gate effects associated with this high electric field, and thus helps to avoid or mitigate a reduced RDSON of the first transistor 701 during operation of the electronic device 700.

[0117] The electronic device 700 includes a stack of epitaxially grown layers, including a buffer stack, formed on a semiconductor substrate 704. The individual layers of the stack structure are described herein as aluminum nitride, aluminum gallium nitride, gallium nitride, etc., and the individual layers may be of any suitable stoichiometry, being or including the specified constituent material alone or with the additional presence of small amounts of impurities, artifacts, or other materials, such as materials that may remain after individual processing steps associated with the manufacture of semiconductor products. An example stack includes an aluminum nitride layer 706 on a substrate 704. In one example, the aluminum nitride layer 706 extends directly onto and contacts the upper or top side of the substrate 704. In another example, other materials, such as impurities, artifacts, or residual materials from manufacturing processes, may be present between the aluminum nitride layer 706 and the substrate 704. In one example, the aluminum nitride layer 706 has a thickness of 300-600 nm.

[0118] A multi-layer, compositionally-graded aluminum gallium nitride buffer stack 708 extends over the aluminum nitride layer 706. The buffer stack 708 includes, in this example, three layers that are or include aluminum gallium nitride. In other examples, a different number of two or more compositionally-graded aluminum gallium nitride buffer stack layers can be used. In different examples, different buffer stack configurations can be used, such as a single or dual superlattice buffer structure (not shown). In the example of FIG. 7 , the buffer stack 708 includes a first aluminum gallium nitride layer 711 over the aluminum nitride layer 706. In one example, the first aluminum gallium nitride 711 extends directly over and contacts the upper or top side of the aluminum nitride 706. In another example, other materials, such as impurities or artifacts or residual materials from the manufacturing process, can be present between the first aluminum gallium nitride layer 711 and the aluminum nitride layer 706. The compositionally-graded AlGaN buffer stack 708 also includes a second aluminum gallium nitride layer 712 over the first aluminum gallium nitride layer 711. In one example, the second aluminum gallium nitride layer 712 extends directly onto and contacts the upper or top side of the first aluminum gallium nitride layer 711. In another example, other materials, such as impurities or artifacts or residual materials from the manufacturing process, may be present between the second aluminum gallium nitride layer 712 and the first aluminum gallium nitride layer 711. The third aluminum gallium nitride layer 713 extends over the second aluminum gallium nitride layer 712. In one example, the third aluminum gallium nitride layer 713 extends directly onto and contacts the upper or top side of the second aluminum gallium nitride layer 712. In another example, other materials, such as impurities or artifacts or residual materials from the manufacturing process, may be present between the third aluminum gallium nitride layer 713 and the second aluminum gallium nitride layer 712.

[0119] In one example, the multi-layer compositionally graded aluminum gallium nitride stack 708 includes a first aluminum gallium nitride sublayer 711 having a first aluminum concentration over the aluminum nitride layer 706, a second aluminum gallium nitride sublayer 712 having a second aluminum concentration over the first aluminum gallium nitride sublayer 711 that is less than the first aluminum concentration, and a third aluminum gallium nitride sublayer 713 having a third aluminum concentration over the second aluminum gallium nitride sublayer 712 that is less than the second aluminum concentration. In one example, the first aluminum concentration is between 60 and 70%, the second aluminum concentration is between 40 and 50%, and the third aluminum concentration is between 20 and 30%. In one example, the first aluminum gallium nitride layer 711 has a thickness of 300 to 600 nm, the second aluminum gallium nitride layer 712 has a thickness of 1.4 to 1.8 μm, and the third aluminum gallium nitride layer 713 has a thickness of 1.4 to 2.0 μm.

[0120] The electronic device 700 further includes a gallium nitride layer 714 over the multilayer, compositionally-graded aluminum gallium nitride stack 708. In one example, the gallium nitride layer 714 has a thickness of 0.5-2.0 μm. In this or another example, the gallium nitride layer 714 has a thickness of 0.1-1.0 μm. In one implementation, the gallium nitride layer 714 includes carbon. In one example, the gallium nitride layer 714 extends directly onto and contacts the upper or top side of the third aluminum gallium nitride layer 713. In another example, other materials, such as impurities or artifacts or residual materials from the manufacturing process, may be present between the gallium nitride layer 714 and the third aluminum gallium nitride layer 713.

[0121] The electronic device 700 also includes a back barrier layer 716 over the buffer structure. The back barrier layer 716, in one example, is or includes aluminum gallium nitride of any suitable stoichiometry. In one example, the back barrier layer 716 extends directly onto and contacts the upper or top side of the gallium nitride layer 714 at an interface 715 between the top side of the gallium nitride layer 714 and the bottom side of the back barrier layer 716. In another example, other materials, such as impurities, artifacts, or residual materials from manufacturing processes, may be present between the back barrier layer 716 and the gallium nitride layer 714. The back barrier layer 716 has a thickness 717 of tens of nanometers to several micrometers, such as 20 nm to 5 μm. In another example, the back barrier layer 716 is or includes aluminum nitride, indium aluminum nitride, or indium aluminum gallium nitride of any suitable stoichiometry.

[0122] An upper gallium nitride layer 718 extends over the back barrier layer 716. Layer 718 is or includes gallium nitride of any suitable stoichiometry. In one example, gallium nitride layer 718 has a thickness 719 of 0.1-1.0 μm. In one implementation, gallium nitride layer 718 includes carbon. In one example, gallium nitride layer 718 extends directly over and contacts the upper or top side of back barrier layer 716. In another example, other materials, such as impurities or artifacts or residual materials from manufacturing processes, may be present between gallium nitride layer 718 and back barrier layer 716.

[0123] Electronic device 700 also includes a heteroepitaxy structure having an aluminum nitride layer 720 on gallium nitride layer 718 and an aluminum gallium nitride layer 721 on aluminum nitride layer 720. In one example, layer 720 is or includes aluminum nitride of any suitable stoichiometry. In one example, aluminum nitride layer 720 extends directly onto and contacts the upper or top side of gallium nitride layer 718. In another example, other materials, such as impurities or artifacts or residual materials from manufacturing processes, may be present between aluminum nitride layer 720 and gallium nitride layer 718. In this or another example, layer 721 is or includes aluminum gallium nitride of any suitable stoichiometry. In one example, aluminum gallium nitride layer 721 extends directly onto and contacts the upper or top side of aluminum nitride layer 720. In another example, other materials, such as impurities or artifacts or residual material from the manufacturing process, may be present between aluminum gallium nitride layer 721 and aluminum nitride layer 720. A heterojunction at the interface between aluminum gallium nitride layer 721 and aluminum nitride layer 720 forms a two-dimensional electron gas region 722. In one example, the heteroepitaxy structure including layers 720 and 721 has a total thickness 723 of 10 to 30 nm. Electronic device 700 also includes one or more transistors, which in the illustrated implementation include a depletion-mode high-side first transistor 701 and a depletion-mode low-side second transistor 702.

[0124] The various buffer layers and layers of the heteroepitaxy structure are fabricated, in one example, to a total thickness of about 5.1 μm using an epitaxial growth deposition process, e.g., a continuous epitaxial deposition process in which the variables and materials forming the constituent layers are varied throughout, and / or two or more sequential epitaxial deposition processes. In depletion-mode transistor 701, the heteroepitaxy structure including layers 720 and 721 has a total thickness of about 10-30 nm, and in enhancement-mode transistor 702, the heteroepitaxy structure has a total thickness of about 10-20 nm. In one example, aluminum nitride layer 720 has a thickness of about 10 Å (1 nm), and aluminum gallium nitride layer 721 has a thickness of about 20 nm. In the illustrated example, gallium nitride layer 718 has a thickness of about 0.1-1.0 μm. In one example, aluminum gallium nitride layer 721 has an aluminum concentration of about 26%.

[0125] The electronic device 700 includes a hole injector structure 726 having a doped gallium nitride structure 724 on an aluminum gallium nitride layer 721. The hole injector structure 726 also includes a conductive structure 725 formed as a contact or via that partially overlies and contacts the doped gallium nitride structure 724. In one example, the doped gallium nitride structure 724 is or includes gallium nitride of any suitable stoichiometry doped with p-type impurities (p-GaN, including magnesium or other p-type impurities). In one example, the doped gallium nitride structure 724 extends directly onto and contacts the upper or top side of the aluminum gallium nitride layer 721. In another example, other materials, such as impurities or artifacts or residual materials from the manufacturing process, may be present between the doped gallium nitride structure 724 and the aluminum gallium nitride layer 721. In one example, p-doped gallium nitride layer 724 includes a magnesium dopant and has a thickness of 50-200 nm, such as about 70 nm in one implementation. Conductive structure 725 is or includes tungsten, copper, aluminum, or another conductive metal. Electronic device 700 further includes an insulating structure 728, such as silicon dioxide of any suitable stoichiometry, between transistors 701 and 702, extending down through aluminum gallium nitride layer 721, aluminum nitride layer 720, gallium nitride layer 718, and back barrier layer 716, and partially into gallium nitride layer 714. In this or another example, isolation between transistors 701 and 702 is achieved by implantation (not shown).

[0126] Electronic device 700 also includes a metallization structure having a first pre-metal dielectric (e.g., PMD) layer 730, comprising, for example, silicon nitride or silicon dioxide, in which various conductive metal structures, including conductive structure 725, are formed. In one example, conductive structure 725 extends directly over and contacts at least a portion of the upper or top side of doped gallium nitride structure 724. In another example, other materials, such as impurities or artifacts or residual material from the manufacturing process, may be present between conductive structure 725 and doped gallium nitride structure 724.

[0127] The PMD layer or level also includes a first drain contact or electrode 731 of the first transistor 701, a first source contact or electrode 732 of the first transistor 701, and a first gate contact or electrode 734 of the first transistor 701. The PMD layer or level further includes a second drain contact or electrode 735 of the second transistor 702, a second source contact or electrode 736 of the second transistor 702, a second gate contact or electrode 738 of the second transistor 702, and one or more conductive contacts or vias 739 that extend through the PMD layer 730 and provide electrical interconnection of the various transistor terminals for routing in a second metallization structure level. The conductive drain and source contacts 731, 735, 732, 736 of the respective first and second transistors 701 and 702 extend partially into the heteroepitaxy structures 720, 721, and the conductive gate contacts 734 and 738 of the respective first and second transistors 701 and 702 extend onto and contact the heteroepitaxy structures 720, 721.

[0128] The electronic device 700 in FIG. 7 further includes a second metallization structure level comprising a dielectric layer 750 (e.g., silicon nitride or silicon dioxide) having one or more conductive routing features 751 (e.g., aluminum, copper, etc.) for providing routing of, for example, drain, source, and gate connections and associated signals to each other and / or to conductive bond pads or to other externally exposed conductive features, which may be electrically interconnected with other circuit elements using bond wires or lead frame electrical connections to integrated circuit leads, such as pins or pads within a packaged electronic device.

[0129] The first transistor 701 in this example has a first drain terminal or lead 761 (D1), a first gate terminal or lead 762 (G1), and a first source terminal or lead 763 (S1). The second transistor 702 has a second drain terminal or lead 764 (D2), a second gate terminal or lead 765 (G2), and a second source terminal or lead 766 (S2), the terminals being electrically coupled to conductive leads of the completed electronic device 700 after packaging, in one example. In the illustrated example, the first drain 761, D1, extends partially into the heteroepitaxy structures 720, 721, and the first gate 762, G1, extends over the heteroepitaxy structures 720, 721 and is laterally spaced apart from the first drain 761, D1 along the first direction X. The first source 763, S1 extends partially into the heteroepitaxy structures 720, 721 and is laterally spaced apart from the first gate 762, G1 along the first direction X. The second drain 764, D2 extends partially into the heteroepitaxy structures 720, 721 and is coupled to the first source 763, S1 by a conductive wiring feature 751 in FIG. 7 to form a switching node SW. The second gate 765, G2 extends onto the heteroepitaxy structures 720, 721 and is laterally spaced apart from the second drain 764, D2 along the first direction X. The second source 766, S2 extends partially into the heteroepitaxy structures 720, 721 and is laterally spaced apart from the second gate 765 (G2) along the first direction X.

[0130] The hole injector structure 726, in this example, is between and laterally spaced apart from the first gate 762 (G1) and the first source 763 (S1) along the first direction X. Furthermore, the metallization structure in this example electrically couples the hole injector structure 726 to the first gate 762 (G1). In operation, when the first transistor 701 is turned on, the hole injector structure 726 operates to inject holes downward into the GaN layer 718. In another implementation, the conductive structure 725 of the hole injector structure 726 is coupled to a control voltage node (not shown) to selectively provide a positive voltage signal to the hole injector structure 726, for example, when the first gate 762 (G1) is powered to turn on the first transistor 701. The first and second transistors 701 and 702 in this example are depletion-mode transistors, and the first and second gates 762 and 765 (G1 and G2) include respective gate contact structures 734 and 738 that extend over and contact the AlGaN layer 721 of the heteroepitaxy structures 720, 721. In this example, the conductive structure 725 of the hole injector structure 726 is coupled to the first gate 762 (G1). The metallization structure includes a conductive routing feature 751 that electrically couples the first source 763 (S1) to the second drain 764 (D2). In operation, when the first transistor 701 is turned on and the first drain D1 is at a high voltage relative to the substrate 704 and the first gate 762, G1, which is higher than the threshold voltage of the first transistor 701, electrons are formed in the channel region at and near the top surface of the gallium nitride layer 718, as shown at 770 in FIG. 7. A voltage on the conductive structure 725 of the hole injector structure 726 causes injection of holes from the p-doped gallium nitride structure 724. The injected holes form a hole layer, shown at 772 in FIG. 7, in the buffer at or near the bottom side of the gallium nitride layer 718 adjacent the interface 715 of the back barrier layer 716 to mitigate the vertical field back gate effect for the first transistor 701.

[0131] 8 shows a partial cross-sectional side elevation view of an electronic device 800 comprising first and second enhancement-mode gallium nitride transistors 801 and 802 with an aluminum gallium nitride back barrier layer between the buffer structure and the gallium nitride layer, and a hole injector structure laterally spaced between and overlying the gate and source contacts of the first transistor. The electronic device 800 includes a stack of epitaxially grown layers, including a buffer stack, formed on a semiconductor substrate 804. Individual layers of the stack structure are described herein as aluminum nitride, aluminum gallium nitride, gallium nitride, etc., and the individual layers may be of any suitable stoichiometry, being or including the specified constituent materials, alone or with the additional presence of small amounts of impurities, artifacts, or other materials, such as materials that may remain after individual processing steps associated with semiconductor product manufacturers. The exemplary stack includes an aluminum nitride layer 806 on the substrate 804. In one example, aluminum nitride layer 806 extends directly onto and contacts the upper or top side of substrate 804. In another example, other materials, such as impurities or artifacts or residual materials from processing, may be present between aluminum nitride layer 806 and substrate 804. In one example, aluminum nitride layer 806 has a thickness of 300-600 nm.

[0132] A multi-layer, compositionally-graded aluminum gallium nitride buffer stack 808 extends over the aluminum nitride layer 806. The buffer stack 808 includes, in this example, three layers that are or include aluminum gallium nitride. In other examples, a different number of two or more compositionally-graded aluminum gallium nitride buffer stack layers can be used. In different examples, different buffer stack configurations can be used, such as a single or dual superlattice buffer structure (not shown). In the example of FIG. 8 , the buffer stack 808 includes a first aluminum gallium nitride layer 811 over the aluminum nitride layer 806. In one example, the first aluminum gallium nitride 811 extends directly over and contacts the upper or top side of the aluminum nitride 806. In another example, other materials, such as impurities or artifacts or residual materials from the manufacturing process, can be present between the first aluminum gallium nitride layer 811 and the aluminum nitride layer 806. The compositionally-graded AlGaN buffer stack 808 also includes a second aluminum gallium nitride layer 812 over the first aluminum gallium nitride layer 811. In one example, the second aluminum gallium nitride layer 812 extends directly onto and contacts the upper or top side of the first aluminum gallium nitride layer 811. In another example, other materials, such as impurities or artifacts or residual materials from the manufacturing process, may be present between the second aluminum gallium nitride layer 812 and the first aluminum gallium nitride layer 811. The third aluminum gallium nitride layer 813 extends over the second aluminum gallium nitride layer 812. In one example, the third aluminum gallium nitride layer 813 extends directly onto and contacts the upper or top side of the second aluminum gallium nitride layer 812. In another example, other materials, such as impurities or artifacts or residual materials from the manufacturing process, may be present between the third aluminum gallium nitride layer 813 and the second aluminum gallium nitride layer 812.

[0133] In one example, the multi-layer compositionally graded aluminum gallium nitride stack 808 includes a first aluminum gallium nitride sublayer 811 having a first aluminum concentration over the aluminum nitride layer 806, a second aluminum gallium nitride sublayer 812 having a second aluminum concentration over the first aluminum gallium nitride sublayer 811 that is less than the first aluminum concentration, and a third aluminum gallium nitride sublayer 813 having a third aluminum concentration over the second aluminum gallium nitride sublayer 812 that is less than the second aluminum concentration. In one example, the first aluminum concentration is 60-70%, the second aluminum concentration is 40-50%, and the third aluminum concentration is 20-30%. In one example, the first aluminum gallium nitride layer 811 has a thickness of 300 to 600 nm, the second aluminum gallium nitride layer 812 has a thickness of 1.4 to 1.8 μm, and the third aluminum gallium nitride layer 811 has a thickness of 1.4 to 2.0 μm.

[0134] Electronic device 800 further includes a gallium nitride layer 814 over multilayer compositionally graded aluminum gallium nitride stack 808. In one example, gallium nitride layer 814 has a thickness of 0.5-2.0 μm. In this or another example, gallium nitride layer 814 has a thickness of 0.1-1.0 μm. In one implementation, gallium nitride layer 814 includes carbon. In one example, gallium nitride layer 814 extends directly onto and contacts the upper or top side of third aluminum gallium nitride layer 813. In another example, other materials, such as impurities or artifacts or residual materials from manufacturing processes, may be present between gallium nitride layer 814 and third aluminum gallium nitride layer 813.

[0135] The electronic device 800 also includes a back barrier layer 816 over the buffer structure. The back barrier layer 816, in one example, is or includes aluminum gallium nitride of any suitable stoichiometry. In one example, the back barrier layer 816 extends directly onto and contacts the upper or top side of the gallium nitride layer 814 at an interface 815 between the top side of the gallium nitride layer 814 and the bottom side of the back barrier layer 816. In another example, other materials, such as impurities, artifacts, or residual materials from manufacturing processes, may be present between the back barrier layer 816 and the gallium nitride layer 814. The back barrier layer 816 has a thickness 817 of tens of nanometers to several micrometers, such as 20 nm to 5 μm. In another example, the back barrier layer 816 is or includes aluminum nitride, indium aluminum nitride, or indium aluminum gallium nitride of any suitable stoichiometry.

[0136] An upper gallium nitride layer 818 extends over the back barrier layer 816. Layer 818 is or includes gallium nitride of any suitable stoichiometry. In one example, gallium nitride layer 818 has a thickness 819 of 0.1 to 1.0 μm. In one implementation, gallium nitride layer 818 includes carbon. In one example, gallium nitride layer 818 extends directly over and contacts the upper or top side of back barrier layer 816. In another example, other materials, such as impurities or artifacts or residual materials from manufacturing processes, may be present between gallium nitride layer 818 and back barrier layer 816.

[0137] Electronic device 800 also includes a heteroepitaxy structure having an aluminum nitride layer 820 on gallium nitride layer 818 and an aluminum gallium nitride layer 821 on aluminum nitride layer 820. In one example, layer 820 is or includes aluminum nitride of any suitable stoichiometry. In one example, aluminum nitride layer 820 extends directly onto and contacts the upper or top side of gallium nitride layer 818. In another example, other materials, such as impurities or artifacts or residual materials from manufacturing processes, may be present between aluminum nitride layer 820 and gallium nitride layer 818. In this or another example, layer 821 is or includes aluminum gallium nitride of any suitable stoichiometry. In one example, aluminum gallium nitride layer 821 extends directly onto and contacts the upper or top side of aluminum nitride layer 820. In another example, other materials, such as impurities or artifacts or residual material from the manufacturing process, may be present between aluminum gallium nitride layer 821 and aluminum nitride layer 820. A heterojunction at the interface between aluminum gallium nitride layer 821 and aluminum nitride layer 820 forms a two-dimensional electron gas region 822. In one example, the heteroepitaxy structure including layers 820 and 821 has a total thickness 823 of 10 to 30 nm. Electronic device 800 also includes one or more transistors, which in the illustrated implementation include a depletion-mode high-side first transistor 801 and a depletion-mode low-side second transistor 802.

[0138] The various buffer layers and layers of the heteroepitaxy structure are fabricated, in one example, to a total thickness of about 5.1 μm using an epitaxial growth deposition process, e.g., a continuous epitaxial deposition process in which the variables and materials forming the constituent layers are varied throughout, and / or two or more sequential epitaxial deposition processes. In depletion-mode transistor 801, the heteroepitaxy structure including layers 820 and 821 has a total thickness of about 10-30 nm, and in enhancement-mode transistor 802, the heteroepitaxy structure has a total thickness of about 10-20 nm. In one example, aluminum nitride layer 820 has a thickness of about 10 Å (1 nm), and aluminum gallium nitride layer 821 has a thickness of about 20 nm. In the illustrated example, gallium nitride layer 818 has a thickness of about 0.1-1.0 μm. In one example, aluminum gallium nitride layer 821 has an aluminum concentration of about 26%.

[0139] The electronic device 800 includes a hole injector structure 826 having a doped gallium nitride structure 824 on an aluminum gallium nitride layer 821. The hole injector structure 826 also includes a conductive structure 825 formed as a contact or via that partially overlies and contacts the doped gallium nitride structure 824. In one example, the doped gallium nitride structure 824 is or includes gallium nitride of any suitable stoichiometry doped with p-type impurities (e.g., p-GaN, including magnesium or other p-type impurities). In one example, the doped gallium nitride structure 824 extends directly onto and contacts the upper or top side of the aluminum gallium nitride layer 821. In another example, other materials, such as impurities or artifacts or residual materials from the manufacturing process, may be present between the doped gallium nitride structure 824 and the aluminum gallium nitride layer 821. In one example, p-doped gallium nitride layer 824 includes a magnesium dopant and has a thickness of 50-200 nm, such as about 70 nm in one implementation. Conductive structure 825 is or includes tungsten, copper, aluminum, or another conductive metal. Electronic device 800 further includes insulating structure 828, such as silicon dioxide of any suitable stoichiometry, between transistors 801 and 802, extending down through aluminum gallium nitride layer 821, aluminum nitride layer 820, gallium nitride layer 818, and back barrier layer 816 and partially into gallium nitride layer 814. In this or another example, isolation between transistors 801 and 802 is achieved by implantation (not shown).

[0140] Electronic device 800 also includes a metallization structure comprising a first pre-metal dielectric (e.g., PMD) layer 830, comprising, for example, silicon nitride or silicon dioxide, in which various conductive metal structures, including conductive structure 825, are formed. In one example, conductive structure 825 extends directly over and contacts at least a portion of the upper or top side of doped gallium nitride structure 824. In another example, other materials, such as impurities or artifacts or residual material from the manufacturing process, may be present between conductive structure 825 and doped gallium nitride structure 824.

[0141] The PMD layer or level also includes a first drain contact or electrode 831 of the first transistor 801, a first source contact or electrode 832 of the first transistor 801, and a first gate contact or electrode 834 of the first transistor 801. The PMD layer or level further includes a second drain contact or electrode 835 of the second transistor 802, a second source contact or electrode 836 of the second transistor 802, and a second gate contact or electrode 838 of the second transistor 802, as well as one or more conductive contacts or vias 839 that extend through the PMD layer 830 and provide electrical interconnection of the various transistor terminals for routing in a second metallization structure level. Conductive drain and source contacts 831, 835, 832, 836 of the respective first and second transistors 801 and 802 extend partially into the heteroepitaxy structures 820, 821, and conductive gate contacts 834 and 838 of the respective first and second transistors 801 and 802 extend onto and contact the heteroepitaxy structures 820, 821.

[0142] The electronic device 800 in FIG. 8 further includes a second metallization structure level comprising a dielectric layer 850 (e.g., silicon nitride or silicon dioxide) having one or more conductive routing features 851 (e.g., aluminum, copper, etc.), for providing, for example, routing of drain, source, and gate connections and associated signals to each other and / or to conductive bond pads or other externally exposed conductive features, so that the transistors 801 and 802 can be electrically interconnected with other circuit elements, for example, using bond wires or lead frame electrical connections to integrated circuit leads, such as pins or pads in a packaged electronic device.

[0143] In this example, the first transistor 801 has a first drain terminal or lead 861 (D1), a first gate terminal or lead 862 (G1), and a first source terminal or lead 863 (S1). The second transistor 802 has a second drain terminal or lead 864 (D2), a second gate terminal or lead 865 (G2), and a second source terminal or lead 866 (S2). 8, the first and second transistors 801 and 802 are enhancement-mode transistors, and the first and second gates 862 and 865 (G1 and G2) include respective gate contact structures 834 and 838 that extend onto and contact respective p-doped GaN structures 824 on the AlGaN layer 821 of the heteroepitaxy structures 820, 821.

[0144] In the illustrated example, a first drain 861, D1 extends partially into the heteroepitaxy structures 820, 821, and a first gate 862, G1 extends above the heteroepitaxy structures 820, 821 onto and in contact with a respective p-doped GaN structure 824 and is laterally spaced apart from the first drain 861, D1 along a first direction (e.g., the "X" direction in the figure). A first source 863, S1 extends partially into the heteroepitaxy structures 820, 821 and is laterally spaced apart from the first gate 862, G1 along the first direction X. A second drain 864, D2 extends partially into the heteroepitaxy structures 820, 821 and is coupled to the first source 863, S1 by a conductive routing feature 851 in FIG. 8 to form a switching node SW. A second gate 865, G2 extends on and contacts the respective p-doped GaN structure 824 on the heteroepitaxy structures 820, 821 and is laterally spaced apart from the second drain 864, D2 along the first direction X. A second source 866, S2 extends partially into the heteroepitaxy structures 820, 821 and is laterally spaced apart from the second gate 865, G2 along the first direction X.

[0145] The hole injector structure 826, in this example, is between and laterally spaced apart from the first gate 862 (G1) and the first source 863 (S1) along the first direction X. Furthermore, the metallization structure in this example electrically couples the hole injector structure 826 to the first gate 862 (G1). In operation, when the first transistor 801 is turned on, the hole injector structure 826 operates to inject holes downward into the GaN layer 818. In another implementation, the conductive structure 825 of the hole injector structure 826 is coupled to a control voltage node (not shown) to selectively provide a positive voltage signal to the hole injector structure 826, for example, when the first gate 862 (G1) is powered to turn on the first transistor 801. The first and second transistors 801 and 802 in this example are depletion-mode transistors, and the first and second gates 862 and 865 (G1 and G2) include respective gate contact structures 834 and 838 that extend over and contact the AlGaN layer 821 of the heteroepitaxy structures 820, 821. In this example, the conductive structure 825 of the hole injector structure 826 is coupled to the first gate 862 (G1). The metallization structure includes a conductive routing feature 851 that electrically couples the first source 863 (S1) to the second drain 864 (D2). In operation, when the first transistor 801 is turned on and the first drain D1 is at a high voltage relative to the substrate 804 and the first gate 862, G1, is at a voltage higher than the threshold voltage of the first transistor 801, and electrons are formed at and near the top side of the gallium nitride layer 818, as shown at 870 in FIG. 8. A voltage on the conductive structure 825 of the hole injector structure 826 causes the injection of holes from the p-doped gallium nitride structure 824. The injected holes create a vertical field backfill for the first transistor 801. To mitigate the gate effect, a hole layer is formed in the buffer at or near the bottom side of the gallium nitride layer 818 adjacent to the interface 815 of the back barrier layer 816, shown at 872 in FIG.

[0146] 9-21, FIG. 9 illustrates an exemplary method 900 for making an electronic device according to a further embodiment, FIGS. 10-20 illustrate partial side views of the electronic device 100 of FIG. 1 undergoing manufacturing processing according to method 900, and FIG. 21 illustrates a perspective view of the completed packaged electronic device 100. Method 900 begins with a starting substrate, such as a silicon wafer, an SOI wafer, or the like. Similar processes can be used to fabricate one or more of the example electronic devices 200, 300, 400, 500, 600, 700, and 800 described above.

[0147] At 901, one or more epitaxial deposition processes are performed, including forming AlN layer 106, buffer structure 108, and layers 114, 116, and 118 in FIG. 1. At 902, an aluminum nitride layer is formed on the substrate. FIG. 10 shows an example of using an epitaxial deposition process 1000 to deposit aluminum nitride layer 106 on the upper surface of silicon substrate 104 in the electronic device 100 described above. In one example, process 1000 includes depositing aluminum nitride to a thickness of 300-600 nm at a temperature of 1000-1150° C.

[0148] The method 900 continues with buffer formation at 903, which includes forming a multi-layer, compositionally-graded aluminum gallium nitride stack 108 on the aluminum nitride layer 106. The multi-layer, compositionally-graded aluminum gallium nitride stack formation at 903, in one example, includes performing a first epitaxial deposition process at 904 to form a first aluminum gallium nitride sub-layer on the aluminum nitride layer 106. FIG. 11 illustrates one example in which an epitaxial deposition process 1100 is performed to deposit a first aluminum gallium nitride sub-layer 111 on the aluminum nitride layer 106. In one example, the process 1100 deposits the first aluminum gallium nitride sub-layer 111 to a thickness of 300-600 nm at a process temperature of 900-1100° C. and has an aluminum content of 60-70%. Also, in one example, the process 1100 deposits the first aluminum gallium nitride sub-layer 111 to a thickness of 300-600 nm at a concentration of 1E17-1E18 atoms / cm using ethane, hexane, or other exogenous carbon source gas. 3 A first aluminum gallium nitride sub-layer 111 having a carbon concentration of

[0149] The method 900 continues at 906 by performing a second epitaxial deposition process to form a second aluminum gallium nitride sublayer 112 on the first aluminum gallium nitride sublayer 111. Figure 12 shows an example in which a second epitaxial deposition process 1200 is performed to deposit the second aluminum gallium nitride sublayer 112 having an aluminum content of 40-50% to a thickness of 1.4-1.8 μm using a process temperature of 900-1100°C. In one implementation, the process 1200 is performed using ethane, hexane, or other extrinsic carbon source gas at a concentration of 1E17-1E19 atoms / cm. 3 A second aluminum gallium nitride sub-layer 112 having a carbon concentration of

[0150] The method 900 continues at 908 by performing a third epitaxial deposition process to form a third aluminum gallium nitride sublayer 113 on the second aluminum gallium nitride sublayer 112. Figure 13 shows an example in which a third epitaxial deposition process 1300 is performed to deposit the third aluminum gallium nitride sublayer 113 having an aluminum content of 20-30% to a thickness of 1.4-2.0 μm using a process temperature of 1000-1100°C. Also, in one implementation, the process 1300 is performed using ethane, hexane, or other extrinsic carbon source gas at a concentration of 1E17-1E19 atoms / cm. 3 A third aluminum gallium nitride sub-layer 113 having a carbon concentration of

[0151] The method 900 continues at 910 by performing an epitaxial deposition process to deposit a gallium nitride layer using an extrinsic carbon source gas. Figure 14 shows an example in which an epitaxial deposition process 1400 is performed to deposit a gallium nitride layer 114 on the top side of the third gallium nitride sublayer 113 of the multilayer compositionally graded aluminum gallium nitride stack 108. In one example, the process 1400 deposits the carbon-doped gallium nitride layer 114 to a thickness of 0.5-1.0 μm using hexane, or other extrinsic carbon gas, at a process temperature of 900-1050°C, with a concentration of 1E18-1E20 atoms / cm. 3 The gallium nitride layer 114 has a carbon concentration of

[0152] The method 900 continues at 911 by forming an aluminum gallium nitride back barrier layer 116 on the buffer structures 106, 108, 114. In another example, processing at 911 forms an aluminum gallium nitride, aluminum nitride, indium aluminum nitride, or indium aluminum gallium nitride back barrier layer 1169 on the buffer structure. Figure 15 shows an example in which an epitaxial deposition process 1500 is performed to deposit the aluminum gallium nitride back barrier layer 116 on top of the gallium nitride layer 114 to a thickness 117 of tens of nanometers to several micrometers, for example, 20 nm to 5 micrometers.

[0153] The method 900 continues at 912 in Figure 9 by forming a gallium nitride layer 118 on (e.g., directly on) the top side of the back barrier layer 116. Figure 16 shows a gallium nitride layer 118 having a density of 1E15 to 1E17 atoms / cm 3 16 shows an example in which an epitaxial deposition process 1600 is performed to deposit a gallium nitride layer 118 on a back barrier layer 116 to a thickness 119 of 0.1 to 1.0 μm at a process temperature of 950 to 1050° C. using intrinsic carbon doping.

[0154] The method 900 continues at 914 with forming heteroepitaxy structures 120, 121 on the gallium nitride layer 118. One example includes forming an aluminum nitride layer 120 at 916 on the top side of the gallium nitride layer 118 using a process 1700, as shown in FIG. 17. In one example, the process 1700 deposits the aluminum nitride layer 120 to a thickness of approximately 10 Å (1 nm) at a process temperature of 900-1100° C. At 918, an aluminum gallium nitride layer 121 is formed on the aluminum nitride layer 120 using an epitaxial deposition process 1800, as shown in FIG. 18. In one example, the process 1800 forms the aluminum gallium nitride layer 121 to a thickness of 10-30 nm at a process temperature of 900-1100° C. The heteroepitaxy structures 120, 121 have a thickness 123, in one example, of 10-30 nm.

[0155] 9 further includes forming and patterning, at 920, a p-doped gallium nitride layer 124 on the aluminum gallium nitride layer 121 of the heteroepitaxy structures 120, 121 for the hole injector structure 126, and optionally a separate p-doped gallium nitride patterned structure for one or more gates of any included enhancement-mode transistors (e.g., FIGS. 2, 4, 6, and 8 above). Figure 19 shows an example in which a process 1900 is performed to form a p-doped gallium nitride layer 124 on a portion of the aluminum gallium nitride layer 121 for the gate of the enhancement-mode transistor 102. Process 1900 can include depositing a doped gallium nitride layer over the top of the wafer, followed by forming and patterning an etch mask over the future p-doped gallium nitride structure or structures 124 for the hole injector structure 126 and any desired enhancement mode transistor gate region of the wafer, and etching the exposed gallium nitride material to leave the patterned p-doped gallium nitride structure 124, as shown in FIG.

[0156] The method 900 further includes forming gate, drain, and source, and other conductive structures (e.g., 125, 131, 132, 134, 135, 136, and 138 in FIG. 1 above, as well as metallization and other back-end processing at 922). FIG. 20 illustrates an example having a metallization process 2000 for forming the metallization configuration described above in connection with FIG. 1. In one example, forming the conductive structures at 922 includes forming 924 a metallization structure that electrically couples the conductive structure 125 of the hole injector structure 126 to the conductive gate contact 134 of the first transistor 101. In this example or another example, processing at 922 includes forming a metallization structure that electrically couples the conductive source contact 132 of the first transistor 101 to the conductive drain contact 135 of the second transistor 102. In these or other examples, processing at 922 includes forming conductive structure 125 of hole injector structure 126 connected to conductive drain contact 131 of first transistor 101. Process 900 further includes packaging at 926, including, for example, singulating or separating individual die portions of the processed wafer and packaging the individual die using any suitable packaging structure, such as a lead frame, a molded structure, system-on-module packaging, chip-on-die packaging, a substrate with conductive features, or a combination thereof, thereby providing a finished electronic device, such as an integrated circuit, including transistors 101 and / or 102, alone or with other circuitry (not shown). Method 900 also includes final device testing at 928. FIG. 21 shows a perspective view of a finished packaged electronic device 100 having a molded package structure 2100 enclosing the semiconductor die and portions of conductive leads 161-166 for electrical connection to terminals of exemplary first and second transistors 101 and 102.

[0157] The described example provides a solution for monolithic integration of high-side and low-side FETs to promote the benefits of GaN FETs by addressing the back-gate effect, mitigating RDSON, increasing switching frequency with minimal parasitic inductance, and reducing overall area, especially for high-side switches in high-voltage applications. The hole injector structure and back buffer layer provide hole injection (e.g., using a p-GaN gate or a structure for providing a p-GaN diode) to form a hole layer within the buffer, which shields the vertical E field effect (no back-gate effect). The described structure and techniques facilitate monolithic integration of high-side and low-side GaN FETs without substrate isolation, and the hole injection and AlGaN or other back barrier enable the formation of a hole layer within the buffer, which shields the back-gate effect. An isolation structure (e.g., 128 in Figure 1 above) insulates the hole layer between the high-side and low-side FETs. In implementations with hole injection in the AlGaN back-barrier buffer epilayer, substrate bias effects are largely or completely shielded, and channel conductivity (e.g., high-side RDS ON) is unaffected by vertical E down to -500V. This solution provides a cost-effective monolithic approach that avoids the increased process complexity and manufacturing costs associated with substrate isolation using silicon-on-insulator (SOI) wafers and deep trench isolation (DTI). The described example also avoids the junction temperature effects of the SOI / DTI approach caused by the low thermal conductivity in the buried oxide. In this regard, the described example does not require special substrates or deep trench isolation, and back-gate effects can be controlled or eliminated without any penalty in thermal performance.

[0158] The foregoing examples are merely illustrative of some of the possible implementations of various aspects of the present disclosure, and equivalent variations and / or modifications will occur to others skilled in the art upon reading and understanding this specification and the accompanying drawings. Modifications may be made to the described examples, and other implementations are possible, within the scope of the claims of the present invention.

Claims

1. An integrated circuit, a buffer structure on the substrate; a first III-N layer over the buffer structure, the first III-N layer comprising aluminum; and a gallium nitride layer on the first III-N layer; and a second III-N layer on the gallium nitride layer, the second III-N layer comprising aluminum; and a first drain contact, a first gate contact, and a first source contact for a first transistor spaced along the second III-N layer; a gallium nitride structure on the second III-N layer; and a terminal connected to the gallium nitride structure, the terminal configured to provide an electrical potential to the gallium nitride structure that causes a hole layer to form at an interface between the first III-N layer and the gallium nitride layer; , an integrated circuit.

2. The integrated circuit of claim 1, a second drain contact, a second gate contact, and a second source contact for a second transistor spaced along the second III-N layer; an isolation structure extending through the first III-N layer between the first and second transistors; The integrated circuit further comprises:

3. The integrated circuit of claim 2, the integrated circuit further comprising a conductive connection from the first source contact to the second drain contact.

4. The integrated circuit of claim 1, the first transistor is a depletion mode transistor and the first gate contact is directly on the second III-N layer.

5. The integrated circuit of claim 1, a doped gallium nitride layer between the first gate contact and the second III-N layer; The integrated circuit wherein the first transistor is an enhancement mode transistor.

6. The integrated circuit of claim 1, the terminal is electrically connected to the first drain contact.

7. The integrated circuit of claim 1, the gallium nitride structure contacts the first drain contact.

8. The integrated circuit of claim 1, the first drain contact is spaced from and between the gallium nitride structure and the first gate contact.

9. The integrated circuit of claim 8, the gallium nitride structure is electrically connected to the first gate contact.

10. The integrated circuit of claim 1, the gallium nitride structure is spaced from and between the first drain contact and the first gate contact.

11. The integrated circuit of claim 10, the gallium nitride structure is electrically connected to the first gate contact.

12. The integrated circuit of claim 1, the gallium nitride structure is spaced from the first gate contact and the first source contact and between the first gate contact and the second source contact.

13. The integrated circuit of claim 12, the gallium nitride structure is electrically connected to the first gate contact.

14. The integrated circuit of claim 1, the gallium nitride structure is electrically connected to the first gate contact.

15. An electronic device comprising: a semiconductor die in a device package including a switching circuit formed thereon, said switching circuit comprising: a heterojunction first transistor, a first semiconductor layer comprising one of aluminum gallium nitride, aluminum nitride, indium aluminum nitride, and indium aluminum gallium nitride; a second semiconductor layer comprising gallium nitride on the first semiconductor layer; a third semiconductor layer including an aluminum-nitrogen layer on the second semiconductor layer; a first source terminal, a first drain terminal, and a first gate terminal on the third semiconductor layer; a gallium nitride layer on the third semiconductor layer; and the first transistor including a second transistor including a second drain terminal, a second gate terminal, and a second source terminal spaced apart along the third semiconductor layer; a conductive connection between the first source terminal and the second drain terminal; , an electronic device.

16. The electronic device of claim 15, An electronic device, wherein the gallium nitride layer is configured to receive an electric potential that causes a hole layer to form at the interface between the first and second semiconductor layers.

17. A method for fabricating an electronic device, comprising: forming a first heterojunction transistor on a semiconductor substrate, the first transistor comprising: a first semiconductor layer over a semiconductor substrate, the first semiconductor layer comprising aluminum gallium nitride, aluminum nitride, indium aluminum nitride, or indium aluminum gallium nitride; a second semiconductor layer comprising gallium nitride on the first semiconductor layer; a third semiconductor layer containing aluminum and nitrogen on the second semiconductor layer; a first source terminal, a first drain terminal, and a first gate terminal on the third semiconductor layer; forming the first transistor, forming a second transistor on the semiconductor substrate, the second transistor including a second drain terminal, a second gate terminal, and a second source terminal spaced apart along the third semiconductor layer; forming a gallium nitride structure on the third semiconductor layer; connecting an electrode to the gallium nitride structure; electrically connecting the first source terminal to the second drain terminal; A method comprising:

18. An electronic device comprising: a semiconductor die within a device package including a switching circuit formed thereon, said switching circuit comprising: A heterojunction transistor, a first semiconductor layer comprising one of aluminum gallium nitride, aluminum nitride, indium aluminum nitride, and indium aluminum gallium nitride; a second semiconductor layer comprising gallium nitride on the first semiconductor layer; a third semiconductor layer including an aluminum-nitrogen layer on the first semiconductor layer; a source terminal, a drain terminal, and a gate terminal on the third semiconductor layer; a gallium nitride layer on the third semiconductor layer, the gallium nitride layer configured to receive an electric potential that forms a hole layer at an interface between the first and second semiconductor layers; and 10. An electronic device comprising: the semiconductor die comprising the heterojunction transistor, 19. An integrated circuit comprising: a buffer structure on the substrate; a first III-N layer over the buffer structure, the first III-N layer comprising aluminum; and a gallium nitride layer on the first III-N layer; and a second III-N layer on the gallium nitride layer, the second III-N layer comprising aluminum; and a first drain contact, a first gate contact, and a first source contact for a first transistor spaced along the second III-N layer; a second drain contact, a second gate contact, and a second source contact for a second transistor spaced along the second III-N layer; an isolation structure extending through the first III-N layer between the first and second transistors; a gallium nitride structure on the second III-N layer; and a terminal connected to the gallium nitride structure; a conductive connection from the first source contact to the second drain contact; , an integrated circuit.

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