Photoelectric conversion device and photoelectric conversion system

Abstract

To provide a photoelectric conversion device and a photoelectric conversion system that reduce the influence of light incident on a peripheral area.SOLUTION: A photoelectric conversion device includes a pixel array area 12E and a peripheral area 13 on the periphery of the pixel array area. Each pixel 101 in the pixel array area includes a first semiconductor area 311 of a first conductivity type arranged on the side of a first surface S1, and a second semiconductor area 315 of a second conductivity type arranged on the side of a second surface S2. Predetermined voltage that causes an avalanche doubling operation is supplied between the first semiconductor area and the second semiconductor area. The peripheral area includes a third semiconductor area 1311 of the first conductivity type arranged on the first surface side, a fourth semiconductor area 1315 of the second conductivity type arranged separate from the third semiconductor area, and a fifth semiconductor area 1313 of the first conductivity type. The concentration of impurities of the first conductivity type in the fifth semiconductor area is lower than the concentration of impurities of the first conductivity type in the third semiconductor area, and voltage is supplied between the third semiconductor area and the fourth semiconductor area.SELECTED DRAWING: Figure 11

Description

Technical field

[0001] The present invention relates to a photoelectric conversion device and a photoelectric conversion system. [Background technology]

[0002] Patent Document 1 describes an APD (avalanche photodiode) intended to reduce crosstalk from pixels and suppress DCR (dark count rate). The APD includes a high electric field region, an isolation region for separating adjacent pixels, and a hole accumulation region for trapping electrons on sidewalls of the isolation region, and the hole accumulation region is electrically connected to the anode. configuration. [Prior art documents] [Patent document]

[0003] [Patent document 1] Japanese Patent Application Laid-Open No. 2018-201005 [Outline of the invention] [Problems to be solved by the invention]

[0004] A semiconductor substrate of a photoelectric conversion device can have a pixel array region and a peripheral region arranged around the pixel array region. When light is unintentionally incident on the peripheral area, photoelectric conversion generates charges (electrons and holes) that can enter the pixels of the pixel array. Alternatively, when charges generated by photoelectric conversion recombine to produce light, this can be detected by pixels of the pixel array, eg, light-shielded pixels (OB pixels).

[0005] SUMMARY OF THE INVENTION An object of the present invention is to provide an advantageous technique for reducing the influence of light incident on the peripheral area of ​​a photoelectric conversion device. [Means for solving the problem]

[0006] One aspect of the present invention relates to a photoelectric conversion device having a semiconductor layer including a pixel array region having a plurality of pixels and a peripheral region arranged around the pixel array region, wherein the semiconductor layer comprises a first Each pixel in the pixel array region includes a first conductivity type first semiconductor region arranged on the first surface side and a second semiconductor region arranged on the second surface side. a two-conductivity-type second semiconductor region, wherein a predetermined voltage capable of causing an avalanche doubling operation is supplied between the first semiconductor region and the second semiconductor region, and the peripheral region comprises the first surface; the third semiconductor region of the first conductivity type arranged on the side of the second conductivity type; the fourth semiconductor region of the second conductivity type arranged apart from the third semiconductor region; and a fifth semiconductor region of the first conductivity type disposed adjacent to the third semiconductor region between the fourth semiconductor region and the impurity concentration of the first conductivity type in the fifth semiconductor region is , a voltage lower than the impurity concentration of the first conductivity type in the third semiconductor region, and a voltage is supplied between the third semiconductor region and the fourth semiconductor region.

Effect of the invention

[0007] According to the present invention, an advantageous technique is provided for reducing the influence of light incident on the peripheral region of the photoelectric conversion device. [Brief description of the drawing]

[0008]

Figure 1

Figure 2

[0009] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. In addition, the following embodiments do not limit the invention according to the scope of claims. Although multiple features are described in the embodiments, not all of these multiple features are essential to the invention, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same or similar configurations are denoted by the same reference numerals, and redundant description is omitted.

[0010] BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail based on the drawings. In the following description, terms indicating specific directions and positions (for example, "upper", "lower", "right", "left", and other terms including those terms) are used as necessary. . These terms are used to facilitate understanding of the embodiments with reference to the drawings, and the technical scope of the present invention is not limited by the meanings of these terms.

[0011] In this specification, "planar view" means viewing from a direction perpendicular to the light incident surface of the semiconductor layer. A cross-sectional view refers to a plane in a direction perpendicular to the light incident surface of the semiconductor layer. When the light incident surface of the semiconductor layer is microscopically rough, the plane view is defined based on the light incident surface of the semiconductor layer macroscopically.

[0012] In the following description, the anode of the avalanche photodiode (APD) is set at a fixed potential and the signal is extracted from the cathode side. Therefore, a semiconductor region of the first conductivity type in which majority carriers are the same polarity as the signal charges is an N-type semiconductor region, and a semiconductor region of the second conductivity type in which majority carriers are charges of a different polarity from the signal charges. is the P-type semiconductor region. The present invention can also be applied when the cathode of the APD is set at a fixed potential and the signal is extracted from the anode side. In this case, the semiconductor region of the first conductivity type having majority carriers of charges of the same polarity as the signal charges is a P-type semiconductor region, and the semiconductor region of the second conductivity type having majority carriers of charges having a polarity different from that of the signal charges. is the N-type semiconductor region. A case where one node of the APD is set to a fixed potential will be described below, but the potentials of both nodes may fluctuate.

[0013] In this specification, when the term "impurity concentration" is simply used, it means the net impurity concentration after subtracting the amount compensated by the impurity of the opposite conductivity type. In other words, "impurity concentration" refers to NET doping concentration. A region in which the P-type impurity concentration is higher than the N-type impurity concentration is a P-type semiconductor region. On the contrary, a region where the N-type impurity concentration is higher than the P-type impurity concentration is an N-type semiconductor region.

[0014] First, the basic configuration and driving method common to photoelectric conversion devices and driving methods thereof according to a plurality of embodiments to be described later will be described with reference to FIGS.

[0015] FIG. 1 is a diagram showing the basic configuration of a photoelectric conversion device 100 of an embodiment. Here, an example in which the photoelectric conversion device 100 is configured as a stacked photoelectric conversion device will be described, but the present invention is also applicable to photoelectric conversion devices other than the stacked photoelectric conversion device. The photoelectric conversion device 100 can be configured, for example, by stacking a plurality of substrates including a sensor substrate 301 and a circuit substrate 401 and electrically connecting the plurality of substrates. The sensor substrate 301 can have a first semiconductor layer having photoelectric conversion elements 102, which will be described later, and a first wiring structure. The circuit board 401 can have a second semiconductor layer having circuits such as the signal processing unit 103, which will be described later, and a second wiring structure. The photoelectric conversion device 100 can be configured by stacking, for example, a second semiconductor layer, a second wiring structure, a first wiring structure, and a first semiconductor layer in this order. The photoelectric conversion devices described in the following embodiments can be, for example, back-illuminated photoelectric conversion devices, but the photoelectric conversion devices according to the present invention may be configured as front-illumination photoelectric conversion devices.

[0016] The sensor substrate 301 and the circuit substrate 401 can each be chips diced from a wafer, but these substrates are not limited to chips. For example, each substrate may be a wafer. Further, the plurality of substrates may be laminated in a wafer state and then diced, or may be formed into chips and then laminated or bonded into a plurality of chips.

[0017] The sensor substrate 301 may include a semiconductor layer including a pixel array region 12 having a plurality of pixels and a peripheral region 13 arranged around the pixel array region 12 . The area between the outer edge of the pixel array area 12 and the outer edge of the sensor substrate 301 can be the peripheral area 13 . A circuit element such as an active element may be arranged in the peripheral region 13, or no circuit element such as an active element may be arranged. Circuit board 401 may include a semiconductor layer including circuit area 22 for processing signals detected by pixels of pixel array area 12 .

[0018] FIG. 2 is a diagram showing a configuration example of the sensor substrate 301. As shown in FIG. In the pixel array region 12, a plurality of pixels 101 can be arranged in a two-dimensional array so as to form a plurality of rows and a plurality of columns. Each pixel 101 can include a photoelectric conversion element 102 including an avalanche photodiode (APD).

[0019] The pixels 101 arranged in the pixel array region 12 can be pixels for forming an image. However, when the sensor substrate 11 or the photoelectric conversion device 100 is applied to TOF (Time of Flight), each pixel 101 may not necessarily be a pixel for forming an image. That is, the pixel 101 may be a pixel for measuring the time and amount of light that light reaches.

[0020] FIG. 3 is a diagram showing the configuration of the circuit board 401. As shown in FIG. The circuit board 401 includes, for example, a signal processing unit 103 that processes charges generated by photoelectric conversion in the photoelectric conversion element 102, a readout circuit 112, a control pulse generation unit 115, a horizontal scanning circuit unit 111, a signal line 113, a vertical scanning circuit. A portion 110 may be included. One signal processing unit 103 can be provided for one pixel 101 . The photoelectric conversion element 102 in FIG. 2 and the signal processing unit 103 in FIG. 3 can be electrically connected via connection wiring provided for each pixel 101 .

[0021] The vertical scanning circuit unit 110 can be configured, for example, to receive the first control pulse supplied from the control pulse generation unit 115, generate the second control pulse, and supply the second control pulse to each pixel 101. FIG. The vertical scanning circuit section 110 can include logic circuits such as shift registers and address decoders, for example. A signal output from the photoelectric conversion element 102 of the pixel 101 can be processed by the signal processing unit 103 provided corresponding to the pixel 101 . The signal processing unit 103 can include counters, memories, and the like, and the memories can hold digital values.

[0022] The horizontal scanning circuit unit 111 can be configured to supply the signal processing unit 103 with a third control pulse that sequentially selects each column in order to read the signal from the memory of each pixel 101 holding the digital signal. The circuit board 401 may have multiple signal lines 113 . Signals are output to the plurality of signal lines 113 from the signal processing units 103 assigned to the pixels 101 in the row selected by the vertical scanning circuit unit 110 . The signals output to the plurality of signal lines 113 can be output to a recording unit or signal processing unit outside the photoelectric conversion device 100 via the output circuit 114 .

[0023] In FIG. 2, the photoelectric conversion elements 102 or the pixels 101 in the pixel array region 12 may be arranged one-dimensionally. Each signal processing unit 103 may be assigned to at least two photoelectric conversion elements 102 or pixels 101 .

[0024] As shown in FIGS. 2 and 3, a plurality of signal processing units 103 can be arranged in a region overlapping the pixel array region 12 in plan view. Then, the vertical scanning circuit section 110, the horizontal scanning circuit section 111, the readout circuit 112, the output circuit 114, and the control pulse are arranged so as to overlap the area between the outer edge of the sensor substrate 11 and the outer edge of the pixel array area 12 in plan view. A generator 115 may be arranged. In other words, the vertical scanning circuit section 110, the horizontal scanning circuit section 111, the readout circuit 112, the output circuit 114, and the control pulse generation section 115 can be arranged in a region overlapping the peripheral region 13 of the sensor substrate 11 in plan view.

[0025] FIG. 4 illustrates an equivalent circuit of one pixel 101 in FIG. 2 and one signal processing unit 103 in FIG. The APD 201 generates charge pairs according to incident light through photoelectric conversion. A voltage VL (first voltage) is supplied to the anode of the APD 201 . Also, the cathode of the APD 201 can be supplied with a voltage VH (second voltage) higher than the voltage VL supplied to the anode. A reverse bias voltage (predetermined voltage) can be supplied between the anode and cathode that can cause the APD 201 to perform an avalanche multiplication operation. With such a reverse bias voltage applied between the anode and cathode, charges generated by incident light can cause avalanche multiplication and generate an avalanche current.

[0026] A mode in which the APD is operated with a voltage between the anode and cathode that is greater than the breakdown voltage is called the Geiger mode. A mode in which the APD operates with a voltage between the anode and cathode near or below the breakdown voltage is called a linear mode. APDs that operate in Geiger mode are called SPADs. For example, the voltage VL (first voltage) is -30V and the voltage VH (second voltage) is 1V. APD 201 may operate in linear mode or in Geiger mode.

[0027] Quenching element 202 may be arranged to connect APD 201 with a power supply providing voltage VH. The quench element 202 functions as a load circuit (quench circuit) during signal multiplication by the avalanche multiplication operation, suppresses the voltage supplied to the APD 201, and has a function of suppressing the avalanche multiplication (quench operation). Also, the quenching element 202 has a function of returning the voltage supplied to the APD 201 to the voltage VH by flowing the current corresponding to the voltage drop in the quenching operation (recharging operation).

[0028] The signal processing section 103 can include a waveform shaping section 210 , a counter circuit 211 and a selection circuit 212 . The signal processing section 103 may be a circuit including at least one of the waveform shaping section 210 , the counter circuit 211 and the selection circuit 212 . The waveform shaping unit 210 can shape the potential change of the cathode of the APD 201 obtained during photon detection and output a pulse signal. As the waveform shaping section 210, for example, an inverter circuit can be used. Although the waveform shaping section 210 is composed of one inverter in FIG. 4, the waveform shaping section 210 may include a series connection of a plurality of inverters, or may include other circuits that have a waveform shaping effect.

[0029] The counter circuit 211 can count the pulse signals output from the waveform shaping section 210 and hold the count value. Also, the counter circuit 211 can be configured to reset the signal held in the counter circuit 211 by being supplied with the control pulse pRES via the drive line 213 . A control pulse pSEL is supplied from the vertical scanning circuit unit 110 in FIG. 3 to the selection circuit 212 via the drive line 214 in FIG. connection or non-connection. Selection circuit 212 may include, for example, a buffer circuit for outputting a signal.

[0030] A switch such as a transistor may be provided between the quench element 202 and the APD 201 and / or between the photoelectric conversion element 102 and the signal processing section 103 to control electrical connection. Similarly, the supply of voltage VH and / or voltage VL to photoelectric conversion element 102 may be controlled by a switch such as a transistor.

[0031] The photoelectric conversion device 100 may be configured to acquire pulse detection timing using a time to digital converter (hereinafter referred to as TDC) and memory instead of the counter circuit 211. FIG. The generation timing of the pulse signal output from the waveform shaping section 210 can be converted into a digital signal by the TDC. A control pulse pREF (reference signal) can be supplied to the TDC from the vertical scanning circuit unit 110 in FIG. 1 via a drive line for measuring the timing of the pulse signal. The TDC can acquire a signal as a digital signal when the input timing of the signal output from each pixel via the waveform shaping section 210 is relative to the control pulse pREF as a reference.

[0032] FIG. 5 is a diagram schematically showing the relationship between the operation of APD 201 and the output signal. FIG. 5(a) is a diagram showing the APD 201, the quench element 202, and the waveform shaping section 210 extracted from FIG. Here, node A is the input side of the waveform shaping section 210, and node B is the output side. FIG. 5(b) shows waveform changes at node A in FIG. 5(a), and FIG. 5(c) shows waveform changes at node B in FIG. 5(a).

[0033] Between time t0 and time t1, a potential difference of VH-VL is applied to the APD 201 in FIG. 5(a). When a photon enters the APD 201 at time t1, an avalanche multiplication operation is induced in the APD 201, an avalanche multiplication current flows through the quench element 202, and the node A voltage drops. When the amount of voltage drop increases further and the potential difference applied to APD 201 decreases, the avalanche multiplication operation of APD 201 stops as at time t2, and the voltage level of node A does not drop beyond a certain value. After that, from the time t2 to the time t3, a current that compensates for the voltage drop from the voltage VL flows through the node A, and at the time t3, the node A stabilizes at the original potential level. At this time, the portion of the output waveform at node A that exceeds a certain threshold is shaped by waveform shaping section 210 and output as a signal at node B. FIG.

[0034] Note that the arrangement of the signal line 113 and the arrangement of the readout circuit 112 and the output circuit 114 are not limited to those shown in FIG. For example, the signal line 113 may be arranged to extend in the row direction, and the readout circuit 112 may be arranged at the end of the signal line 113 extending.

[0035] Here, a first configuration example of the pixel 101 will be described with reference to FIGS. 6, 7A, and 7B. For the sake of convenience, FIGS. 7A and 7B show an example in which the pixel array region is composed of 4 pixels of 2 rows×2 columns. An opening OP is provided around the pixel array region, and a pad electrode PE is arranged in the opening OP. FIG. 6(a) schematically shows a planar view of the cathodes of two pixels 101 and their periphery, and FIG. 6(b) schematically shows a planar view of the anodes of two pixels 101 and their periphery. shown in FIG. 7A schematically shows a cross-sectional view of the two pixels 101 of FIGS. 6(a) and (b) in the opposite side direction, and FIG. 7B shows the two pixels of FIGS. 6(a) and (b). A diagonal cross-sectional view of 101 is shown schematically. The opposite side direction is, for example, a direction connecting one side of a pixel and another side facing the one side. A diagonal direction is, for example, a direction connecting one corner of a pixel and another corner facing the one corner.

[0036] The sensor substrate 301 may include a first semiconductor layer 302 having a first side S1 and a second side S2 and a first wiring structure 303. As shown in FIG. Circuit board 401 may include a second semiconductor layer 402 and a second wiring structure 403 . A first wiring structure 303 may be disposed between the first surface S 1 of the first semiconductor layer 302 and the circuit board 401 . A second wiring structure 403 may be disposed between the sensor substrate 301 and the second semiconductor layer 402 .

[0037] Each pixel 101 can include a first conductivity type first semiconductor region 311 as the cathode of the APD 201 and a second conductivity type second semiconductor region 315 as the anode of the APD 201 . The first semiconductor region 311 of the first conductivity type is arranged on the side of the first surface S1 of the first semiconductor layer 302, and the second semiconductor region 315 of the second conductivity type is arranged on the second surface S2 of the first semiconductor layer 302. can be placed on the side of A predetermined voltage may be applied between the first semiconductor region 311 and the second semiconductor region 315 to cause an avalanche doubling operation. Each pixel 101 can include a first conductivity type semiconductor region 313 disposed adjacent to the first semiconductor region 311 between the first semiconductor region 311 as the cathode and the second semiconductor region 315 as the anode. . The first conductivity type impurity concentration in the semiconductor region 313 is lower than the first conductivity type impurity concentration in the first conductivity type first semiconductor region 311 as the cathode.

[0038] Each pixel 101 may include a second conductivity type semiconductor region 312 between a first conductivity type first semiconductor region 311 as a cathode and a second conductivity type second semiconductor region 315 as an anode. For example, if semiconductor region 312 is at the same node as second semiconductor region 315 as an anode, semiconductor region 312 can also function as an anode. A region between the first semiconductor region 311 and the semiconductor region 312 can be an avalanche multiplication region. Between the first surface S1 and the semiconductor region 312 of the second conductivity type, a semiconductor region 316 of the first conductivity type or the second conductivity type is provided so as to surround the first semiconductor region 311 of the first conductivity type as a cathode. can be placed. When the semiconductor region 316 has the first conductivity type, the impurity concentration of the first conductivity type in the semiconductor region 316 is lower than the impurity concentration of the first conductivity type in the semiconductor region 313 as the cathode. When the semiconductor region 316 has the second conductivity type, the second conductivity type impurity concentration in the semiconductor region 316 is lower than the second conductivity type impurity concentration in the second conductivity type semiconductor region 312 .

[0039] A first or second conductivity type semiconductor region 316 may be arranged between the second conductivity type semiconductor region 312 and the second conductivity type second semiconductor region 315 as an anode. When the semiconductor region 316 has the first conductivity type, the impurity concentration of the first conductivity type in the semiconductor region 316 may be lower than the impurity concentration of the first conductivity type in the semiconductor region 313 . When the semiconductor region 316 has the second conductivity type, the second conductivity type impurity concentration in the semiconductor region 316 may be lower than the second conductivity type impurity concentration in the second conductivity type semiconductor region 312 .

[0040] A semiconductor region 317 of the first conductivity type may be arranged between the second semiconductor region 315 of the second conductivity type and the semiconductor region 312 of the second conductivity type as the anode. The semiconductor region 316 surrounds the portion arranged between the second semiconductor region 315 of the second conductivity type as an anode and the semiconductor region 317 of the first conductivity type and the side surface of the semiconductor region 317 of the first conductivity type. can contain parts.

[0041] A second conductivity type isolation region 314 can be arranged between adjacent pixels 101 in the plurality of pixels 101 . A second conductivity type contact region 318 may be disposed between the second conductivity type isolation region 314 and the first surface S1 so as to be electrically connected to the second conductivity type isolation region 314 . The second conductivity type impurity concentration in the second conductivity type contact region 318 is higher than the second conductivity type impurity concentration in the second conductivity type isolation region 314 . The second conductivity type isolation region 314 can be arranged to be electrically connected to the second conductivity type second semiconductor region 315 as an anode. The contact region 318 of the second conductivity type is supplied with an anode voltage (anode potential) via a conductive path arranged in the first wiring structure 303, whereby the second semiconductor region 315 of the second conductivity type serves as an anode. can be supplied with an anode voltage (anode potential). In the example of FIG. 6, four contact regions 318 are provided for one pixel 101, but any number of contact regions 318 may be provided for one pixel 101. Alternatively, two or more pixels 101 may be grouped and one or more contact regions 318 may be provided for each group.

[0042] An insulating isolation portion 324 may be disposed in the isolation region 314 of the second conductivity type. The insulating isolation portion 324 can include a groove provided in the isolation region 314 and an insulator arranged to cover at least the surface (inner surface) of the groove. The insulator may be a film, and the inside of the film may be filled with an insulating material or a conductive material. The insulation isolation part 324 can be called DTI (Deep Trench Isolation). The isolation part 324 or the trench may be arranged so as to penetrate the first semiconductor layer 302 or may be arranged so as not to penetrate the first semiconductor layer 302 . The insulating isolation portion 324 or trench can electrically separate the isolation region 314 of the second conductivity type into an isolation region on the side of one pixel 101 and an isolation region on the side of the next pixel 101 . In addition, the insulating isolation part 324 can be composed of a groove, an insulator disposed so as to cover the inner surface of the groove, and a metal or light shield disposed inside the insulator. Also, the insulating isolation part 324 does not have to penetrate the semiconductor layer.

[0043] A pinning layer 331 (illustrated by a thick line) may be arranged on the second surface S2 side of the second conductivity type second semiconductor region 315 as an anode. The pinning layer 331 can also be called a fixed charge film. The pinning layer 331 is arranged to contact the second surface S2, and can be formed by ALD (Atomic Layer Deposition), for example. The pinning layer 331 can be made of a material selected from, for example, hafnium oxide, aluminum oxide, zirconium oxide, titanium oxide, tantalum oxide, and ruthenium oxide. The pinning layer 331 may consist of multiple layers. The aforementioned film covering the surface (inner surface) of the groove provided in the isolation region 314 may be the pinning layer 331 .

[0044] The pinning layer 331 and the second surface S2 may be covered with an insulating film 321. FIG. The insulating film 321 can be, for example, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. The insulating film 321 may be composed of a plurality of films. A concave-convex structure 325 may be provided in the second semiconductor region 315 of the second conductivity type as an anode. A surface of the uneven structure 325 may be covered with a pinning layer 331 . The uneven structure 325 functions to diffract incident light and lengthen the optical path within the semiconductor layer 302 . This is advantageous for improving near-infrared sensitivity. Concavo-convex structure 325 can be composed of a groove provided in semiconductor layer 302, and pinning layer 331 and an insulator disposed in the groove. A pinning layer 331 may be provided to cover the exposed surface of the semiconductor layer 302 . That is, the pinning layer 331 is arranged along the grooves of the concave-convex structure and the second surface S2. The insulator arranged in the trench may be composed of the insulating film 321 .

[0045] The insulating layer 321 may be covered with a planarization layer 322 . Microlenses 323 may be disposed over the planarization layer 322 . The examples shown in FIGS. 7A and 7B are of a back-illuminated type in which external light is incident on the second surface S of the semiconductor layer 302 through the microlenses 323, but the photoelectric conversion device 100 is of a front-illuminated type. may be configured. Although not shown, on the second surface S2 side of the semiconductor layer 302, in addition to the flattening layer 322, a filter layer such as a color filter or an infrared cut filter may be provided.

[0046] A second configuration example of the pixel 101 will be described below with reference to FIGS. 8, 9A, and 9B. For the sake of convenience, FIGS. 9A and 9B show an example in which the pixel array region is composed of 4 pixels of 2 rows×2 columns. An opening OP is provided around the pixel array region, and a pad electrode PE is arranged in the opening OP. FIG. 8(a) schematically shows a planar view of the cathodes of two pixels 101 and their periphery, and FIG. 8(b) schematically shows a planar view of the anodes of two pixels 101 and their periphery. shown in 9A schematically shows a cross-sectional view of the two pixels 101 in FIGS. 8(a) and 8(b) in the opposite direction, and FIG. 9B shows the two pixels 101 in FIGS. 8(a) and 8(b). A diagonal cross-sectional view of 101 is shown schematically.

[0047] The sensor substrate 301 may include a first semiconductor layer 302 having a first side S1 and a second side S2 and a first wiring structure 303. As shown in FIG. Circuit board 401 may include a second semiconductor layer 402 and a second wiring structure 403 . A first wiring structure 303 may be disposed between the first surface S 1 of the first semiconductor layer 302 and the circuit board 401 . A second wiring structure 403 may be disposed between the sensor substrate 301 and the second semiconductor layer 402 .

[0048] Each pixel 101 can include a first conductivity type first semiconductor region 311 as the cathode of the APD 201 and a second conductivity type second semiconductor region 315 as the anode of the APD 201 . The first semiconductor region 311 of the first conductivity type is arranged on the side of the first surface S1 of the first semiconductor layer 302, and the second semiconductor region 315 of the second conductivity type is arranged on the second surface S2 of the first semiconductor layer 302. can be placed on the side of A predetermined voltage may be applied between the first semiconductor region 311 and the second semiconductor region 315 to cause an avalanche doubling operation. Each pixel 101 includes a ring-shaped first conductive type semiconductor region 311 disposed between a first semiconductor region 311 as a cathode and a second semiconductor region 315 as an anode and in close proximity to the peripheral portion of the first semiconductor region 311. A semiconductor region 313 may be included. The first conductivity type impurity concentration of the semiconductor region 313 is lower than the first conductivity type impurity concentration of the first conductivity type first semiconductor region 311 as the cathode.

[0049] Each pixel 101 has a first semiconductor region 311 of the first conductivity type as a cathode and a second semiconductor region 315 of the second conductivity type as an anode, adjacent to the central portion of the first semiconductor region 311. It can include a semiconductor region 312 of two conductivity types. For example, if semiconductor region 312 is at the same node as second semiconductor region 315 as an anode, semiconductor region 312 can also function as an anode. A region between the first semiconductor region 311 and the semiconductor region 312 can be an avalanche multiplication region. A first or second conductivity type semiconductor region 316 may be arranged between the second conductivity type semiconductor region 312 and the second conductivity type second semiconductor region 315 as an anode. When the semiconductor region 316 has the first conductivity type, the impurity concentration of the first conductivity type in the semiconductor region 316 may be lower than the impurity concentration of the first conductivity type in the semiconductor region 313 . When the semiconductor region 316 has the second conductivity type, the second conductivity type impurity concentration in the semiconductor region 316 may be lower than the second conductivity type impurity concentration in the second conductivity type semiconductor region 312 . The semiconductor region 316 can be arranged to surround the semiconductor region 313 of the first conductivity type. Also, the semiconductor region 316 can include a portion disposed between the semiconductor region 313 of the first conductivity type and the second semiconductor region 315 of the second conductivity type as an anode.

[0050] A second conductivity type isolation region 314 can be arranged between adjacent pixels 101 in the plurality of pixels 101 . A second conductivity type contact region 318 may be disposed between the second conductivity type isolation region 314 and the first surface S1 so as to be electrically connected to the second conductivity type isolation region 314 . The second conductivity type impurity concentration in the second conductivity type contact region 318 is higher than the second conductivity type impurity concentration in the second conductivity type isolation region 314 . The second conductivity type isolation region 314 can be arranged to be electrically connected to the second conductivity type second semiconductor region 315 as an anode. The contact region 318 of the second conductivity type is supplied with an anode voltage (anode potential) via a conductive path arranged in the first wiring structure 303, whereby the second semiconductor region 315 of the second conductivity type serves as an anode. can be supplied with an anode voltage (anode potential). In the example of FIG. 8, four contact regions 318 are provided for one pixel 101, but any number of contact regions 318 may be provided for one pixel 101. Alternatively, two or more pixels 101 may be grouped and one or more contact regions 318 may be provided for each group.

[0051] An insulating isolation portion 324 may be disposed in the isolation region 314 of the second conductivity type. The insulating isolation portion 324 can include a groove provided in the isolation region 314 and an insulator arranged to cover at least the surface (inner surface) of the groove. The insulator may be a film, and the inside of the film may be filled with an insulating material or a conductive material. The insulation isolation part 324 can be called DTI (Deep Trench Isolation). The isolation part 324 or the trench may be arranged so as to penetrate the first semiconductor layer 302 or may be arranged so as not to penetrate the first semiconductor layer 302 . The insulating isolation portion 324 or trench can electrically separate the isolation region 314 of the second conductivity type into an isolation region on the side of one pixel 101 and an isolation region on the side of the next pixel 101 .

[0052] A pinning layer 331 (illustrated by a thick line) may be arranged on the second surface S2 side of the second conductivity type second semiconductor region 315 as an anode. The pinning layer 331 can also be called a fixed charge film. The pinning layer 331 is arranged to contact the second surface S2, and can be formed by ALD (Atomic Layer Deposition), for example. The pinning layer 331 can be made of, for example, polysilicon, hafnium oxide film, aluminum oxide film, or the like. The pinning layer 331 and the second surface S2 may be covered with an insulating film 321. FIG. The insulating film 321 can be, for example, a SiO film, a SiN film, or a SiON film. A concave-convex structure 325 may be provided in the second semiconductor region 315 of the second conductivity type as an anode. A surface of the uneven structure 325 may be covered with a pinning layer 331 . The uneven structure 325 functions to diffract incident light and lengthen the optical path within the semiconductor layer 302 . This is advantageous for improving near-infrared sensitivity.

[0053] The insulating layer 321 may be covered with a planarization layer 322 . Microlenses 323 may be disposed over the planarization layer 322 . The examples shown in FIGS. 9A and 9B are of a back-illuminated type in which external light is incident on the second surface S of the semiconductor layer 302 through the microlenses 323, but the photoelectric conversion device 100 is of a front-illuminated type. may be configured.

[0054] The configuration of the photoelectric conversion device 100 of the first embodiment will be described below with reference to FIGS. 10 and 11. FIG. The photoelectric conversion device 100 of the first embodiment provides an example in which the charge discharging unit 1350 is applied to the photoelectric conversion device 100 having the configuration according to the first configuration example described with reference to FIGS. 6, 7A, and 7B. do. Descriptions of items that are the same as those already described will be omitted. Specifically, the photoelectric conversion device of the first embodiment differs from that of the first configuration example in that it does not include an insulating isolation section or an uneven structure.

[0055] The photoelectric conversion device 100 of the first embodiment includes a semiconductor layer 302 including a pixel array region 12 having a plurality of pixels 101 and a peripheral region 13 arranged around the pixel array region 12 (or It has a sensor substrate 301). The pixel array region 12 includes an effective pixel region 12E in which pixels (effective pixels) 102 that output signals according to incident light are arranged, and an OB pixel region 12E in which light-shielded pixels (OB pixels or light-shielded pixels) 102 are arranged. pixel area 12OB. The OB pixel area 12OB can be arranged along at least part of the perimeter of the effective pixel area 12E. The OB pixel area 12OB can typically be arranged to surround the effective pixel area 12E. At least one, typically a plurality of pad electrodes PE can be arranged in the peripheral region 13 . In the OB pixel 101, the APD 201 including the anode and cathode is shielded by the light shielding film LSM. The pixels 101 in the OB pixel area 12OB can have the same configuration as the pixels 101 in the effective pixel area 12E except that the APD 201 is shielded by the light shielding film LSM.

[0056] One or more charge drains 1350 may be arranged in the peripheral region 13 . In FIG. 10(a), one charge discharging portion 1350 is indicated by a black circle. FIG. 10(b) is a schematic plan view of one charge discharging section 1350. FIG. Here, it is preferable that the plurality of charge discharging portions 1350 are arranged along each of the four sides of the pixel array region 12 with a predetermined pitch. The predetermined pitch is preferably larger than the arrangement pitch of the plurality of pixels 101 in the pixel array region 12. FIG. A plurality of charge discharging units 1350 may be arranged along each of the four sides of the pixel array region 12 to form a plurality of columns. A plurality of charge discharging units 1350 may be arranged in a houndstooth pattern along each of the four sides of the pixel array region 12 .

[0057] As illustrated in FIG. 11, the semiconductor layer 302 has a first surface S1 and a second surface S2. Each pixel 101 arranged in the pixel array region 12 (effective pixel region 12E, OB pixel region 12OB) has the same structure as the first configuration example described with reference to FIGS. 6, 7A, and 7B. sell. 11, 6, 7A and 7B will be referred to each other for explanation.

[0058] Each pixel 101 can include a first conductivity type first semiconductor region 311 as the cathode of the APD 201 and a second conductivity type second semiconductor region 315 as the anode of the APD 201 . The first semiconductor region 311 of the first conductivity type is arranged on the side of the first surface S1 of the first semiconductor layer 302, and the second semiconductor region 315 of the second conductivity type is arranged on the second surface S2 of the first semiconductor layer 302. can be placed on the side of A predetermined voltage may be applied between the first semiconductor region 311 and the second semiconductor region 315 to cause an avalanche doubling operation. Each pixel 101 can include a first conductivity type semiconductor region 313 disposed adjacent to the first semiconductor region 311 between the first semiconductor region 311 as the cathode and the second semiconductor region 315 as the anode. . The first conductivity type impurity concentration of the semiconductor region 313 is lower than the first conductivity type impurity concentration of the first conductivity type first semiconductor region 311 as the cathode.

[0059] Each pixel 101 may include a second conductivity type semiconductor region 312 between a first conductivity type first semiconductor region 311 as a cathode and a second conductivity type second semiconductor region 315 as an anode. Between the first surface S1 and the semiconductor region 312 of the second conductivity type, a semiconductor region 316 of the first conductivity type or the second conductivity type is provided so as to surround the first semiconductor region 311 of the first conductivity type as a cathode. can be placed. When the semiconductor region 316 has the first conductivity type, the impurity concentration of the first conductivity type in the semiconductor region 316 is lower than the impurity concentration of the first conductivity type in the semiconductor region 313 as the cathode. When the semiconductor region 316 has the second conductivity type, the second conductivity type impurity concentration in the semiconductor region 316 is lower than the second conductivity type impurity concentration in the second conductivity type semiconductor region 312 .

[0060] A first or second conductivity type semiconductor region 316 may be arranged between the second conductivity type semiconductor region 312 and the second conductivity type second semiconductor region 315 as an anode. When the semiconductor region 316 has the first conductivity type, the impurity concentration of the first conductivity type in the semiconductor region 316 may be lower than the impurity concentration of the first conductivity type in the semiconductor region 313 . When the semiconductor region 316 has the second conductivity type, the second conductivity type impurity concentration in the semiconductor region 316 may be lower than the second conductivity type impurity concentration in the second conductivity type semiconductor region 312 .

[0061] A semiconductor region 317 of the first conductivity type may be arranged between the second semiconductor region 315 of the second conductivity type and the semiconductor region 312 of the second conductivity type as the anode. The semiconductor region 316 surrounds the portion arranged between the second semiconductor region 315 of the second conductivity type as an anode and the semiconductor region 317 of the first conductivity type and the side surface of the semiconductor region 317 of the first conductivity type. can contain parts.

[0062] A second conductivity type isolation region 314 can be arranged between adjacent pixels 101 in the plurality of pixels 101 . A second conductivity type contact region 318 may be disposed between the second conductivity type isolation region 314 and the first surface S1 so as to be electrically connected to the second conductivity type isolation region 314 . The second conductivity type impurity concentration in the second conductivity type contact region 318 is higher than the second conductivity type impurity concentration in the second conductivity type isolation region 314 . The second conductivity type isolation region 314 can be arranged to be electrically connected to the second conductivity type second semiconductor region 315 as an anode. The contact region 318 of the second conductivity type is supplied with an anode voltage (anode potential) via a conductive path arranged in the first wiring structure 303, whereby the second semiconductor region 315 of the second conductivity type serves as an anode. can be supplied with an anode voltage (anode potential).

[0063] An insulating isolation portion 324 may be disposed in the isolation region 314 of the second conductivity type. The insulating isolation portion 324 can include a groove provided in the isolation region 314 and an insulator arranged to cover at least the surface (inner surface) of the groove. The insulator may be a film, and the inside of the film may be filled with an insulating material or a conductive material. The insulation isolation part 324 can be called DTI (Deep Trench Isolation). The isolation part 324 or the trench may be arranged so as to penetrate the first semiconductor layer 302 or may be arranged so as not to penetrate the first semiconductor layer 302 . The insulating isolation portion 324 or trench can electrically separate the isolation region 314 of the second conductivity type into an isolation region on the side of one pixel 101 and an isolation region on the side of the adjacent pixel 101 .

[0064] A pinning layer 331 (illustrated by a thick line) may be arranged on the second surface S2 side of the second conductivity type second semiconductor region 315 as an anode. The pinning layer 331 can also be called a fixed charge film. The pinning layer 331 is arranged to contact the second surface S2, and can be formed by ALD (Atomic Layer Deposition), for example. The pinning layer 331 can be made of, for example, polysilicon, hafnium oxide, aluminum oxide, or the like. The pinning layer 331 and the second surface S2 may be covered with an insulating film 321. FIG.

[0065] The peripheral region 13 includes a first conductivity type third semiconductor region 1311 arranged on the side of the first surface S1 and a second conductivity type fourth semiconductor region 1315 arranged apart from the third semiconductor region 1311. can include The fourth semiconductor region 1315 may include an extended portion EP extending parallel to the second surface S2. A predetermined voltage may be applied between the third semiconductor region 1311 and the fourth semiconductor region 1315 . The voltage supplied between the third semiconductor region 1311 and the fourth semiconductor region 1315 is the same as the voltage supplied between the first semiconductor region 311 as the anode and the second semiconductor region 315 as the cathode. may A pn junction is formed between the third semiconductor region 1311 of the first conductivity type and the fourth semiconductor region 1315 of the second conductivity type, and a pn junction is provided between the third semiconductor region 1311 and the fourth semiconductor region 1315 of the second conductivity type. can be reverse-biased by a voltage and act as a photodiode.

[0066] The peripheral region 13 also includes a first conductivity type impurity concentration lower than that of the third semiconductor region 1311 between the third semiconductor region 1311 of the first conductivity type and the fourth semiconductor region 1315 of the second conductivity type. A fifth semiconductor region 1313 of conductivity type may be included. A fifth semiconductor region 1313 may be disposed adjacent to the third semiconductor region 1311 . The first conductivity type fifth semiconductor region 1313 is arranged to surround the side surface of the third semiconductor region 1311 . The first conductivity type fifth semiconductor region 1313 can include a portion disposed between the third semiconductor region 1311 and the fourth semiconductor region 1315 so as to be in contact with the third semiconductor region 1311 . The first-conductivity-type third semiconductor region 1311 , the second-conductivity-type fourth semiconductor region 1315 , and the first-conductivity-type fifth semiconductor region 1313 can constitute the charge discharging portion 1350 . The fifth semiconductor region 1313 of the first conductivity type can function to relax the electric field in the vicinity of the third semiconductor region 1311 of the first conductivity type.

[0067] The first conductivity type third semiconductor region 1311 has the same depth (for example, the depth from the first surface S1) as the first conductivity type first semiconductor region 311 as the cathode of the pixel 101 in the pixel array region 12. can be formed in a region. Also, the first semiconductor region 311 and the third semiconductor region 1311 may be arranged between the first surface S1 and the first depth. The first conductivity type impurity concentration in the third semiconductor region 1311 may be the same as the first conductivity type impurity concentration in the first semiconductor regions 311 of the pixels 101 in the pixel array region 12 . The first conductivity type third semiconductor region 1311 may be formed simultaneously with the first conductivity type first semiconductor region 311 of the pixel 101 in the pixel array region 12 .

[0068] The second conductivity type fourth semiconductor region 1315 has the same depth (for example, the depth from the first surface S1) as the second conductivity type second semiconductor region 315 as the anode of the pixel 101 in the pixel array region 12. can be formed in a region. Also, the second semiconductor region 315 and the fourth semiconductor region 1315 may be arranged between the second surface S2 and the second depth. The second conductivity type impurity concentration in the fourth semiconductor region 1315 may be the same as the second conductivity type impurity concentration in the second semiconductor regions 315 of the pixels 101 in the pixel array region 12 . The second conductivity type fourth semiconductor region 1315 may be formed simultaneously with the second conductivity type second semiconductor region 315 of the pixel 101 in the pixel array region 12 . The second conductivity type fourth semiconductor region 1315 in the peripheral region 13 may be formed integrally with the second conductivity type second semiconductor region 315 in the pixel array region 12 .

[0069] A first or second conductivity type semiconductor region 316 may be disposed between the first conductivity type fifth semiconductor region 1313 and the second conductivity type fourth semiconductor region 1315 . When the semiconductor region 316 has the first conductivity type, the first conductivity type impurity concentration in the semiconductor region 316 is lower than the first conductivity type impurity concentration in the semiconductor region 1313 . When the semiconductor region 316 has the second conductivity type, the second conductivity type impurity concentration in the semiconductor region 316 is lower than the second conductivity type impurity concentration in the second conductivity type semiconductor region 1315 . The semiconductor region 316 in the peripheral region 13 can have the same conductivity type and the same impurity concentration as the semiconductor region 316 in the pixel array region 12 . Semiconductor region 316 may be an epitaxially grown layer.

[0070] Light (or photons) LL can enter the semiconductor region 316 of the peripheral region 13, for example, through an opening OP for the pad electrode PE or through a region without the light shielding film LSM. The light LL incident on the semiconductor region 316 of the peripheral region 13 can generate electrons (e−) and holes (h+) by photoelectric conversion. If the peripheral region 13 does not have the charge drain 1350, electrons and holes generated by light incident on the peripheral region 13 may move to the pixel array region 12 and cause an avalanche multiplication operation. Alternatively, electrons and holes generated by light incident on peripheral region 13 may recombine to generate light that is detected by pixels 101 of pixel array region 12 . Alternatively, light incident on peripheral region 13 may cause avalanche multiplication. These can degrade the quality of the image or signal detected by the photoelectric conversion device 100 .

[0071] In the first embodiment, the charge discharging part 1350 provided in the peripheral region 13 can operate to discharge electrons and holes generated by light incident on the peripheral region 13 . Here, when the first conductivity type is n-type and the second conductivity type is p-type, the generated electrons are drawn into the third semiconductor region 1311 of the first conductivity type, and the generated holes are of the second conductivity type. It is drawn into the fourth semiconductor region 1315 of the mold.

[0072] In the peripheral region 13, a pinning layer 331 (illustrated by a thick line) can be arranged on the second surface S2 side of the fourth semiconductor region 1315 of the second conductivity type. The pinning layer 331 is arranged to contact the second surface S2, and can be formed by ALD (Atomic Layer Deposition), for example. The pinning layer 331 can be made of, for example, polysilicon, hafnium oxide, aluminum oxide, or the like. The pinning layer 331 and the second surface S2 can be covered with an insulating film 321 such as a SiN film. The pinning layer 331 in the peripheral region 13 may have the same composition as the pinning layer 331 in the pixel array region 12 and may be formed simultaneously with the pinning layer 331 in the pixel array region 12 .

[0073] The semiconductor layer 302 can have a second conductivity type isolation region 314 in the boundary region between the pixel array region 12 and the peripheral region 13 . The isolation region 314 is electrically connected to the second conductivity type second semiconductor region 315 and can be supplied with the same potential as the second conductivity type second semiconductor region 315 . The second-conductivity-type separation region 314 arranged in the boundary region between the pixel array region 12 and the peripheral region 13 can also constitute the charge discharging portion 1350 .

[0074] The light shielding film LSM may include a light shielding structure LSS in the boundary region between the pixel array region 12 and the peripheral region 13, for example, the separation region 314 in plan view. In one example, the light shielding film LSM can be electrically connected to the second conductivity type second semiconductor region 315 and / or the second conductivity type fourth semiconductor region 1315 via the light shielding structure LSS. The light shielding structure LSS may include, for example, one or more walls. The one or more walls can be electrically connected to the second semiconductor region 315 of the second conductivity type and / or the fourth semiconductor region 1315 of the second conductivity type through the pinning layer 331 .

[0075] The configuration of the photoelectric conversion device 100 of the second embodiment will be described below with reference to FIGS. 12 and 13. FIG. The photoelectric conversion device 100 of the second embodiment provides an example in which the charge discharging unit 1350 is applied to the photoelectric conversion device 100 having the configuration according to the first configuration example described with reference to FIGS. 6, 7A, and 7B. do. Descriptions of items that are the same as those already described will be omitted. The photoelectric conversion device 100 of the second embodiment differs from the photoelectric conversion device 100 of the first embodiment in the configuration of the charge discharging section 1350 and / or the voltage supplied to the charge discharging section 1350. FIG.

[0076] The photoelectric conversion device 100 of the second embodiment can include a voltage generator VG. The voltage generator VG can generate a voltage (potential) to be supplied to the third semiconductor region 1311 of the first conductivity type. In another aspect, the voltage generator VG can generate a voltage to be supplied between the third semiconductor region 1311 of the first conductivity type and the fourth semiconductor region 1315 of the second conductivity type. The voltage generator VG converts the voltage (potential) supplied to the third semiconductor region 1311 of the first conductivity type, for example, by transforming the voltage supplied to one pad electrode PE out of the plurality of pad electrodes PE. can generate The voltage generator VG can be arranged on the circuit board 401, for example. Instead of such a configuration, the voltage (potential) supplied to the third semiconductor region 1311 of the first conductivity type may be supplied from outside the photoelectric conversion device 100. FIG.

[0077] The voltage supplied to the charge discharging unit 1350, in other words, the voltage supplied between the third semiconductor region 1311 of the first conductivity type and the fourth semiconductor region 1315 of the second conductivity type is applied to the anode of the pixel array region 12. and the cathode. In one example, the voltage supplied to the charge drainer 1350 may be less than half the voltage supplied between the anode and cathode of the pixel array region 12 . Alternatively, the voltage (potential) supplied to the first conductivity type third semiconductor region 1311 may be the ground potential in the photoelectric conversion device 100 . This is advantageous for simplifying the structure of the photoelectric conversion device 100. FIG.

[0078] If the electric field generated around the third semiconductor region 1311 of the first conductivity type is sufficiently weak, the fifth semiconductor region 1313 as provided in the charge discharging portion 1350 in the first embodiment may be removed. FIGS. 12 and 13 illustrate the charge discharge portion 1350 with the fifth semiconductor region 1313 removed. In addition, this voltage can also be applied to a configuration having an insulation isolation portion as shown in FIGS. 7A and 7B.

[0079] The configuration of the photoelectric conversion device 100 of the third embodiment will be described below with reference to FIGS. 14, 15A, and 15B. The photoelectric conversion device 100 of the third embodiment provides an example in which the charge discharging unit 1350 is applied to the photoelectric conversion device 100 having the configuration according to the first configuration example described with reference to FIGS. 6, 7A, and 7B. do. Descriptions of items that are the same as those already described will be omitted. The photoelectric conversion device 100 according to the third embodiment differs from the photoelectric conversion device 100 according to the first embodiment in that it includes an insulating separation section 324. FIG. Further, for example, the photoelectric conversion device 100 of the third embodiment is different from the photoelectric conversion device 100 of the first embodiment in that the concave-convex structure 325 is provided. The uneven structure 325 shown in FIGS. 15A and 15B is similar to the uneven structure 325 shown in FIGS. 7A and 7B.

[0080] A second conductivity type isolation region 314 can be arranged between adjacent pixels 101 in the plurality of pixels 101 . Similarly, a second conductivity type isolation region 314 may be disposed between the pixel array region 12 and the peripheral region 13 . A second conductivity type contact region 318 may be disposed between the second conductivity type isolation region 314 and the first surface S1 so as to be electrically connected to the second conductivity type isolation region 314 . The second conductivity type impurity concentration in the second conductivity type contact region 318 is higher than the second conductivity type impurity concentration in the second conductivity type isolation region 314 . The second conductivity type isolation region 314 can be arranged to be electrically connected to the second conductivity type second semiconductor region 315 as an anode. The contact region 318 of the second conductivity type is supplied with an anode voltage (anode potential) via a conductive path arranged in the first wiring structure 303, whereby the second semiconductor region 315 of the second conductivity type serves as an anode. can be supplied with an anode voltage (anode potential).

[0081] In the pixel array region 12, an insulating isolation portion 324 may be arranged in the isolation region 314 of the second conductivity type. Similarly, in the peripheral region 13, an insulating isolation portion 324 may be arranged in the isolation region 314 of the second conductivity type. The insulating isolation portion 324 can include a groove provided in the isolation region 314 and an insulator arranged to cover at least the surface (inner surface) of the groove. The insulator may be a film, and the inside of the film may be filled with an insulating material or a conductive material. Such a film may be the pinning layer 331 . The insulation isolation part 324 can be called DTI (Deep Trench Isolation). The isolation part 324 or the trench may be arranged so as to penetrate the first semiconductor layer 302 or may be arranged so as not to penetrate the first semiconductor layer 302 . In addition, as shown in FIG. 15A, a plurality of isolation portions may be provided so as to sandwich the opening OP. The difference in refractive index between the insulating material of the insulating separation portion and the first semiconductor layer 302 can reduce the incidence of light from the opening OP.

[0082] In the pixel array region 12, the insulating isolation portion 324 or groove can electrically separate the second conductivity type isolation region 314 into an isolation region on the side of one pixel 101 and an isolation region on the side of the adjacent pixel 101. . Similarly, in the peripheral region 13, the insulating isolation portion 324 or trench separates the second conductivity type isolation region 314 from the first isolation region 314A on the pixel array region 12 side and the second isolation region 314B on the peripheral region 13 side. can be arranged to be electrically isolated from each other. The first wiring structure 303 laminated to the first semiconductor layer 302 includes a first conductive path that applies a potential to the first isolation region 314A and a second conductive path that provides a potential to the second isolation region 314B. It can have a conductive path. The first conductive path and the second conductive path may be electrically connected in the first wiring structure 303 . Conductive paths may include, for example, contact plugs, wiring, and the like.

[0083] The configuration of the photoelectric conversion device 100 of the fourth embodiment will be described below with reference to FIGS. 16A and 16B. The photoelectric conversion device 100 of the fourth embodiment provides an example in which the charge discharging unit 1350 is applied to the photoelectric conversion device 100 having the configuration according to the first configuration example described with reference to FIGS. 6, 7A, and 7B. do. Descriptions of items that are the same as those already described will be omitted. The photoelectric conversion device 100 of the fourth embodiment has a configuration obtained by removing the second conductivity type semiconductor region 1315 from the photoelectric conversion device 100 of the third embodiment. The uneven structure 325 shown in FIGS. 16A and 16B is similar to the uneven structure 325 shown in FIGS. 7A and 7B.

[0084] Also in the fourth embodiment, the charge discharging part 1350 provided in the peripheral region 13 can operate to discharge electrons and holes generated by light incident on the peripheral region 13 . Here, if the first conductivity type is the n-type and the second conductivity type is the p-type, the generated electrons can be drawn into the third semiconductor region 1311 of the first conductivity type and discharged. On the other hand, the generated holes are generated by charges induced in the vicinity of the surface of the semiconductor region 316 (near the second surface S2) by the pinning layer 331, thereby forming a semiconductor region of the second conductivity type near the surface, the separation region 314 and the It can be discharged through the second semiconductor region 315 of the second conductivity type. The second-conductivity-type semiconductor region formed in the surface region of the semiconductor region 316 by charges induced by the pinning layer 331 functions in the same manner as the fourth semiconductor region 1315 (extended portion EP) described above. When the second conductivity type is p-type, the charges induced by the pinning layer 331 are holes.

[0085] The configuration of the photoelectric conversion device 100 of the fifth embodiment will be described below with reference to FIG. The photoelectric conversion device 100 of the seventh embodiment provides an example in which the charge discharging unit 1350 is applied to the photoelectric conversion device 100 having the configuration according to the second configuration example described with reference to FIGS. 8, 9A, and 9B. do. Descriptions of items that are the same as those already described will be omitted. The first to fourth embodiments can also be applied to the photoelectric conversion device 100 having the configuration according to the second configuration example described with reference to FIGS. 8, 9A, and 9B. The uneven structure 325 shown in FIG. 17 is similar to the uneven structure 325 shown in FIGS. 9A and 9B.

[0086] Hereinafter, a photoelectric conversion system in which the photoelectric conversion device exemplified through the first to fifth embodiments is incorporated will be exemplified. FIG. 18 shows an example of a photoelectric conversion system. The photoelectric conversion devices described in the first to fifth embodiments are applicable to various photoelectric conversion systems. Examples of applicable photoelectric conversion systems include digital still cameras, digital camcorders, surveillance cameras, copiers, facsimiles, mobile phones, vehicle-mounted cameras, and observation satellites. A camera module including an optical system such as a lens and an imaging device is also included in the photoelectric conversion system.

[0087] The photoelectric conversion system is configured as an imaging system SYS, for example. The imaging system SYS is an information terminal having a camera and imaging functions. The imaging device IS can further include a package PKG that accommodates the photoelectric conversion device 100 configured as an imaging device IC. The package PKG can include a base to which the imaging device IC is fixed, a lid facing the imaging device IC, and a connecting member that connects terminals provided on the base and terminals provided on the imaging device IC. . The imaging device IS can also mount a plurality of imaging device ICs side by side in a common package PKG. In addition, the image pickup device IS can be mounted in a common package PKG with the image pickup device IC and another semiconductor device IC stacked on top of each other.

[0088] The imaging system SYS may comprise an optical system OU imaging onto the imaging device IS. Further, the imaging system SYS includes at least one of a control device CU that controls the imaging device IS, a processing device PU that processes signals obtained from the imaging device IS, and a display device DU that displays an image obtained from the imaging device IS. can be provided. The imaging system SYS may also include a storage device MU for storing images obtained from the imaging device IS.

[0089] FIG. 19(a) illustrates the configuration of a photoelectric conversion system applied to a vehicle-mounted camera. The photoelectric conversion system 2300 can have the photoelectric conversion device 100 configured as an imaging device 2310 . The photoelectric conversion system 2300 includes an image processing unit 2312 that performs image processing on a plurality of image data acquired by the imaging device 2310, and a parallax (phase difference of parallax image) from the plurality of image data acquired by the photoelectric conversion system 2300. It has a parallax acquisition unit 2314 that calculates . The photoelectric conversion system 2300 also includes a distance acquisition unit 2316 that calculates the distance to the object based on the calculated parallax, and a collision determination unit that determines whether there is a possibility of collision based on the calculated distance. 2318 and Here, the parallax acquisition unit 2314 and the distance acquisition unit 2316 are examples of distance information acquisition means for acquiring distance information to the object. That is, the distance information is information related to parallax, defocus amount, distance to the object, and the like. The collision determination unit 2318 may use any of these distance information to determine the possibility of collision. The distance information acquisition means may be implemented by specially designed hardware, or may be implemented by a software module. Moreover, it may be implemented by FPGA (Field Programmable Gate Array), ASIC (Application Specific Integrated Circuit), or the like, or by a combination thereof.

[0090] The photoelectric conversion system 2300 is connected to a vehicle information acquisition device 2320, and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. Photoelectric conversion system 2300 is also connected to control ECU 2330, which is a control unit that outputs a control signal for generating braking force to the vehicle based on the determination result of collision determination unit 2318. FIG. The photoelectric conversion system 2300 is also connected to an alarm device 2340 that issues an alarm to the driver based on the judgment result of the collision judgment section 2318. FIG. For example, if the collision determination unit 2318 determines that there is a high possibility of a collision, the control ECU 2330 performs vehicle control to avoid a collision and reduce damage by applying the brakes, releasing the accelerator, or suppressing the engine output. The alarm device 2340 warns the user by sounding an alarm such as sound, displaying alarm information on a screen of a car navigation system or the like, or vibrating a seat belt or steering wheel. In this embodiment, the photoelectric conversion system 2300 captures an image of the surroundings of the vehicle, for example, the front or rear. FIG. 19(b) shows a photoelectric conversion system configured to capture an image in front of the vehicle (imaging range 2350). Vehicle information acquisition device 2320 sends an instruction to photoelectric conversion system 2300 or imaging device 2310 . With such a configuration, the accuracy of distance measurement can be further improved.

[0091] In the above, an example of controlling the vehicle so that it does not collide with another vehicle has been explained, but it can also be applied to the control of automatically driving following another vehicle or the control of automatically driving so as not to stray from the lane. . Furthermore, the photoelectric conversion system can be applied not only to vehicles such as own vehicles but also to moving objects (moving devices) such as ships, aircraft, and industrial robots. In addition, it can be applied not only to mobile objects but also to devices that widely use object recognition, such as intelligent transportation systems (ITS).

[0092] FIG. 20 illustrates the configuration of a photoelectric conversion system configured as a distance image sensor. Distance image sensor 40 is configured with optical system 407 , photoelectric conversion device 408 , image processing circuit 404 , monitor 405 , and memory 406 . Then, the distance image sensor 40 receives the light (modulated light or pulsed light) projected from the light source device 409 toward the subject and reflected by the surface of the subject, thereby producing a distance image corresponding to the distance to the subject. can be obtained.

[0093] The optical system 407 includes one or more lenses, guides image light (incident light) from the subject to the photoelectric conversion device 408, and forms an image on the light receiving surface (sensor section) of the photoelectric conversion device 408. Let As the photoelectric conversion device 408 , the photoelectric conversion device of each of the embodiments described above is applied, and a distance signal indicating the distance obtained from the received light signal output from the photoelectric conversion device 408 is supplied to the image processing circuit 404 .

[0094] The image processing circuit 404 performs image processing for constructing a distance image based on the distance signal supplied from the photoelectric conversion device 408 . A distance image (image data) obtained by the image processing is supplied to the monitor 405 to be displayed, or supplied to the memory 406 to be stored (recorded). In the distance image sensor 40 configured in this manner, by applying the above-described photoelectric conversion device, it is possible to obtain, for example, a more accurate distance image as the characteristics of the pixels are improved.

[0095] FIG. 21 illustrates the configuration of a photoelectric conversion system configured as an endoscopic surgery system. FIG. 21 shows an operator (doctor) 1131 performing surgery on a patient 1132 on a patient bed 1133 using an endoscopic surgery system 1150 . As illustrated, the endoscopic surgery system 1150 is composed of an endoscope 1100, a surgical tool 1110, and a cart 1134 loaded with various devices for endoscopic surgery.

[0096] An endoscope 1100 is composed of a lens barrel 1101 whose distal end is inserted into a body cavity of a patient 1132 and a camera head 1102 connected to the proximal end of the lens barrel 1101 . The illustrated example shows an endoscope 1100 configured as a so-called rigid endoscope having a rigid lens barrel 1101, but the endoscope 1100 may be configured as a so-called flexible endoscope having a flexible lens barrel. good.

[0097] The tip of the lens barrel 1101 is provided with an opening into which an objective lens is fitted. A light source device 1203 is connected to the endoscope 1100, and light generated by the light source device 1203 is guided to the tip of the lens barrel 1101 by a light guide extending inside the lens barrel 1101, whereupon the objective lens through the body cavity of the patient 1132 toward the observation target. Note that the endoscope 1100 may be a straight scope, a perspective scope, or a side scope.

[0098] An optical system and a photoelectric conversion device are provided inside the camera head 1102, and the reflected light (observation light) from the observation target is converged on the photoelectric conversion device by the optical system. The photoelectric conversion device photoelectrically converts the observation light to generate an electrical signal corresponding to the observation light, that is, an image signal corresponding to the observation image. As the photoelectric conversion device, the photoelectric conversion device described in each of the above embodiments can be used. The image signal is sent to a camera control unit (CCU: Camera Control Unit) 1135 as RAW data.

[0099] The CCU 1135 is composed of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and controls the operations of the endoscope 1100 and the display device 1136 in an integrated manner. Furthermore, the CCU 1135 receives an image signal from the camera head 1102 and performs various image processing such as development processing (demosaicing) on ​​the image signal for displaying an image based on the image signal.

[0100] The display device 1136 displays an image based on an image signal subjected to image processing by the CCU 1135 under the control of the CCU 1135 . The light source device 1203 is composed of, for example, a light source such as an LED (Light Emitting Diode), and supplies the endoscope 1100 with irradiation light for photographing a surgical site or the like. Input device 1137 is an input interface to endoscopic surgery system 1150 . A user can input various information and instructions to the endoscopic surgery system 1150 via the input device 1137 . The treatment instrument control device 1138 controls driving of the energy treatment instrument 1112 for tissue cauterization, incision, blood vessel sealing, or the like.

[0101] The light source device 1203 that supplies irradiation light to the endoscope 1100 for photographing the surgical site can be composed of, for example, a white light source composed of an LED, a laser light source, or a combination thereof. When a white light source is configured by combining RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high accuracy. It can be carried out. In this case, the laser light from each of the RGB laser light sources is irradiated to the observation target in a time division manner, and by controlling the drive of the imaging element of the camera head 1102 in synchronization with the irradiation timing, each of the RGB can be handled. It is also possible to pick up images by time division. According to this method, a color image can be obtained without providing a color filter in the imaging element.

[0102] Further, the driving of the light source device 1203 may be controlled so as to change the intensity of the output light at predetermined time intervals. By controlling the drive of the imaging element of the camera head 1102 in synchronization with the timing of the change in the intensity of the light to acquire images in a time-division manner and synthesizing the images, a high dynamic A range of images can be generated.

[0103] Also, the light source device 1203 may be configured to be able to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation, for example, utilizes the wavelength dependence of light absorption in body tissues. Specifically, a predetermined tissue such as a blood vessel on the surface of the mucous membrane is imaged with high contrast by irradiating light with a narrower band than the irradiation light (that is, white light) used in normal observation. Alternatively, in special light observation, fluorescence observation may be performed in which an image is obtained from fluorescence generated by irradiation with excitation light. In fluorescence observation, the body tissue is irradiated with excitation light and fluorescence from the body tissue is observed, or a reagent such as indocyanine green (ICG) is locally injected into the body tissue and the fluorescence wavelength of the reagent is observed in the body tissue. It is possible to obtain a fluorescent image by irradiating excitation light corresponding to . The light source device 1203 can be configured to supply narrowband light and / or excitation light corresponding to such special light observation.

[0104] FIG. 22(a) illustrates the configuration of a photoelectric conversion system configured as glasses 1600 (smart glasses). Glasses 1600 have a photoelectric conversion device 1602 to which the photoelectric conversion device 100 is applied. The photoelectric conversion device 1602 is the photoelectric conversion device described in each of the above embodiments. Also, a display device including a light emitting device such as OLED or LED may be provided on the rear surface side of the lens 1601 . One or more photoelectric conversion devices 1602 may be provided. Further, a plurality of types of photoelectric conversion devices may be used in combination. The arrangement position of the photoelectric conversion device 1602 is not limited to that shown in FIG. 22(a).

[0105] Glasses 1600 further comprise controller 1603 . The control device 1603 functions as a power source that supplies power to the photoelectric conversion device 1602 and the display device. Also, the control device 1603 controls the operation of the photoelectric conversion device 1602 and the display device. An optical system for condensing light onto the photoelectric conversion device 1602 is formed in the lens 1601 .

[0106] FIG. 22(b) illustrates the configuration of a photoelectric conversion system configured with glasses 1610 (smart glasses). The glasses 1610 have a control device 1612, and the control device 1612 is equipped with a photoelectric conversion device corresponding to the photoelectric conversion device 1602 and a display device. The lens 1611 is formed with a photoelectric conversion device in the control device 1612 and an optical system for projecting light emitted from the display device, and an image is projected onto the lens 1611 . The control device 1612 functions as a power source that supplies power to the photoelectric conversion device and the display device, and controls the operation of the photoelectric conversion device and the display device. The control device may have a line-of-sight detection unit that detects the line of sight of the wearer. Infrared rays may be used for line-of-sight detection. The infrared light emitting section emits infrared light to the eyeballs of the user who is gazing at the display image. A captured image of the eyeball is obtained by detecting reflected light of the emitted infrared light from the eyeball by an imaging unit having a light receiving element. By having a reduction means for reducing light from the infrared light emitting section to the display section in plan view, deterioration in image quality is reduced.

[0107] The line of sight of the user with respect to the display image is detected from the captured image of the eye obtained by imaging the infrared light. Any known method can be applied to line-of-sight detection using captured images of eyeballs. As an example, it is possible to use a line-of-sight detection method based on a Purkinje image obtained by reflection of irradiation light on the cornea. More specifically, line-of-sight detection processing based on the pupillary corneal reflection method is performed. The user's line of sight is detected by calculating a line-of-sight vector representing the orientation (rotation angle) of the eyeball based on the pupil image and the Purkinje image included in the captured image of the eyeball using the pupillary corneal reflection method. be.

[0108] The display device of this embodiment may have a photoelectric conversion device having a light receiving element, and may control a display image of the display device based on the user's line-of-sight information from the photoelectric conversion device.

[0109] Specifically, the display device determines a first visual field area that the user gazes at and a second visual field area other than the first visual field area, based on the line-of-sight information. The first viewing area and the second viewing area may be determined by the control device of the display device, or may be determined by an external control device. In the display area of ​​the display device, the display resolution of the first viewing area may be controlled to be higher than the display resolution of the second viewing area. That is, the resolution of the second viewing area may be lower than that of the first viewing area.

[0110] Further, the display area has a first display area and a second display area different from the first display area. may be determined. The first viewing area and the second viewing area may be determined by the control device of the display device, or may be determined by an external control device. The resolution of areas with high priority may be controlled to be higher than the resolution of areas other than areas with high priority. That is, the resolution of areas with relatively low priority may be lowered.

[0111] It should be noted that AI may be used to determine the first field of view area and areas with high priority. AI is a model that is configured to estimate the angle of the line of sight from the eyeball image and the distance to the object ahead of the line of sight, using the eyeball image and the direction the eyeball was actually looking in the image as training data. It's okay. The AI ​​program may be possessed by a display device, a photoelectric conversion device, or an external device. If the external device has it, it is communicated to the display device via communication.

[0112] In the case of performing display control based on visual recognition detection, it can be preferably applied to smart glasses that further have a photoelectric conversion device that captures an image of the outside. Smart glasses can display captured external information in real time.

[0113] The photoelectric conversion device 100 of the above embodiment may be applied to electronic devices such as smartphones and tablets as exemplified below. FIG. 23 is a diagram showing an example of the appearance of an electronic device 120 equipped with the photoelectric conversion device 100 configured as a solid-state imaging device. 23A shows the front side of the electronic device 120, and FIG. 23B shows the rear side of the electronic device 120. As shown in FIG.

[0114] As shown in A of FIG. 23, a display 121 for displaying an image is arranged in the center of the surface of the electronic device 120 . Along the upper side of the surface of electronic device 120, front cameras 122-1 and 122-2 using photoelectric conversion device 100, IR light source 123 that emits infrared light, and visible light source 124 that emits visible light. are placed.

[0115] 23B, rear cameras 125-1 and 125-2 using photoelectric conversion device 100, IR light source 126 emitting infrared light, and , a visible light source 127 for emitting visible light is arranged.

[0116] By applying the above-described photoelectric conversion device 100 to the electronic device 120 configured in this manner, for example, an image with higher sensitivity can be captured. Note that the photoelectric conversion device 100 can also be applied to other electronic devices such as an infrared sensor, a ranging sensor using an active infrared light source, a security camera, and a personal or biometric authentication camera. This makes it possible to improve the sensitivity and performance of those electronic devices. Also, it is possible to reduce the power consumption of the system by reducing the light source power.

[0117] The invention is not limited to the embodiments described above, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, the claims are appended to make public the scope of the invention. [Description of symbols]

[0118] 12: pixel array region, 13: peripheral region, 301: sensor substrate, 302: first semiconductor layer, 303: first wiring structure, S1: first surface, S2: second surface, 311: first semiconductor region, 315 : second semiconductor region, 1311: third semiconductor region, 1315: fourth semiconductor region, 1313: fifth semiconductor region

Claims

1. A photoelectric conversion device having a semiconductor layer including a pixel array region having a plurality of pixels and a peripheral region arranged around the pixel array region, the semiconductor layer has a first surface and a second surface; Each pixel in the pixel array region includes a first semiconductor region of a first conductivity type arranged on the first surface side and a second semiconductor region of a second conductivity type arranged on the second surface side, and a predetermined voltage capable of causing an avalanche multiplication operation is supplied between the first semiconductor region and the second semiconductor region, the peripheral region includes a third semiconductor region of the first conductivity type arranged on the first surface side, a fourth semiconductor region of the second conductivity type arranged apart from the third semiconductor region, and a fifth semiconductor region of the first conductivity type arranged between the third semiconductor region and the fourth semiconductor region and adjacent to the third semiconductor region, a concentration of the first conductive type impurity in the fifth semiconductor region is lower than a concentration of the first conductive type impurity in the third semiconductor region, and a voltage is supplied between the third semiconductor region and the fourth semiconductor region. A photoelectric conversion device comprising:

2. the voltage supplied between the third semiconductor region and the fourth semiconductor region is the predetermined voltage; 2. The photoelectric conversion device according to claim 1.

3. The fifth semiconductor region is disposed so as to surround the third semiconductor region.

3. The photoelectric conversion device according to claim 1 or 2.

4. A photoelectric conversion device having a semiconductor layer including a pixel array region having a plurality of pixels and a peripheral region arranged around the pixel array region, the semiconductor layer has a first surface and a second surface; Each pixel in the pixel array region includes a first semiconductor region of a first conductivity type arranged on the first surface side and a second semiconductor region of a second conductivity type arranged on the second surface side, and a predetermined voltage capable of causing an avalanche multiplication operation is supplied between the first semiconductor region and the second semiconductor region, the peripheral region includes a third semiconductor region of the first conductivity type disposed on the first surface side, and a fourth semiconductor region of the second conductivity type disposed apart from the third semiconductor region, a voltage lower than the predetermined voltage is supplied between the third semiconductor region and the fourth semiconductor region; A photoelectric conversion device comprising:

5. a depth of the third semiconductor region from the first surface is equal to a depth of the first semiconductor region from the first surface; 5. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

6. A depth of the fourth semiconductor region from the first surface is equal to a depth of the second semiconductor region from the first surface.

6. The photoelectric conversion device according to claim 5.

7. a pinning layer disposed in contact with the second semiconductor region and the fourth semiconductor region; 7. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

8. the second conductivity type isolation region is disposed between the pixel array region and the peripheral region; 8. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

9. the fourth semiconductor region and the isolation region are electrically connected to each other; 9. The photoelectric conversion device according to claim 8.

10. An insulating isolation portion is provided in the isolation region.

10. The photoelectric conversion device according to claim 8 or 9.

11. The insulating isolation portion is disposed so as to penetrate the semiconductor layer. The photoelectric conversion device according to claim 10 .

12. the insulating separation portion is disposed so as to electrically separate the separation region into a first separation region on the side of the pixel array region and a second separation region on the side of the peripheral region. The photoelectric conversion device according to claim 11 .

13. a first conductive path for applying a potential to the first isolation region and a second conductive path for applying a potential to the second isolation region are provided in a wiring structure laminated on the semiconductor layer; 13. The photoelectric conversion device according to claim 12.

14. the first conductive path and the second conductive path are electrically connected in the wiring structure.

14. The photoelectric conversion device according to claim 13.

15. A groove is provided in the separation region; a pinning layer disposed in contact with the second semiconductor region and the fourth semiconductor region and covering a surface of the groove; 15. The photoelectric conversion device according to claim 8,

16. the second conductivity type isolation region is disposed between adjacent pixels in the plurality of pixels; 16. The photoelectric conversion device according to claim 8,

17. Further comprising a light-shielding film disposed on the second surface, the light-shielding film is electrically connected to the fourth semiconductor region; 17. The photoelectric conversion device according to claim 1,

18. a plurality of third semiconductor regions including the third semiconductor region are arranged at a predetermined pitch in the peripheral region; the predetermined pitch is greater than an arrangement pitch of the plurality of pixels; 18. The photoelectric conversion device according to claim 1,

19. The fifth semiconductor region is disposed spaced apart from the fourth semiconductor region.

4. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

20. The fourth semiconductor region includes a portion extending from the second surface to the first surface, the extending portion is disposed between the first semiconductor region and the third semiconductor region.

20. The photoelectric conversion device according to claim 1,

21. An end of the extending portion is spaced from the first surface.

21. The photoelectric conversion device according to claim 20.

22. The photoelectric conversion device according to any one of claims 1 to 21, and a signal processing unit that processes a signal output from the photoelectric conversion device.

Images