Semiconductor package

Abstract

To provide a circuit board in which the line width and space of an electrode layer arranged on a core layer are miniaturized, and a semiconductor package including the same.SOLUTION: On a circuit board, a core layer 100 includes a first insulating layer 110 including a top surface and a bottom surface, a first through electrode 140 penetrating through the upper and lower surfaces of the first insulating layer, and a first electrode layer 120 disposed on the top surface of the first insulating layer and the top surface of the first through electrode. The first electrode layer includes a first region R1 arranged on the upper surface of the first insulating layer and a second region R2 arranged on the upper surface of a through electrode layer, and the thickness of the first region of the first electrode layer is different from the thickness of the second region of the first electrode layer.SELECTED DRAWING: Figure 2a

Description

[Technical Field]

[0001] The embodiments relate to semiconductor packages, and more particularly to semiconductor packages including a core layer. [Background technology]

[0002] Recently, circuit boards have been provided as multilayer circuit boards, which are manufactured by forming inner electrode layers on the surface of a core substrate such as a copper clad laminate (CCL) using an additive or subtractive process, and then laminating insulating layers in order to form outer electrode layers using the same process as the inner electrode layers.

[0003] Meanwhile, the circuit board includes a through electrode. The through electrode electrically connects electrode layers arranged on different layers. For example, the through electrode electrically connects an inner electrode layer and an outer electrode layer. That is, the circuit board forms the through electrode by forming a through hole in the core substrate and chemically and / or electrically plating the inside of the formed through hole.

[0004] In conventional circuit boards, the thickness of the core substrate is increased to improve strength and warpage characteristics. For example, the thickness of the core substrate is 200 μm or more. Preferably, the thickness of the conventional core substrate is in the range of 400 μm to 800 μm. In this case, when the thickness of the core substrate increases, the size of the drill used in the process of forming through holes penetrating the core substrate also increases. Furthermore, when the drill size increases, there is a problem in that the size of the through holes and the through electrodes correspondingly increases.

[0005] Furthermore, conventional circuit boards have limitations in miniaturizing the electrode layers due to the increased thickness of the core substrate and the increased size of the through electrodes. For example, the line width of the electrode layers of conventional circuit boards exceeds 30 μm. For example, the space between electrode layers of conventional circuit boards exceeds 30 μm.

[0006] Therefore, in a circuit board including the core substrate, a solution is required that can reduce the line width and space of the electrode layer while reducing the size of the through electrodes. Summary of the Invention [Problem to be solved by the invention]

[0007] In the embodiments, a circuit board including a core layer with a new structure and a semiconductor package including the same are provided.

[0008] In addition, the present invention provides a circuit board including a core layer made up of a plurality of insulating layers made of different materials, and a semiconductor package including the same.

[0009] In addition, the present invention provides a circuit board in which the line width and spacing of an electrode layer disposed on a core layer are miniaturized, and a semiconductor package including the same.

[0010] In the proposed embodiments, the technical problems to be solved are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by a person having ordinary skill in the art to which the embodiments pertain from the following description. [Means for solving the problem]

[0011] A semiconductor package according to an embodiment includes a first insulating layer including a through hole, an insulating member disposed in the through hole of the first insulating layer, a first electrode layer disposed on the insulating member, a second insulating layer disposed on the first electrode layer, and a first through electrode that penetrates the second insulating layer, wherein the first through electrode vertically overlaps the first electrode layer and the insulating member.

[0012] The semiconductor package further includes a second through electrode disposed in the through hole and surrounding at least a portion of the insulating member, and the first electrode layer is disposed on the second through electrode and the insulating member.

[0013] The first electrode layer includes a first region that vertically overlaps the first insulating layer and a second region that vertically overlaps the insulating member, and the thickness of the first region of the first electrode layer is different from the thickness of the second region of the first electrode layer.

[0014] Furthermore, the thickness of the first region of the first electrode layer is greater than the thickness of the second region of the first electrode layer.

[0015] The first electrode layer further includes a third region provided between the first region and the second region and vertically overlapping the first through electrode, and the thickness of the third region of the first electrode layer is greater than the thickness of the second region.

[0016] The upper surface of the insulating member is located higher than the upper surface of the first insulating layer.

[0017] The first electrode layer also includes a first metal layer disposed on an upper surface of the first insulating layer, and a second metal layer disposed on the first metal layer and the first through-electrode.

[0018] The second metal layer of the first electrode layer has a first region and a second region that are different in thickness, and a lower surface of the second metal layer includes a recess that is recessed toward the insulating member.

[0019] The first insulating layer includes a copper clad laminate (CCL).

[0020] The first insulating layer has a thickness in the range of 80 μm to 150 μm.

[0021] The semiconductor package further includes a second electrode layer disposed on the first through-electrode, the second electrode layer vertically overlapping the first through-electrode.

[0022] The second insulating layer includes one of a prepreg and an Ajinomoto Build-up Film (ABF).

[0023] The first insulating layer and the second insulating layer are core layers of the circuit board.

[0024] The first through electrode, the first electrode layer, and the second through electrode are through-core electrodes that penetrate the upper and lower surfaces of the core layer.

[0025] Furthermore, the first through electrodes are not disposed in areas of the second insulating layer that do not vertically overlap the second through electrodes.

[0026] The inclination of the side surface of the second through electrode is perpendicular to the upper surface or the lower surface of the first insulating layer.

[0027] Furthermore, the shape of the first through electrode is different from the shape of the second through electrode.

[0028] The semiconductor package further includes a third insulating layer disposed on the second insulating layer, a third electrode layer disposed on the third insulating layer, a connection portion disposed on the third electrode layer, and a semiconductor element disposed on the connection portion. [Effects of the Invention]

[0029] The circuit board in the embodiment includes a through electrode layer penetrating a first insulating layer and a first electrode layer disposed on the first insulating layer. The through electrode layer includes a first through electrode and an insulating member disposed on the inner wall of a first through hole penetrating the first insulating layer. The first electrode layer includes a first region R1 that does not vertically overlap the insulating member and a second region R2 that vertically overlaps the insulating member. The first region R1 of the first electrode layer has a multilayer structure including a first metal layer and a second metal layer. The second region R2 of the first electrode layer may include only the second metal layer. For example, the number of metal layers in the first region R1 of the first electrode layer may be greater than the number of metal layers in the second region R2 of the first electrode layer.

[0030] As a result, the thickness of the first region R1 of the first electrode layer may be greater than the thickness of the second region R2. Preferably, the thickness of the first electrode layer in the region that vertically overlaps the insulating member may be smaller than the thickness of the first electrode layer in the region that does not vertically overlap the insulating member. As a result, in the embodiment, the thickness of the first electrode layer in the second region R2 can be reduced compared to the comparative example. As a result, in the embodiment, the plating process time for forming the first electrode layer can be reduced, and further the cost of the plating process can be reduced.

[0031] In the embodiment, the core layer of the circuit board is not formed solely of a copper clad laminate as described above, but is formed of a combination of a copper clad laminate and a prepreg or ABF. This allows the thickness of the electrode layers disposed on the upper and lower surfaces of the core layer of the circuit board to be reduced. Furthermore, in the embodiment, the line width and spacing of the electrode layers disposed on the upper and lower surfaces of the core layer of the circuit board can be reduced. This allows the electrode layers disposed on the upper and lower surfaces of the core layer to be miniaturized, thereby reducing the overall thickness of the circuit board. [Brief explanation of the drawings]

[0032] [Figure 1] FIG. 10 is a diagram showing a circuit board according to a comparative example. [Figure 2a] FIG. 2 is a diagram showing a circuit board according to the first embodiment. [Figure 2b] FIG. 10 is a diagram showing a circuit board according to a second embodiment. [Figure 3] FIG. 2 is a diagram showing the overall layer structure of a core layer in the circuit board according to the embodiment. [Figure 4] FIG. 2 is a diagram showing the overall layer structure of the circuit board according to the embodiment. [Figure 5] 1A and 1B are diagrams illustrating a semiconductor package according to an embodiment. [Figure 6] 4A to 4C are diagrams for explaining a method for manufacturing the circuit board according to the embodiment shown in FIG. 3 in the order of steps. [Figure 7]4A to 4C are diagrams for explaining a method for manufacturing the circuit board according to the embodiment shown in FIG. 3 in the order of steps. [Figure 8] 4A to 4C are diagrams for explaining a method for manufacturing the circuit board according to the embodiment shown in FIG. 3 in the order of steps. [Figure 9] 4A to 4C are diagrams for explaining a method for manufacturing the circuit board according to the embodiment shown in FIG. 3 in the order of steps. [Figure 10] 4A to 4C are diagrams for explaining a method for manufacturing the circuit board according to the embodiment shown in FIG. 3 in the order of steps. [Figure 11] 4A to 4C are diagrams for explaining a method for manufacturing the circuit board according to the embodiment shown in FIG. 3 in the order of steps. [Figure 12] 4A to 4C are diagrams for explaining a method for manufacturing the circuit board according to the embodiment shown in FIG. 3 in the order of steps. [Figure 13] 4A to 4C are diagrams for explaining a method for manufacturing the circuit board according to the embodiment shown in FIG. 3 in the order of steps. [Figure 14] 4A to 4C are diagrams for explaining a method for manufacturing the circuit board according to the embodiment shown in FIG. 3 in the order of steps. [Figure 15] 4A to 4C are diagrams for explaining a method for manufacturing the circuit board according to the embodiment shown in FIG. 3 in the order of steps. [Figure 16] 4A to 4C are diagrams for explaining a method for manufacturing the circuit board according to the embodiment shown in FIG. 3 in the order of steps. DETAILED DESCRIPTION OF THE INVENTION

[0033] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0034] However, the technical concept of the present invention is not limited to the described embodiments, but may be embodied in various different forms, and one or more of the components of the embodiments may be selectively combined or substituted within the scope of the technical concept of the present invention.

[0035] Furthermore, unless otherwise clearly defined and described, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as meanings commonly understood by those of ordinary skill in the art to which the present invention belongs, and commonly used terms such as predefined terms may be interpreted in light of the contextual meaning of the relevant art. Furthermore, the terms used in the embodiments of the present invention are intended to describe the embodiments and do not limit the present invention.

[0036] In this specification, unless otherwise stated in the phrase, the singular can also include the plural, and when referring to "A and (and) at least one (or more) of B and C," it can include one or more of all combinations that can be combined with A, B, and C. Furthermore, terms such as first, second, A, B, (a), (b), etc. can be used to describe components of the present invention.

[0037] Such terms are used merely to distinguish a component from other components, and are not intended to limit the essence, order, or sequence of the components. When a component is described as being "coupled," "bonded," or "connected" to another component, it can include not only a case where the component is directly coupled, coupled, or connected to the other component, but also a case where the component is "coupled," "coupled," or "connected" by another component between the component and the other component.

[0038] Furthermore, when it is stated that something is formed or placed "above or below" each component, "above" or "below" includes not only the case where two components are in direct contact with each other, but also the case where one or more other components are formed or placed between the two components. Furthermore, when it is expressed as "above" or "below," it can mean not only the upward direction based on one component, but also the downward direction.

[0039] -Comparative Example (Conventional Structure and Its Problems)- Fig. 1 is a diagram showing a circuit board according to a comparative example, and in particular, Fig. 1 is a diagram showing a core layer in the circuit board of the comparative example.

[0040] Problems with the circuit board including the core layer according to the comparative example will be described below with reference to FIG.

[0041] Before describing the comparative example, it is noted that circuit boards are required to have a higher density as electronic devices become more functional and semiconductor devices become more highly integrated, and therefore circuit boards have a multi-layer structure.

[0042] Products to which such multi-layer circuit boards are applied include FCBGA (Flip Chip Ball Grid Array) and FCCSP (Flip-Chip Chip Scale Package), and the circuit boards applied to FCBGA and FCCSP may include a core layer.

[0043] The core layer has a thickness of 200 μm or more to realize a multi-layer build-up. Furthermore, the core layer has through electrodes formed therein for electrical connection between the electrode layers. The through electrodes can be formed by filling through holes that penetrate the upper and lower surfaces of the core layer with a conductive material. However, when the core layer has a thickness of 300 μm or more, the process of forming the through holes and / or the process of forming the through electrodes in the comparative example have the following problems.

[0044] The circuit board of the comparative example includes an insulating layer 10, a first electrode layer 20, a second electrode layer 30, and a through electrode layer.

[0045] The insulating layer 10 is a core layer and may be a copper clad laminate (CCL). The insulating layer 10 may have a thickness t of 200 μm or more. In this case, through holes may be formed in the insulating layer 10 having a thickness t of 200 μm or more by one of the following two methods.

[0046] That is, the through hole can be formed by performing a laser process on both the upper and lower sides of the insulating layer 10. The vertical cross section of the through hole formed in this manner has an hourglass shape. In other words, if the thickness of the insulating layer 10 exceeds 200 μm, it is difficult to form a through hole penetrating the insulating layer 10 only on one of the upper and lower sides. Therefore, when forming a through hole in an insulating layer 10 such as a core layer using a laser, a process of forming the through hole on both the upper and lower sides of the insulating layer 10 is generally performed. For example, when forming a through hole in the insulating layer 10 through laser processing, a first hole part of the through hole is formed on the upper side of the insulating layer 10 according to the target hole width and hole depth, and a second hole part connected to the first hole part of the through hole is formed on the lower side of the insulating layer 10.

[0047] However, the through hole has an hourglass shape, and therefore, the width of the through hole decreases with increasing distance from the upper and lower surfaces of the insulating layer 10. In this case, the target width of the through hole is determined based on the width of the center where the first hole part and the second hole part are connected. As a result, the through hole has widths greater than the target width in regions adjacent to the upper surface and the lower surface of the insulating layer 10, resulting in a problem of an increased overall area of ​​the through hole. For example, if the target width of the through hole is determined based on the widths of the first and second hole parts, a problem of incomplete connection may occur, in which the first and second hole parts are not connected to each other.

[0048] Therefore, a CNC (Computer Numerical Control) drill is generally used to form a through hole in the insulating layer 10 of the core layer. When a CNC drill is used, the through hole has the same width on both the top and bottom surfaces. That is, the through hole has a columnar shape with the same width on both the top and bottom surfaces.

[0049] In this case, if the through hole has a columnar shape, it is difficult to uniformly fill the through hole with a conductive material. That is, when plating is performed to fill a columnar through hole, plating is completed earlier on the outside of the through hole than on the center of the through hole, resulting in the presence of an unplated space (e.g., a void) in the center. In addition, the upper and lower surfaces of the through electrode layer formed in the through hole are not flat but have curved surfaces (e.g., concave or convex curved surfaces toward the center of the through hole). Furthermore, if the upper and lower surfaces of the through electrode layer have curved surfaces, the flatness of the substrate is reduced, which can result in poor alignment when an additional electrode layer is formed.

[0050] To solve this problem, in the comparative example, the through holes are filled by a hole plugging method, so that the through electrode layer of the circuit board in the comparative example includes a first through electrode 40 formed on the inner wall of the through hole and an insulating member 50 filling the through hole.

[0051] On the other hand, the circuit board of the comparative example includes a first electrode layer 20 disposed on the upper surface of the insulating layer 10. In this case, the first electrode layer 20 is disposed on the upper surface of the insulating layer 10, the upper surface of the first through-hole electrode 40, and the upper surface of the insulating member 50. For example, the first electrode layer 20 includes a first portion disposed on the upper surface of the insulating layer 10, a second portion disposed on the upper surface of the first through-hole electrode 40, and a third portion disposed on the upper surface of the insulating member 50. The first to third portions of the first electrode layer 20 have the same thickness.

[0052] The circuit board of the comparative example also includes a second electrode layer 30 disposed on the lower surface of the insulating layer 10. In this case, the second electrode layer 30 is disposed on the lower surface of the insulating layer 10, the lower surface of the first through-hole electrode 40, and the lower surface of the insulating member 50. For example, the second electrode layer 30 includes a first portion disposed on the lower surface of the insulating layer 10, a second portion disposed on the lower surface of the first through-hole electrode 40, and a third portion disposed on the lower surface of the insulating member 50. The first to third portions of the second electrode layer 30 have the same thickness.

[0053] As described above, the first electrode layer 20 and the second electrode layer 30 in the comparative example are disposed on the insulating layer 10 having a thickness t of 200 μm or more, and therefore increase in proportion to the thickness of the insulating layer 10. Furthermore, the first to third portions of the first electrode layer 20 and the second electrode layer 30 have the same thickness, which increases the manufacturing cost for forming the first electrode layer 20 and the second electrode layer 30.

[0054] Furthermore, in the circuit board of the comparative example, the thickness of the first electrode layer 20 and the thickness of the second electrode layer 30 increase according to the thickness t of the insulating layer 10. As the thickness of the first electrode layer 20 increases, the line width and spacing of the first electrode layer 20 also increase. For example, in the comparative example, the line width of the first electrode layer 20 exceeds 30 μm, and the spacing between the plurality of first electrode layers 20 exceeds 30 μm. For example, in the comparative example, the line width of the second electrode layer 30 exceeds 30 μm, and the spacing between the plurality of second electrode layers 30 exceeds 30 μm.

[0055] As described above, in the comparative example, there is a limit to miniaturizing the line width and space of the first electrode layer 20 and the second electrode layer 30 disposed on the surface of the insulating layer 10 that constitutes the core layer.

[0056] This allows the first and second electrode layers to have thicknesses that vary horizontally, and also allows the line widths and spaces of the first and second electrode layers disposed on the surface of the core layer to be reduced.

[0057] As a result, in the embodiment, a through electrode with improved electrical and physical reliability can be formed inside a through hole formed in a core layer having a thickness of 300 μm or more. For example, in the embodiment, a circuit board including a through electrode with a new structure and a package substrate including the same are provided.

[0058] -Electronic Devices- Before describing the embodiments, a package substrate having a structure in which a chip is mounted on a circuit board according to the embodiments can be included in an electronic device.

[0059] In this case, the electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to a package substrate according to the embodiment. Various chips may be mounted on the package substrate. Mainly, memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as a central processor (e.g., CPU), graphics processor (e.g., GPU), digital signal processor, encryption processor, microprocessor, and microcontroller; and logic chips such as an analog-to-digital converter and an application-specific integrated circuit (ASIC).

[0060] In addition, the present invention provides a package substrate that can mount at least two different types of chips on one substrate while reducing the thickness of the package substrate connected to the main board of the electronic device.

[0061] In this case, the electronic device may be a smartphone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automobile, etc. However, it is not limited to these, and it may also be any other electronic device that processes data.

[0062] -Circuit board- Fig. 2a is a diagram showing a circuit board according to an embodiment. For example, Fig. 2 is a diagram showing a part of a core layer in a circuit board according to an embodiment. That is, the core layer of the circuit board according to the embodiment is composed of a plurality of insulating layers. Fig. 2a may also show an insulating layer and an electrode layer arranged at the center of the core layer composed of a plurality of insulating layers.

[0063] Referring to FIG. 2 a, the circuit board may include a first insulating layer 110 , a first electrode layer 120 , a second electrode layer 130 , a first through electrode 140 , and an insulating member 150 .

[0064] The circuit board of the embodiment may have a multi-layer structure. For example, the circuit board of the embodiment may include multiple insulating layers. However, FIG. 2 may mainly show the first insulating layer among the multiple insulating layers constituting the core layer of the circuit board having a multi-layer structure.

[0065] The first insulating layer 110 may be a core layer. For example, the first insulating layer 110 may be a rigid insulating layer or a copper clad lamination (CCL) in which copper foils are laminated on both sides of an insulating layer.

[0066] In particular, a copper clad laminate is generally a disc from which a circuit board is manufactured, and is a laminate in which copper foil is applied to an insulating layer, and depending on the application, can include glass / epoxy copper clad laminates, heat-resistant resin copper clad laminates, paper / phenolic copper clad laminates, high-frequency copper clad laminates, flexible copper clad laminates (e.g., polyimide films), composite copper clad laminates, etc. In this case, the first insulating layer 110 of the embodiment can be a glass / epoxy copper clad laminate for manufacturing double-sided circuit boards and multilayer circuit boards.

[0067] The glass / epoxy copper clad laminate consists of a reinforcing substrate made of glass fiber or organic fiber impregnated with epoxy resin and copper foil. Glass / epoxy copper clad laminates are classified by the reinforcing substrate, and generally graded according to the reinforcing substrate and heat resistance, such as FR-1 to FR-5, according to the standards established by the National Electrical Manufacturers Association (NEMA). Among these grades, FR-4 is the most widely used, but recently, there has been an increasing demand for FR-5, which has improved glass transition temperature (Tg) characteristics of the resin.

[0068] The first insulating layer 110 may have a constant thickness T1. In this case, the thickness T1 of the first insulating layer 110 may be smaller than the thickness of the core layer of the comparative example. Preferably, the thickness T1 of the first insulating layer 110 may be 150 μm or less. That is, the core layer of the comparative example had a thickness of 200 μm or more. As a result, the circuit board of the comparative example had problems such as an increased size of the through holes formed in the core layer and an increased thickness, line width, and space of the electrode layers disposed on the upper and lower surfaces of the insulating layer.

[0069] As a result, in the embodiment, the core layer is configured with a plurality of insulating layers, and the first insulating layer 110 configured as a copper clad laminate has a thickness T1 of 150 μm or less. As a result, in the embodiment, the width of the through hole TH1 penetrating the first insulating layer 110 can be reduced in accordance with the reduction in the thickness T1 of the first insulating layer 110. Also, in the embodiment, the thickness, line width, and space of each of the first electrode layer 120 and the second electrode layer 130 can be reduced in accordance with the reduction in the thickness T1 of the first insulating layer 110.

[0070] Preferably, the thickness T1 of the first insulating layer 110 may be in the range of 80 μm to 150 μm. For example, the thickness T1 of the first insulating layer 110 may be in the range of 90 μm to 148 μm. For example, the thickness T1 of the first insulating layer 110 may be in the range of 100 μm to 145 μm.

[0071] If the thickness T1 of the first insulating layer 110 is less than 80 μm, the rigidity and warpage characteristics of the circuit board may be reduced. Also, if the thickness T1 of the first insulating layer 110 is more than 150 μm, the degree of reduction in the width of the through holes formed in the first insulating layer 110 may be insignificant compared to the comparative example. Also, if the thickness T1 of the first insulating layer 110 is more than 150 μm, it may be difficult to reduce the thickness, line width, and spacing of the first electrode layer 120 and the second electrode layer 130 disposed on the first insulating layer 110.

[0072] The first electrode layer 120 is disposed on the upper surface of the first insulating layer 110 .

[0073] In addition, the second electrode layer 130 is disposed on the lower surface of the first insulating layer 110 .

[0074] At this time, the first electrode layer 120 and the second electrode layer 130 may be manufactured by a typical circuit board manufacturing process such as an additive process, a subtractive process, a modified semi-additive process (MSAP), a semi-additive process (SAP), etc. At this time, the first electrode layer 120 and the second electrode layer 130 may have different numbers of layers depending on the manufacturing process.

[0075] For example, when the first electrode layer 120 and the second electrode layer 130 are manufactured using the SAP method, the first electrode layer 120 and the second electrode layer 130 may have a two-layer structure. Furthermore, when the first electrode layer 120 and the second electrode layer 130 are manufactured using the MSAP method, the first electrode layer 120 and the second electrode layer 130 may have a three-layer structure including a copper foil layer. Hereinafter, the first electrode layer 120 and the second electrode layer 130 will be described as being manufactured using the SAP method. However, the embodiments are not limited thereto. For example, when the first electrode layer 120 and the second electrode layer 130 are manufactured using the MSAP method, the first metal layer of each of the first electrode layer 120 and the second electrode layer 130 may have a two-layer structure including a copper foil layer and a chemical copper plating layer.

[0076] The first electrode layer 120 may be configured in multiple layers. For example, the first electrode layer 120 may include a first metal layer 121 disposed on the upper surface of the first insulating layer 110 and a second metal layer 122 disposed on the first metal layer 121.

[0077] The second electrode layer 130 may be configured in multiple layers. For example, the second electrode layer 130 may include a third metal layer 131 disposed on the lower surface of the first electrode layer 120 and a fourth metal layer 132 disposed on the lower surface of the third metal layer 131.

[0078] The first metal layer 121 and the second metal layer 122 of the first electrode layer 120 and the third metal layer 131 and the fourth metal layer 132 of the second electrode layer 130 may each be made of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). For example, the first metal layer 121 and the second metal layer 122 of the first electrode layer 120 and the third metal layer 131 and the fourth metal layer 132 of the second electrode layer 130 may each be made of a paste or solder paste containing at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn), which has excellent bonding strength. Preferably, the first metal layer 121 and the second metal layer 122 of the first electrode layer 120 and the third metal layer 131 and the fourth metal layer 132 of the second electrode layer 130 may each be made of copper (Cu), which has high electrical conductivity and is relatively inexpensive.

[0079] In the above description, the first metal layer 121 of the first electrode layer 120 and the third metal layer 131 of the second electrode layer 130 are described as separate metal layers to distinguish the first electrode layer 120 from the second electrode layer 130. However, this is not limited to this. For example, the first metal layer 121 of the first electrode layer 120, the third metal layer 131 of the second electrode layer 130, and the first through electrode 140 may essentially represent a single metal layer. For example, in the embodiment, a through hole TH1 is formed in the first insulating layer 110, and a chemical copper plating layer is formed by plating the upper surface of the first insulating layer 110, the lower surface of the first insulating layer 110, and the inner wall of the through hole TH1. The first metal layer 121 of the first electrode layer 120, the third metal layer 131 of the second electrode layer 130, and the first through electrode 140 may represent the formed chemical copper plating layer. However, for convenience of explanation, the first metal layer 121 of the first electrode layer 120, the third metal layer 131 of the second electrode layer 130, and the through electrode 140 will be described as separate metal layers.

[0080] Meanwhile, a through electrode layer is disposed in the through hole TH1 penetrating the first insulating layer 110. The through electrode layer may refer to a material layer filling the inside of the through hole TH1.

[0081] In this case, the through hole TH1 may penetrate through the upper and lower surfaces of the first insulating layer 110. The width of the through hole TH1 in a region adjacent to the upper surface of the first insulating layer 110 and the width of the region adjacent to the lower surface of the first insulating layer 110 may be the same. Alternatively, the width of the through hole TH1 may not change from the region adjacent to the upper surface of the first insulating layer 110 to the region adjacent to the lower surface of the first insulating layer 110. Preferably, the through hole TH1 may have a columnar shape whose width does not change in the thickness direction.

[0082] The through electrode layer can be disposed in the through hole TH1 having the columnar shape.

[0083] The through electrode layer includes a first through electrode 140 disposed on an inner wall of the through hole TH1. The first through electrode 140 may include an electrically conductive metal material. For example, the first through electrode 140 may be made of the same metal material as the first metal layer 121 of the first electrode layer 120 and the third metal layer 131 of the second electrode layer 130.

[0084] The through electrode layer may also include the insulating member 150 disposed in the through hole TH1. The insulating member 150 may be disposed to fill the inside of the through hole TH1. Preferably, a portion of the through hole TH1 may be filled with the first through electrode 140, and the remaining portion of the through hole TH1 may be filled with the insulating member 150. The insulating member 150 may be formed of plugging ink, which is a paste made of an insulating layer ink material. Thus, the insulating member 150 may be referred to as a hole plugging layer. However, embodiments are not limited thereto, and the insulating member 150 may also include a conductive paste containing conductive metal powder.

[0085] The insulating member 150 is disposed in the through hole TH1. The insulating member 150 may be surrounded by the first through electrode 140. For example, the first through electrode 140 may be provided to surround at least a portion of the insulating member 140. Preferably, the first through electrode 140 may be provided to surround the upper surface, lower surface, and side surfaces of the insulating member 140.

[0086] The insulating member 150 may protrude above and below the through-hole TH1.

[0087] For example, the upper surface of the insulating member 150 may be positioned higher than the upper surface of the first insulating layer 110. Also, the lower surface of the insulating member 150 may be positioned lower than the lower surface of the first insulating layer 110.

[0088] In this case, at least a portion of the first electrode layer 120 may be in contact with the insulating member 150. For example, at least a portion of the first electrode layer 120 may overlap the insulating member 150 vertically.

[0089] The thickness of the first electrode layer 120 in the region vertically overlapping the insulating member 150 may be different from the thickness of the region not vertically overlapping the insulating member 150 .

[0090] For example, the first metal layer 121 of the first electrode layer 120 is disposed on the upper surface of the first insulating layer 110. In addition, the second metal layer 122 of the first electrode layer 120 is disposed on the upper surface of the first metal layer 121 of the first electrode layer 120 and the upper surface of the insulating member 150.

[0091] In this case, the first electrode layer 120 includes a first region R1 that does not vertically overlap the insulating member 150 and a second region R2 that vertically overlaps the insulating member 150.

[0092] The first region R1 of the first electrode layer 120 has a multi-layer structure including the first metal layer 121 and the second metal layer 122. The second region R2 of the first electrode layer 120 may include only the second metal layer 122. For example, the number of metal layers in the first region R1 of the first electrode layer 120 may be greater than the number of metal layers in the second region R2 of the first electrode layer 120.

[0093] Therefore, the thickness of the first region R1 of the first electrode layer 120 may be greater than the thickness of the second region R2. Preferably, the thickness of the first electrode layer 120 in the region vertically overlapping with the insulating member 150 may be less than the thickness of the first electrode layer 120 in the region not vertically overlapping with the insulating member 150. As a result, in the embodiment, the thickness of the first electrode layer 120 in the second region R2 can be reduced compared to the comparative example. As a result, in the embodiment, the plating process time for forming the first electrode layer 120 can be reduced, and further the plating process cost can be reduced.

[0094] Correspondingly, at least a portion of the second electrode layer 130 may be in contact with the insulating member 150. For example, at least a portion of the second electrode layer 130 may vertically overlap the insulating member 150.

[0095] The second electrode layer 130 may have a thickness different between a region that vertically overlaps the insulating member 150 and a region that does not vertically overlap the insulating member 150 .

[0096] For example, the third metal layer 131 of the second electrode layer 130 is disposed on the lower surface of the first insulating layer 110. In addition, the fourth metal layer 132 of the second electrode layer 130 is disposed on the lower surface of the third metal layer 131 and the lower surface of the insulating member 150.

[0097] In this case, the second electrode layer 130 includes a third region R3 that does not overlap the insulating member 150 vertically and a fourth region R4 that overlaps the insulating member 150 vertically.

[0098] The third region R3 of the second electrode layer 130 has a multi-layer structure including the third metal layer 131 and the fourth metal layer 132. The fourth region R4 of the second electrode layer 130 may include only the fourth metal layer 132. For example, the number of metal layers in the third region R3 of the second electrode layer 130 may be greater than the number of metal layers in the fourth region R4 of the second electrode layer 130.

[0099] As a result, the thickness of the third region R3 of the second electrode layer 130 may be greater than the thickness of the fourth region R4. Preferably, the thickness of the second electrode layer 130 in the region that vertically overlaps the insulating member 150 may be less than the thickness of the second electrode layer 130 in the region that does not vertically overlap the insulating member 150. As a result, in the embodiment, the thickness of the fourth region R4 of the second electrode layer 130 can be reduced compared to the comparative example. As a result, in the embodiment, the plating process time for forming the second electrode layer 130 can be reduced, and further the plating process cost can be reduced.

[0100] FIG. 2b is a diagram showing a circuit board according to the second embodiment.

[0101] Referring to Figure 2b, the basic structure of the circuit board is the same as Figure 2a.

[0102] However, FIG. 2b may have a different structure of the electrode layer compared to FIG. 2a.

[0103] The first electrode layer 120-1 may have a multi-layer structure and may include the first metal layer 121 disposed on the upper surface of the first insulating layer 110 and the second metal layer 122-1 disposed on the first metal layer 121.

[0104] In this case, the first electrode layer 120 in the first embodiment has different thicknesses in the first region R1 and the second region R2, and the second metal layer 122 has the same thickness in the first region R1 and the second region R2.

[0105] In contrast, in the second embodiment, the first electrode layer 120-1 may have different thicknesses in the first region R1 and the second region R2, and the second metal layer 122-1 may also have different thicknesses in the first region R1 and the second region R2.

[0106] For example, the thickness of the first region R1 of the second metal layer 122-1 may be greater than the thickness of the second region R2 of the second metal layer 122-1. For example, the top surface of the insulating member 150 may be positioned higher than the top surface of the first metal layer 121 of the first electrode layer 120-1.

[0107] Therefore, the lower surface of the second metal layer 122-1 of the first electrode layer 120-1 may have a step. For example, among the lower surfaces of the second metal layer 122-1 of the first electrode layer 120-1, the lower surface that vertically overlaps the insulating member 150 may be positioned higher than the other lower surfaces.

[0108] For example, the lower surface of the second metal layer 122-1 may include a concave portion that is concave toward the insulating member 150. For example, the upper surface of the second metal layer 122-1 may include a convex portion that is convex toward the upper surface of the second metal layer 122-1.

[0109] The second electrode layer 130-1 may have a multi-layer structure, and may include a third metal layer 131 disposed on the lower surface of the first insulating layer 110 and a fourth metal layer 132-1 disposed on the third metal layer 131.

[0110] In this case, in the second electrode layer 130 in the first embodiment, the thicknesses of the third region R3 and the fourth region R4 are different from each other, and the thicknesses of the third region R3 and the fourth region R4 of the fourth metal layer 132 are the same.

[0111] In contrast, in the second embodiment, the second electrode layer 130-1 may have different thicknesses in the third region R3 and the fourth region R4, and the fourth metal layer 132-1 may also have different thicknesses in the third region R3 and the fourth region R4.

[0112] For example, the thickness of the third region R3 of the fourth metal layer 132-1 may be greater than the thickness of the fourth region R4 of the fourth metal layer 132-1. For example, the lower surface of the insulating member 150 may be located lower than the lower surface of the third metal layer 131 of the second electrode layer 130-1.

[0113] Therefore, the upper surface of the fourth metal layer 132-1 of the second electrode layer 130-1 may have a step. For example, among the upper surfaces of the fourth metal layer 132-1 of the second electrode layer 130-1, the upper surface that vertically overlaps the insulating member 150 may be positioned lower than the other upper surfaces.

[0114] For example, the upper surface of the fourth metal layer 132-1 may include a concave portion that is concave toward the insulating member 150. For example, the upper surface of the fourth metal layer 132-1 may include a convex portion that is convex toward the lower surface of the fourth metal layer 132-1.

[0115] The overall layer structure of the core layer in the circuit board according to the embodiment will be described below. Specifically, the first insulating layer, the first electrode layer, the second electrode layer, the first through electrode, and the insulating member shown in Fig. 2 can constitute a portion of the overall core layer of the circuit board.

[0116] FIG. 3 is a diagram showing the overall layer structure of the core layer in the circuit board according to the embodiment.

[0117] 3, the circuit board according to the embodiment includes a core layer 100. In this case, the core layer 100 may refer to a core substrate.

[0118] Preferably, the circuit board shown in Fig. 2a may represent a portion of the layer of the core substrate, for example, the circuit board in Fig. 2a may represent a layer disposed in the center of the overall layer structure of the core substrate.

[0119] However, the overall layer structure of the circuit board described below is not limited to that of FIG. 3, and the circuit board can also be manufactured by applying the structure of the core layer 100-1 of FIG. 2b instead of FIG. 2a.

[0120] In the example, unlike the comparative example, the core layer is not a single-layer copper clad laminate but has a multi-layer structure.

[0121] For example, the core layer 100 of the circuit board in the embodiment may include multiple insulating layers, and the total thickness T2 of the multiple insulating layers may correspond to the thickness t of the insulating layer 10 in the comparative example.

[0122] That is, in the embodiment, the thickness t of the insulating layer 10 of the comparative example is maintained, but the insulating layer is configured as multiple insulating layers containing different insulating materials. As a result, in the embodiment, the thickness, line width, and spacing of the electrode layer formed on the core layer can be reduced. As a result, in the embodiment, in a circuit board including the core layer 100, the electrode layer disposed on the surface of the core layer 100 can be miniaturized.

[0123] That is, the core layer 100 of the circuit board in the embodiment includes a first insulating layer 110 , a first electrode layer 120 , a second electrode layer 130 , a first through electrode 140 , and an insulating member 150 .

[0124] The core layer 100 of the circuit board includes a second insulating layer 161 disposed on the first insulating layer 110. The core layer 100 of the circuit board also includes a third insulating layer 162 disposed below the first insulating layer 110.

[0125] That is, the core layer 100 in the embodiment includes the first insulating layer 110 , the second insulating layer 161 , and the third insulating layer 162 .

[0126] In this case, the second insulating layer 161 and the third insulating layer 162 may be prepreg. Alternatively, the second insulating layer 161 and the third insulating layer 162 may be Ajinomoto Build-up Film (ABF).

[0127] That is, in the embodiment, a part of the core layer 100 is formed of a copper clad laminate, and the remaining part is formed of prepreg or ABF. As a result, in the core layer 100, electrode layers that essentially function as signal transmission wiring are disposed on the upper surface of the second insulating layer 161 and the lower surface of the third insulating layer 162.

[0128] In other words, the first electrode layer 120 and the second electrode layer 130 function as through-hole electrodes for interlayer signal transmission. Accordingly, the first electrode layer 120 is disposed in a region of the upper surface of the first insulating layer 110 where the first through-hole electrodes 140 are disposed. The first electrode layer 120 may not be disposed in a region where the first through-hole electrodes 140 are not disposed. For example, a general electrode layer includes pads and traces. The traces may also be disposed in a region of the upper surface of the first insulating layer 110 where the first through-hole electrodes 140 are not disposed. Alternatively, in the embodiment, the first electrode layer 120 may be selectively disposed only in a region where the first through-hole electrodes 140 are disposed. Correspondingly, the second electrode layer 130 may be disposed in a region of the lower surface of the first insulating layer 110 where the first through-hole electrodes 140 are disposed.

[0129] Meanwhile, the circuit board may include a second through electrode 181 penetrating the second insulating layer 161. The second through electrode 181 may be formed by filling a through hole penetrating the second insulating layer 161 with a conductive material. In this case, the through hole formed in the second insulating layer 161 may have a different shape from the through hole TH1 formed in the first insulating layer 110. Preferably, the through hole formed in the second insulating layer 161 may have a slope in which the width gradually decreases from the upper surface to the lower surface of the second insulating layer 161. For example, the through hole formed in the second insulating layer 161 may have a trapezoidal shape in which the width of the upper surface is greater than the width of the lower surface.

[0130] In this case, the second through-hole electrode 181 may vertically overlap the first through-hole electrode 140. Preferably, the second through-hole electrode 181 may be disposed in a region of the second insulating layer 161 that vertically overlaps the first through-hole electrode 140. In other words, the second through-hole electrode 181 may not be disposed in a region of the second insulating layer 161 that does not vertically overlap the first through-hole electrode 140. This is because the core layer of the embodiment includes the first insulating layer 110, the second insulating layer 161, and the third insulating layer 162.

[0131] The circuit board may also include a third through-electrode 182 penetrating the third insulating layer 162. The third through-electrode 182 may be formed by filling a through-hole penetrating the third insulating layer 162 with a conductive material. In this case, the through-hole formed in the third insulating layer 162 may have a different shape from the through-hole TH1 formed in the first insulating layer 110. Preferably, the through-hole formed in the third insulating layer 162 may have a slope in which the width gradually decreases from the lower surface to the upper surface of the third insulating layer 162. For example, the through-hole formed in the third insulating layer 162 may have a trapezoidal shape in which the width of the lower surface is greater than the width of the upper surface.

[0132] In this case, the third through-hole electrode 182 may vertically overlap the first through-hole electrode 140. Preferably, the third through-hole electrode 182 may be disposed in a region of the third insulating layer 162 that vertically overlaps the first through-hole electrode 140. In other words, the third through-hole electrode 182 may not be disposed in a region of the third insulating layer 162 that does not vertically overlap the first through-hole electrode 140.

[0133] In conclusion, the first through electrode 140, the second through electrode 181, and the third through electrode 182 in the embodiment may vertically overlap each other.

[0134] For example, when a plurality of first through electrodes 140 are arranged on the first insulating layer 110, the plurality of first through electrodes 140 may vertically overlap with a plurality of second through electrodes 181 and a plurality of third through electrodes 182, respectively.

[0135] For example, when a plurality of second through electrodes 181 are disposed in the second insulating layer 161, the second through electrodes 181 may vertically overlap the plurality of first through electrodes 140 and the plurality of third through electrodes 182, respectively.

[0136] For example, when a plurality of third through electrodes 182 are disposed in the third insulating layer 162, the third through electrodes 182 may vertically overlap the plurality of first through electrodes 140 and the plurality of second through electrodes 181, respectively.

[0137] As a result, in the example, the through electrode penetrating the core layer can have a multi-layer structure. For example, in the comparative example, the through electrode penetrating the core layer includes a first through electrode and an insulating member.

[0138] Alternatively, in the embodiment, the through electrode penetrating the core layer may include a first through electrode 140, an insulating member 150, a first electrode layer 120, a second electrode layer 130, a second through electrode 181, and a third through electrode 182.

[0139] Meanwhile, a third electrode layer 171 is disposed on the upper surface of the second insulating layer 161. A fourth electrode layer 172 is disposed on the lower surface of the third insulating layer 162.

[0140] Here, the third electrode layer 171 in the embodiment may refer to signal wiring arranged on the upper surface of the core layer. In the comparative example, the line width of the first electrode layer arranged on the upper surface of the core layer exceeds 30 μm, and the space between the multiple first electrode layers exceeds 30 μm. In contrast, the line width of the third electrode layer 171 arranged on the upper surface of the core layer in the embodiment may range from 5 μm to 15 μm. For example, the line width of the third electrode layer 171 arranged on the upper surface of the core layer in the embodiment may range from 6 μm to 13 μm. For example, the line width of the third electrode layer 171 arranged on the upper surface of the core layer in the embodiment may range from 7 μm to 12 μm. This is because the core layer in the embodiment is not made of a copper foil laminate, but is made of a combination of a copper foil laminate and a prepreg or ABF.

[0141] Furthermore, in the embodiment, the spacing between the multiple third electrode layers 171 arranged on the upper surface of the core layer can be in the range of 5 μm to 20 μm. For example, the spacing between the multiple third electrode layers 171 arranged on the upper surface of the core layer can be in the range of 6 μm to 19 μm. For example, the spacing between the multiple third electrode layers 171 arranged on the upper surface of the core layer can be in the range of 7 μm to 18 μm. This is because the core layer in the embodiment is not made of a copper foil laminate alone, but is made of a combination of a copper foil laminate and a prepreg or ABF.

[0142] Correspondingly, the line width of the fourth electrode layer 172 disposed on the lower surface of the core layer in the embodiment may be in the range of 5 μm to 15 μm. For example, the line width of the fourth electrode layer 172 disposed on the lower surface of the core layer in the embodiment may be in the range of 6 μm to 13 μm. For example, the line width of the fourth electrode layer 172 disposed on the lower surface of the core layer in the embodiment may be in the range of 7 μm to 12 μm. This is because the core layer in the embodiment is not made of a copper foil laminate, but is made of a combination of a copper foil laminate and a prepreg or ABF.

[0143] Furthermore, in the embodiment, the spacing between the multiple fourth electrode layers 172 arranged on the lower surface of the core layer can be in the range of 5 μm to 20 μm. For example, the spacing between the multiple fourth electrode layers 172 arranged on the lower surface of the core layer can be in the range of 6 μm to 19 μm. For example, the spacing between the multiple fourth electrode layers 172 arranged on the lower surface of the core layer can be in the range of 7 μm to 18 μm. This is because the core layer in the embodiment is not made of a copper foil laminate alone, but is made of a combination of a copper foil laminate and a prepreg or ABF.

[0144] In the embodiment, the core layer of the circuit board is not formed solely from a copper clad laminate as described above, but is formed from a combination of a copper clad laminate and a prepreg or ABF. This allows the thickness of the electrode layers disposed on the upper and lower surfaces of the core layer of the circuit board to be reduced. Furthermore, in the embodiment, the line width and spacing of the electrode layers disposed on the upper and lower surfaces of the core layer of the circuit board can be reduced. This allows the electrode layers disposed on the upper and lower surfaces of the core layer to be finer, thereby reducing the overall thickness of the circuit board.

[0145] FIG. 4 is a diagram showing the overall layer structure of the circuit board according to the embodiment.

[0146] 4, the circuit board may include the core layer 100 described in FIG 3. In addition, in the embodiment, the circuit board may further include an insulating layer and an electrode layer disposed on at least one surface of the core layer 100.

[0147] For example, the circuit board in the embodiment may have a multi-layer structure.

[0148] For example, the circuit board 200 in the embodiment may include a fourth insulating layer 210 disposed on the top surface of the core layer 100 .

[0149] In addition, the circuit board 200 in the embodiment may include a fifth insulating layer 220 disposed on the lower surface of the core layer 100 .

[0150] The circuit board 200 of the embodiment also includes a fifth electrode layer 220 disposed on the upper surface of the fourth insulating layer 210. The circuit board 200 of the embodiment also includes a fourth through electrode 230 that penetrates the fourth insulating layer 210. In this case, the fourth through electrode 230 may vertically overlap the first through electrode 140, the second through electrode 181, and the third through electrode 182 of the core layer 100, or may not vertically overlap. That is, the first through electrode 140, the second through electrode 181, and the third through electrode 182 disposed on the core layer 100 are all disposed to vertically overlap. This is because the through electrodes disposed on the core layer 100 are configured by a combination of the first through electrode 140, the second through electrode 181, and the third through electrode 182.

[0151] The fourth through-hole electrode 230 may include a 4-1 through-hole electrode that vertically overlaps the first through-hole electrode 140, the second through-hole electrode 181, and the third through-hole electrode 182. The fourth through-hole electrode 230 may also include a 4-2 through-hole electrode that does not vertically overlap the first through-hole electrode 140, the second through-hole electrode 181, and the third through-hole electrode 182. In this case, the 4-2 through-hole electrode may vertically overlap the third electrode layer 171 of the core layer 100.

[0152] The circuit board 200 of the embodiment also includes a sixth electrode layer 250 disposed on the lower surface of the fifth insulating layer 220. The circuit board 200 of the embodiment also includes a fifth through electrode 250 penetrating the fifth insulating layer 220. In this case, the fifth through electrode 250 may vertically overlap the first through electrode 140, the second through electrode 181, and the third through electrode 182 of the core layer 100, or may not vertically overlap them.

[0153] That is, the fifth through-hole electrode 250 may include a 5-1 through-hole electrode that vertically overlaps the first through-hole electrode 140, the second through-hole electrode 181, and the third through-hole electrode 182. The fifth through-hole electrode 250 may also include a 5-2 through-hole electrode that does not vertically overlap the first through-hole electrode 140, the second through-hole electrode 181, and the third through-hole electrode 182. In this case, the 5-2 through-hole electrode may vertically overlap the fourth electrode layer 172 of the core layer 100.

[0154] Meanwhile, the circuit board 200 may include a first protective layer 270 disposed on an upper surface of the fourth insulating layer 210 and a second protective layer 280 disposed on a lower surface of the fifth insulating layer 220 .

[0155] The first protective layer 270 may include an opening (not shown) that vertically overlaps with the upper surface of the fifth electrode layer 220. In addition, the second protective layer 280 may include an opening (not shown) that vertically overlaps with the lower surface of the sixth electrode layer 250.

[0156] The first and second protective layers 270 and 280 may be resist layers. For example, the first and second protective layers 270 and 280 may be solder resist layers including an organic polymer material. For example, the first and second protective layers 270 and 280 may include an epoxy acrylate resin. In particular, the first and second protective layers 270 and 280 may include a resin, a hardener, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. However, the embodiment is not limited thereto, and the first and second protective layers 270 and 280 may be any one of a photo solder resist layer, a coverlay, and a polymer material.

[0157] The first protective layer 270 and the second protective layer 280 may have a thickness of 1 μm to 20 μm. The first protective layer 270 and the second protective layer 280 may have a thickness of 1 μm to 15 μm. For example, the first protective layer 270 and the second protective layer 280 may have a thickness of 5 μm to 20 μm. If the thickness of the first protective layer 270 and the second protective layer 280 exceeds 20 μm, the thickness of the circuit board may increase. If the thickness of the first protective layer 270 and the second protective layer 280 is less than 1 μm, the electrode layers included in the circuit board may not be stably protected, which may result in a decrease in electrical reliability or physical reliability.

[0158] The circuit board in the embodiment includes a through electrode layer penetrating a first insulating layer and a first electrode layer disposed on the first insulating layer. The through electrode layer includes a first through electrode and an insulating member disposed on the inner wall of a first through hole penetrating the first insulating layer. The first electrode layer includes a first region R1 that does not vertically overlap the insulating member and a second region R2 that vertically overlaps the insulating member. The first region R1 of the first electrode layer has a multilayer structure including a first metal layer and a second metal layer. The second region R2 of the first electrode layer may include only the second metal layer. For example, the number of metal layers in the first region R1 of the first electrode layer may be greater than the number of metal layers in the second region R2 of the first electrode layer.

[0159] As a result, the thickness of the first region R1 of the first electrode layer may be greater than the thickness of the second region R2. Preferably, the thickness of the first electrode layer in the region that vertically overlaps the insulating member may be smaller than the thickness of the first electrode layer in the region that does not vertically overlap the insulating member. As a result, in the embodiment, the thickness of the first electrode layer in the second region R2 can be reduced compared to the comparative example. As a result, in the embodiment, the plating process time for forming the first electrode layer can be reduced, and further the plating process cost can be reduced.

[0160] In the embodiment, the core layer of the circuit board is not formed solely of a copper clad laminate as described above, but is formed by a combination of a copper clad laminate and a prepreg or ABF. This allows the thickness of the electrode layers disposed on the upper and lower surfaces of the core layer of the circuit board to be reduced. Furthermore, in the embodiment, the line width and spacing of the electrode layers disposed on the upper and lower surfaces of the core layer of the circuit board can be reduced. This allows the electrode layers disposed on the upper and lower surfaces of the core layer to be miniaturized, thereby reducing the overall thickness of the circuit board.

[0161] FIG. 5 is a diagram illustrating a semiconductor package according to an embodiment.

[0162] Referring to FIG. 5, an embodiment of a semiconductor package includes the circuit board of FIG. 4, at least one chip mounted on the circuit board, a molding layer for molding the chip, and a connection portion for connecting the chip to an external substrate.

[0163] For example, the semiconductor package of the embodiment may include a first connection portion 310 disposed on the fifth electrode layer 220, which is the outermost electrode layer of the circuit board. The cross section of the first connection portion 310 may be circular or semicircular. For example, the cross section of the first connection portion 310 may be partially or entirely rounded. The cross section of the first connection portion 310 may be flat on one side and curved on the other side. The first connection portion 310 may be, but is not limited to, a solder ball.

[0164] Meanwhile, in an embodiment, a chip 320 may be disposed on the first connection portion 310. The chip 320 may be a processor chip. For example, the chip 320 may be an application processor (AP) chip among a central processor (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller. A terminal 325 of the chip 320 may be connected to the fifth electrode layer 220 via the first connection portion 310. For example, the fifth electrode layer 220 may include a mounting pad on which the chip 220 is mounted.

[0165] Furthermore, although not shown in the drawings, the package substrate of the embodiment may further include additional chips. For example, in the embodiment, at least two chips selected from the group consisting of a central processor (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller may be arranged on the circuit board with a certain interval between them. For example, the chip 320 in the embodiment may include, but is not limited to, a central processor chip and a graphics processor chip.

[0166] Meanwhile, the chips may be spaced apart from one another at regular intervals on the circuit board. For example, the spacing between the chips may be 150 μm or less. For example, the spacing between the chips may be 120 μm or less. For example, the spacing between the chips may be 100 μm or less.

[0167] Preferably, the spacing between the plurality of chips may be in the range of 60 μm to 150 μm. Preferably, the spacing between the plurality of chips may be in the range of 70 μm to 120 μm. Preferably, the spacing between the plurality of chips may be in the range of 80 μm to 110 μm. If the spacing between the plurality of chips is less than 60 μm, mutual interference between the plurality of chips may cause problems in operational reliability. If the spacing between the plurality of chips is greater than 150 μm, signal transmission loss may increase as the distance between the plurality of chips increases. If the spacing between the plurality of chips is greater than 150 μm, the volume of the semiconductor package may increase.

[0168] The package substrate may include a molding layer 330. The molding layer 330 may be disposed to cover the chip 320. For example, the molding layer 330 may be, but is not limited to, an epoxy mold compound (EMC) formed to protect the mounted chip 320.

[0169] In this case, the molding layer 330 may have a low dielectric constant to enhance heat dissipation characteristics. For example, the dielectric constant Dk of the molding layer 330 may be 0.2 to 10. For example, the dielectric constant Dk of the molding layer 330 may be 0.5 to 8. For example, the dielectric constant Dk of the molding layer 330 may be 0.8 to 5. Thus, in this embodiment, the molding layer 330 has a low dielectric constant, thereby enhancing heat dissipation characteristics for heat generated in the chip 320.

[0170] Meanwhile, the semiconductor package may include a second connection part 240 disposed on the bottom side of the circuit board. The second connection part 240 may be disposed on the bottom surface of the sixth electrode layer 250, which may be vertically overlapped with the opening of the second protection layer 280.

[0171] -Manufacturing method- 3 according to the embodiment will be described in the order of steps. Preferably, the method for manufacturing the core layer 100 of the circuit board of the embodiment will be described in the order of steps.

[0172] 6 to 16 are diagrams for explaining the manufacturing method of the circuit board according to the embodiment shown in FIG. 3 in the order of steps.

[0173] 6 , in an embodiment, a copper clad laminate is prepared as a base for manufacturing a core layer 100. The copper clad laminate includes a first insulating layer 110. The copper clad laminate also includes a copper clad layer disposed on a surface of the first insulating layer 110. For example, the copper clad laminate includes a first copper clad layer 111 disposed on an upper surface of the first insulating layer 110 and a second copper clad layer 112 disposed on a lower surface of the first insulating layer 110.

[0174] Next, referring to FIG. 7 , in an embodiment, a process of removing the first copper foil layer 111 and the second copper foil layer 112 from the prepared copper clad laminate may be performed. Here, the process of removing the first copper foil layer 111 and the second copper foil layer 112 may be selectively performed depending on the manufacturing method of the electrode layer constituting the core layer. For example, the electrode layer of the core layer 100 may be manufactured using the first copper foil layer 111 and the second copper foil layer 112. When the electrode layer is manufactured using the first copper foil layer 111 and the second copper foil layer 112, the process of removing the first copper foil layer 111 and the second copper foil layer 112 may be omitted. The following description focuses on a process of manufacturing an electrode layer with the first copper foil layer 111 and the second copper foil layer 112 removed. In an embodiment, after the first copper foil layer 111 and the second copper foil layer 112 are removed, a process of forming a through hole TH1 penetrating the first insulating layer 110 may be performed.

[0175] 8, in an embodiment, a process of forming a metal layer on an upper surface of the first insulating layer 110, a lower surface of the first insulating layer 110, and an inner wall of the through hole TH1 may be performed. At this time, the formed metal layer may include a first metal layer 121 constituting a first electrode layer 120, a third metal layer 131 constituting a second electrode layer 130, and a first through electrode 140.

[0176] 9, in an embodiment, a process of forming masks on the upper and lower sides of the first insulating layer 110 may be performed. For example, in an embodiment, a process of forming a first mask M1 on the upper side of the first insulating layer 110 may be performed. The first mask M1 may be disposed on the first metal layer 121 of the first electrode layer 120. In this case, the first mask M1 may include an opening (not shown) that vertically overlaps with the through hole TH1 that penetrates the first insulating layer 110.

[0177] In addition, in the embodiment, a process of forming a second mask M2 under the first insulating layer 110 may be performed. The second mask M2 may be disposed under the third metal layer 131 of the second electrode layer 130. In this case, the second mask M2 may include an opening (not shown) that vertically overlaps with the through hole TH1 that penetrates the first insulating layer 110.

[0178] 10 , in an embodiment, a hole plugging process may be performed to form an insulating member 150 in the through hole TH1 that vertically overlaps with the openings of the first mask M1 and the second mask M2. At this time, the upper surface of the insulating member 150 may be formed to be higher than the upper surface of the first insulating layer 110. Also, the lower surface of the insulating member 150 may be formed to be lower than the lower surface of the first insulating layer 110.

[0179] For example, the upper surface of the insulating member 150 may be formed to be flush with the upper surface of the first metal layer 121 of the first electrode layer 120. However, the embodiment is not limited thereto. Preferably, the hole plugging process may be performed such that the upper surface of the insulating member 150 is higher than the upper surface of the first metal layer 121 of the first electrode layer 120.

[0180] For example, the lower surface of the insulating member 150 may be formed to be flush with the lower surface of the third metal layer 131 of the second electrode layer 130. However, the embodiment is not limited thereto. Preferably, the hole plugging process may be performed such that the lower surface of the insulating member 150 is lower than the lower surface of the third metal layer 131 of the second electrode layer 130.

[0181] Next, referring to FIG. 11, in this embodiment, after the process of forming the insulating member 150 is completed, a process of removing the first mask M1 and the second mask M2 may be performed.

[0182] 12, in an embodiment, a process of forming a third mask M3 on an upper surface of the first metal layer 121 of the first electrode layer 120 may be performed. At this time, the third mask M3 may include an opening (not shown) that vertically overlaps with a region of the upper surface of the first metal layer 121 of the first electrode layer 120 where the second metal layer 122 is to be disposed.

[0183] In addition, in the embodiment, a process of forming a fourth mask M4 on a lower surface of the third metal layer 131 of the second electrode layer 130 may be performed. In this case, the fourth mask M4 may include an opening (not shown) that vertically overlaps with a region of the lower surface of the third metal layer 131 of the second electrode layer 130 where the fourth metal layer 132 is to be disposed.

[0184] Next, in an embodiment, a step of performing electrolytic plating using the first metal layer 121 as a seed layer to form a second metal layer 122 of the first electrode layer 120 that fills the openings of the third mask M3 can be performed. Also, in an embodiment, a step of performing electrolytic plating using the third metal layer 131 as a seed layer to form a fourth metal layer 132 of the second electrode layer 130 that fills the openings of the fourth mask M4 can be performed.

[0185] 13 , in an embodiment, after the formation of the second metal layer 122 of the first electrode layer 120 and the fourth metal layer 132 of the second electrode layer 130 is completed, a process of removing the third mask M3 and the fourth mask M4 may be performed. Then, in an embodiment, a process of etching away a portion of the first metal layer 121 of the first electrode layer 120 that does not vertically overlap the second metal layer 122 may be performed to form the first electrode layer 120. Also, in an embodiment, a process of etching away a portion of the third metal layer 131 of the second electrode layer 130 that does not vertically overlap the fourth metal layer 132 may be performed to form the second electrode layer 130.

[0186] 14 , in an embodiment, a process may be performed in which a second insulating layer 161 is disposed on an upper surface of the first insulating layer 110 and a third insulating layer 162 is disposed on a lower surface of the first insulating layer 110. In this case, each of the second insulating layer 161 and the third insulating layer 162 may include an insulating material different from that of the first insulating layer 110. For example, the second insulating layer 161 and the third insulating layer 162 may include prepreg or ABF. In addition, the second insulating layer 161 and the third insulating layer 162 may have a thickness smaller than that of the first insulating layer 110.

[0187] 15 , in an embodiment, a process of forming second through holes TH2 in the second insulating layer 161 may be performed. Preferably, in an embodiment, a process of forming second through holes TH2 may be performed in a region of the entire second insulating layer 161 that vertically overlaps with the first through hole TH1 or a region that vertically overlaps with the first through electrode 140 and the insulating member 150.

[0188] In addition, in the embodiment, a step of forming a third through hole TH3 in the third insulating layer 162 can be performed. Preferably, in the embodiment, a step of forming a third through hole TH3 can be performed in a region of the entire region of the third insulating layer 162 that vertically overlaps with the first through hole TH1 and the second through hole TH2.

[0189] In this case, the second through hole TH2 and the third through hole TH3 may have a different shape from the first through hole TH1.

[0190] 16 , in an embodiment, a process may be performed in which a second through-electrode 181 is formed in the second through-hole TH2 of the second insulating layer 161 and a third electrode layer 171 is formed on the upper surface of the second insulating layer 161. In addition, in an embodiment, a process may be performed in which a third through-electrode 182 is formed in the third through-hole TH3 of the third insulating layer 162 and a fourth electrode layer 172 is formed on the lower surface of the third insulating layer 162.

[0191] The circuit board in the embodiment includes a through electrode layer penetrating a first insulating layer and a first electrode layer disposed on the first insulating layer. The through electrode layer includes a first through electrode and an insulating member disposed on the inner wall of a first through hole penetrating the first insulating layer. The first electrode layer includes a first region R1 that does not vertically overlap the insulating member and a second region R2 that vertically overlaps the insulating member. The first region R1 of the first electrode layer has a multilayer structure including the first metal layer and the second metal layer. The second region R2 of the first electrode layer may include only the second metal layer. For example, the number of metal layers in the first region R1 of the first electrode layer may be greater than the number of metal layers in the second region R2 of the first electrode layer.

[0192] As a result, the thickness of the first region R1 of the first electrode layer may be greater than the thickness of the second region R2. Preferably, the thickness of the first electrode layer in the region that vertically overlaps the insulating member may be smaller than the thickness of the first electrode layer in the region that does not vertically overlap the insulating member. As a result, in the embodiment, the thickness of the second region R2 of the first electrode layer can be reduced compared to the comparative example. As a result, in the embodiment, the plating process time for forming the first electrode layer can be reduced, and further the plating process cost can be reduced.

[0193] In the embodiment, the core layer of the circuit board is not formed solely of a copper clad laminate as described above, but is formed by a combination of a copper clad laminate and a prepreg or ABF. This allows the thickness of the electrode layers disposed on the upper and lower surfaces of the core layer of the circuit board to be reduced. Furthermore, in the embodiment, the line width and spacing of the electrode layers disposed on the upper and lower surfaces of the core layer of the circuit board can be reduced. This allows the electrode layers disposed on the upper and lower surfaces of the core layer to be miniaturized, thereby reducing the overall thickness of the circuit board.

[0194] Meanwhile, when a circuit board having the above-described inventive features is used in IT devices or home appliances such as smartphones, server computers, and TVs, it can stabilize functions such as signal transmission or power supply. For example, when a circuit board having the features of the present invention performs a semiconductor packaging function, it can safely protect the semiconductor chip from external moisture and contaminants, and can solve problems such as leakage current, electrical shorts between terminals, and electrical open circuits in terminals supplying power to the semiconductor chip. Furthermore, when performing a signal transmission function, it can solve noise problems. As a result, a circuit board having the above-described inventive features can maintain stable functions in IT devices and home appliances, and the entire product and the circuit board to which the present invention is applied can achieve functional integration or technical interrelationship with each other.

[0195] When a circuit board having the features of the present invention is used in a transportation device such as a vehicle, it can solve the problem of distortion of signals transmitted to the transportation device, safely protect the semiconductor chip that controls the transportation device from the outside, and solve the problems of leakage current, electrical short circuits between terminals, and electrical open circuits of terminals supplying power to the semiconductor chip, thereby further improving the stability of the transportation device. Therefore, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interlocking with each other.

[0196] The features, structures, effects, etc. described in the above embodiments are included in at least one embodiment and are not necessarily limited to one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by a person skilled in the art to which the embodiment belongs. Therefore, the contents related to such combinations and modifications should be interpreted as being included in the scope of the embodiments.

[0197] Although the above description has focused on the embodiments, these are merely illustrative and are not intended to limit the scope of the embodiments. Those skilled in the art will appreciate that various modifications and applications not exemplified above are possible within the scope of the essential characteristics of the embodiments. For example, each component specifically illustrated in the embodiments may be modified and implemented. Differences related to such modifications and applications should be construed as being included within the scope of the embodiments defined in the appended claims.

Claims

1. a first insulating layer including a through hole; an insulating member disposed in the through hole of the first insulating layer; a first electrode layer disposed on the insulating member; a second insulating layer disposed on the first electrode layer; a first through electrode that penetrates the second insulating layer; The semiconductor package, wherein the first through-hole electrode overlaps the first electrode layer and the insulating member in a vertical direction.

2. a second through electrode disposed in the through hole and surrounding at least a portion of the insulating member; The semiconductor package according to claim 1 , wherein the first electrode layer is disposed on the second through-electrode and the insulating member.

3. The first electrode layer is a first region vertically overlapping the first insulating layer; a second region vertically overlapping the insulating member; The semiconductor package of claim 2 , wherein a thickness of the first region of the first electrode layer is different from a thickness of the second region of the first electrode layer.

4. The semiconductor package according to claim 3 , wherein the thickness of the first region of the first electrode layer is greater than the thickness of the second region of the first electrode layer.

5. the first electrode layer further includes a third region provided between the first region and the second region and vertically overlapping the first through-electrode; The semiconductor package according to claim 3 , wherein the thickness of the third region of the first electrode layer is greater than the thickness of the second region.

6. The semiconductor package according to claim 3 , wherein an upper surface of the insulating member is positioned higher than an upper surface of the first insulating layer.

7. the first electrode layer includes a first metal layer disposed on an upper surface of the first insulating layer; The semiconductor package according to claim 3 , further comprising: a second metal layer disposed on the first metal layer and the first through-electrode.

8. The second metal layer of the first electrode layer is the thickness of the first region and the thickness of the second region are different, The lower surface of the second metal layer is The semiconductor package of claim 7 , further comprising a recess that is recessed toward the insulating member.

9. The semiconductor package of claim 3 , wherein the first insulating layer comprises a copper clad laminate (CCL).

10. 10. The semiconductor package of claim 9, wherein the first insulating layer has a thickness in the range of 80 μm to 150 μm.

11. a second electrode layer disposed on the first through-electrode; The semiconductor package according to claim 5 , wherein the second electrode layer overlaps the first through-electrode in a vertical direction.

12. The semiconductor package of claim 11, wherein the second insulating layer includes one of a prepreg and an Ajinomoto Build-up Film (ABF).

13. The semiconductor package according to claim 3 , wherein the first insulating layer and the second insulating layer are core layers of a circuit board.

14. The semiconductor package according to claim 13 , wherein the first through-electrode, the first electrode layer, and the second through-electrode are through-core electrodes that penetrate the upper and lower surfaces of the core layer.

15. The semiconductor package according to claim 13 , wherein the first through-electrodes are not disposed in a region of the second insulating layer that does not vertically overlap the second through-electrodes.

16. The semiconductor package according to claim 5 , wherein the inclination of the side surface of the second through electrode is perpendicular to the upper surface or the lower surface of the first insulating layer.

17. The semiconductor package according to claim 9 , wherein the first through-electrode has a different shape from the second through-electrode.

18. a third insulating layer disposed on the second insulating layer; a third electrode layer disposed on the third insulating layer; a connection portion disposed on the third electrode layer; The semiconductor package according to claim 3 , further comprising: a semiconductor element disposed on the connection portion.

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