ESD protection circuit and semiconductor device

Abstract

To provide an ESD protection circuit according to an operating voltage and a breakdown voltage of a protected circuit.SOLUTION: An ESD protection circuit 100 is connected between a VDD terminal and a VSS terminal, operates at an operating voltage, and protects an internal circuit C from electrostatic discharge by being connected in parallel with the internal circuit C, which is destroyed at the time of exceeding a breakdown voltage, and includes a plurality of ESD protection elements 110 and 120 connected in series. The plurality of ESD protection elements 110 and 120 are transistors, diode elements, or a combination thereof, and the sum of the current-voltage characteristics of the plurality of ESD protection elements 110 and 120 at a voltage higher than the operating voltage is higher than the operating voltage and lower than the breakdown voltage until the sum becomes a discharge current value or more which can protect the internal circuit C.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an ESD protection circuit and a semiconductor device. [Background technology]

[0002] Semiconductor integrated circuits are vulnerable to electrostatic discharge (ESD) and can be easily destroyed. Specifically, if a semiconductor integrated circuit contains elements with a MOS (Metal-Oxide-Semiconductor) structure, electric field breakdown such as gate insulating film breakdown often occurs. For this reason, semiconductor integrated circuits often include an ESD protection circuit to protect the internal circuitry from electrostatic discharge.

[0003] Examples of ESD protection circuits include a diode-type ESD protection circuit that utilizes a breakdown phenomenon, and a gg (gate grounded) NMOS-type ESD protection circuit that utilizes the snapback action of an NMOS (N-channel MOS) transistor.

[0004] As a diode-type ESD protection circuit, for example, one has been proposed in which a string of two or more serially connected diodes is connected between an external connection terminal connected to an internal circuit and a power supply line, etc., thereby expanding the allowable voltage range of the external connection terminal in proportion to the number of diodes (see Patent Document 1).

[0005] As a ggNMOS type ESD protection circuit, for example, an ESD protection circuit has been proposed that can reduce the layout area by connecting ESD protection elements between power supply terminals of a plurality of different power supply voltages (see Patent Document 2). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2003-23084 [Patent Document 2] Japanese Patent Application Laid-Open No. 2011-181848 Summary of the Invention [Problem to be solved by the invention]

[0007] Therefore, one aspect of the present invention aims to provide an ESD protection circuit that is responsive to the operating voltage and breakdown voltage of the circuit to be protected. [Means for solving the problem]

[0008] The ESD protection circuit in one embodiment of the present invention comprises: An ESD protection circuit connected between a first terminal and a second terminal, operating at an operating voltage, and connected in parallel with a protected circuit that is destroyed by a breakdown voltage or higher to protect the protected circuit from electrostatic discharge, comprising: A plurality of ESD protection elements connected in series, the plurality of ESD protection elements are transistors, diode elements, or a combination thereof; The sum of the current-voltage characteristics of the plurality of ESD protection elements at a voltage higher than the operating voltage is higher than the operating voltage and lower than the breakdown voltage until it reaches or exceeds a discharge current value capable of protecting the protected circuit. [Effects of the Invention]

[0009] According to one aspect of the present invention, it is possible to provide an ESD protection circuit that is responsive to the operating voltage and breakdown voltage of a circuit to be protected. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a circuit diagram showing an example of an ESD protection circuit and a semiconductor device according to the present invention. [Figure 2] FIG. 2 is a circuit diagram showing an example of an ESD protection circuit and a semiconductor device according to the first embodiment. [Figure 3] FIG. 3 is a graph showing an example of current-voltage characteristics when the ESD protection element is a low-voltage MOS transistor. [Figure 4] FIG. 4 is a graph showing some examples of current-voltage characteristics of the ESD protection circuit according to the first embodiment. [Figure 5] FIG. 5 is a circuit diagram showing an ESD protection circuit and a semiconductor device according to the second embodiment. [Figure 6A] FIG. 6A is a graph showing current-voltage characteristics of a high-voltage NMOS transistor and a low-voltage transistor according to the second embodiment. [Figure 6B] FIG. 6B is a graph showing the current-voltage characteristics of the high-voltage NMOS transistor, the low-voltage transistor, and the ESD protection circuit according to the second embodiment. [Figure 7] FIG. 7 is a schematic cross-sectional view showing an example of the structure of a high-voltage NMOS transistor according to the second embodiment. [Figure 8] FIG. 8 is a schematic cross-sectional view showing another example of the structure of the high voltage NMOS transistor according to the second embodiment. [Figure 9] FIG. 9 is a circuit diagram showing an ESD protection circuit and a semiconductor device according to a modification of the second embodiment. [Figure 10] FIG. 10 is a graph showing current-voltage characteristics of a high-voltage NMOS transistor, a low-voltage transistor, and an ESD protection circuit in a modification of the second embodiment. [Figure 11] FIG. 11 is a circuit diagram showing an ESD protection circuit and a semiconductor device according to the third embodiment. [Figure 12] FIG. 12 is a graph showing some examples of current-voltage characteristics of the ESD protection circuit according to the third embodiment. [Figure 13] FIG. 13 is a graph showing the current-voltage characteristics of a conventional low-voltage ESD protection circuit. [Figure 14] FIG. 14 is a graph showing current-voltage characteristics of conventional low-voltage and high-voltage ESD protection circuits. DETAILED DESCRIPTION OF THE INVENTION

[0011] In a ggNMOS-type ESD protection circuit, the gate and source of the NMOS (N-channel MOS) transistor are connected to ground potential, and when a positive surge voltage is applied to the terminal connected to the drain, the drain end of the NMOS transistor breaks down. When the product of the avalanche current generated by this breakdown and the substrate resistance exceeds the diffusion barrier voltage of the PN junction (approximately 0.6V), a parasitic NPN bipolar transistor operates. When a discharge current begins to flow between the drain and source due to the operation of this parasitic bipolar transistor, the drain voltage temporarily drops to the holding voltage Vh, and then increases as the discharge current gradually increases.

[0012] An ESD protection circuit that uses this type of snapback action may not be able to protect the protected circuit unless the trigger voltage and holding voltage for the snapback action are set higher than the operating voltage of the protected circuit and lower than the breakdown voltage. Also, it is preferable to set the breakdown voltage of the parasitic diode in the NMOS transistor higher than the operating voltage in order to reduce leakage current during operation of the protected circuit. The operating voltage is the specified voltage at which the protected circuit can operate. For example, it is not limited to the range between the minimum and maximum operating voltages specified in the specifications, but also includes the range of voltages at which the circuit can actually operate. Specifically, if the maximum operating voltage is 30V and the minimum activation voltage of the ESD protection circuit is 35V, but the specifications specify a maximum operating voltage of 40V, the actual operating voltage should be considered. The breakdown voltage is the voltage at which the protected circuit can break down. A trigger voltage higher than the breakdown voltage will destroy the protected circuit if it is higher than the breakdown voltage of the protected circuit. If the holding voltage falls below the maximum operating voltage and the parasitic NPN bipolar transistor operates, current will continue to flow through the parasitic NPN bipolar transistor even after the surge voltage is applied.

[0013] Setting all of the breakdown voltage, trigger voltage, and holding voltage higher than the maximum operating voltage of the protected circuit and lower than the breakdown voltage of the protected circuit is easy to achieve for a low-voltage protected circuit, but is difficult to achieve for a high-voltage protected circuit.

[0014] For example, for a low-voltage protected circuit with a maximum operating voltage of 5 V and a breakdown voltage of 12 V, it is easy to set the breakdown voltage BV, trigger voltage Vtrig, and holding voltage Vh all to be higher than the maximum operating voltage Vmax of the protected circuit and lower than the breakdown voltage Vit, as shown by L in FIG. 13. Specifically, when an NMOS transistor with a breakdown voltage of 5 V is applied to a ggNMOS-type ESD protection circuit, the breakdown voltage BV becomes 9 V, the trigger voltage Vtrig becomes 11 V, and the holding voltage Vh becomes 6 V, and it is easy to make these three parameters higher than the maximum operating voltage Vmax of 5 V and lower than the breakdown voltage Vit of 12 V. Such a low-breakdown-voltage ESD protection circuit can have a layout area of ​​about 70 μm × 70 μm.

[0015] Next, consider the case where a structure that increases the collector-emitter resistance of the parasitic bipolar transistor is adopted for a high-voltage protected circuit with a maximum operating voltage Vmax of 100 V and a breakdown voltage Vit of 140 V. In this case, if the breakdown voltage BV is set to 120 V, as shown by A in Figure 14, and compared to L in Figure 13 shown on the scale of Figure 14, the holding voltage Vh is often not high enough.

[0016] If the holding voltage Vh is made higher than the maximum operating voltage Vmax of the protected circuit, even if snapback occurs, the collector-emitter resistance of the parasitic bipolar transistor becomes too high to allow a large discharge current to flow, resulting in destruction of the protected circuit, as shown in B in Figure 14. On the other hand, if the breakdown voltage of the parasitic diode is made higher, the trigger voltage becomes higher than the breakdown voltage of the protected circuit, as shown in C in Figure 14, resulting in destruction of the protected circuit.

[0017] If the gate width W is widened, the voltage gradually increases and the current reaches 1.3 A without causing snapback, as shown by D in Figure 14. This allows the circuit to function as an ESD protection circuit, but the layout area exceeds 400 μm × 400 μm for a protected circuit with a high withstand voltage of about 100 V maximum operating voltage.

[0018] Therefore, an ESD protection circuit according to one embodiment of the present invention combines a plurality of ESD protection elements according to the operating voltage and breakdown voltage of the circuit to be protected.

[0019] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals, and redundant explanations may be omitted. In addition, the X-axis, Y-axis, and Z-axis shown in the drawings are perpendicular to one another. The X-axis direction may be referred to as the "width direction," the Y-axis direction as the "depth direction," and the Z-axis direction as the "height direction" or "thickness direction." The surface of each film on the +Z direction side may be referred to as the "front surface" or "top surface," and the surface on the -Z direction side as the "back surface" or "bottom surface." Furthermore, the drawings are schematic, and the ratios of width, depth, and thickness are not as shown. The number, position, shape, structure, size, etc. of the multiple films or layers, or the semiconductor element obtained by structurally combining them, are not limited to the embodiments shown below, and may be any number, position, shape, structure, size, etc. that is preferable for implementing the present invention.

[0020] FIG. 1 is a circuit diagram showing an example of an ESD protection circuit and a semiconductor device according to the present invention. As shown in FIG. 1, a semiconductor device 10 according to an embodiment of the present invention includes an ESD protection circuit 100 and an internal circuit C. In one embodiment of the present invention, the ESD protection circuit 100 includes a first terminal, V DD terminal and V as the second terminal SS It is connected between the terminals and is connected in parallel with the internal circuit C.

[0021] The internal circuit C is a protected circuit that is protected from electrostatic discharge by the ESD protection circuit 100, and V DD V terminal and ground potential SS The internal circuit C operates at an operating voltage applied between the terminals. The internal circuit C operates at an operating voltage equal to or lower than a predetermined maximum operating voltage Vmax, and can be destroyed at a predetermined breakdown voltage Vit or higher.

[0022] The ESD protection circuit 100 is a circuit that protects an internal circuit C from being destroyed by electrostatic discharge. The ESD protection circuit 100 has a plurality of ESD protection elements 110 and 120 connected in series. The ESD protection elements 110 and 120 are MOS transistors, diode elements, or a combination of these. That is, the ESD protection elements 110 and 120 may both be MOS transistors, both be diode elements, or a combination of MOS transistors and diode elements. By appropriately selecting the ESD protection elements 110 and 120, the sum of the current-voltage characteristics of the ESD protection elements 110 and 120 is made higher than the operating voltage of the internal circuit C and lower than the breakdown voltage within the range of discharge current that can protect the internal circuit C. As a result, the ESD protection circuit 100 can obtain current-voltage characteristics according to the operating voltage and breakdown voltage of the internal circuit C, and can avoid breakdown due to electrostatic discharge without interfering with the operation of the internal circuit C.

[0023] In FIG. 1, the plurality of ESD protection elements are two, namely, the ESD protection elements 110 and 120, but this is not limitative, and at least two or more ESD protection elements may be combined. Furthermore, as long as the sum of the current-voltage characteristics of the multiple ESD protection elements can be higher than the operating voltage of the internal circuit and lower than the breakdown voltage, the MOS transistors may be N-channel or P-channel, and the withstand voltage may be the same as or different from that of the other ESD protection elements. The diode elements may be the same as or different from that of the other ESD protection elements.

[0024] To illustrate these variations, three embodiments are given below. In the first embodiment, an ESD protection circuit in which a low-voltage NMOS transistor and a low-voltage PMOS (P-channel MOS) transistor are combined will be described. In the second embodiment and its modification, an ESD protection circuit in which a high-voltage NMOS transistor and a low-voltage NMOS transistor are combined will be described. In the third embodiment, an ESD protection circuit in which a high-voltage diode element and a low-voltage MOS transistor are combined will be described.

[0025] In each embodiment, the "low withstand voltage" is a voltage in the vicinity of 5V, and the "high withstand voltage" is a voltage in the vicinity of 100V, but this is not limiting. Furthermore, in each embodiment, the "discharge current value capable of protecting the internal circuit" is set to 1.3 A because a discharge current of 1.3 A is sufficient to protect against electrostatic discharge of 2 kV in HBM (Human Body Model), but is not limited to this.

[0026] (First embodiment) FIG. 2 is a circuit diagram showing an example of an ESD protection circuit and a semiconductor device according to the first embodiment. The ESD protection circuit 200 of the semiconductor device 20 in the first embodiment is formed by connecting in series a total of 12 appropriately selected low-voltage NMOS transistors and low-voltage PMOS transistors. 2 shows the ESD protection circuit 200 formed by connecting both a low-voltage NMOS transistor and a low-voltage PMOS transistor in series. The low-voltage NMOS transistor and the low-voltage PMOS transistor are diode-connected, with their gate terminals connected to their source terminals. Also, in Figure 2, V DD A low-voltage NMOS transistor is placed on the terminal side, and V SS A low-voltage PMOS transistor is placed on the terminal side, but V DD A low-voltage PMOS transistor is placed on the terminal side, and VSS A low-voltage NMOS transistor may be placed on the terminal side. In either case, the same breakdown voltage BV, trigger voltage Vtrig, and holding voltage Vh can be obtained. However, since the ESD tolerance may change depending on the arrangement order, the preferred arrangement order should be selected as appropriate. Furthermore, the order of arrangement should preferably be selected appropriately, since the ESD tolerance may differ depending not only on whether the MOS transistor is N-channel or P-channel, but also on the order of the ESD protection elements.

[0027] FIG. 3 is a graph showing an example of current-voltage characteristics when the ESD protection element is a low-voltage MOS transistor. When the ESD protection element is a low-voltage NMOS transistor, its current-voltage characteristics are as shown by Ln in Figure 3. When the ESD protection element is a low-voltage PMOS transistor, its current-voltage characteristics are as shown by Lp in Figure 3. Comparing Ln and Lp, the NMOS transistor has a larger snapback action than the PMOS transistor, resulting in a lower holding voltage Vh and a lower voltage at which 1.3 A can flow. Conversely, the PMOS transistor has a smaller snapback action than the NMOS transistor, resulting in a higher holding voltage Vh and a higher voltage at which 1.3 A can flow.

[0028] Next, the current-voltage characteristics of the ESD protection circuit 200, which combines a low-voltage NMOS transistor and a low-voltage PMOS transistor, will be described. Fig. 4 is a graph showing some examples of current-voltage characteristics of the ESD protection circuit according to the first embodiment. L1 to L5 in Fig. 4 represent the current-voltage characteristics of the ESD protection circuit 200 formed by connecting the following numbers of low-voltage NMOS transistors and low-voltage PMOS transistors in series: L1: 12 low-voltage NMOS transistors L2: 9 low-voltage NMOS transistors, 3 low-voltage PMOS transistors L3: 6 low-voltage NMOS transistors, 6 low-voltage PMOS transistors L4: 3 low-voltage NMOS transistors, 9 low-voltage PMOS transistors L5: 12 low-voltage PMOS transistors

[0029] As shown in FIG. 4, the current-voltage characteristics of the ESD protection circuit 200 show that the greater the proportion of low-breakdown-voltage NMOS transistors, the greater the snapback action, and therefore the lower the holding voltage Vh. As a result, in the ESD protection circuit 200, which has a high proportion of low-voltage NMOS transistors, if the holding voltage Vh is higher than the operating voltage of the internal circuit C, the voltage at which a discharge current of 1.3 A necessary for protection from an electrostatic discharge of 2 kV in HBM can easily be made lower than the breakdown voltage of the internal circuit C. Furthermore, if the ESD protection circuit 200 can adjust the holding voltage Vh low to near the operating voltage of the internal circuit C, the discharge current will more easily flow before the discharge voltage due to electrostatic discharge approaches the breakdown voltage of the internal circuit C, and the internal circuit C can be more reliably protected from electrostatic discharge.

[0030] From this perspective, for example, when the breakdown voltage of the internal circuit C is 140V and the operating voltage of the internal circuit C is 70V, the current-voltage characteristic indicated by L1 in Fig. 4 is optimal, and therefore the ESD protection circuit 200 is preferably formed with 12 low-voltage NMOS transistors. Furthermore, when the operating voltage of the internal circuit C is 90V, the current-voltage characteristic indicated by L3 in Fig. 4 is optimal, and therefore the ESD protection circuit 200 is preferably formed with 6 low-voltage NMOS transistors and 6 low-voltage PMOS transistors. Furthermore, when the operating voltage of the internal circuit C is 100V, the current-voltage characteristic indicated by L4 in Fig. 4 is optimal, and therefore the ESD protection circuit 200 is preferably formed with 3 low-voltage NMOS transistors and 9 low-voltage PMOS transistors.

[0031] In this way, by combining low-voltage NMOS transistors and low-voltage PMOS transistors, the ESD protection circuit 200 in the first embodiment can obtain current-voltage characteristics according to the operating voltage and breakdown voltage of the internal circuit C. In particular, in the ESD protection circuit 200, the snapback action increases when the proportion of low-voltage NMOS transistors is increased, and therefore the discharge current required to protect the internal circuit C can be passed at a lower voltage, thereby more reliably protecting the internal circuit C. Although twelve low-voltage MOS transistors are used in the first embodiment, the number is not limited to this, and any number of MOS transistors may be used as long as optimal current-voltage characteristics are obtained.

[0032] (Second embodiment) FIG. 5 is a circuit diagram showing an ESD protection circuit and a semiconductor device according to the second embodiment. 5, the semiconductor device 30 of the second embodiment is the same as that of the first embodiment, except that the ESD protection circuit 200 of the semiconductor device 20 of the first embodiment is replaced with an ESD protection circuit 300 formed of two NMOS transistors with different breakdown voltages. Therefore, the ESD protection circuit 300 will be described in detail below.

[0033] The ESD protection circuit 300 is formed by connecting a high-voltage NMOS transistor 310 and a low-voltage NMOS transistor 320 in series. The high voltage NMOS transistor 310 is V DD A drain 310D is connected to the terminal. The low-voltage NMOS transistor 320 has a drain 320D connected to the source 310S and gate 310G of the high-voltage NMOS transistor 310, and a source 320S and gate 320G connected to V SS is connected to the terminal. In Figure 5, V DD A high-voltage NMOS transistor 310 is placed on the terminal side, and V SS A low-voltage NMOS transistor 320 is placed on the terminal side, but V DDA low-voltage NMOS transistor 320 is placed on the terminal side, and V SS Alternatively, a high-voltage NMOS transistor 310 may be placed on the terminal side. In either case, the same breakdown voltage BV, trigger voltage Vtrig, and holding voltage Vh can be obtained. However, since the ESD tolerance may change depending on the arrangement order, a preferable arrangement order should be selected as appropriate.

[0034] FIG. 6A is a graph showing current-voltage characteristics of a high-voltage NMOS transistor and a low-voltage transistor according to the second embodiment. 6A, the high voltage NMOS transistor 310 has a high collector-emitter resistance, so that its breakdown voltage BV is set to 110 V. As a result, the high voltage NMOS transistor 310 has a breakdown voltage BV higher than 100 V, which is the maximum operating voltage Vmax of the internal circuit C, and therefore can reduce the leakage current during operation of the internal circuit C.

[0035] Furthermore, because the high-voltage NMOS transistor 310 has a wide gate width W, it has diode-like current-voltage characteristics, allowing the current to reach 1.3 A in a range lower than 140 V, which is the breakdown voltage Vit of the internal circuit C. In other words, the current-voltage characteristics of the high-voltage NMOS transistor 310 are shifted 10 V lower than the current-voltage characteristics shown in D of FIG. 14, and this can be achieved without changing the manufacturing process. Furthermore, the layout area of ​​the high-voltage NMOS transistor 310 can be reduced by the amount of the current-voltage characteristics shifted 10 V lower compared to the NMOS transistor having the current-voltage characteristics shown in D of FIG. 14, and can be approximately 200 μm × 200 μm.

[0036] As shown by L in FIG. 6A, the current-voltage characteristics of the low-voltage NMOS transistor 320 are similar to the current-voltage characteristics shown by L in FIGS. Therefore, the layout area of ​​the low voltage NMOS transistor 320 can be reduced to about 70 μm×70 μm.

[0037] The current-voltage characteristics of the ESD protection circuit 300 are the sum of the current-voltage characteristics of the high-voltage NMOS transistor 310 and the low-voltage NMOS transistor 320, and are shown as (H1+L) in Figure 6B. In other words, the current-voltage characteristics of the ESD protection circuit 300 shown as (H1+L) are in a range higher than the maximum operating voltage Vmax of 100 V and lower than the breakdown voltage Vit of 140 V until they reach the 1.3 A required for protection from electrostatic discharge. This allows the ESD protection circuit 300 to protect the internal circuit C from electrostatic discharge.

[0038] The layout area of ​​the ESD protection circuit 300 is 200 μm×200 μm (40,000 μm 2 ) and the low-voltage NMOS transistor 320 of 70 μm×70 μm (4,900 μm 2 ) can be added together to obtain the layout area of ​​the MOS transistor relating to the current-voltage characteristics shown in D of FIG. 14, which is 400 μm×400 μm (160,000 μm 2 ), the layout area of ​​the ESD protection circuit 300 can be reduced by about 70%.

[0039] In this way, the ESD protection circuit 300 can protect the internal circuit C from electrostatic discharge, and can reduce the layout area even for the internal circuit C with a high withstand voltage.

[0040] Next, an example of the structure of the high voltage NMOS transistor 310 will be described with reference to FIGS.

[0041] FIG. 7 is a schematic cross-sectional view showing an example of the structure of a high-voltage NMOS transistor according to the second embodiment. As shown in FIG. 7, the high voltage NMOS transistor 310 has a so-called DMOS (Double-diffused MOS) structure.

[0042] Specifically, a LOCOS (Local Oxidation of Silicon) 312 serving as a field oxide film is formed on the surface of an N-type semiconductor substrate 311. A gate electrode 313 is formed of polysilicon so as to cover a part of the LOCOS 312. A drain region 314 and a source region 315 are formed as N-type heavily doped regions on the upper part of the semiconductor substrate 311, sandwiching the LOCOS 312 and the gate electrode 313 in a plan view. An N-type drift layer 316 is formed inside the semiconductor substrate 311 so as to be in contact with the periphery of the bottom and side surfaces of the LOCOS 312 and the drain region 314. A P-type well layer 317 is formed so as to be in contact with the periphery of the bottom and side surfaces of the source region 315. The gate electrode 313, the drain region 314 and the source region 315 are connected to the gate 310G, the drain 310D and the source 310S, respectively.

[0043] If the high voltage NMOS transistor 310 has such a DMOS structure, it is advantageous in that the breakdown voltage can be easily adjusted by changing the length of the LOCOS 312 in the Y-axis direction.

[0044] 8, a structure may be employed in which an N-type low-concentration region 318 is formed so as to be in contact with or at least partially overlap with a part of the bottom surface of the N-type drift layer 316. With the structure shown in Fig. 8, the withstand voltage can be adjusted by changing the length of the low-concentration region 318 in the Y-axis direction without changing the length of the LOCOS 312 in the Y-axis direction, and the surge voltage withstand capability can be improved.

[0045] In this embodiment, the high voltage NMOS transistor has a DMOS structure, but is not limited to this and may have, for example, an LDMOS (Laterally Double Diffused MOS) structure or an LDD (Lightly Doped Drain) structure. Furthermore, a salicide block region may be formed in each MOS transistor. Furthermore, in this embodiment, N-channel MOS transistors are used as the high-voltage and low-voltage MOS transistors, but this is not limiting, and at least one of the high-voltage and low-voltage MOS transistors may be a P-channel MOS transistor, which can increase the holding voltage Vh.

[0046] (Modification of the second embodiment) FIG. 9 is a circuit diagram showing an ESD protection circuit and a semiconductor device according to a modification of the second embodiment. As shown in FIG. 9, in the semiconductor device 40 according to the modification of the second embodiment, the breakdown voltage BV of the high-voltage NMOS transistor 310 in the ESD protection circuit 300 shown in FIG. 5 is set to 100 V, and the breakdown voltage BV of the low-voltage NMOS transistor 320 is set to 100 V. SS The semiconductor device is the same as the semiconductor device 30 except that a low-voltage NMOS transistor 330 is further connected in series between the terminals. The low voltage NMOS transistors 420 and 430 have the same structure and current-voltage characteristics as the low voltage NMOS transistor 320 . That is, in the ESD protection circuit 400 according to the modification of the second embodiment, the high-voltage NMOS transistor 310 in the ESD protection circuit 300 according to the second embodiment is replaced with a high-voltage NMOS transistor 410 having a breakdown voltage BV set to 100 V, and a low-voltage NMOS transistor 430 similar to the low-voltage NMOS transistor 320 is provided in the ESD protection circuit 300 according to the second embodiment. SS It is the same as the ESD protection circuit 300 except that it is further connected in series between the terminals.

[0047] FIG. 10 is a graph showing current-voltage characteristics of a high-voltage NMOS transistor, a low-voltage transistor, and an ESD protection circuit in a modification of the second embodiment. 10, H2 indicates the current-voltage characteristics of the high voltage NMOS transistor 410 whose breakdown voltage BV is set to 100V, and L indicates the current-voltage characteristics of the low voltage NMOS transistor 420 and the low voltage NMOS transistor 430. In FIG.

[0048] As shown by H2 in FIG. 10 , the high-voltage NMOS transistor 410 has a breakdown voltage BV of 100 V by making the collector-emitter resistance lower than that of the high-voltage NMOS transistor 310. The high-voltage NMOS transistor 410 has a wide gate width W, similar to the high-voltage NMOS transistor 310, but the gate width W is narrower than that of the high-voltage NMOS transistor 310 due to the lower breakdown voltage BV. In other words, the current-voltage characteristics of the high-voltage NMOS transistor 410 are shifted 20 V lower than those shown by D in FIG. 14 , and can be realized without changing the manufacturing process. The layout area of ​​the high-voltage NMOS transistor 410 can be reduced by the amount of the shift of the current-voltage characteristics 20 V lower compared to the NMOS transistor having the current-voltage characteristics shown by D in FIG. 14 , and can be reduced to approximately 150 μm × 150 μm.

[0049] The current-voltage characteristics of the low voltage NMOS transistor 430 are the same as those of the low voltage NMOS transistor 320, and are indicated by L in FIGS. 6A and 6B. Therefore, the layout area of ​​the low voltage NMOS transistor 430 can be set to about 70 μm×70 μm, similar to the low voltage NMOS transistor 320.

[0050] The current-voltage characteristics of the ESD protection circuit 400 are obtained by adding the current-voltage characteristics of the high-voltage NMOS transistor 410 to the current-voltage characteristics of the low-voltage NMOS transistors 420 and 430, and are shown as (H2+2×L) in Figure 10. In other words, the current-voltage characteristics of the ESD protection circuit 400 shown by (H2+2×L) are within the range of 100 V or more (maximum operating voltage Vmax) and 140 V or less (breakdown voltage Vit) until the current reaches 1.3 A. This allows the ESD protection circuit 400 to protect the internal circuit C from electrostatic discharge.

[0051] The layout area of ​​the ESD protection circuit 400 can be calculated by adding 150 μm×150 μm of the high-voltage NMOS transistor 410 to 70 μm×70 μm of the low-voltage NMOS transistors 320 and 330, resulting in 32,300 μm 2 Then, the layout area of ​​the MOS transistor relating to the current-voltage characteristics shown in D of FIG. 14 is 400 μm×400 μm (160,000 μm 2 ), the layout area of ​​the ESD protection circuit 400 can be reduced by about 80%. In this way, in the modified example of the second embodiment, the layout area can be made smaller than in the second embodiment even if the number of MOS transistors is increased.

[0052] (Third embodiment) FIG. 11 is a circuit diagram showing an ESD protection circuit and a semiconductor device according to the third embodiment. As shown in FIG. 11, an ESD protection circuit 500 and a semiconductor device 50 according to the third embodiment include at least diode elements as a plurality of ESD protection elements. 11 shows an ESD protection circuit 500 formed by connecting both a high-voltage diode element and a low-voltage NMOS transistor in series. The low-voltage NMOS transistor is diode-connected, with its source terminal and gate terminal connected.

[0053] Next, the current-voltage characteristics of the ESD protection circuit 500 when the multiple ESD protection elements include high-voltage diode elements will be described. Fig. 12 is a graph showing some examples of current-voltage characteristics of the ESD protection circuit according to the third embodiment. L6 to L9 in Fig. 4 represent the current-voltage characteristics of the ESD protection circuit 500 formed by connecting the following numbers of high-voltage diode elements and low-voltage NMOS transistors or low-voltage PMOS transistors in series: L6: 1 high voltage diode element L7: 1 high-voltage diode element, 1 low-voltage NMOS transistor L8: 1 high-voltage diode element, 2 low-voltage NMOS transistors L9: 1 high-voltage diode element, 2 low-voltage PMOS transistors

[0054] 12, the current-voltage characteristics of the ESD protection circuit 500 can be adjusted by the number of low-voltage NMOS transistors or low-voltage PMOS transistors. Low-voltage NMOS transistors and low-voltage PMOS transistors have the same breakdown voltage BV, but N-channel transistors have a larger switchback operation than P-channel transistors. Therefore, the ESD protection circuit 500 using low-voltage NMOS transistors can lower the voltage at which a discharge current of 1.3 A, which is necessary to protect against electrostatic discharge of 2 kV in HBM, can flow. As a result, the ESD protection circuit 500 using low-voltage NMOS transistors makes it easier for a discharge current to flow before the discharge voltage due to electrostatic discharge approaches the breakdown voltage of the internal circuit C, thereby more reliably protecting the internal circuit C from electrostatic discharge.

[0055] From this perspective, for example, when the breakdown voltage of the internal circuit C is 140V and the operating voltage of the internal circuit C is 110V, the current-voltage characteristic shown by L7 in FIG. 12 is optimal, and therefore the ESD protection circuit 500 is preferably formed with one high-voltage diode element and one low-voltage NMOS transistor. Furthermore, when the operating voltage of the internal circuit C is 120V, the current-voltage characteristic shown by L8 in FIG. 12 is optimal, and therefore the ESD protection circuit 500 is preferably formed with one high-voltage diode element and two low-voltage NMOS transistors. Furthermore, when the operating voltage of the internal circuit C is 130V, the current-voltage characteristic shown by L9 in FIG. 12 is optimal, and therefore the ESD protection circuit 500 is preferably formed with one high-voltage diode element and two low-voltage PMOS transistors.

[0056] In this way, by combining a high-voltage diode element with a low-voltage NMOS transistor or a low-voltage PMOS transistor, the ESD protection circuit 500 in the third embodiment can obtain current-voltage characteristics according to the operating voltage and breakdown voltage of the internal circuit C. In particular, since the snapback action increases when the number of low-voltage NMOS transistors is increased, the ESD protection circuit 500 can pass the discharge current required to protect the internal circuit C at a lower voltage, thereby more reliably protecting the internal circuit C.

[0057] In the third embodiment, a low-voltage NMOS transistor or a low-voltage PMOS transistor is combined with a high-voltage diode element, but a low-voltage NMOS transistor or a low-voltage PMOS transistor may also be combined with a high-voltage diode element. Furthermore, in the third embodiment, high-voltage diode elements are used, but the present invention is not limited to this, and low-voltage diode elements may be used, or high-voltage diode elements and low-voltage diode elements may be combined.

[0058] As described above, the ESD protection circuit in each embodiment of the present invention is connected between a first terminal and a second terminal, operates at an operating voltage, and is connected in parallel with a protected circuit that is destroyed at or above a breakdown voltage. This ESD protection circuit has multiple ESD protection elements connected in series, and the multiple ESD protection elements are transistors, diode elements, or a combination of these. By appropriately selecting the multiple ESD protection elements, the sum of the current-voltage characteristics of the multiple ESD protection elements at voltages higher than the operating voltage is made higher than the operating voltage of the protected circuit and lower than the breakdown voltage, until it reaches or exceeds a discharge current value that can protect the protected circuit. This allows the ESD protection circuit to obtain current-voltage characteristics that correspond to the operating voltage and breakdown voltage of the circuit to be protected, and makes it possible to avoid breakdown due to electrostatic discharge without interfering with the operation of the circuit to be protected. Furthermore, combining multiple ESD protection elements and ensuring that the breakdown voltage of at least one ESD protection element is different from the breakdown voltages of the others allows for fine adjustment of the breakdown voltage and holding voltage, making it easier to protect the circuit being protected. Specifically, if only transistors with a breakdown voltage of 10 V are combined, the total breakdown voltage will be in 10 V increments, but if transistors with a breakdown voltage of 15 V are combined, the total breakdown voltage will be in 5 V increments, allowing for fine adjustment.

[0059] Although the embodiments of the present invention have been described in detail above, the present invention is not limited to these embodiments, and includes designs within the scope of the invention that do not deviate from the gist of the invention. Specifically, in each embodiment, the first terminal is connected to V DD Although the terminals are described as such, they are not limited to this and may be, for example, signal input terminals or output terminals. Furthermore, in each embodiment, snapback of a MOS transistor is utilized, that is, the operation of a parasitic bipolar transistor of a MOS transistor is utilized, but the present invention is not limited to this, and a bipolar transistor may also be used.

[0060] Furthermore, although several examples of the arrangement order of the ESD protection elements have been shown in each embodiment, other characteristics such as latch-up resistance may change depending on the arrangement order, so it is preferable to select an appropriate order taking into account factors other than ESD characteristics. Furthermore, in terms of improving latch-up resistance, it is preferable to form deep trenches called deep trench isolation in the silicon semiconductor substrate between each ESD protection element, which also makes it possible to narrow the distance between each ESD protection element. It is also preferable to select the shape and structure of each ESD protection element, including the channel width, perimeter length, and area of ​​the junction. [Explanation of symbols]

[0061] 10, 20, 30, 40, 50 Semiconductor devices 100,200,300,400,500 ESD protection circuit 110,120 ESD protection devices C Internal circuit (protected circuit)

Claims

1. An ESD protection circuit connected between a first terminal and a second terminal, operating at an operating voltage, and connected in parallel with a protected circuit that is destroyed by a breakdown voltage or higher to protect the protected circuit from electrostatic discharge, comprising: a plurality of ESD protection elements connected in series; the plurality of ESD protection elements are transistors, diode elements, or a combination thereof; The ESD protection circuit is characterized in that the sum of the current-voltage characteristics of the plurality of ESD protection elements at a voltage higher than the operating voltage is higher than the operating voltage and lower than the breakdown voltage until the sum reaches a discharge current value that can protect the protected circuit.

2. 2. The ESD protection circuit according to claim 1, wherein a breakdown voltage in the sum of the current-voltage characteristics of said plurality of ESD protection elements is higher than said operating voltage.

3. the plurality of ESD protection elements include the transistor; 2. The ESD protection circuit according to claim 1, wherein a holding voltage in the sum of the current-voltage characteristics of said plurality of ESD protection elements is higher than said operating voltage.

4. 2. The ESD protection circuit of claim 1, wherein the transistor is a MOS transistor or a bipolar transistor.

5. 5. The ESD protection circuit according to claim 4, wherein the MOS transistor is an N-channel or P-channel transistor, and has a withstand voltage equal to or different from that of the other ESD protection elements.

6. 6. The ESD protection circuit according to claim 5, wherein the plurality of ESD protection elements include both the N-channel MOS transistor and the P-channel MOS transistor.

7. 5. The ESD protection circuit of claim 4, wherein said MOS transistor is a DMOS structure.

8. The ESD protection circuit according to claim 1 , wherein the plurality of ESD protection elements include both the transistor and the diode element.

9. 2. The ESD protection circuit according to claim 1, wherein the diode element has a withstand voltage equal to or different from that of the other ESD protection elements.

10. 2. The ESD protection circuit of claim 1, wherein a breakdown voltage of at least one of the plurality of ESD protection elements is different from a breakdown voltage of other of the ESD protection elements.

11. 11. A semiconductor device comprising: an ESD protection circuit according to claim 1; and a circuit to be protected from electrostatic discharge by said ESD protection circuit, said circuit being connected in parallel.

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