Process of processing wafer of 4h-sic material to form 3c-sic layer in direct contact with 4h-sic material

Abstract

To provide a process for processing a 4H-SiC wafer to form a layer having a reduced band gap with respect to 4H-SiC, such as 3C-SiC or silicon layer, on the 4H-SiC wafer.SOLUTION: A method of manufacturing a 3C-SiC layer 24 includes the steps of: providing a 4H-SiC wafer 21 having a surface 21a; heating a selectable portion of the wafer 21 via a laser beam 102 to at least a melting temperature of a material in the selectable portion; forming the 3C-SiC layer 24, a silicon layer 26a on the 3C-SiC layer, and a carbon rich layer 26b on the silicon layer 26a by allowing cooling and crystallization of the molten selectable portion; and completely removing the carbon rich layer 26b and the silicon layer 26a to expose the 3C-SiC layer 24.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a process for treating a 4H—SiC wafer to form a layer on the 4H—SiC wafer, such as a 3C—SiC or silicon layer, that has a reduced bandgap relative to 4H—SiC. [Background technology]

[0002] As is known, semiconductor devices are typically fabricated on silicon wafers. However, silicon carbide (SiC) wafers are becoming increasingly popular, at least in part due to SiC's beneficial physicochemical properties. For example, SiC typically has a higher bandgap than silicon, resulting in a larger barrier height when, for example, a Schottky contact is formed. Furthermore, the breakdown voltage of SiC is higher than that of silicon due to the fact that the critical electric field of SiC is approximately 10 times greater than that of silicon. In general, the advantage associated with fabricating devices on a 4H-SiC substrate (bulk) is to maintain the advantage in breakdown voltage, but have a material with a lower bandgap (e.g., silicon or 3C-SiC) on its surface to, for example, reduce the barrier height of the Schottky contact. In other words, it is desirable to maintain the advantage in reverse bias and minimize the voltage drop in forward bias.

[0003] Silicon carbide exists in different crystalline forms, also called polytypes. The most common polytypes are the cubic polytype (polytype 3C-SiC), the hexagonal polytype (polytypes 4H-SiC and 6H-SiC), and the rhombohedral polytype (polytype 15R-SiC). Among these, the cubic polytype 3C-SiC is currently being intensively studied due to its unique properties compared to those of other wafer polytypes. Polytype 3C-SiC offers several advantages for metal-oxide-semiconductor (MOS) device applications. For example, its reduced oxide / 3C-SiC interface trap density may contribute to increased drift mobility. The reduced bandgap of 3C-SiC contributes to a reduction in the electric field strength required to obtain channel inversion. Another property that makes 3C-SiC attractive is its low on-state resistance (Ron), which is particularly useful for devices operating up to and beyond 650 V.

[0004] Due to its greater ease of fabrication relative to other polytypes, 4H-SiC is commonly used as a substrate. However, the bandgap of 4H-SiC (3.2 eV) is larger than that of 3C-SiC (2.3 eV) or silicon (1.12 eV), making 4H-SiC less attractive for some electronic applications compared to 3C-SiC or silicon. For example, in the case of Schottky barrier diodes, the ability to control the Schottky barrier height (SBH) is an important aspect for reducing energy consumption and minimizing conduction losses. Therefore, the realization of metal / 3C-SiC or metal / Si contacts yields lower SBH values ​​compared to those of metal / 4H-SiC contacts, making it possible to fabricate more efficient Schottky diodes.

[0005] Different methods have been proposed for growing cubic silicon carbide (3C-SiC) on hexagonal silicon carbide (4H-SiC or 6H-SiC) substrates. One of them is known as the vapor-liquid-solid (VLS) mechanism, which is described, for example, in Soueidan M. et al., "A Vapor-Liquid-Solid Mechanism for Growing 3C-SiC Single-Domain Layers on 6H-SiC(0001)," Advanced Functional Materials, Vol. 16, pp. 975-979, May 2, 2006.

[0006] Another method is known as sublimation epitaxy (SE).

[0007] However, the above-mentioned methods require multiple growth steps and high control of the surface morphology, especially for layers or films grown by the SE method on off-axis 4H—SiC substrates (off-axis 4H—SiC substates).

[0008] An alternative to the above-mentioned techniques for producing 3C-SiC layers is chemical vapor deposition (CVD) on silicon substrates. However, 3C-SiC layers so formed have a high defect density (10 8 10 9 cm 3 (This arises from a lattice mismatch of about 20% between the two materials.)

[0009] Other solutions have also been proposed, such as the heteroepitaxial growth of 3C-SiC on an in-axis 6H-SiC substrate, for example by CVD techniques or by sublimation, but the large number of parameters that must be set in order to obtain a final product with good quality and the large number of variables that influence the formation of the 3C-SiC layer limit the use of known methods, especially in the industrial and mass production fields. [Prior art documents] [Non-patent literature]

[0010] [Non-Patent Document 1] Choi, I., Jeong, H., Shin, H. et al., "Laser-induced phase separation of silicon carbide," Nature Communications 7, 13562 (2016) Summary of the Invention [Problem to be solved by the invention]

[0011] It is an object of the present invention to provide a process or method for processing 4H-SiC wafers in a manner that overcomes the drawbacks and limitations of the prior art. [Means for solving the problem]

[0012] According to the present invention, a process for treating 4H-SiC wafers is provided as defined in the claims.

[0013] In order that the invention may be better understood, preferred embodiments thereof will now be described, purely by way of non-limiting example, with reference to the accompanying drawings, in which: [Brief explanation of the drawings]

[0014] [Figure 1] 1A-1F are schematic diagrams illustrating successive steps in a process for fabricating a 3C-SiC layer according to one embodiment of the present invention. [Figure 2] 5A-5C are schematic diagrams illustrating certain steps in a process for manufacturing a 3C-SiC layer according to a further embodiment of the invention; [Figure 3] 1A-1E are schematic diagrams illustrating successive steps of a process for producing a 3C-SiC layer according to a further embodiment of the present invention. [Figure 4]5A-5C are schematic diagrams illustrating certain steps in a process for manufacturing a 3C-SiC layer according to a further embodiment of the invention; DETAILED DESCRIPTION OF THE INVENTION

[0015] A method for forming a silicon carbide layer of polytype 3C-SiC according to one embodiment of the present invention will now be described with reference to Figures 1(A) through 1(F), which are represented in a three-axis reference system having mutually orthogonal X, Y, and Z axes.

[0016] 1(A), a silicon carbide wafer 1 of polytype 4H—SiC, particularly crystalline 4H—SiC, and even more particularly single crystal 4H—SiC, is provided. Wafer 1 includes a front side 1a and a back side 1b opposite each other along the Z axis. Wafer 1, in one embodiment, has a first electrical conductivity type, e.g., N conductivity type, and 10 18 10 22 Number of children / cm 3 The wafer 1 has a doping in the range, for example, a thickness, measured along the Z axis, equal to about 100-400 μm.

[0017] In general, the present invention applies to any 4H—SiC substrate.

[0018] In a further embodiment, the wafer 1 has a different conductivity type (i.e. P-type). However, for the purposes of the present invention, the conductivity type, i.e. the starting doping type, of the wafer 1 is irrelevant.

[0019] Wafer 1 is manufactured in a manner known per se and is not the object of the present invention, however 4H-SiC wafers are commercially available.

[0020] 1(B), a step of implanting doping species (indicated by arrows 2 parallel to the Z axis) is carried out, which is carried out on the front side 1a and without an implant mask (although an implant mask may be used based on need and design choice).

[0021] Thus, a doped layer 3 is formed, which extends uniformly on the front side 1a, and which extends to a depth within the wafer 1 and reaches a maximum depth of between 100 nm and 1000 nm measured from the surface of the front side 1a.

[0022] The doping step of FIG. 1B can, in one embodiment, be performed with doping species having a first conductivity type (N), such as nitrogen (N) and phosphorus (P). 17 10 20 Number of children / cm 3 To form a doped layer 3 having a dopant concentration between 20 and 500 keV, an implantation energy between 10 and 500 keV is used. 14 and 10 16 Number of children / cm 2 It is carried out in doses.

[0023] The doping step of FIG. 1B can, in a different embodiment, be a doping with a doping species having a second conductivity type (P) opposite to the first conductivity type, such as aluminum. 17 and 10 20 Number of children / cm 3 To form a doped layer 3 having a dopant concentration between 20 and 500 keV, an implantation energy between 10 and 500 keV is used. 14 and 10 16 Number of children / cm 2 It is carried out at a dose between 100 and 150 mg / kg.

[0024] The implantation process "breaks" the crystalline structure of the 4H-SiC, allowing the melting process described below to be carried out at lower temperatures than would be possible with crystalline material (e.g., as illustrated in FIG. 3(B)).

[0025] Then, referring to FIG. 1(C), a thermal budget, ie, a thermal history, is created at the surface of the front side 1a in order to cause local melting of a portion of the wafer 1 at the front side 1a.

[0026] For that purpose, a laser source 100 is used which is configured to generate a beam 102 such that the beam 102 heats the front side 1a, and in particular the doped layer 3, to a temperature between 1600° C. and 3000° C. Given the maximum depth reached by the doped layer 3, a temperature of about 2000° C. at the level of the surface of the front side 1a is sufficient to ensure a temperature within the aforementioned range even at the maximum depth reached by the doped layer 3.

[0027] This temperature is such that melting of the doped layer 3 occurs, and by interrupting the generation of the beam 102, i.e., by interrupting the heating of the wafer 1, re-solidification of the previously melted portion and its crystallization are observed. In particular, the inventors have discovered that the crystallization of the wafer 1 generates multiple superimposed layers, including a 3C—SiC layer 4 on the unmelted 4H—SiC material, a silicon layer 6 a on the 3C—SiC layer 4, and one or more carbon-rich layers 6 b (e.g., including one or more graphite layers and / or one or more graphene layers) on the silicon layer 6, as shown in FIG. 1(D).

[0028] The generation of the aforementioned layers by melting and subsequent crystallization of the 4H-SiC substrate is described, for example, in Choi, I., Jeong, H., Shin, H. et al., "Laser-induced phase separation of silicon carbide," Nature Communications. 7, 13562 (2016).

[0029] In one embodiment, the conversion of doped layer 3 into layers 4, 6a, 6b occurs by appropriately moving laser 100 to heat the entire front side 1a of wafer 1. For example, multiple scans of laser 100 are performed in the XY plane (e.g., multiple scans parallel to each other and to the X and / or Y axes).

[0030] In a further embodiment, only certain portions of the doped layer 3 are treated by the laser 100 in order to form the 3C-SiC layer exclusively in some areas of the wafer 1 (for example, only in the areas where the active areas of the devices intended to be provided / integrated in the wafer 1 will be formed).

[0031] The laser 100 is, for example, an excimer UV laser. Other types of lasers can be used, including lasers with wavelengths in the visible light range.

[0032] The configuration and operating parameters of laser 100 optimized to achieve the objectives of the present invention based on the embodiment of FIGS. 1(A)-(D) are as follows:

[0033] Wavelength: between 290 and 370 nm, especially 310 nm; Pulse duration: between 100ns and 300ns, especially 160ns; Number of pulses: between 1 and 10, especially 2; Energy density: 1.6 and 4 J / cm 2 Especially between 2.6J / cm 2 Consideration at the surface level of the front side 1a); and Temperature: between 1400° C. and 3000° C., in particular 1800° C. (considered at the level of the surface 1a).

[0034] The area of ​​the spot of the beam 102 at the level of the front side 1a is, for example, between 0.7 and 1.5 cm 2 It is between.

[0035] Crystallization of the molten part occurs in an environment with a temperature between 1600°C and 2700°C for a time between 100 ns and 300 ns.

[0036] Next, referring to FIG. 1(E), an oxidation step is performed on the carbon-rich layer 6b and the underlying silicon layer 6a to form respective oxide layers (collectively designated by the reference numeral 8 in FIG. 1(E)). This step is performed by inserting the wafer 1 into a furnace at a temperature of 800° C. for 60 minutes in an oxidizing environment, such as an oxygen-rich environment. This contributes to the oxidation of both the carbon-rich layer and the silicon layer. The inventors did not observe any corresponding oxidation of the 3C—SiC layer or the 4H—SiC substrate.

[0037] Then, referring to FIG. 1(F), a subsequent immersion in a suitable wet etching solution, such as BOE (buffered oxide etchant), allows the oxide layer 8 to be completely removed, exposing the underlying 3C—SiC layer 4.

[0038] The etching chemical solution selectively removes material of the oxide layer 8 , so that the etching proceeds until the oxide layer 8 is completely removed without removing the underlying 3C—SiC layer 4 .

[0039] In a further embodiment of the invention illustrated in FIG. 2, after carrying out the steps already described with reference to FIGS. 1(A)-(C), melting and subsequent resolidification (recrystallization) of the material of wafer 1 results in the formation of a further 6H—SiC layer 10 intermediate the 4H—SiC material of wafer 1 and the 3C-SiC layer 4.

[0040] The formation of the 6H—SiC layer is caused by appropriate selection of the thermal budget applied to the 4H—SiC wafer via laser 100, i.e., by adjusting the configuration and operating parameters of laser 100 during the melting process of the portion of the wafer being processed. Subsequent crystallization of the melted portion causes the additional formation of the 6H—SiC layer in a natural manner (i.e., without being controlled by further intervention by an operator). The configuration / operating parameters of laser 100 (i.e., of the radiation emitted by the laser) are as follows:

[0041] Wavelength: between 290 and 370 nm, especially 310 nm; Pulse duration: between 100ns and 300ns, especially 160ns; Number of pulses: between 1 and 10, especially 2; Energy density: 1.6 and 4 J / cm 2 Especially between 2.6J / cm 2 considered at the level of the surface of the front side 1a); and Temperature: between 1400° C. and 2600° C., in particular 1800° C. (considered at the level of the surface 1a).

[0042] Crystallization of the molten part occurs in an environment at a temperature between 1600°C and 2700°C for a time between 100 ns and 300 ns.

[0043] Next, the oxidation and etching steps already described with reference to FIGS. 1(E) and 1(F) are carried out.

[0044] Figures 3(A)-(E) illustrate further embodiments of the present invention, which are illustrated in a three-axis reference system with mutually orthogonal X, Y and Z axes.

[0045] 3(A), a silicon carbide wafer 21 of polytype 4H—SiC, particularly crystalline 4H—SiC, and even more particularly single crystal 4H—SiC, is provided. Wafer 21 includes a front side 21a and a back side 21b opposite each other along the Z axis. Wafer 21, in one embodiment, has a first conductivity type, e.g., N-type, and a density of 1e18-1e22 atoms / cm. 3 The doping ranges.

[0046] The wafer 21 has, for example, a thickness measured along the Z axis equal to about 100 and 400 μm.

[0047] In a further embodiment, wafer 21 has a different conductivity type (i.e., P-type), however, for purposes of the present invention, the conductivity type or starting doping type of wafer 21 does not matter.

[0048] Wafer 1 is manufactured in a manner known per se and is not the object of the present invention, however 4H-SiC wafers are commercially available.

[0049] Then, referring to FIG. 3B, a thermal budget, ie, a thermal history, is generated at the surface of the front side 21a to cause localized melting of a portion of the wafer 21 at the front side 21a.

[0050] For this purpose, a laser source 100 is used, configured to generate a beam 102 for heating the front side 21a to a temperature equal to approximately 1600-3000° C. A temperature of approximately 3000° C. at the level of the surface of the front side 21a is sufficient to ensure a temperature within the above-mentioned range at a depth in the wafer 21 equal to, for example, approximately 10 μm. This temperature is what causes melting of the part of the wafer 21 being processed via the laser 100. By interrupting the generation of the beam 102, i.e. by interrupting the heating of the wafer 21, a resolidification of the melted part and, in particular, its recrystallization in a predefined and predictable manner is observed. In particular, the inventors have discovered that recrystallization of wafer 21 generates multiple superimposed layers, including a 3C—SiC layer 24 on the unmelted 4H—SiC material, a silicon layer 26 a on the 3C—SiC layer 24, and one or more carbon-rich layers 26 b (e.g., including graphite or graphene multilayers) on the silicon layer 26 a, as illustrated in FIG. 3(C).

[0051] In one embodiment, the conversion of a portion of the wafer 1 into layers 24, 26a, 26b occurs by heating the entire front side 21a of the wafer 21 by appropriately moving the laser 100. For example, multiple scans of the laser 100 are performed in the XY plane (e.g., multiple scans parallel to each other and to the X and / or Y axes). In a further embodiment, only some areas of the wafer 1 (in the XY plan view) are treated by the laser 100 in order to obtain the formation of the 3C—SiC layer 24 exclusively in some areas of the wafer 21 (e.g., only in areas where the active areas of devices intended to be provided / integrated in the wafer 21 will be formed).

[0052] The configuration and operating parameters of the laser 100 optimized to achieve the objectives of the present invention based on the embodiment of FIGS. 3A-3C are as follows:

[0053] Wavelength: between 290 and 370 nm, especially 310 nm; Pulse duration: between 100ns and 300ns, and goes to 160ns; Number of pulses: between 1 and 10, especially 2; Energy density: 1.6 and 5 J / cm 2 Especially 3.8J / cm 2 considered at the level of the surface of the front side 1a); and Temperature: between 2000 and 3000° C., in particular 2600° C. (considered at the level of the surface 1a).

[0054] The area of ​​the spot of the beam 102 at the level of the front side 1a is, for example, between 0.7 and 1.5 cm 2 It is between.

[0055] Crystallization of the molten part occurs in an environment with temperatures between 1600 and 2700°C in a time between 100 and 300 ns.

[0056] Next, referring to FIG. 3(D), an oxidation process is performed on the silicon layer 26a and the carbon-rich layer 26b, similar to that previously described, to form respective oxide layers (indicated in the figure by the general reference numeral 28).

[0057] This step is performed by inserting wafer 21 into a furnace at a temperature of 800° C. for 60 minutes in an oxidizing environment, specifically an oxygen environment. This contributes to the oxidation of both the carbon-rich layer and the silicon layer. We did not observe corresponding oxidation of the 3C—SiC layer and the 4H—SiC substrate.

[0058] Then, referring to FIG. 3(E), the oxide layer 28 can be completely removed by a subsequent immersion in a suitable wet etching solution, such as BOE (buffered oxide etchant), exposing the underlying 3C—SiC layer 24.

[0059] Because the etching chemical solution selectively removes material of oxide layer 28, the etching proceeds until the oxide layer is completely removed without removing the underlying 3C-SiC layer 24.

[0060] In a further embodiment of the invention illustrated in FIG. 4, after carrying out the steps already described with reference to FIGS. 3A and 3B, melting and subsequent recrystallization of the material of wafer 21 results in the formation of a further 6H—SiC layer 29 intermediate the 4H—SiC material of wafer 21 and the 3C—SiC layer 24.

[0061] Formation of the 6H—SiC layer 29 occurs by appropriately adjusting the configuration and operating parameters of the laser 100 (as previously described with reference to FIG. 2) to emit a suitable beam, as follows:

[0062] Wavelength: between 290 and 370 nm, especially 310 nm; Pulse duration: between 100ns and 300ns, especially 160ns; Number of pulses: between 1 and 10, especially 2; Energy density: 1.6 and 4 J / cm 2 Especially between 2.6J / cm 2 considered at the level of the surface of the front side 1a); and Temperature: between 1400° C. and 2600° C., in particular 1800° C. (considered at the level of the surface 1a).

[0063] Crystallization of the molten part occurs in an environment with temperatures between 1600°C and 2700°C in a time between 100 ns and 300 ns.

[0064] Next, the oxidation and etching steps already described with reference to FIGS. 3(D) and 3(E) are carried out.

[0065] From an examination of the properties of the present invention provided in accordance with this disclosure, the advantages it offers are apparent.

[0066] In particular, 3C—SiC layers with desirable electrical properties, such as reduced bandgap and high electron mobility, can be produced in a fast and inexpensive manner and can be integrated with known industrial processes.

[0067] Furthermore, according to the verification by the present inventors, the defect density of the 3C-SiC layer thus produced is low.

[0068] The possibility of producing 3C-SiC layers on 4H-SiC substrates makes it possible to fully take advantage of the properties of silicon carbide.

[0069] Furthermore, the heating and melting process occurs in a single step during which the laser parameters (e.g., energy and number of pulses) can be precisely controlled, making the process highly reproducible.

[0070] Although specific embodiments of the present invention have been described in detail above, the present invention should not be limited to these specific embodiments, and it goes without saying that various modifications and alterations can be made without departing from the technical scope of the present invention.

Claims

1. 1. A method for processing a wafer (1;21) of 4H—SiC material, comprising: heating a selectable portion of the surface (1a, 21a) of the wafer (1; 21) via a laser beam (102) to at least the melting temperature of the material of said selectable portion; allowing the molten selectable portion to crystallize, forming a stack of superimposed layers including a 3C-SiC layer (4; 24) in contact with the 4H-SiC material of the wafer (1; 21), a silicon layer (6a; 26a) above the 3C-SiC layer (4; 24), and a carbon-rich layer (6b; 26b) above the silicon layer (6a; 26a); and Completely removing said carbon-rich layer (6b; 26b), A method that encompasses the above.

2. 2. The method of claim 1, further comprising the step of completely removing the silicon layer (6a; 26a) to expose the 3C-SiC layer (4; 24).

3. 2. The method of claim 1, wherein the selectable portion comprises crystalline 4H-SiC material, particularly single crystal 4H-SiC.

4. 2. The method of claim 1, further comprising, before the heating step, implanting a doping species into the surface (1 a; 21 a) to form an implanted region (3), wherein the selectable portion comprises the implanted region (3).

5. 2. A method according to claim 1, wherein the heating step is carried out by generating a temperature between 1600 and 3000°C at the level of the surface (1a; 21a).

6. 2. The method of claim 1, wherein the step of allowing the molten selectable portion to crystallize comprises placing the wafer (1; 21) in an environment at a temperature between 1600 and 2700°C for a time between 100 ns and 300 ns.

7. 3. The method of claim 2, wherein the step of removing the carbon-rich layer (6b; 26b) comprises performing the steps of oxidizing the carbon-rich layer (6b; 26b) to form an oxidized carbon layer (8; 28) and etching the oxidized carbon layer (8; 28).

8. 8. The method of claim 7, wherein the step of removing the silicon layer (8a; 26a) comprises performing the steps of oxidizing the silicon layer (6a; 26a) to form an oxidized silicon layer (8; 28) and etching the oxidized silicon layer (8; 28).

9. 9. A method according to claim 8, wherein the steps of oxidizing the silicon layer (6a; 26a) and oxidizing the carbon-rich layer (6b; 26b) are carried out simultaneously and / or the steps of etching the oxidized silicon layer (8; 28) and etching the oxidized carbon layer (8; 28) are carried out simultaneously.

10. The laser beam (102) has the following parameters: wavelengths between 290 nm and 370 nm; Pulse duration between 100 and 300 ns; Number of pulses between 1 and 10; 1.6 and 5 J / cm ２ Energy density between The method of claim 3, wherein the signal is generated according to:

11. The laser beam (102) has the following parameters: wavelengths between 290 nm and 370 nm; Pulse duration between 100 and 300 ns; Number of pulses between 1 and 10; 1.6 and 4 J / cm ２ Energy density between 5. The method of claim 4, wherein the signal is generated according to:

12. 2. The method of claim 1, wherein the selectable portion has a shape and extent that, in plan view, corresponds to the shape and extent of a wafer (1; 21).

13. 2. The method of claim 1, wherein the selectable portion has an extent, in plan view, lower than the extent of the wafer (1; 21).

14. 2. The method of claim 1, wherein the selectable portion extends into the wafer (1; 21) to a maximum depth of between 10 and 100 nm.

15. 2. The method of claim 1, wherein the carbon-rich layer (6; 26) comprises one or more graphene layers and / or one or more graphite layers.

16. The step of forming a 6H—SiC layer (9; 29) interposed between the 4H—SiC material and the 3C—SiC layer (4; 24) of the wafer (1; 21) is performed by adjusting the following parameters: wavelengths between 290 nm and 370 nm; Pulse duration between 100 and 300 ns; Number of pulses between 1 and 10; 1.6 and 4 J / cm ２ Energy density between 10. The method of any one of the preceding claims, further comprising generating the laser beam (102) according to:

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