Voltage detection circuit, charge control circuit, charging and discharge control circuit, and semiconductor device
Patent Information
- Application Number
- JP2022190306
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2022-03-29
- Filing Date
- 2022-11-29
- Publication Date
- 2025-10-02
AI Technical Summary
Conventional voltage detection circuits for multi-cell secondary batteries face challenges with increased circuit area and power consumption due to high breakdown voltage requirements, leading to larger element sizes and increased channel lengths.
The proposed solution involves a voltage detection circuit with a cascade connection of transistors, including an input transistor with a lower breakdown voltage and a cascode transistor, along with a protection circuit to clamp the input voltage, reducing the overall circuit area and power consumption.
This configuration effectively suppresses the increase in circuit area and power consumption, maintaining reliability and reducing the breakdown voltage of transistors, thereby minimizing the overall size and power requirements of the voltage detection circuit.
Smart Images
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Abstract
Description
Technical Field
[0001] The present invention relates to a voltage detection circuit, a charge control circuit, a charge / discharge control circuit, and a semiconductor device.
Background Art
[0002] From the viewpoint of obtaining a higher voltage, a battery device incorporating a secondary battery having a plurality of battery cells (hereinafter referred to as "multi-cell") connected in series may be applied. In a circuit to which a multi-cell secondary battery is connected, in a voltage detection circuit that detects the voltage between intermediate terminals, when an intermediate terminal is short-circuited to a power supply terminal or a ground terminal, that is, when there is an open circuit or a short circuit to ground, a higher voltage than that of a battery device incorporating a single secondary battery cell (hereinafter referred to as "single cell") is applied to the intermediate terminal. A charge / discharge control circuit including a voltage detection circuit having a comparator is known in order to detect an open circuit or a short circuit to ground of an intermediate terminal as an abnormality during charge / discharge (see, for example, Patent Document 1). In addition, from the viewpoint of simplifying the configuration of the voltage detection circuit, it is also possible to replace it with a voltage detection circuit in which the comparator is more simplified.
[0003] FIG. 8 is a circuit diagram schematically showing a main configuration including a conventional voltage detection circuit 30 in which the comparator described in Patent Document 1 is configured more simply, among a charge / discharge control circuit 100 which is an example of a conventional charge / discharge control circuit. Here, when 2 or more natural numbers n are the number of battery cells connected in series of a multi-cell configured secondary battery, the charge / discharge control circuit 100 is configured to be connectable to a secondary battery having n battery cells connected in series. In FIG. 8, the final-stage voltage detection circuit 30 and level shifter 40 connected to the last battery cell are shown from the positive electrode side to the negative electrode side of the secondary battery.
[0004] In Figure 8, the charge / discharge control circuit 100 comprises a voltage detection circuit 30, a level shifter 40, an overvoltage detection circuit 12, and a control circuit 15. The voltage detection circuit 30 and the level shifter 40 are constructed using MOS transistors, which are an example of field-effect transistors (hereinafter referred to as "FETs"). The voltage detection circuit 30 has an enhancement-type NMOS transistor 31 and a depletion-type NMOS transistor 32. The level shifter 40 has an enhancement-type PMOS transistor 41 and a constant current source 42.
[0005] NMOS transistor 31 includes a drain, a gate connected to the connection point P_(n-1) of resistors 21_(n-1) and 22_(n-1) connected in series between the positive and negative terminals of a single battery cell, and a source connected to the negative power supply input terminal VSS. The negative power supply input terminal VSS is connected to power supply terminal 9, which is supplied with the power supply voltage Vss. NMOS transistor 32 includes a drain connected to power supply terminal 8, which is supplied with a power supply voltage Vdd, which is different from voltage Vss, a source connected to the drain of NMOS transistor 31, and a gate short-circuited to its own source. Furthermore, the connection point between the drain of NMOS transistor 31 and the source of NMOS transistor 32 is connected to the gate of PMOS transistor 41.
[0006] The PMOS transistor 41 includes a source connected to the power supply terminal 8, a gate connected to the drain of the NMOS transistor 31 and the source of the NMOS transistor 32, and a drain. The constant current source 42 includes a first terminal connected to the drain of the PMOS transistor 41 and a second terminal connected to the negative power supply input terminal VSS. The second terminal of the constant current source 42 and the connection point between the drain of the PMOS transistor 41 and the first terminal of the constant current source 42 are connected to the subsequent overvoltage detection circuit 12.
[0007] The overvoltage detection circuit 12 has a function to determine whether each cell 2_1, ..., 2_n is overvoltage based on the voltage across its terminals. When the voltage of the negative power supply input terminal VSS and the voltage of the drain of the PMOS transistor 41 are input to the overvoltage detection circuit 12, it determines whether each cell 2_1, ..., 2_n is overvoltage. The determination result from the overvoltage detection circuit 12 is transmitted from the overvoltage detection circuit 12 to the control circuit 15.
[0008] The control circuit 15 is configured to output a control signal to the charge control signal output terminal CO or the discharge control signal output terminal DO that switches the transistor on and off in response to signals input from other circuits, including circuits other than the overvoltage determination circuit 12, such as an over-discharge detection circuit and an overcharge detection circuit, which are not shown in the figure. [Prior art documents] [Patent Documents]
[0009] [Patent Document 1] Japanese Patent Publication No. 2020-10536 [Overview of the Initiative] [Problems that the invention aims to solve]
[0010] In conventional multi-cell secondary battery circuits, such as the charge / discharge control circuit 100 illustrated in Figure 8, if a short circuit occurs and the gate voltage of the NMOS transistor 31 rises, the signal level of the drain of the NMOS transistor 31 inverts from a high (hereinafter referred to as "H") level to a low (hereinafter referred to as "L") level. That is, the voltage detection circuit 30 can detect the presence or absence of a short circuit based on the signal level of the drain of the NMOS transistor 31. The withstand voltage of the element that receives the voltage at the cell connection terminal VC(n-1), which is an intermediate terminal of the voltage detection circuit 30, is determined considering the voltage of the secondary battery. This is because if the path connecting the positive terminals of the n battery cells and the cell connection terminal VC(n-1) is short-circuited (short-circuited with the power supply terminal 8), the voltage obtained by connecting the n battery cells in series will be applied to the gate of the NMOS transistor 31.
[0011] The breakdown voltage of NMOS transistors 31 and 32 is determined by considering the voltage of the secondary battery, i.e., the magnitude of n, and the breakdown voltage increases as the number of battery cells increases. Semiconductor elements like NMOS transistors 31 have the disadvantage that the area of the element increases as the breakdown voltage increases, so the area of the voltage detection circuit increases as the number of battery cells increases. In addition, in order to achieve low power consumption while ensuring breakdown voltage, it is necessary to increase the channel length (L length), so the tendency for the circuit area to increase becomes more pronounced.
[0012] The present invention has been made in view of the above circumstances, and aims to provide a voltage detection circuit, a charging control circuit, a charge / discharge control circuit, and a semiconductor device that can suppress the increase in area of a voltage detection circuit connected to a multi-cell secondary battery. [Means for solving the problem]
[0013] A voltage detection circuit according to an embodiment of the present invention is characterized by comprising: an input transistor including a gate to which a voltage to be detected is applied, a source connected to a first power supply terminal, and a drain; a bypass transistor including a gate connected to the gate of the input transistor, a drain connected to the drain of the input transistor, a source connected to the gate of the input transistor and its own gate, and a back gate connected to the first power supply terminal; a first transistor including a first terminal connected to the input transistor and a second terminal connected to an output terminal to which a signal indicating the voltage detection result is output; a second transistor including a drain connected to a second power supply terminal, a gate, and a source connected to its own gate; and a third transistor cascaded with the second transistor. [Effects of the Invention]
[0014] According to the present invention, it is possible to suppress the increase in the area of the voltage detection circuit connected to a multi-cell secondary battery that occurs as the number of cells increases. [Brief explanation of the drawing]
[0015] [Figure 1] This is a schematic diagram showing an example configuration of a charge / discharge control circuit and semiconductor device according to the first embodiment of the present invention. [Figure 2] This is a schematic circuit diagram showing the main configurations of a voltage detection circuit and a charge / discharge control circuit equipped therewith according to a first embodiment of the present invention. [Figure 3] This is a schematic circuit diagram showing the main configuration of a voltage detection circuit according to a second embodiment of the present invention. [Figure 4] This is a schematic circuit diagram showing the main configuration of another example (first modified example) of the voltage detection circuit according to an embodiment of the present invention. [Figure 5] This is a schematic circuit diagram showing the main configuration of another example (second modified example) of the voltage detection circuit according to an embodiment of the present invention. [Figure 6]It is a circuit diagram schematically showing the main configuration of another configuration example (third modification example) of the voltage detection circuit according to an embodiment of the present invention. [Figure 7] It is a schematic diagram showing another configuration example (fourth modification example) of the charge control circuit according to an embodiment of the present invention and the semiconductor device according to an embodiment of the present invention. [Figure 8] It is a circuit diagram schematically showing the main configuration including the conventional voltage detection circuit among the conventional charge-discharge control circuits.
Embodiments for Carrying Out the Invention
[0016] Hereinafter, the voltage detection circuit, charge control circuit, charge-discharge control circuit, and semiconductor device according to the embodiments of the present invention will be described with reference to the drawings. In the following description, components that are substantially the same as those of the charge-discharge control circuit 100 shown in FIG. 8 as an example of the conventional charge-discharge control circuit are denoted by the same reference numerals and the description thereof is omitted.
[0017] [First Embodiment] FIG. 1 is a block diagram showing the circuit configuration of a battery device 1 which is an example of a semiconductor device according to the first embodiment of the present invention.
[0018] The battery device 1 includes an IC chip formed on a semiconductor substrate by a semiconductor process, specifically, a charge-discharge control circuit 10 that controls the charge and discharge of the secondary battery 2.
[0019] The battery device 1 and the charge-discharge control circuit 10 are an example of the semiconductor device and the charge-discharge control circuit according to the first embodiment, respectively. The battery device 1 includes a secondary battery 2 including a so-called multi-cell configured battery pack, an external positive electrode terminal P+ and an external negative electrode terminal P-, a discharge control FET (Field Effect Transistor) 3, a charge control FET 4, and a charge-discharge control circuit 10 for controlling the charge and discharge of the secondary battery 2.
[0020] The secondary battery 2 is a so-called multi-cell battery, which includes a battery pack consisting of n battery cells (hereinafter simply referred to as "cells") 2_1 to 2_n connected in series, where "n" is the number of cells connected in series. In the case of a multi-cell battery, n is a natural number greater than or equal to 2, i.e., multiple. The n cells 2_1, ..., 2_n are connected in series in this order, from the positive electrode 2a of the secondary battery 2 to the negative electrode 2b of the secondary battery 2.
[0021] The charge / discharge control device 20 comprises an external positive terminal P+ and an external negative terminal P-, a discharge control FET 3, a charge control FET 4, and a charge / discharge control circuit 10. In other words, the charge / discharge control device 20 as a semiconductor device is a device that omits the secondary battery 2 from the battery device 1.
[0022] The external positive terminal P+ and external negative terminal P- are terminals for connecting to external devices (not shown), such as a charger and a load. Within the battery device 1, the path connecting the external positive terminal P+ and the external negative terminal P- (hereinafter referred to as the "inter-external terminal path") connects, for example, the secondary battery 2, the overcurrent detection resistor 5, the discharge control FET 3, and the charge control FET 4 in that order, starting from the external positive terminal P+ side.
[0023] The battery device 1 and the charge / discharge control device 20 are equipped with a discharge control FET 3 and a charge control FET 4 on the external negative terminal P- side, i.e., the low side. Both the discharge control FET 3 and the charge control FET 4 are NMOS transistors, and their drains are connected to each other.
[0024] The discharge control FET 3 includes a gate connected to the discharge control signal output terminal DO, a drain as one end connected to the drain of the charge control FET 4, and a source as the other end connected to one end of the overcurrent detection resistor 5.
[0025] The charge control FET 4 includes a gate connected to the charge control signal output terminal CO, a source as one end connected to the external negative terminal P-, and a drain as the other end connected to the drain of the discharge control FET 3.
[0026] The charge / discharge control circuit 10 includes a positive power input terminal VDD, a negative power input terminal VSS, cell connection terminals VC1, ..., VC(n-1), a charge control signal output terminal CO, a discharge control signal output terminal DO, an external negative voltage input terminal VM, and an overcurrent detection terminal VINI.
[0027] The positive power input terminal VDD, which serves as the first power input terminal, is connected to the positive terminal 2a via resistor R1, and is supplied with voltage from the positive terminal 2a of the secondary battery 2. The negative power input terminal VSS, which serves as the second power input terminal, is connected to the negative terminal 2b, and is supplied with voltage from the negative terminal 2b.
[0028] Cell connection terminal VC1 is connected via resistor R2 to the contacts of the first cell 2_1 and the second cell 2_2, namely the negative terminal of the first cell 2_1 and the positive terminal of the second cell 2_2. Similarly to cell connection terminal VC1, cell connection terminals VC2, ..., VC(n-1) are connected via resistors R3, ..., Rn to the negative terminal of the second cell 2_2 and the positive terminal of the third cell 2_3, ..., the negative terminal of the (n-1)th cell 2_(n-1) and the positive terminal of the nth cell 2_n, respectively.
[0029] Here, the end of resistor R1,...,Rn that connects from the first cell 2_1 to the nth cell 2_n (the left end in Figure 1) is referred to as the first end, and the end that connects to the positive power input terminal VDD, the cell connection terminals VC1,...,VC(n-1) and the negative power input terminal VSS, that is, the end in the opposite direction from the first end, is referred to as the second end (the right end in Figure 1).
[0030] Capacitor C1 is connected between the second terminal of resistor R1 and the positive power input terminal VDD, and between the negative terminal 2b and the negative power input terminal VSS, for voltage fluctuation suppression. Similarly to capacitor C1, capacitors C2, ..., Cn are connected between the second terminals of resistors R2, ..., Rn and the cell connection terminals VC1, ..., VC(n-1), and between the negative terminal 2b and the negative power input terminal VSS, respectively.
[0031] The charge control signal output terminal CO is a terminal that outputs a charge control signal, which controls the stopping and enabling of charging of the secondary battery 2 and is generated within the charge / discharge control circuit 10, to the outside of the charge / discharge control circuit 10. The charge control signal output terminal CO is connected to the gate of the charge control FET 4.
[0032] The discharge control signal output terminal DO is a terminal that outputs a discharge control signal, which controls the stopping and enabling of the discharge of the secondary battery 2, generated within the charge / discharge control circuit 10, to the outside of the charge / discharge control circuit 10. The discharge control signal output terminal DO is connected to the gate of the discharge control FET 3.
[0033] The external negative voltage input terminal VM is connected to the external negative terminal P- and the source of the charge control FET 4 via resistor 6.
[0034] The overcurrent detection terminal VINI is connected to one end of the overcurrent detection resistor 5 and the source of the discharge control FET 3.
[0035] Figure 2 is a schematic circuit diagram showing the main components of a charge / discharge control circuit 10, which is an example of a charge / discharge control circuit according to this embodiment.
[0036] The charge / discharge control circuit 10 differs from the charge / discharge control circuit 100 (see Figure 8) in that it includes a voltage detection circuit 50 instead of a voltage detection circuit 30 (see Figure 8), but otherwise there are no substantial differences. Therefore, in the description of the charge / discharge control circuit 10, the explanation will focus on the voltage detection circuit 50, and components such as the level shifter 40 (see Figure 8), which are substantially the same, will be given the same reference numerals and their explanations will be simplified or omitted.
[0037] The charge / discharge control circuit 10 includes a voltage detection circuit 50, which is an example of a voltage detection circuit according to this embodiment, a level shifter 40, an overvoltage determination circuit 12, and a control circuit 15. The voltage detection circuit 50 has the following differences from the voltage detection circuit 30: it has an enhancement-type NMOS transistor 51 instead of an NMOS transistor 31, it has a protection circuit 60 instead of an NMOS transistor 32, and it further has a depletion-type NMOS transistor 52, a depletion-type NMOS transistor 53, and an enhancement-type NMOS transistor 54.
[0038] The NMOS transistor 51, used as an input transistor, is connected in the same way as the NMOS transistor 31, but its breakdown voltage is lower than that of the NMOS transistor 31, making it a relatively low-voltage FET. In other words, the NMOS transistor 51 has a smaller area than the NMOS transistor 31. The NMOS transistor 51 is set to have a gate breakdown voltage that is greater than or equal to the voltage applied to the gate in a normal state where no ceiling or ground faults occur, specifically greater than or equal to the voltage of a single cell.
[0039] An example of a FET, the NMOS transistor 52 is a so-called cascode transistor and is connected to the NMOS transistor 51 to ensure a certain level of drain-source voltage VDS. The NMOS transistor 52 includes a source as the first terminal, which is connected to the drain of the NMOS transistor 51. The connection point between the source of the NMOS transistor 52 and the drain of the NMOS transistor 51 constitutes node P2. The NMOS transistor 52 also includes a gate, which is connected to the gate of the NMOS transistor 51, and a drain, which is the second terminal, which is connected to the output terminal P3 of the voltage detection circuit 50. In other words, the drain of the NMOS transistor 52 is connected to the level shifter 40 (more specifically, the gate of the PMOS transistor 41) of the downstream circuit of the voltage detection circuit 50.
[0040] The NMOS transistor 54, acting as a bypass transistor, includes a gate connected to the gate of NMOS transistor 51 and the gate of NMOS transistor 52, a source connected to the gate of NMOS transistor 51 and its own gate, a drain connected to the drain of NMOS transistor 51 and the source of NMOS transistor 52, and a back gate connected to the source of NMOS transistor 51 and the power supply terminal 9. The connection point of the drain of NMOS transistor 54, the drain of NMOS transistor 51, and the source of NMOS transistor 52 constitutes node P2. Like NMOS transistor 51, NMOS transistor 54 is a relatively low-voltage FET, with a voltage rating lower than that of NMOS transistor 31.
[0041] The NMOS transistor 53 includes a drain connected to the power supply terminal 8, a gate, and a source connected to its own gate, and operates as a constant current source. The connection point between the NMOS transistor 53 and the protection circuit 60 constitutes node P1. Because the NMOS transistor 53 is protected by the voltage withstand voltage protection circuit 60, a relatively low voltage FET can be used.
[0042] The protection circuit 60 includes, for example, PMOS transistors 61, 62, and 63, which are examples of FETs, and a constant current source 65.
[0043] PMOS transistor 61 includes a source connected to the power supply terminal 8, a gate, and a drain connected to its own gate. PMOS transistor 62 includes a source connected to the drain of PMOS transistor 61, a gate, and a drain connected to its own gate. PMOS transistor 63 includes a source connected to the gate and source of NMOS transistor 53, a gate connected to the gate and drain of PMOS transistor 62, and a drain connected to the drain of NMOS transistor 52 and the gate of PMOS transistor 41.
[0044] The constant current source 65 includes a first terminal connected to the gate and drain of PMOS transistor 62 and the gate of PMOS transistor 63, and a second terminal connected to the power supply terminal 9.
[0045] In the protection circuit 60, two PMOS transistors 61 and 62, which are connected in cascade, and a constant current source 65 that supplies drain current to the PMOS transistors 61 and 62, constitute a clamp circuit. PMOS transistor 63 constitutes the output transistor of the protection circuit 60, receiving the output voltage from the clamp circuit at its gate. PMOS transistors 61, 62, and 63 have a voltage rating similar to that of the NMOS transistor 32.
[0046] The overvoltage detection circuit 12 has a function to determine whether each cell 2_1, ..., 2_n is overvoltage based on the input voltage across its terminals, and is configured to determine whether each cell 2_1, ..., 2_n is overvoltage. The control circuit 15 is configured to supply a control signal to switch the transistor on and off at the charge control signal output terminal CO or the discharge control signal output terminal DO in response to signals input from other circuits, including circuits other than the overvoltage detection circuit 12, which include at least one of an over-discharge detection circuit and an overcharge detection circuit (not shown in the figure).
[0047] Next, we will explain the operation of the voltage detection circuit 50 by giving an example of a case in which the highest voltage is applied to the voltage detection circuit 50, specifically when the cell connection terminal VC(n-1) is short-circuited (short-circuited with the power supply terminal 8).
[0048] In the normal state before the cell connection terminal VC(n-1) experiences a short circuit, NMOS transistors 51 and 54 are off. The voltage at node P2 is voltage Vdd. The voltage at the output terminal P3 of the voltage detection circuit 50 corresponds to a signal indicating the voltage detection result, and is at a high level in the normal state.
[0049] When the cell connection terminal VC(n-1) experiences a short circuit, the voltage Vdd of the power supply terminal 8, which corresponds to the voltage of the secondary battery 2, is applied to the gate of the NMOS transistor 51. After the cell connection terminal VC(n-1) experiences a short circuit, the voltage at the gate of the NMOS transistor 51 gradually increases, and eventually the voltage at the gate of the NMOS transistor 51 exceeds the threshold voltage of the NMOS transistor 51. When the voltage at the gate of the NMOS transistor 51 exceeds the threshold voltage of the NMOS transistor 51, the NMOS transistor 51 turns on and conducts.
[0050] When NMOS transistor 51 conducts, the voltage at node P2 drops to "gate voltage of NMOS transistor 51 - threshold voltage of NMOS transistor 52". As the voltage at node P2 decreases, the voltage at output terminal P3 also decreases, transitioning from a high level to a low level. That is, a signal indicating that a short circuit has been detected at the cell connection terminal VC(n-1) is output from output terminal P3 to the level shifter 40. The voltage at node P2 is higher than the gate voltage of NMOS transistor 51 because the threshold voltage of NMOS transistor 52 is negative. Even after NMOS transistor 51 conducts, NMOS transistor 54 remains off until the gate voltage of NMOS transistor 51 reaches the reference voltage Vref. While NMOS transistor 54 remains off, the voltage at node P2 remains higher than the gate voltage of NMOS transistor 51.
[0051] Furthermore, when the gate voltage of NMOS transistor 51 rises to above the reference voltage Vref, NMOS transistor 54 turns on and conducts. When NMOS transistor 54 turns on and conducts, the voltage at node P2 drops to "gate voltage of NMOS transistor 51 - threshold voltage of NMOS transistor 51 - overdrive voltage of NMOS transistor 51".
[0052] Here, the voltage at the same node as the gate of NMOS transistor 51 is greater than or equal to the voltage at node P2, based on the relationship between the threshold voltage and overdrive voltage of NMOS transistor 51. Therefore, a bypass current flows from the drain to the source of NMOS transistor 51 via NMOS transistor 54, so that the gate voltage of NMOS transistor 51 is clamped to the reference voltage Vref. As a result, the voltage rise at the gate of NMOS transistor 51 is suppressed to near the reference voltage Vref.
[0053] The protection circuit 60 protects the NMOS transistor 53 from overvoltage by clamping the voltage at the source of the NMOS transistor 53, i.e., the voltage at node P1, to a predetermined voltage. The predetermined voltage is set considering the voltage Vdd at the power supply terminal 8, the source-drain voltage of the NMOS transistor 53 when conducting, and the breakdown voltage of the NMOS transistor 53. For example, if the PMOS transistors 61, 62, and 63 are all FETs with the same threshold voltage |Vthp|, the voltage at node P1 will be clamped to the voltage (Vdd - |Vthp|).
[0054] The signal processing after the voltage detection circuit 50 is the same as that of a conventional charge / discharge control circuit 100, a charge / discharge control device equipped with the charge / discharge control circuit 100, and a battery device. That is, in the example shown in Figure 2, the overvoltage determination circuit 12 determines whether or not cell 2_n is overvoltage based on the voltage input from the voltage detection circuit 50 via the level shifter 40, and transmits a signal corresponding to the determination result to the control circuit 15. Based on the signal corresponding to the received determination result, the control circuit 15 supplies a control signal to the charge control signal output terminal CO that switches the charge control FET 4 on and off, while supplying a control signal to the discharge control signal output terminal DO that switches the discharge control FET 3 on and off.
[0055] With the voltage detection circuit 50, and the charge / discharge control circuit 10, charge / discharge control device 20, and battery device 1 equipped with the voltage detection circuit 50, the input voltage to the NMOS transistor 51, which includes a gate to which the voltage input to the voltage detection circuit 50 is applied, can be kept lower than in the conventional design. Because the input voltage to the NMOS transistor 51 can be kept lower than in the conventional design, the breakdown voltage of the NMOS transistor 51 can be kept lower than that of the NMOS transistor 31 in the conventional voltage detection circuit 30 (see Figure 8).
[0056] Furthermore, the breakdown voltage of NMOS transistors 53 and 54 can be kept to the same level as NMOS transistor 51 (relatively low breakdown voltage). In addition, due to the functional differences between NMOS transistor 53 and NMOS transistor 54, a channel length (L length) that is significantly shorter (by about one to two orders of magnitude smaller) than that of NMOS transistor 51 can be applied to NMOS transistors 53 and 54. On the other hand, NMOS transistors 52 and PMOS transistors 61, 62, and 63 require a similar breakdown voltage to NMOS transistors 31 and 32, but due to the functional differences, their channel length (L length) can be made even shorter (by about one to two orders of magnitude smaller).
[0057] Therefore, although the voltage detection circuit 50 has more elements than the voltage detection circuit 30, the area of each element is smaller than that of the NMOS transistors 31 and 32, and in terms of total area, the area of the voltage detection circuit 50 can be kept smaller than that of the conventional voltage detection circuit 30. Furthermore, although the area of each circuit in the voltage detection circuit 50 and the voltage detection circuit 30 increases, with the voltage detection circuit 50, and the charge / discharge control circuit 10, charge / discharge control device 20, and battery device 1 equipped with the voltage detection circuit 50, even when the number of cells 2_1 to 2_n connected in series, n, is large and the voltage of the secondary battery 2 is high, the increase in the area of the voltage detection circuit 50 can be kept smaller than the increase in the area of the voltage detection circuit 30.
[0058] With the voltage detection circuit 50, and the charge / discharge control circuit 10, charge / discharge control device 20, and battery device 1 equipped with the voltage detection circuit 50, the input voltage of the NMOS transistor 51 can be kept lower than in the conventional method, thereby reducing PBTI (Positive Bias Temperature Instability) compared to the conventional method. Furthermore, because PBTI can be reduced compared to the conventional method, the threshold voltage shift of the N-type transistor can be suppressed, and the detection voltage shift after long-term reliability testing can be suppressed compared to the conventional method.
[0059] Furthermore, since the voltage detection circuit 50 has an NMOS transistor 52 that is cascaded with the NMOS transistor 51, the drain-source voltage VDS of the NMOS transistor 51 can be kept constant. In other words, the drain-source voltage VDS of the NMOS transistor 51 can be set to a voltage that does not depend on the voltage Vdd.
[0060] Although the voltage detection circuit 50 described above illustrates an example in which a clamp circuit is included within the protection circuit 60, it is not limited to this configuration as long as the PMOS transistor 63 is capable of receiving the clamped voltage at its gate. For example, if a clamp circuit is provided outside the voltage detection circuit 50 and the output voltage of the clamp circuit is available, the protection circuit 60 may be a PMOS transistor 63 that includes a gate to which the output voltage of the clamp circuit is applied.
[0061] [Second Embodiment] Figure 3 is a schematic circuit diagram showing the main configuration of a voltage detection circuit 50A, which is an example of a voltage detection circuit according to the second embodiment.
[0062] The semiconductor device, charge / discharge control circuit, and voltage detection circuit according to the second embodiment differ from those according to the first embodiment in that the configuration of the voltage detection circuit is different, but otherwise they are substantially the same. Therefore, in this description of the embodiment, the voltage detection circuit 50A, which differs from the voltage detection circuit 50, will be described in detail, and other substantially similar components will be given the same reference numerals and redundant descriptions will be omitted.
[0063] The charge / discharge control circuit 10A differs from the charge / discharge control circuit 10 in that it has a voltage detection circuit 50A instead of the voltage detection circuit 50, but otherwise there are no substantial differences. The voltage detection circuit 50A differs from the voltage detection circuit 30 in that it has an NMOS transistor 51 instead of the NMOS transistor 31, and further has an NMOS transistor 52, an NMOS transistor 53, and an NMOS transistor 54, but otherwise there are no substantial differences. Furthermore, the voltage detection circuit 50A differs from the voltage detection circuit 50 in that it has an NMOS transistor 32 instead of the protection circuit 60, but otherwise there are no substantial differences.
[0064] In the voltage detection circuit 50A, an NMOS transistor 32 is connected between the drain of the NMOS transistor 53 and the power supply terminal 8 to protect the NMOS transistor 53 from overvoltage. That is, the NMOS transistor 32, acting as a third transistor, is cascaded with the NMOS transistor 53 (more specifically, its gate and source). In addition, the NMOS transistor 53 is connected to its own gate and source, as well as to the gate of the NMOS transistor 32, the drain of the NMOS transistor 52, and the gate of the PMOS transistor 41. The gate and source of the NMOS transistor 53 are the output terminal P3 in the voltage detection circuit 50A.
[0065] Next, we will explain the operation of the voltage detection circuit 50A by giving an example of a case in which the highest voltage is applied to the voltage detection circuit 50A, specifically the case when the cell connection terminal VC(n-1) is short-circuited.
[0066] The voltage detection circuit 50A differs from the voltage detection circuit 50 in that it uses an NMOS transistor 32 to protect the NMOS transistor 53 from breakdown voltage, whereas the voltage detection circuit 60 protects the NMOS transistor 53 from breakdown voltage. However, the overall circuit operation, including the protection operation of the NMOS transistor 51, is substantially the same. The explanation of the circuit operation of the voltage detection circuit 50A is omitted by following the explanation of the circuit operation of the voltage detection circuit 50.
[0067] According to the voltage detection circuit, charge / discharge control circuit, charge / discharge control device, and battery device of the second embodiment, the same effects as those of the voltage detection circuit, charge / discharge control circuit, charge / discharge control device, and battery device of the first embodiment can be obtained.
[0068] Furthermore, the voltage detection circuit 50A can use even fewer FETs with relatively higher voltage ratings compared to the voltage detection circuit 50, thus further reducing the circuit area. Therefore, even when n, the number of cells 2_1 to 2_n connected in series, is large and the voltage of the secondary battery 2 is high, the increase in area of the voltage detection circuit 50A can be kept smaller than the increase in area of the voltage detection circuits 30 and 50.
[0069] It should be noted that the present invention is not limited to the embodiments described above, and in practice, it can be implemented in various forms other than those described above, and various omissions, additions, substitutions, or modifications can be made without departing from the spirit of the invention. Therefore, several examples of modifications of the present invention will be described below.
[0070] (First variation) Figure 4 is a schematic diagram showing the configuration of a voltage detection circuit 50B, which is another configuration example (first modification) of the voltage detection circuit according to the embodiment of the present invention.
[0071] The voltage detection circuit 50B differs from the voltage detection circuit 50A in that it has an enhancement-type NMOS transistor 72 instead of a depletion-type NMOS transistor 52, but is otherwise substantially the same. The NMOS transistor 72 differs from the NMOS transistor 52 in that, because it has a positive threshold voltage, its gate is connected to a connection point with a higher voltage than connection point P_(n-1), such as connection point P_(n-2), rather than connection point P_(n-1). However, in terms of operation and function, it is substantially the same as the NMOS transistor 52.
[0072] The voltage detection circuit 50B configured in this manner operates in the same way as the voltage detection circuit 50A and can achieve the same effects. Therefore, in the voltage detection circuit according to the embodiment of the present invention, and in the charge / discharge control circuit, charge / discharge control device, and battery device equipped with the voltage detection circuit, the voltage detection circuit 50B may be applied instead of the voltage detection circuit 50A. In short, even in the charge / discharge control circuit 10B, charge / discharge control device 20, and battery device 1 in which the voltage detection circuit 50A is replaced with the voltage detection circuit 50B, they operate in the same way as the charge / discharge control circuit 10A, charge / discharge control device 20, and battery device 1 equipped with the voltage detection circuit 50A, and can achieve the same effects.
[0073] (Second variation) Figure 5 is a schematic diagram showing the configuration of a voltage detection circuit 50C, which is another configuration example (second modification) of the voltage detection circuit according to the embodiment of the present invention.
[0074] The voltage detection circuit 50C differs from the voltage detection circuit 50A in that it further includes a current mirror circuit 56 with two PMOS transistors 561 and 562, and in the arrangement of the NMOS transistors 32 and 56, but otherwise there are no substantial differences. Therefore, in the description of the voltage detection circuit 50C, the same reference numerals are used for substantially identical components such as the NMOS transistor 51, and their descriptions are omitted.
[0075] The voltage detection circuit 50C includes NMOS transistors 32, 51, 52, 53, and 54, and a current mirror circuit 56. In the current mirror circuit 56, PMOS transistor 561 includes a source connected to the power supply terminal 8, a gate connected to the gate of PMOS transistor 562, and a drain. PMOS transistor 562 also includes a source connected to the power supply terminal 8, a gate connected to the gate of PMOS transistor 561, and a drain connected to its own gate. The current flowing through the drain of PMOS transistor 561 is configured to be equal to the current flowing through the drain of PMOS transistor 562.
[0076] The drain of PMOS transistor 561 is connected to the output terminal P3 of voltage detection circuit 50C and the drain of NMOS transistor 52. On the other hand, NMOS transistors 32 and 53 of voltage detection circuit 50A are connected between the drain of PMOS transistor 562 and the power supply terminal 9. Specifically, the source of NMOS transistor 32 is connected to the drain of NMOS transistor 53. The gate of NMOS transistor 53 is connected to the gate of NMOS transistor 32 and the source of NMOS transistor 53. The connection point between the gate of NMOS transistor 32, the gate of NMOS transistor 53, and the source of NMOS transistor 53 is connected to the power supply terminal 9.
[0077] The voltage detection circuit 50C configured in this way operates in the same manner as the voltage detection circuits 50A and 50B, and the same effects can be obtained. In short, even in the charge / discharge control circuit 10C, charge / discharge control device 20, and battery device 1 in which the voltage detection circuit 50A is replaced with the voltage detection circuit 50C, they operate in the same manner as the charge / discharge control circuit 10A, charge / discharge control device 20, and battery device 1 equipped with the voltage detection circuit 50A, and the same effects can be obtained.
[0078] (Third variation) Figure 6 is a schematic diagram showing the configuration of a voltage detection circuit 50D, which is another configuration example (third modification) of the voltage detection circuit according to the embodiment of the present invention.
[0079] The voltage detection circuit 50D differs from the voltage detection circuit 50C in that it has an enhancement-type NMOS transistor 72 instead of a depletion-type NMOS transistor 52, but is otherwise substantially the same. In other words, the voltage detection circuit 50D is a circuit to which the modifications of the first modification are applied to the voltage detection circuit 50C.
[0080] The voltage detection circuit 50D configured in this way operates in the same manner as the voltage detection circuits 50A, 50B, and 50C, and can achieve the same effects. In short, even in the charge / discharge control circuit 10D, charge / discharge control device 20, and battery device 1 in which the voltage detection circuit 50A is replaced with the voltage detection circuit 50D, they operate in the same manner as the charge / discharge control circuit 10A, charge / discharge control device 20, and battery device 1 equipped with the voltage detection circuit 50A, and can achieve the same effects.
[0081] (Fourth variation) Figure 7 is a schematic diagram showing the configuration of a charging control circuit 210, a charging control device 220, and a battery device 201, which is another example (fourth modified example) of the charging control circuit and semiconductor device according to the present invention.
[0082] The charge control device 220 is a so-called fuse-protected charge control device and comprises an open circuit 80 including fuses 81 and 82, and a charge control circuit 210. Fuses 81 and 82 are connected in series with each other. Specifically, one end of fuse 82 is connected to the EB+ terminal. The other end of fuse 82 is connected to one end of fuse 81. The other end of fuse 81 is connected to the + terminal of the first cell 2_1. The charge control circuit 210 is a circuit that omits the discharge control terminal DO and the signal path connected to the discharge control terminal DO compared to the charge / discharge control circuit 10 (see Figure 2), and is otherwise substantially the same as the charge control circuit 10.
[0083] The charge control FET 4 is, for example, an N-channel field-effect transistor having a gate, source, and drain. The gate is connected to the CO terminal of the charge control circuit 210. The source is connected to the EB- terminal. The drain is connected to one end of resistor 85. The charge control FET 4 controls the on / off state between the source terminal and the drain terminal based on the signal output from the CO terminal. The other end of resistor 85 is connected to the connection between fuses 81 and 82. Resistor 85 functions as a heater element that blows fuses 81 and 82 when the charge control FET 4 is turned on.
[0084] As with the charge control device 220 and battery device 201 described above, a semiconductor device with a different configuration from the charge / discharge control device 20 and battery device 1 may be used as the semiconductor device according to the embodiment of the present invention. The charge control device circuit 210, charge control device 220 and battery device 201 can obtain the same effects as the charge / discharge control circuit 10, charge / discharge control device 20 and battery device 1.
[0085] The MOS transistor mentioned above is merely an example of an FET; any type of FET is acceptable. For example, different types of FETs, such as junction FETs (JFETs) or metal-insulated semiconductor FETs (MISFETs), may be used.
[0086] These embodiments and their variations are included within the scope and essence of the invention, as well as within the scope of the invention and its equivalents as described in the claims. [Explanation of Symbols]
[0087] 1,201 Battery device (semiconductor device) 2 Secondary battery 3. Discharge control FET 4. Charge control FET 8 Power terminal 9 Power terminal 10, 10A, 10B, 10C, 10D Charge / Discharge Control Circuit 210 Charging control circuit 12 Overvoltage detection circuit 15 Control circuits 20 Charge / Discharge Control Device (Semiconductor Device) 220 Charging control circuit (semiconductor device) 50, 50A, 50B, 50C, 50D Voltage Detection Circuit 32. Depletion-type NMOS transistor (the third transistor) 51. Enhancement-type NMOS transistor (input transistor) 52 Depletion-type NMOS transistor (first transistor) 53 Depletion-type NMOS transistor (second transistor) 54. Enhancement-type NMOS transistor (bypass transistor) 63. Enhancement-type PMOS transistor (third transistor) 80 open circuit 81,82 fuses CO charging control signal output terminal DO discharge control signal output terminal
Claims
1. an input transistor including a gate to which a voltage to be detected is applied, a source connected to the first power supply terminal, and a drain; a bypass transistor including a gate connected to the gate of the input transistor, a drain connected to the drain of the input transistor, a source connected to the gate of the input transistor and its own gate, and a back gate connected to the first power supply terminal; a first transistor including a first terminal connected to the input transistor and a second terminal connected to an output terminal from which a signal indicating a voltage detection result is output; a second transistor including a drain, a gate, and a source connected to its gate, for supplying a constant current to the first transistor and the input transistor; a third transistor cascade-connected with the second transistor; A voltage detection circuit comprising:
2. 2. The voltage detection circuit according to claim 1, wherein the third transistor is a depletion-type transistor including a drain, a gate connected to the gate and source of the second transistor, and a source connected to the drain of the second transistor, and through which the constant current flows between its drain and source.
3. 2. The voltage detection circuit according to claim 1, wherein the third transistor is an enhancement type transistor including a source connected to the gate and source of the second transistor, a drain connected to the second terminal of the first transistor, and a gate.
4. A voltage detection circuit according to any one of claims 1 to 3; a first power input terminal and a second power input terminal; a charge control signal output terminal connected to the gate of a charge control FET that controls charging of a secondary battery including a battery pack formed by connecting a plurality of battery cells in series; an overvoltage determination circuit capable of determining whether the secondary battery is at an overvoltage based on the voltage output from the voltage detection circuit; a control circuit capable of supplying a control signal to the charge control signal output terminal to switch the charge control FET on and off in response to a signal input from another circuit including the overvoltage determination circuit; A charging control circuit comprising:
5. A voltage detection circuit according to any one of claims 1 to 3; a first power input terminal and a second power input terminal; a charge control signal output terminal connected to the gate of a charge control FET that controls charging of a secondary battery including a battery pack formed by connecting a plurality of battery cells in series; a discharge control signal output terminal connected to the gate of a discharge control FET that controls the discharge of the secondary battery; an external negative voltage input terminal, to which a voltage of the external negative terminal is input, of an external positive terminal and an external negative terminal to which either a charger for charging the secondary battery or a load for discharging the secondary battery is connected; an overvoltage determination circuit capable of determining whether the secondary battery is at an overvoltage based on the voltage output from the voltage detection circuit; a control circuit that supplies a control signal to the charge control signal output terminal for switching on and off the charge control FET in response to a signal input from another circuit including the overvoltage determination circuit, and that supplies a control signal to the discharge control signal output terminal for switching on and off the discharge control FET; A charge and discharge control circuit comprising:
6. a charging control circuit according to claim 4; an external positive terminal and an external negative terminal to which either a charger for charging the secondary battery or a load for discharging the secondary battery is connected; the charge control FET, the gate of which is connected to a charge control signal output terminal; an open circuit including a fuse connected to the charge control FET; A semiconductor device comprising:
7. The semiconductor device according to claim 6 , further comprising the secondary battery.
8. a charge / discharge control circuit according to claim 5; the external positive electrode terminal and the external negative electrode terminal; the discharge control FET, the drain and source of which are connected in series with a path connecting the external positive terminal and the external negative terminal, and the gate of which is connected to a discharge control signal output terminal; the charge control FET, the drain and source of which are connected in series with a path connecting the external positive terminal and the external negative terminal, and the gate of which is connected to a charge control signal output terminal; A semiconductor device comprising:
9. The semiconductor device according to claim 8 , further comprising the secondary battery.