Method of manufacturing semiconductor device

Abstract

To achieve a semiconductor device with high mobility and high reliability.SOLUTION: A method of manufacturing a semiconductor device includes the following steps of: forming on a substrate a first metal oxide layer containing aluminum as a main component; forming an oxide semiconductor layer on the first metal oxide layer; forming a gate insulating layer on the oxide semiconductor layer; forming on the gate insulating layer a second metal oxide layer containing aluminum as a main component; performing heat treatment in a state where the second metal oxide layer is formed on the gate insulating layer; removing the second metal oxide layer after the heat treatment; and forming a gate electrode on the gate insulating layer.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a method for manufacturing a semiconductor device. In particular, one embodiment of the present invention relates to a method for manufacturing a semiconductor device in which an oxide semiconductor is used as the channel. [Background technology]

[0002] In recent years, the development of semiconductor devices using oxide semiconductors as channels has progressed, replacing amorphous silicon, low-temperature polysilicon, and single-crystal silicon (for example, Patent Documents 1-6). Semiconductor devices using oxide semiconductors as channels can be formed with a simple structure and low-temperature processes, similar to semiconductor devices using amorphous silicon as channels. Semiconductor devices using oxide semiconductors as channels are known to have higher mobility than semiconductor devices using amorphous silicon as channels.

[0003] For semiconductor devices using oxide semiconductors as channels to operate stably, it is important to supply oxygen to the oxide semiconductor layer during the manufacturing process and reduce oxygen vacancies formed in the oxide semiconductor layer. As one method of supplying oxygen to the oxide semiconductor layer, for example, a technique has been disclosed in which an insulating layer covering the oxide semiconductor layer is formed under conditions in which the insulating layer contains a larger amount of oxygen. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2021-141338 [Patent Document 2] Japanese Patent Publication No. 2014-099601 [Patent Document 3] Japanese Patent Publication No. 2021-153196 [Patent Document 4] Japanese Patent Publication No. 2018-006730 [Patent Document 5] Japanese Patent Application Laid-Open No. 2016-184771 [Patent Document 6] Japanese Patent Application Laid-Open No. 2021-108405 [Summary of the Invention] [Problems to be Solved by the Invention]

[0005] However, an insulating layer formed under conditions containing more oxygen contains many defects. Due to this influence, characteristic abnormalities of semiconductor devices or characteristic fluctuations in reliability tests, which are considered to be caused by electrons being trapped in these defects, occur. On the other hand, when using an insulating layer with few defects, the amount of oxygen contained in the insulating layer cannot be increased. Therefore, sufficient oxygen cannot be supplied from the insulating layer to the oxide semiconductor layer. Thus, it is required to realize a structure that can repair oxygen deficiencies formed in the oxide semiconductor layer while reducing defects in the insulating layer that cause characteristic fluctuations of semiconductor devices.

[0006] Furthermore, it is known that a semiconductor device having high mobility can be obtained by relatively increasing the ratio of indium contained in the oxide semiconductor layer, but oxygen deficiencies are likely to be formed in the oxide semiconductor layer. Therefore, in order to realize high mobility while maintaining high reliability, it is necessary to devise the configuration of the insulating layer around the oxide semiconductor layer.

[0007] One of the embodiments of the present invention has an object of realizing a semiconductor device with high reliability and high mobility. [Means for Solving the Problems]

[0008] A method for manufacturing a semiconductor device according to an embodiment of the present invention includes forming a first metal oxide layer mainly composed of aluminum on a substrate, forming an oxide semiconductor layer on the first metal oxide layer, forming a gate insulating layer on the oxide semiconductor layer, forming a second metal oxide layer mainly composed of aluminum on the gate insulating layer, performing a heat treatment in a state where the second metal oxide layer is formed on the gate insulating layer, removing the second metal oxide layer after the heat treatment, and forming a gate electrode on the gate insulating layer.

Brief Description of the Drawings

[0009] [Figure 1] It is a cross-sectional view showing an overview of a semiconductor device according to an embodiment of the present invention. [Figure 2] It is a plan view showing an overview of a semiconductor device according to an embodiment of the present invention. [Figure 3] It is a sequence diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 4] It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 5] It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 6] It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7] It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 8] It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 9] It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 10] It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 11] It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 12] It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 13]This is a sequence diagram showing a method for manufacturing a semiconductor device according to a modified example of one embodiment of the present invention. [Figure 14] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to a modified example of one embodiment of the present invention. [Figure 15] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to a modified example of one embodiment of the present invention. [Figure 16] This is a cross-sectional view showing an overview of a semiconductor device according to a modified example of one embodiment of the present invention. [Figure 17] This is a sequence diagram showing a method for manufacturing a semiconductor device according to a modified example of one embodiment of the present invention. [Figure 18] This is a cross-sectional view showing an overview of a semiconductor device according to a modified example of one embodiment of the present invention. [Figure 19] This is a plan view showing an overview of a semiconductor device according to a modified example of one embodiment of the present invention. [Figure 20] This is a sequence diagram showing a method for manufacturing a semiconductor device according to a modified example of one embodiment of the present invention. [Figure 21] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to a modified example of one embodiment of the present invention. [Figure 22] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to a modified example of one embodiment of the present invention. [Figure 23] This is a plan view showing an overview of a display device according to one embodiment of the present invention. [Figure 24] A block diagram showing the circuit configuration of a display device according to one embodiment of the present invention. [Figure 25] This is a circuit diagram showing the pixel circuit of a display device according to one embodiment of the present invention. [Figure 26] This is a cross-sectional view showing an overview of a display device according to one embodiment of the present invention. [Figure 27] This is a plan view of the pixel electrodes and common electrodes of a display device according to one embodiment of the present invention. [Figure 28] This is a circuit diagram showing the pixel circuit of a display device according to one embodiment of the present invention. [Figure 29] This is a cross-sectional view showing an overview of a display device according to one embodiment of the present invention. [Figure 30] This figure shows the electrical characteristics of a semiconductor device according to one embodiment of the present invention. [Figure 31] This figure shows the electrical characteristics of a semiconductor device according to one embodiment of the present invention. [Figure 32] This figure shows the reliability test results of a semiconductor device relating to one embodiment of the present invention. [Figure 33] This figure shows the electrical characteristics of a semiconductor device according to one embodiment of the present invention. [Modes for carrying out the invention]

[0010] The embodiments of the present invention will be described below with reference to the drawings. The following disclosure is merely an example. Configurations that a person skilled in the art could easily conceive by appropriately modifying the configuration of the embodiments while maintaining the spirit of the invention are naturally included within the scope of the present invention. In order to clarify the explanation, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual embodiment. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention. In this specification and each drawing, elements similar to those described above with respect to previously shown drawings are denoted by the same reference numerals, and detailed explanations may be omitted as appropriate.

[0011] In each embodiment of the present invention, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "upwards." Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "downwards." Thus, for the sake of explanation, the terms "up" or "downwards" are used, but for example, the substrate and the oxide semiconductor layer may be arranged in a way that is the opposite of the illustrated relationship. In the following explanation, for example, the expression "oxide semiconductor layer on the substrate" merely describes the relationship between the substrate and the oxide semiconductor layer as described above, and other components may be arranged between the substrate and the oxide semiconductor layer. "Up" or "downwards" refers to the stacking order in a structure in which multiple layers are stacked. When referring to the pixel electrode above the transistor, the positional relationship between the transistor and the pixel electrode may not overlap in a plan view. On the other hand, when referring to the pixel electrode vertically above the transistor, it means the positional relationship between the transistor and the pixel electrode overlap in a plan view.

[0012] A "display device" refers to a structure that displays images using an electro-optical layer. For example, the term "display device" may refer to a display panel including an electro-optical layer, or to a structure in which other optical components (e.g., polarizing members, backlights, touch panels, etc.) are attached to a display cell. The "electro-optical layer" may include liquid crystal layers, electroluminescent (EL) layers, electrochromic (EC) layers, and electrophoretic layers, as long as there is no technical inconsistency. Therefore, in the embodiments described later, liquid crystal display devices including a liquid crystal layer and organic EL display devices including an organic EL layer will be used as examples, but the structure in these embodiments can be applied to other display devices including the electro-optical layers described above.

[0013] In this specification, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A, B, and C, unless otherwise specified. Furthermore, these expressions do not exclude cases where α includes other elements.

[0014] Furthermore, the following embodiments can be combined with each other, provided that no technical inconsistencies arise.

[0015] <First Embodiment> A semiconductor device according to one embodiment of the present invention will be described with reference to Figures 1 to 12. The semiconductor device of the embodiment shown below may be used not only as a transistor used in a display device, but also as an integrated circuit (IC) such as a microprocessing unit (MPU), or as a memory circuit.

[0016] [Configuration of semiconductor device 10] The configuration of the semiconductor device 10 according to one embodiment of the present invention will be described using Figures 1 and 2. Figure 1 is a cross-sectional view showing an overview of the semiconductor device according to one embodiment of the present invention. Figure 2 is a plan view showing an overview of the semiconductor device according to one embodiment of the present invention.

[0017] As shown in Figure 1, the semiconductor device 10 is mounted on top of the substrate 100. The semiconductor device 10 includes a gate electrode 105, gate insulating layers 110, 120, metal oxide layer 130, oxide semiconductor layer 140, gate insulating layer 150, gate electrode 160, insulating layers 170, 180, source electrode 201, and drain electrode 203. When the source electrode 201 and drain electrode 203 are not specifically distinguished, they may be collectively referred to as the source / drain electrode 200.

[0018] The gate electrode 105 is provided on the substrate 100. The gate insulating layer 110 and the gate insulating layer 120 are provided on the substrate 100 and the gate electrode 105. The metal oxide layer 130 is provided on the gate insulating layer 120. The metal oxide layer 130 is in contact with the gate insulating layer 120. The oxide semiconductor layer 140 is provided on the metal oxide layer 130. The oxide semiconductor layer 140 is in contact with the metal oxide layer 130. Of the main surfaces of the oxide semiconductor layer 140, the surface in contact with the metal oxide layer 130 is called the bottom surface 142. The edges of the metal oxide layer 130 and the edges of the oxide semiconductor layer 140 are approximately coincident.

[0019] In this embodiment, no semiconductor layer or oxide semiconductor layer is provided between the metal oxide layer 130 and the substrate 100.

[0020] In this embodiment, a configuration is exemplified in which the metal oxide layer 130 is in contact with the gate insulating layer 120 and the oxide semiconductor layer 140 is in contact with the metal oxide layer 130, but the embodiment is not limited to this configuration. Other layers may be provided between the gate insulating layer 120 and the metal oxide layer 130. Other layers may be provided between the metal oxide layer 130 and the oxide semiconductor layer 140.

[0021] In Figure 1, the sidewalls of the metal oxide layer 130 and the oxide semiconductor layer 140 are aligned in a straight line, but the configuration is not limited to this. The angle of the sidewalls of the metal oxide layer 130 with respect to the main surface of the substrate 100 may be different from the angle of the sidewalls of the oxide semiconductor layer 140. The cross-sectional shape of at least one of the sidewalls of the metal oxide layer 130 and the oxide semiconductor layer 140 may be curved.

[0022] The gate electrode 160 faces the oxide semiconductor layer 140. The gate insulating layer 150 is provided between the oxide semiconductor layer 140 and the gate electrode 160. The gate insulating layer 150 is in contact with the oxide semiconductor layer 140. Of the main surfaces of the oxide semiconductor layer 140, the surface in contact with the gate insulating layer 150 is called the upper surface 141. The surface between the upper surface 141 and the lower surface 142 is called the side surface 143. Insulating layers 170 and 180 are provided on the gate insulating layer 150 and the gate electrode 160. The insulating layers 170 and 180 are provided with openings 171 and 173 that reach the oxide semiconductor layer 140. The source electrode 201 is provided inside the opening 171. The source electrode 201 is in contact with the oxide semiconductor layer 140 at the bottom of the opening 171. The drain electrode 203 is provided inside the opening 173. The drain electrode 203 is in contact with the oxide semiconductor layer 140 at the bottom of the opening 173.

[0023] The gate electrode 105 functions as the bottom gate of the semiconductor device 10 and as a light-shielding film for the oxide semiconductor layer 140. The gate insulating layer 110 functions as a barrier film that shields against impurities diffusing from the substrate 100 toward the oxide semiconductor layer 140. The gate insulating layers 110 and 120 function as gate insulating layers for the bottom gate. The metal oxide layer 130 is a layer containing metal oxide mainly composed of aluminum and functions as a gas barrier film that shields against gases such as oxygen and hydrogen.

[0024] The oxide semiconductor layer 140 is divided into a source region S, a drain region D, and a channel region CH. The channel region CH is the region of the oxide semiconductor layer 140 vertically below the gate electrode 160. The source region S is the region of the oxide semiconductor layer 140 that does not overlap with the gate electrode 160 and is closer to the source electrode 201 than the channel region CH. The drain region D is the region of the oxide semiconductor layer 140 that does not overlap with the gate electrode 160 and is closer to the drain electrode 203 than the channel region CH. The oxide semiconductor layer 140 in the channel region CH possesses semiconductor properties. The oxide semiconductor layer 140 in the source region S and drain region D possesses conductive properties.

[0025] The gate electrode 160 functions as a light-shielding film for the top gate and oxide semiconductor layer 140 of the semiconductor device 10. The gate insulating layer 150 functions as a gate insulating layer for the top gate and has the function of releasing oxygen through heat treatment in the manufacturing process. The insulating layers 170 and 180 insulate the gate electrode 160 from the source and drain electrodes 200 and have the function of reducing parasitic capacitance between them. The operation of the semiconductor device 10 is mainly controlled by the voltage supplied to the gate electrode 160. An auxiliary voltage is supplied to the gate electrode 105. However, when the gate electrode 105 is used simply as a light-shielding film, no specific voltage is supplied to the gate electrode 105, and it may be floating. In other words, the gate electrode 105 may simply be called a "light-shielding film".

[0026] In this embodiment, a configuration is exemplified in which a dual-gate transistor, in which gate electrodes are provided both above and below the oxide semiconductor layer, is used as the semiconductor device 10, but the invention is not limited to this configuration. For example, a bottom-gate transistor, in which the gate electrode is provided only below the oxide semiconductor layer, or a top-gate transistor, in which the gate electrode is provided only above the oxide semiconductor layer, may be used as the semiconductor device 10. The above configuration is merely one embodiment, and the present invention is not limited to the above configuration.

[0027] As shown in Figure 2, in a plan view, the planar pattern of the metal oxide layer 130 is substantially the same as the planar pattern of the oxide semiconductor layer 140. Referring to Figures 1 and 2, the lower surface 142 of the oxide semiconductor layer 140 is covered by the metal oxide layer 130. In particular, in this embodiment, the entire lower surface 142 of the oxide semiconductor layer 140 is covered by the metal oxide layer 130. In the D1 direction, the width of the gate electrode 105 is greater than the width of the gate electrode 160. The D1 direction is the direction connecting the source electrode 201 and the drain electrode 203, and is the direction indicating the channel length L of the semiconductor device 10. Specifically, the length in the D1 direction of the region where the oxide semiconductor layer 140 and the gate electrode 160 overlap (channel region CH) is the channel length L, and the width in the D2 direction of the channel region CH is the channel width W.

[0028] In this embodiment, a configuration is illustrated in which the entire lower surface 142 of the oxide semiconductor layer 140 is covered by the metal oxide layer 130, but the embodiment is not limited to this configuration. For example, a portion of the lower surface 142 of the oxide semiconductor layer 140 does not need to be in contact with the metal oxide layer 130. For example, the entire lower surface 142 of the oxide semiconductor layer 140 in the channel region CH may be covered by the metal oxide layer 130, while all or part of the lower surface 142 of the oxide semiconductor layer 140 in the source region S and drain region D does not need to be covered by the metal oxide layer 130. In other words, all or part of the lower surface 142 of the oxide semiconductor layer 140 in the source region S and drain region D does not need to be in contact with the metal oxide layer 130. However, in the above configuration, a portion of the lower surface 142 of the oxide semiconductor layer 140 in the channel region CH is not covered by the metal oxide layer 130, and the other portion of the lower surface 142 is in contact with the metal oxide layer 130.

[0029] In this embodiment, a configuration is illustrated in which the gate insulating layer 150 is formed over the entire surface and openings 171 and 173 are provided in the gate insulating layer 150, but the configuration is not limited to this. The gate insulating layer 150 may be patterned in a shape different from the shape in which the openings 171 and 173 are provided. For example, the gate insulating layer 150 may be patterned so as to expose all or part of the oxide semiconductor layer 140 in the source region S and the drain region D. In other words, the gate insulating layer 150 in the source region S and the drain region D may be removed, and the oxide semiconductor layer 140 and the insulating layer 170 may be in contact in these regions.

[0030] Figure 2 illustrates a configuration in which the source and drain electrodes 200 do not overlap with the gate electrodes 105 and 160 in a plan view, but the invention is not limited to this configuration. For example, in a plan view, the source and drain electrodes 200 may overlap with at least one of the gate electrodes 105 and 160. The above configuration is merely one embodiment, and the present invention is not limited to the above configuration.

[0031] [Materials of each component of the semiconductor device 10] As the substrate 100, a rigid substrate having light transmissivity, such as a glass substrate, a quartz substrate, and a sapphire substrate, is used. When the substrate 100 needs to have flexibility, as the substrate 100, a substrate containing a resin, such as a polyimide substrate, an acrylic substrate, a siloxane substrate, and a fluororesin substrate, is used. When a substrate containing a resin is used as the substrate 100, impurities may be introduced into the above resin in order to improve the heat resistance of the substrate 100. In particular, when the semiconductor device 10 is a top emission type display, since the substrate 100 does not need to be transparent, impurities that deteriorate the transparency of the substrate 100 may be used. When the semiconductor device 10 is used in an integrated circuit that is not a display device, as the substrate 100, a substrate that does not have light transmissivity, such as a semiconductor substrate such as a silicon substrate, a silicon carbide substrate, and a compound semiconductor substrate, or a conductive substrate such as a stainless steel substrate, is used.

[0032] As the gate electrodes 105, 160, and the source / drain electrodes 200, a general metal material is used. For example, as these members, for example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof are used. As the gate electrodes 105, 160, and the source / drain electrodes 200, the above materials may be used in a single layer or in a laminated form.

[0033] As the gate insulating layers 110, 120 and the insulating layers 170, 180, a general insulating material is used. For example, as these insulating layers, silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), silicon nitride (SiN x ), silicon oxynitride (SiN x O y ), aluminum oxide (AlO x ), aluminum oxynitride (AlO x N y ), aluminum oxynitride (AlNx O y ), aluminum nitride (AlN x Inorganic insulating layers such as ) are used.

[0034] As the gate insulating layer 150, an insulating layer containing oxygen from the above insulating layers is used. For example, as the gate insulating layer 150, silicon oxide (SiO x ), silicon oxide nitride (SiO x N y ), aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y Inorganic insulating layers such as ) are used.

[0035] As the gate insulating layer 120, an insulating layer having the function of releasing oxygen through heat treatment is used. The heat treatment temperature at which the gate insulating layer 120 releases oxygen is, for example, 600°C or lower, 500°C or lower, 450°C or lower, or 400°C or lower. In other words, the gate insulating layer 120 releases oxygen at the heat treatment temperature performed in the manufacturing process of the semiconductor device 10, for example, when a glass substrate is used as the substrate 100.

[0036] As the gate insulating layer 150, an insulating layer with few defects is used. For example, when comparing the oxygen composition ratio in the gate insulating layer 150 with the oxygen composition ratio in an insulating layer with a similar composition to the gate insulating layer 150 (hereinafter referred to as "other insulating layer"), the oxygen composition ratio in the gate insulating layer 150 is closer to the stoichiometric ratio for that insulating layer than the oxygen composition ratio in the other insulating layer. Specifically, silicon oxide (SiO₂) is used in both the gate insulating layer 150 and the insulating layer 180. x When this is used, the oxygen composition ratio in the silicon oxide used as the gate insulating layer 150 is closer to the stoichiometric ratio of silicon oxide than the oxygen composition ratio in the silicon oxide used as the insulating layer 180. For example, a layer in which no defects are observed when evaluated by electron spin resonance (ESR) may be used as the gate insulating layer 150.

[0037] The above SiO x Ny and AlO x N y These are silicon and aluminum compounds that contain nitrogen (N) in a smaller proportion (x>y) than oxygen (O). x O y and AlN x O y These are silicon compounds and aluminum compounds that contain oxygen in a smaller proportion (x > y) than nitrogen.

[0038] As the metal oxide layer 130 and the metal oxide layer 190 used in the manufacturing process as described later, an aluminum-based metal oxide is used. For example, as the metal oxide layer 130 (or metal oxide layer 190), aluminum oxide (AlO) x ), aluminum oxide nitride (AlO x N y ), aluminum nitride (AlN x O y ), aluminum nitride (AlN x An inorganic insulating layer such as ) is used. "Aluminum-based metal oxide layer" means that the proportion of aluminum contained in the metal oxide layer 130 (or metal oxide layer 190) is 1% or more of the total metal oxide layer 130 (or metal oxide layer 190). The proportion of aluminum contained in the metal oxide layer 130 (or metal oxide layer 190) may be 5% to 70%, 10% to 60%, or 30% to 50% of the total metal oxide layer 130. The above ratios may be by mass ratio or by weight ratio.

[0039] As the oxide semiconductor layer 140, an oxide metal having semiconductor properties can be used. For example, as the oxide semiconductor layer 140, an oxide semiconductor containing two or more metals including indium (In) can be used. The ratio of indium to the total oxide semiconductor layer 140 is 50% or more. In addition to indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconia (Zr), and lanthanides can be used as the oxide semiconductor layer 140. Other elements may also be used as the oxide semiconductor layer 140.

[0040] The oxide semiconductor layer 140 may be amorphous or crystalline. Furthermore, the oxide semiconductor layer 140 may be a multiphase of amorphous and crystalline material. As shown below, in oxide semiconductor layers 140 with an indium ratio of 50% or more, oxygen vacancies are easily formed. Crystalline oxide semiconductors are less prone to oxygen vacancies than amorphous oxide semiconductors. Therefore, it is preferable that the oxide semiconductor layer 140 described above is crystalline.

[0041] [Problems newly identified in the process leading to the present invention] A high-mobility semiconductor device 10 can be realized by having an indium ratio of 50% or more in the oxide semiconductor layer 140. On the other hand, in such an oxide semiconductor layer 140, the oxygen contained in the oxide semiconductor layer 140 is easily reduced, and oxygen vacancies are easily formed in the oxide semiconductor layer 140.

[0042] In the semiconductor device 10, during the heat treatment process of the manufacturing process, hydrogen is released from layers located on the substrate 100 side of the oxide semiconductor layer 140 (for example, gate insulating layers 110 and 120). This hydrogen reaches the oxide semiconductor layer 140, causing oxygen vacancies in the oxide semiconductor layer 140. The occurrence of these oxygen vacancies is more pronounced the larger the pattern size of the oxide semiconductor layer 140. To suppress the occurrence of such oxygen vacancies, it is necessary to suppress the arrival of hydrogen to the lower surface 142 of the oxide semiconductor layer 140. The above is the first problem.

[0043] In addition to the above issues, there is a second issue as follows: The upper surface 141 of the oxide semiconductor layer 140 is affected by processes after the oxide semiconductor layer 140 is formed (for example, a patterning process or an etching process). On the other hand, the lower surface 142 of the oxide semiconductor layer 140 (the surface of the oxide semiconductor layer 140 that faces the substrate 100) is not affected in the same way.

[0044] Therefore, the oxygen vacancies formed on the upper surface 141 of the oxide semiconductor layer 140 are greater than the oxygen vacancies formed on the lower surface 142 of the oxide semiconductor layer 140. In other words, the oxygen vacancies in the oxide semiconductor layer 140 are not uniformly distributed in the thickness direction of the oxide semiconductor layer 140, but rather have a non-uniform distribution in the thickness direction of the oxide semiconductor layer 140. Specifically, the oxygen vacancies in the oxide semiconductor layer 140 are less towards the lower surface 142 and more towards the upper surface 141 of the oxide semiconductor layer 140.

[0045] When an oxide semiconductor layer 140 having the oxygen vacancy distribution described above is uniformly subjected to oxygen supply treatment, supplying the amount of oxygen necessary to repair the oxygen vacancies formed on the upper surface 141 of the oxide semiconductor layer 140 results in an excess supply of oxygen to the lower surface 142 of the oxide semiconductor layer 140. As a result, on the lower surface 142, defect levels different from the oxygen vacancies are formed due to the excess oxygen, leading to phenomena such as characteristic fluctuations in reliability tests or a decrease in field-effect mobility. Therefore, in order to suppress such phenomena, it is necessary to supply oxygen to the upper surface 141 of the oxide semiconductor layer 140 while suppressing the supply of oxygen to the lower surface 142 of the oxide semiconductor layer 140.

[0046] The above-mentioned problems were newly recognized during the process of arriving at the present invention and were not problems that had been recognized before. In conventional configurations and manufacturing methods, even if the initial characteristics of the semiconductor device were improved by the oxygen supply treatment to the oxide semiconductor layer, characteristic fluctuations occurred during reliability testing, resulting in a trade-off relationship between initial characteristics and reliability testing. However, with the configuration according to this embodiment, the above-mentioned problems are solved, and good initial characteristics and reliability test results for the semiconductor device 10 can be obtained.

[0047] [Manufacturing method for semiconductor device 10] A method for manufacturing a semiconductor device according to one embodiment of the present invention will be described using Figures 3 to 12. Figure 3 is a sequence diagram showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figures 4 to 12 are cross-sectional views showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. In the following description of the manufacturing method, a method for manufacturing a semiconductor device 10 in which aluminum oxide is used as the metal oxide layers 130 and 190 will be described.

[0048] As shown in Figures 3 and 4, a gate electrode 105 is formed as a bottom gate on the substrate 100, and gate insulating layers 110 and 120 are formed on the gate electrode 105 (Step S2001 "Bottom GI / GE formation" in Figure 3). For example, silicon nitride is formed as the gate insulating layer 110. For example, silicon oxide is formed as the gate insulating layer 120. The gate insulating layers 110 and 120 are deposited by the CVD (Chemical Vapor Deposition) method. One or both of the gate insulating layers 110 and 120 may be referred to as the "first insulating layer".

[0049] By using silicon nitride as the gate insulating layer 110, the gate insulating layer 110 can block impurities that diffuse from the substrate 100 side toward the oxide semiconductor layer 140. The silicon oxide used as the gate insulating layer 120 is silicon oxide that releases oxygen through heat treatment.

[0050] As shown in Figures 3 and 5, a metal oxide layer 130 and an oxide semiconductor layer 140 are formed on the gate insulating layer 120 (step S2002 "OS / AlOx film formation" in Figure 3). In this process, there are cases where the gate insulating layers 110 and 120 are formed on the substrate 100, and the metal oxide layer 130 is formed on the gate insulating layers 110 and 120. Alternatively, there are cases where the metal oxide layer 130 is formed on the substrate 100, and the oxide semiconductor layer 140 is formed on the metal oxide layer 130. Specifically, the oxide semiconductor layer 140 is formed in contact with the metal oxide layer 130. The metal oxide layer 130 and the oxide semiconductor layer 140 are formed by sputtering or atomic layer deposition (ALD).

[0051] The thickness of the metal oxide layer 130 is, for example, 1 nm to 100 nm, 1 nm to 50 nm, 1 nm to 30 nm, or 1 nm to 10 nm. In this embodiment, aluminum oxide is used as the metal oxide layer 130. Aluminum oxide has high barrier properties against gases. In this embodiment, the aluminum oxide used as the metal oxide layer 130 blocks hydrogen and oxygen released from the gate insulating layer 120 and suppresses the release of hydrogen and oxygen reaching the oxide semiconductor layer 140.

[0052] The thickness of the oxide semiconductor layer 140 is, for example, 10 nm to 100 nm, 15 nm to 70 nm, or 20 nm to 40 nm. The oxide semiconductor layer 140 before the heat treatment (OS annealing) described later is amorphous.

[0053] When the oxide semiconductor layer 140 is crystallized by OS annealing, as described later, it is preferable that the oxide semiconductor layer 140 is amorphous (a state with a small amount of crystalline oxide semiconductor components) after deposition and before OS annealing. In other words, it is preferable that the deposition conditions for the oxide semiconductor layer 140 are such that the oxide semiconductor layer 140 does not crystallize as much as possible immediately after deposition. For example, when the oxide semiconductor layer 140 is deposited by sputtering, the oxide semiconductor layer 140 is deposited while controlling the temperature of the object to be deposited (substrate 100 and the structure formed thereon).

[0054] When a film is deposited on an object using the sputtering method, ions generated in the plasma and atoms recoiling from the sputtering target collide with the object, causing the temperature of the object to rise during the deposition process. When the temperature of the object rises during the deposition process, microcrystals are included in the oxide semiconductor layer 140 immediately after deposition, inhibiting subsequent crystallization by OS annealing. To control the temperature of the object as described above, for example, the deposition process can be performed while cooling the object. For example, the object can be cooled from the opposite side of the deposition surface so that the temperature of the deposition surface (hereinafter referred to as "deposition temperature") is 100°C or less, 70°C or less, 50°C or less, or 30°C or less. As described above, by depositing the oxide semiconductor layer 140 while cooling the object, it is possible to deposit an oxide semiconductor layer 140 with a low crystalline component immediately after deposition.

[0055] As shown in Figures 3 and 6, a pattern is formed on the oxide semiconductor layer 140 (step S2003 "OS pattern formation" in Figure 3). Although not shown, a resist mask is formed on the oxide semiconductor layer 140, and the oxide semiconductor layer 140 is etched using the resist mask. Wet etching or dry etching may be used for etching the oxide semiconductor layer 140. For wet etching, etching can be performed using an acidic etchant. For example, oxalic acid or hydrofluoric acid can be used as the etchant.

[0056] After pattern formation of the oxide semiconductor layer 140, the oxide semiconductor layer 140 is subjected to heat treatment (OS annealing) ("OS annealing" in step S2004 of Figure 3). In this embodiment, the oxide semiconductor layer 140 crystallizes as a result of this OS annealing.

[0057] As shown in Figures 3 and 7, a pattern is formed on the metal oxide layer 130 (Step S2005 in Figure 3, "AlOx pattern formation"). The metal oxide layer 130 is etched using the oxide semiconductor layer 140 patterned in the above process as a mask. Wet etching or dry etching may be used for etching the metal oxide layer 130. For wet etching, for example, diluted hydrofluoric acid (DHF) can be used. As described above, by etching the metal oxide layer 130 using the oxide semiconductor layer 140 as a mask, the photolithography process can be omitted.

[0058] As shown in Figures 3 and 8, a gate insulating layer 150 is deposited on the oxide semiconductor layer 140 ("GI formation" in step S2006 of Figure 3). For example, silicon oxide is formed as the gate insulating layer 150. The gate insulating layer 150 is formed by the CVD method. For example, in order to form an insulating layer with few defects as described above, the gate insulating layer 150 may be deposited at a deposition temperature of 350°C or higher. The thickness of the gate insulating layer 150 is, for example, 50 nm to 300 nm, 60 nm to 200 nm, or 70 nm to 150 nm. After depositing the gate insulating layer 150, a process of implanting oxygen into a part of the gate insulating layer 150 may be performed. The gate insulating layer 150 is sometimes called the "second insulating layer". A metal oxide layer 190 is deposited on the gate insulating layer 150 ("AlOx deposition" in step S2007 of Figure 22). The metal oxide layer 190 is deposited by sputtering. The deposition of the metal oxide layer 190 implants oxygen into the gate insulating layer 150.

[0059] The thickness of the metal oxide layer 190 is, for example, 5 nm to 100 nm, 5 nm to 50 nm, 5 nm to 30 nm, or 7 nm to 15 nm. In this embodiment, aluminum oxide is used as the metal oxide layer 190. Aluminum oxide has high barrier properties against gases. In this embodiment, the aluminum oxide used as the metal oxide layer 190 suppresses the outward diffusion of oxygen injected into the gate insulating layer 150 during the formation of the metal oxide layer 190.

[0060] For example, when a metal oxide layer 190 is formed by sputtering, the process gas used in sputtering remains in the metal oxide layer 190. For instance, if Ar is used as the process gas for sputtering, Ar may remain in the metal oxide layer 190. The remaining Ar can be detected by SIMS (Secondary Ion Mass Spectrometry) analysis of the metal oxide layer 190.

[0061] A gate insulating layer 150 is deposited on the oxide semiconductor layer 140, and a metal oxide layer 190 is deposited on the gate insulating layer 150. With this state, a heat treatment (oxidation annealing) is performed to supply oxygen to the oxide semiconductor layer 140 (step S2008 "oxidation annealing" in Figure 3). In other words, heat treatment (oxidation annealing) is performed on the metal oxide layer 130 and oxide semiconductor layer 140 that have been patterned as described above. During the process between the deposition of the oxide semiconductor layer 140 and the deposition of the gate insulating layer 150 on the oxide semiconductor layer 140, many oxygen vacancies occur on the upper surface 141 and side surface 143 of the oxide semiconductor layer 140. Through the above oxidation annealing, oxygen released from the gate insulating layers 120 and 150 is supplied to the oxide semiconductor layer 140, and the oxygen vacancies are repaired.

[0062] During annealing, oxygen released from the gate insulating layer 120 is blocked by the metal oxide layer 130, making it difficult for oxygen to be supplied to the lower surface 142 of the oxide semiconductor layer 140. Oxygen released from the gate insulating layer 120 diffuses from the region where the metal oxide layer 130 is not formed to the gate insulating layer 150 provided on top of the gate insulating layer 120, and reaches the oxide semiconductor layer 140 via the gate insulating layer 150. As a result, oxygen released from the gate insulating layer 120 is difficult to supply to the lower surface 142 of the oxide semiconductor layer 140, and is mainly supplied to the side surfaces 143 and upper surface 141 of the oxide semiconductor layer 140. Furthermore, during annealing, oxygen released from the gate insulating layer 150 is supplied to the upper surface 141 and side surfaces 143 of the oxide semiconductor layer 140. Although hydrogen may be released from the gate insulating layers 110 and 120 during the above annealing, this hydrogen is blocked by the metal oxide layer 130.

[0063] As described above, the oxide annealing process makes it possible to suppress the supply of oxygen to the lower surface 142 of the oxide semiconductor layer 140, which has a small amount of oxygen vacancy, while supplying oxygen to the upper surface 141 and side surface 143 of the oxide semiconductor layer 140, which has a large amount of oxygen vacancy.

[0064] Similarly, in the above-described oxide annealing, the oxygen injected into the gate insulating layer 150 is blocked by the metal oxide layer 190, thus suppressing its release into the atmosphere. Therefore, the oxide annealing efficiently supplies the oxygen to the oxide semiconductor layer 140, repairing oxygen vacancies.

[0065] As shown in Figures 3 and 9, after annealing, the metal oxide layer 190 is etched (removed) (Step S2009 "AlOx removal" in Figure 3). Wet etching or dry etching may be used for etching the metal oxide layer 190. Diluted hydrofluoric acid (DHF) is used as a wet etching agent. This etching removes the metal oxide layer 190 formed over the entire surface. In other words, the removal of the metal oxide layer 190 is performed without using a mask. To put it another way, this etching removes all of the metal oxide layer 190 in the region that overlaps with the oxide semiconductor layer 140 formed in a certain pattern, at least in a plan view.

[0066] As shown in Figures 3 and 10, a gate electrode 160 is deposited on the gate insulating layer 150 ("GE formation" in step S2010 of Figure 3). The gate electrode 160 is deposited by sputtering or atomic layer deposition and patterned through a photolithography process. As described above, the gate electrode 160 is formed to be in contact with the gate insulating layer 150 that is exposed when the metal oxide layer 190 is removed.

[0067] With the gate electrode 160 patterned, the source region S and drain region D of the oxide semiconductor layer 140 are made less resistive (step S2011 "SD resistance reduction" in Figure 3). Specifically, impurities are implanted into the oxide semiconductor layer 140 from the gate electrode 160 side via the gate insulating layer 150 by ion implantation. For example, argon (Ar), phosphorus (P), and boron (B) are implanted into the oxide semiconductor layer 140 by ion implantation. The oxide semiconductor layer 140 becomes less resistive because oxygen vacancies are formed in the oxide semiconductor layer 140 by ion implantation. Since the gate electrode 160 is provided above the oxide semiconductor layer 140 which functions as the channel region CH of the semiconductor device 10, no impurities are implanted into the oxide semiconductor layer 140 of the channel region CH.

[0068] As shown in Figures 3 and 11, insulating layers 170 and 180 are deposited as interlayer films on the gate insulating layer 150 and gate electrode 160 (step S2012 "Interlayer Film Deposition" in Figure 3). The insulating layers 170 and 180 are deposited by CVD. For example, silicon nitride is formed as insulating layer 170 and silicon oxide is formed as insulating layer 180. The materials used for insulating layers 170 and 180 are not limited to those mentioned above. The thickness of insulating layer 170 is 50 nm to 500 nm. The thickness of insulating layer 180 is 50 nm to 500 nm.

[0069] As shown in Figures 3 and 12, openings 171 and 173 are formed in the gate insulating layer 150 and the insulating layers 170 and 180 ("Contact opening" in step S2013 of Figure 3). The oxide semiconductor layer 140 of the source region S is exposed by opening 171. The oxide semiconductor layer 140 of the drain region D is exposed by opening 173. By forming source and drain electrodes 200 on the oxide semiconductor layers 140 exposed by openings 171 and 173 and on the insulating layer 180 ("SD formation" in step S2014 of Figure 3), the semiconductor device 10 shown in Figure 1 is completed.

[0070] In the semiconductor device 10 manufactured by the above manufacturing method, the mobility is 50 [cm²] in the range where the channel length L of the channel region CH is 2 μm or more and 4 μm or less, and the channel width of the channel region CH is 2 μm or more and 25 μm or less. 2 / Vs] or more, 55[cm 2 / Vs] or more, or 60[cm 2 Electrical characteristics of [Vs] or higher can be obtained. In this embodiment, mobility refers to the field-effect mobility in the saturation region of the semiconductor device 10, and means the maximum value of the field-effect mobility in the region where the potential difference (Vd) between the source electrode and the drain electrode is greater than the value obtained by subtracting the threshold voltage (Vth) of the semiconductor device 10 from the voltage supplied to the gate electrode (Vg) (Vg-Vth).

[0071] <Variation 1 of the First Embodiment> A modified example 1 of this embodiment will be described using Figures 13 to 15. The structure of the semiconductor device 10 according to modified example 1 is the same as in Figure 1, but its manufacturing method differs from that shown in Figures 3 to 12. In the following description, the steps common to the manufacturing method shown in Figures 3 to 12 will be omitted, and the manufacturing method will mainly be described in relation to the differences.

[0072] Figure 13 is a sequence diagram showing a method for manufacturing a semiconductor device according to a modified example of one embodiment of the present invention. Figures 14 and 15 are cross-sectional views showing a method for manufacturing a semiconductor device according to a modified example of one embodiment of the present invention. As shown in Figure 13, in Modification 1, the patterns of the metal oxide layer 130 and the oxide semiconductor layer 140 are formed at once ("OS / AlOx pattern formation" in step S2020). That is, the patterned metal oxide layer 130 and oxide semiconductor layer 140 are subjected to heat treatment (OS annealing and oxide annealing).

[0073] As shown in Figure 14, after depositing the metal oxide layer 130 and the oxide semiconductor layer 140, a resist mask 220 is formed on the oxide semiconductor layer 140. Then, as shown in Figure 15, the resist mask 220 is used to form patterns of the metal oxide layer 130 and the oxide semiconductor layer 140. Wet etching or dry etching may be used for etching the metal oxide layer 130 and the oxide semiconductor layer 140. When the metal oxide layer 130 and the oxide semiconductor layer 140 are etched by wet etching, the same etchant as described above can be used. In Modification 1, OS annealing is performed with the patterns of the metal oxide layer 130 and the oxide semiconductor layer 140 formed (step S2004). Subsequent steps S2006 to S2014 are the same as in Figure 3, so a detailed explanation is omitted.

[0074] <Modification 2 of the First Embodiment> A modified example 2 of this embodiment will be described using Figures 16 and 17. The structure and manufacturing method of the semiconductor device 10 according to modified example 2 differ from those in Figures 1 and 3 to 12. In the following description, the process common to the manufacturing method shown in Figures 1 and 3 to 12 will be omitted, and the manufacturing method will mainly be described in terms of the differences.

[0075] Figure 16 is a cross-sectional view showing an overview of a semiconductor device according to a modified example of one embodiment of the present invention. Figure 17 is a sequence diagram showing a method for manufacturing a semiconductor device according to a modified example of one embodiment of the present invention.

[0076] As shown in Figure 16, the structure of the semiconductor device 10 according to Modification 2 is similar to the structure of the semiconductor device 10 shown in Figure 1, but differs from the structure of the semiconductor device 10 shown in Figure 1 in that the pattern of the metal oxide layer 130 is not formed. In other words, in Modification 2, the metal oxide layer 130 extends outward beyond the pattern of the oxide semiconductor layer 140. The metal oxide layer 130 is in contact with the gate insulating layer 150 outside the pattern of the oxide semiconductor layer 140.

[0077] As shown in Figure 17, the manufacturing method of the semiconductor device 10 according to Modification 2 is similar to the manufacturing method of the semiconductor device 10 shown in Figure 3, but differs in that it does not include pattern formation of the metal oxide layer 130 (step S2005 in Figure 3). In other words, in Modification 2, the oxide semiconductor layer 140 formed on the metal oxide layer 130 is patterned, and heat treatment (OS annealing and oxide annealing) is performed on the metal oxide layer 130 and the patterned oxide semiconductor layer 140. Subsequent steps S2006 to S2014 are the same as in Figure 3, so a detailed explanation is omitted.

[0078] <Modification 3 of the First Embodiment> A third modified example of this embodiment will be described using Figures 18 to 22. The structure and manufacturing method of the semiconductor device 10 according to this third modified example differ from those shown in Figures 1 to 12. In the following description, the process common to the manufacturing method shown in Figures 1 to 12 will be omitted, and the manufacturing method will mainly be described in relation to the differences.

[0079] Figure 18 is a cross-sectional view showing an overview of a semiconductor device according to one embodiment of the present invention. Figure 19 is a plan view showing an overview of a semiconductor device according to one embodiment of the present invention.

[0080] As shown in Figures 18 and 19, the structure of the semiconductor device 10 according to Modification 3 is similar to the structure of the semiconductor device 10 shown in Figures 1 and 2, but differs from the structure of the semiconductor device 10 shown in Figure 1 in that the pattern of the metal oxide layer 130 is different from the pattern of the oxide semiconductor layer 140. Specifically, in the cross-sectional view of Figure 18, the pattern of the oxide semiconductor layer 140 extends outward from the pattern of the metal oxide layer 130. In other words, the oxide semiconductor layer 140 extends beyond the pattern of the metal oxide layer 130. The oxide semiconductor layer 140 is in contact with the gate insulating layer 120 outside the pattern of the metal oxide layer 130. The gate insulating layer 120 is sometimes referred to as the "first insulating layer".

[0081] The source and drain electrodes 200 are in contact with the oxide semiconductor layer 140 in areas where the metal oxide layer 130 is not present. In the plan view of Figure 19, the pattern of the metal oxide layer 130 is located inside the pattern of the oxide semiconductor layer 140. Openings 171 and 173 are provided in areas that do not overlap with the pattern of the metal oxide layer 130.

[0082] Figure 20 is a sequence diagram showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figures 21 and 22 are cross-sectional views showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. As shown in Figure 20, in Modification 3, the pattern of the metal oxide layer 130 is formed ("AlOx film formation" in step S2030 and "AlOx pattern formation" in S2031), and then the pattern of the oxide semiconductor layer 140 is formed ("OS film formation" in step S2032 and "OS pattern formation" in S2033). Unlike Figure 3, OS annealing ("OS annealing" in step S2034) is performed after the gate insulating layer 150 is formed. In other words, the metal oxide layer 130 is patterned, then the oxide semiconductor layer 140 is formed, and the oxide semiconductor layer 140 is patterned. Then, heat treatment (OS annealing and oxide annealing) is performed on the patterned oxide semiconductor layer 140 and the metal oxide layer 130.

[0083] As shown in Figure 21, a metal oxide layer 130 is deposited on the gate insulating layer 120 (step S2030), and a pattern of the metal oxide layer 130 is formed (step S2031). The pattern formation (etching) of the metal oxide layer 130 is performed in the same manner as described above.

[0084] As shown in Figure 22, an oxide semiconductor layer 140 is deposited on the patterned metal oxide layer 130 (step S2032), and a pattern is formed on the oxide semiconductor layer 140 (step S2033). Pattern formation (etching) of the oxide semiconductor layer 140 is performed in the same manner as described above. Then, OS annealing is performed in the state shown in Figure 22 (step S2034). Steps S2006 to S2012 are the same as in Figure 3, so a detailed explanation is omitted.

[0085] As described above, the semiconductor device 10 according to Modifications 1 to 3 of this embodiment can be used to obtain the same effects as in this embodiment.

[0086] <Second Embodiment> A display device using a semiconductor device according to one embodiment of the present invention will be described with reference to Figures 23 to 27. In the embodiments described below, a configuration in which the semiconductor device 10 described in the first embodiment above is applied to the circuit of a liquid crystal display device will be described.

[0087] [Overview of the display device 20] Figure 23 is a plan view showing an overview of a display device according to one embodiment of the present invention. As shown in Figure 23, the display device 20 includes an array substrate 300, a sealing portion 310, a counter substrate 320, a flexible printed circuit board 330 (FPC330), and an IC chip 340. The array substrate 300 and the counter substrate 320 are bonded together by the sealing portion 310. Multiple pixel circuits 301 are arranged in a matrix in the liquid crystal region 22 surrounded by the sealing portion 310. The liquid crystal region 22 is the region that overlaps with the liquid crystal element 311, which will be described later, in a plan view.

[0088] The sealing region 24, where the sealing portion 310 is provided, is the area surrounding the liquid crystal region 22. The FPC 330 is provided in the terminal region 26. The terminal region 26 is the area where the array substrate 300 is exposed from the opposing substrate 320, and is provided outside the sealing region 24. The area outside the sealing region 24 means the area outside where the sealing portion 310 is provided and the area enclosed by the sealing portion 310. The IC chip 340 is provided on the FPC 330. The IC chip 340 supplies signals to drive each pixel circuit 301.

[0089] [Circuit configuration of display device 20] Figure 24 is a block diagram showing the circuit configuration of a display device according to one embodiment of the present invention. As shown in Figure 24, a source driver circuit 302 is provided at a position adjacent to the liquid crystal area 22 where the pixel circuit 301 is arranged in the D1 direction (column direction), and a gate driver circuit 303 is provided at a position adjacent to the liquid crystal area 22 in the D2 direction (row direction). The source driver circuit 302 and the gate driver circuit 303 are provided in the seal area 24. However, the area in which the source driver circuit 302 and the gate driver circuit 303 are provided is not limited to the seal area 24, but can be any area outside the area in which the pixel circuit 301 is provided.

[0090] Source wiring 304 extends from source driver circuit 302 in the D1 direction and is connected to multiple pixel circuits 301 arranged in the D1 direction. Gate wiring 305 extends from gate driver circuit 303 in the D2 direction and is connected to multiple pixel circuits 301 arranged in the D2 direction.

[0091] A terminal section 306 is provided in the terminal area 26. The terminal section 306 and the source driver circuit 302 are connected by a connecting wire 307. Similarly, the terminal section 306 and the gate driver circuit 303 are connected by a connecting wire 307. When the FPC 330 is connected to the terminal section 306, the external device to which the FPC 330 is connected is connected to the display device 20, and each pixel circuit 301 provided in the display device 20 is driven by a signal from the external device.

[0092] The semiconductor device 10 shown in the first embodiment is used as a transistor included in the pixel circuit 301, the source driver circuit 302, and the gate driver circuit 303.

[0093] [Pixel circuit 301 of display device 20] Figure 25 is a circuit diagram showing a pixel circuit of a display device according to one embodiment of the present invention. As shown in Figure 25, the pixel circuit 301 includes elements such as a semiconductor device 10, a retaining capacitor 350, and a liquid crystal element 311. The semiconductor device 10 has a gate electrode 160, a source electrode 201, and a drain electrode 203. The gate electrode 160 is connected to a gate wiring 305. The source electrode 201 is connected to a source wiring 304. The drain electrode 203 is connected to the retaining capacitor 350 and the liquid crystal element 311. In this embodiment, for the sake of explanation, the electrode indicated by reference numeral "201" is referred to as the source electrode, and the electrode indicated by reference numeral "203" is referred to as the drain electrode. However, the electrode indicated by reference numeral "201" may function as the drain electrode, and the electrode indicated by reference numeral "203" may function as the source electrode.

[0094] [Cross-sectional structure of the display device 20] Figure 26 is a cross-sectional view of a display device according to one embodiment of the present invention. As shown in Figure 26, the display device 20 is a display device that uses a semiconductor device 10. In this embodiment, a configuration in which the semiconductor device 10 is used in a pixel circuit 301 is illustrated, but the semiconductor device 10 may also be used in peripheral circuits including a source driver circuit 302 and a gate driver circuit 303. In the following description, the configuration of the semiconductor device 10 is the same as that of the semiconductor device 10 shown in Figure 1, so the description is omitted.

[0095] An insulating layer 360 is provided on the source electrode 201 and the drain electrode 203. A common electrode 370, which is provided in common to multiple pixels, is provided on the insulating layer 360. An insulating layer 380 is provided on the common electrode 370. An opening 381 is provided in the insulating layers 360 and 380. A pixel electrode 390 is provided on the insulating layer 380 and inside the opening 381. The pixel electrode 390 is connected to the drain electrode 203.

[0096] Figure 27 is a plan view of the pixel electrode and common electrode of a display device according to one embodiment of the present invention. As shown in Figure 27, the common electrode 370 has an overlapping region that overlaps with the pixel electrode 390 in a plan view, and a non-overlapping region that does not overlap with the pixel electrode 390. When a voltage is supplied between the pixel electrode 390 and the common electrode 370, a transverse electric field is formed from the pixel electrode 390 in the overlapping region toward the common electrode 370 in the non-overlapping region. The liquid crystal molecules contained in the liquid crystal element 311 are activated by this transverse electric field, thereby determining the grayscale of the pixels.

[0097] <Third Embodiment> A display device using a semiconductor device according to one embodiment of the present invention will be described with reference to Figures 28 and 29. In this embodiment, a configuration in which the semiconductor device 10 described in the first embodiment above is applied to the circuit of an organic EL display device will be described. The overview and circuit configuration of the display device 20 are the same as those shown in Figures 23 and 24, so the explanation will be omitted.

[0098] [Pixel circuit 301 of display device 20] Figure 28 is a circuit diagram showing the pixel circuit of a display device according to one embodiment of the present invention. As shown in Figure 28, the pixel circuit 301 includes elements such as a drive transistor 11, a selection transistor 12, a retention capacitor 210, and a light-emitting element DO. The drive transistor 11 and the selection transistor 12 have the same configuration as the semiconductor device 10. The source electrode of the selection transistor 12 is connected to the signal line 211, and the gate electrode of the selection transistor 12 is connected to the gate line 212. The source electrode of the drive transistor 11 is connected to the anode power line 213, and the drain electrode of the drive transistor 11 is connected to one end of the light-emitting element DO. The other end of the light-emitting element DO is connected to the cathode power line 214. The gate electrode of the drive transistor 11 is connected to the drain electrode of the selection transistor 12. The retention capacitor 210 is connected to the gate electrode and drain electrode of the drive transistor 11. The signal line 211 is supplied with a gradation signal that determines the light emission intensity of the light-emitting element DO. The gate line 212 is supplied with a signal that selects the pixel row on which the above gradation signal is written.

[0099] [Cross-sectional structure of the display device 20] Figure 29 is a cross-sectional view of a display device according to one embodiment of the present invention. The configuration of the display device 20 shown in Figure 29 is similar to that of the display device 20 shown in Figure 26, however, the structure of the display device 20 in Figure 29 above the insulating layer 360 differs from the structure of the display device 20 in Figure 26 above the insulating layer 360. In the following description, the configuration of the display device 20 in Figure 29 that is the same as that of the display device 20 in Figure 26 will be omitted, and the differences between the two will be explained.

[0100] As shown in Figure 29, the display device 20 has a pixel electrode 390, a light-emitting layer 392, and a common electrode 394 (light-emitting element DO) above an insulating layer 360. The pixel electrode 390 is provided on top of the insulating layer 360 and inside the aperture 381. The insulating layer 362 is provided on top of the pixel electrode 390. The insulating layer 362 has an aperture 363. The aperture 363 corresponds to the light-emitting region. In other words, the insulating layer 362 defines the pixels. The light-emitting layer 392 and the common electrode 394 are provided on top of the pixel electrode 390 exposed by the aperture 363. The pixel electrode 390 and the light-emitting layer 392 are provided individually for each pixel. On the other hand, the common electrode 394 is provided in common for multiple pixels. Different materials are used for the light-emitting layer 392 depending on the display color of the pixel.

[0101] In the second and third embodiments, examples were given of configurations in which the semiconductor device described in the first embodiment is applied to a liquid crystal display device and an organic EL display device. However, the semiconductor device may also be applied to display devices other than these (for example, self-emissive display devices other than organic EL displays or electronic paper display devices). Furthermore, the above-mentioned semiconductor device can be applied to a wide range of display devices, from small to medium-sized to large, without any particular limitations. [Examples]

[0102] [Electrical characteristics of semiconductor device 10] The electrical characteristics of the semiconductor device 10 according to the above embodiment will be explained using Figures 30 and 31. The electrical characteristics shown in Figures 30 and 31 are those of the semiconductor device 10 shown in the first embodiment.

[0103] [Initial characteristics] The measurement conditions for the electrical characteristics shown in Figures 30 and 31 are as follows. • Channel region CH size: W / L = 3.0 μm / 3.0 μm Source-drain voltage: 0.1V (dotted line), 10V (solid line) Gate voltage: -15V to +15V • Measurement environment: Room temperature, darkroom

[0104] Figures 30 and 31 show the electrical characteristics (Id-Vg characteristics) and mobility of the semiconductor device 10. As indicated by the arrows in the graphs of Figures 30 and 31, the vertical axis for drain current (Id) is shown on the left side of the graph, and the vertical axis for mobility calculated from the drain current is shown on the right side of the graph.

[0105] As shown in Figure 30, the electrical characteristics of the semiconductor device 10 according to the first embodiment exhibit a so-called normally-off characteristic, where the drain current Id begins to flow when the gate voltage Vg is higher than 0V. The mobility calculated from these electrical characteristics is approximately 59 cm[cm]. 2 [Vs]

[0106] Figure 31 shows the dependence of the electrical characteristics of the semiconductor device 10 according to the first embodiment on the channel length L and channel width W. Figure 31 shows the electrical characteristics when the channel length is 2 μm to 4 μm and the channel width is 2 μm to 25 μm. As shown in Figure 31, it was confirmed that good electrical characteristics can be obtained even with the electrical characteristics of a channel length of 2 μm and a channel width of 2 μm, and also with the electrical characteristics of a channel length of 4 μm and a channel width of 25 μm. In each graph of Figure 31, the mobility is 40 [cm 2 / Vs] and 60[cm 2 A horizontal dotted line is drawn at the value of [Vs]. For semiconductor devices 10 of all sizes shown in Figure 31, 40 [cm 2 Mobility of 60 [cm² / Vs] or higher has been achieved, and in some sizes of semiconductor device 10, mobility of 60 [cm² / Vs] has been achieved. 2 A mobility of / Vs or higher has been achieved.

[0107] [Reliability testing] Figure 32 shows the reliability test results of a semiconductor device according to one embodiment of the present invention. Figure 32 shows the reliability evaluation results using Positive Bias Temperature Stress (PBTS) and the reliability evaluation results using Negative Bias Temperature Illumination Stress (NBTIS). The reliability test results shown in Figure 32 are for the semiconductor device 10 shown in the first embodiment.

[0108] The conditions for the PBTS reliability test are as follows: • Channel region CH size: W / L = 3.0 μm / 3.0 μm • Light irradiation conditions: No irradiation (darkroom) Gate voltage: +30V Source and drain voltage: 0V Stage temperature under stress: 60°C

[0109] The conditions for the NBTIS reliability test are as follows: • Channel region CH size: W / L = 3.0 μm / 3.0 μm • Light irradiation conditions: Irradiation present (8000 cd / m²) 2 ) Gate voltage: -30V Source and drain voltage: 0V Stage temperature under stress: 60°C

[0110] As shown in Figure 32, the results of evaluating the electrical characteristics of each semiconductor device before stress application (0 sec) and after stress application (3600 sec) are displayed overlaid on the screen. In Figure 32, the electrical characteristics before stress application (0 sec) are shown as dotted lines, and the electrical characteristics after stress application (3600 sec) are shown as solid lines.

[0111] The measurement conditions for the electrical characteristics of the semiconductor device 10 before and after stress application are as follows. Source-drain voltage: 0.1V, 10V Gate voltage: -15V to +15V Measurement environment: 60°C, darkroom

[0112] As shown in Figure 32, in the semiconductor device 10 according to the first embodiment, the electrical characteristics remain almost unchanged in both the NBTIS test and the PBTS test.

[0113] [Influence of sputtering method on the electrical characteristics of semiconductor device 10] Figure 33 shows the dependence of the electrical properties of the semiconductor device 10 according to the first embodiment on the deposition conditions of the oxide semiconductor layer 140. Figure 33 is a diagram showing the electrical properties of a semiconductor device according to one embodiment of the present invention. In the manufacturing method of the semiconductor device 10 in which the electrical properties shown in Figure 33 were measured, all conditions were the same except for the deposition temperature of the oxide semiconductor layer 140. As shown in Figure 33, the lower the deposition temperature of the oxide semiconductor layer 140, the better the electrical properties of the semiconductor device 10. It is thought that by depositing the oxide semiconductor layer 140 while cooling the object to be filmed, it was possible to deposit an oxide semiconductor layer 140 with a low crystalline component, and that a good crystalline state of the oxide semiconductor layer 140 was obtained by subsequent OS annealing.

[0114] The embodiments described above as embodiments of the present invention can be combined and implemented as appropriate, insofar as they do not contradict each other. Furthermore, semiconductor devices and display devices of each embodiment that have been modified by those skilled in the art by adding, deleting, or changing components, or by adding, omitting, or changing processes, are also included within the scope of the present invention, as long as they retain the essence of the present invention.

[0115] Any effects or benefits other than those brought about by the embodiments described above, if they are clear from the description herein or easily predictable to a person skilled in the art, are naturally considered to be brought about by the present invention. [Explanation of Symbols]

[0116] 10: Semiconductor device, 11: Driving transistor, 12: Selecting transistor, 20: Display device, 22: Liquid crystal area, 24: Seal area, 26: Terminal area, 100: Substrate, 105, 160: Gate electrode, 110, 120, 150: Gate insulating layer, 130, 190: Metal oxide layer, 140: Oxide semiconductor layer, 141: Top surface, 142: Bottom surface, 143: Side surface, 170, 180: Insulating layer, 171, 173: Aperture, 200: Source / drain electrodes, 201: Source electrode, 203: Drain electrode, 210: Holding capacitance, 211: Signal line, 212: Gate line, 213: Anode power line, 214: Cathode power line, 220: Resist mask, 300: Array substrate, 301: Pixel circuit 302: Source driver circuit, 303: Gate driver circuit, 304: Source wiring, 305: Gate wiring, 306: Terminal section, 307: Connection wiring, 310: Seal section, 311: Liquid crystal element, 320: Opposing substrate, 330: Flexible printed circuit board (FPC), 340: IC chip, 350: Holding capacitance, 360, 362: Insulating layer, 363, 381: Aperture, 370: Common electrode, 380: Insulating layer, 390: Pixel electrode, 392: Light-emitting layer, 394: Common electrode

Claims

1. forming a first metal oxide layer containing aluminum as a main component on a substrate; forming an oxide semiconductor layer on the first metal oxide layer; forming a gate insulating layer on the oxide semiconductor layer; forming a second metal oxide layer mainly composed of aluminum on the gate insulating layer; performing a heat treatment in a state in which the second metal oxide layer is formed on the gate insulating layer; removing the second metal oxide layer after the heat treatment; A method of manufacturing a semiconductor device in which a gate electrode is formed on the gate insulating layer.

2. 2 . The method for manufacturing a semiconductor device according to claim 1 , wherein the gate electrode is formed so as to be in contact with the gate insulating layer exposed by removing the second metal oxide layer.

3. forming a first insulating layer on the substrate; The method for manufacturing a semiconductor device according to claim 1 , further comprising forming the first metal oxide layer on the first insulating layer.

4. A method for manufacturing a semiconductor device as described in claim 1 or 2, wherein the gate insulation layer is formed so as to be in contact with the entire upper surface of the oxide semiconductor.

5. forming a gate electrode on the substrate; forming a gate insulating layer on the gate electrode; forming a first metal oxide layer mainly composed of aluminum on the gate insulating layer; forming an oxide semiconductor layer on the first metal oxide layer; forming a first insulating layer on the oxide semiconductor layer; forming a second metal oxide layer mainly composed of aluminum on the first insulating layer; performing a heat treatment in a state in which the second metal oxide layer is formed on the first insulating layer; The method of manufacturing a semiconductor device further comprises removing the second metal oxide layer after the heat treatment.

6. The method for manufacturing a semiconductor device described in Claim 5, wherein the first insulating layer is formed so as to contact the entire upper surface of the oxide semiconductor.

7. The method for manufacturing a semiconductor device according to claim 1 , wherein the oxide semiconductor layer is formed so as to be in contact with the first metal oxide layer.

8. 8. The method of claim 1, wherein the second metal oxide layer is removed without using a mask.

9. 9. The method for manufacturing a semiconductor device according to claim 1, wherein the first metal oxide layer is formed by a sputtering method.

10. 10. The method for manufacturing a semiconductor device according to claim 1, wherein the second metal oxide layer is formed by a sputtering method.

11. patterning the oxide semiconductor layer formed on the first metal oxide layer; The method for manufacturing a semiconductor device according to claim 1 , further comprising the step of: subjecting the first metal oxide layer and the patterned oxide semiconductor layer to a heat treatment.

12. patterning the oxide semiconductor layer and the first metal oxide layer; The method for manufacturing a semiconductor device according to claim 1 , further comprising the step of: subjecting the patterned oxide semiconductor layer and the first metal oxide layer to a heat treatment.

13. patterning the oxide semiconductor layer; patterning the first metal oxide layer using the patterned oxide semiconductor layer as a mask; The method for manufacturing a semiconductor device according to claim 1 , further comprising the step of: subjecting the patterned oxide semiconductor layer and the first metal oxide layer to a heat treatment.

14. Prior to depositing the oxide semiconductor layer, the first metal oxide layer is patterned; forming the oxide semiconductor layer after the first metal oxide layer is patterned; patterning the oxide semiconductor layer; The method for manufacturing a semiconductor device according to claim 1 , further comprising the step of: subjecting the patterned oxide semiconductor layer and the first metal oxide layer to a heat treatment.

15. 15. The method for manufacturing a semiconductor device according to claim 11, wherein in one independent pattern of the oxide semiconductor layer, all of the second metal oxide layer overlapping the oxide semiconductor layer at least in a plan view is removed.

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