ESD protection circuit and semiconductor device

Abstract

To provide an ESD protection circuit capable of protecting an internal circuit against electrostatic discharge with a short rise time.SOLUTION: An ESD protection circuit 1 includes an off-transistor. The off-transistor comprises: a P-type semiconductor substrate 7; an N-type well region 9 formed in an upper part of the semiconductor substrate 7; an N-type drain region 6 formed in an upper part A of the well region 9 and having a higher impurity concentration than the well region 9; an N-type source region 4 formed separated from the drain region 6 in the upper part A of the well region 9 and having a higher impurity concentration than the well region 9; a gate insulation film 10 formed between the drain region 6 and the source region 4; a gate electrode 5 formed on a surface of the gate insulation film 10; and a P-type high concentration region 8 formed so as to come in contact with the drain region 6 near a corner R of at least the channel region in the upper part A of the well region 9 and having a higher impurity concentration than the well region 9.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to an ESD protection circuit and a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art Semiconductor devices often include an electrostatic discharge (ESD) protection circuit to protect internal circuits from ESD.

[0003] Examples of ESD protection circuits include circuits that use independent or parasitically formed diode elements, bipolar elements, thyristor elements, etc. Among these, the so-called "off transistor" is well known, in which the drain of an N-type MOS (Metal-Oxide-Semiconductor) transistor is connected to an external terminal and the gate and source are grounded to operate in the off state. This off transistor directs surge currents caused by ESD to the ground potential terminal of the mounting board, preventing electrostatic damage to the internal circuitry.

[0004] Various proposals have been made for such off-transistors. For example, an off-transistor connected to an RC timer, in which a resistive element and a capacitive element are connected in series, has been proposed for the purpose of improving ESD protection characteristics (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-146899 Summary of the Invention [Problem to be solved by the invention]

[0006] An object of one aspect of the present invention is to provide an ESD protection circuit that can protect an internal circuit even against electrostatic discharge with a short rise time. [Means for solving the problem]

[0007] An ESD protection circuit according to one aspect of the present invention comprises: a semiconductor substrate of a first conductivity type; a second conductivity type well region formed in an upper portion of the semiconductor substrate; a drain region of a first conductivity type formed above the well region and having an impurity concentration higher than that of the well region; a source region of a first conductivity type formed above the well region and spaced apart from the drain region, the source region having an impurity concentration higher than that of the well region; a gate insulating film formed on the surface of the semiconductor substrate between the drain region and the source region; a gate electrode formed on a surface of the gate insulating film; a second conductivity type high concentration region formed in an upper portion of the well region so as to be in contact with the drain region at least in the vicinity of a corner of the channel region, the high concentration region having an impurity concentration higher than that of the well region; The off-transistor has [Effects of the Invention]

[0008] According to one aspect of the present invention, it is possible to provide an ESD protection circuit that can protect an internal circuit even against electrostatic discharge with a short rise time. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a plan view showing an off-transistor according to the embodiment. [Figure 2] FIG. 2 is a schematic cross-sectional view of the off transistor taken along line II-II in FIG. [Figure 3]FIG. 3 is a schematic cross-sectional view of the off transistor taken along line III-III in FIG. [Figure 4] FIG. 4 illustrates an example of a circuit diagram of a semiconductor device including an ESD protection circuit using the off transistor illustrated in FIGS. [Figure 5] FIG. 5 is a plan view showing a conventional off transistor. [Figure 6] FIG. 6 is a schematic cross-sectional view of the off transistor shown in FIG. 5 taken along line VI-VI. [Figure 7] FIG. 7 is a schematic cross-sectional view of the off transistor taken along line VII-VII in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, an ESD protection circuit using an off-transistor according to an embodiment of the present invention will be described with reference to the drawings. In the following description, for convenience, mutually orthogonal X, Y, and Z axes are set, and the +Z direction is referred to as the upper layer side, the -Z direction is referred to as the lower layer side, etc.

[0011] 5 to 7 show an ESD protection circuit 100 in which a conventional, general MOS (Metal Oxide Semiconductor) field effect transistor is used as an off transistor 100a. The ESD protection circuit 100 includes a drain region 6 in an upper portion A of a P-type well region 9 formed on the surface of an N-type semiconductor substrate 7, and a source region 4 formed in the upper portion A in the same layer direction (X direction) as the drain region 6 and spaced apart from it. The ESD protection circuit 100 includes a gate electrode 5 on the upper layer side of a channel region between the drain region 6 and the source region 4. A gate insulating film 10 is formed between the gate electrode 5 and the well region 9. The gate electrode 5 is formed by implanting N-type impurities into polycrystalline silicon at a high concentration.

[0012] A peripheral wall 3 is formed around the drain region 6, the source region 4, and the gate electrode 5, separating the regions in which the transistors are formed. The peripheral wall 3 is formed by implanting a high concentration of P-type impurities into a portion of the upper part A of the well region 9. In the region inside the peripheral wall 3 in a plan view, a high concentration region 8 is formed by implanting a high concentration of P-type impurities into the region excluding the drain layer 6, the source layer 4, and the gate layer 5. An insulating film 2 is formed on the upper surface side of the high concentration region 8 and on the exposed portion of the upper surface side of the well region 9. The insulating film 2 is, for example, an oxide film such as silicon dioxide, and is formed by LOCOS (Local Oxidation of Silicon) or the like.

[0013] When the off-transistor 100a is viewed from above in the Z direction, a corner R (see FIG. 5) of the channel region tends to have a high localized electric field strength when ESD occurs. If a surge current flows from the drain region 6 to the high-concentration region 8 due to the snapback action of the parasitic bipolar transistor of the off-transistor 100a when ESD occurs, the current flowing after the snapback action may be concentrated at the corner R, causing destruction.

[0014] Furthermore, as semiconductor devices are miniaturized to meet the recent demand for high-density packaging in mobile devices, the parasitic resistance and parasitic capacitance in the path from the external terminal to the semiconductor chip are reduced, which can shorten the rise time of the surge voltage. In particular, in the Charged Device Model (CDM), which is one of the electrostatic discharge models, the rise time of the surge voltage is short, and the off-transistor structures proposed so far may not be able to protect the internal circuitry of miniaturized semiconductor devices.

[0015] Therefore, in order to suppress electrostatic breakdown at the corner R due to ESD, which has a short rise time for surge voltage such as CDM, one embodiment of the present invention has a structure in which a region with a high impurity concentration is formed in at least the well region near this corner, making it easier for current to flow.

[0016] 1 to 3 show an off transistor according to one embodiment of the present invention. An ESD protection circuit 1 is formed using this off transistor 1a. The off-transistor 1a is formed on a semiconductor substrate 7. The semiconductor substrate 7 is made of a P-type silicon substrate, and a well region 9 is provided on the surface thereof by implanting P-type impurities. In an upper portion A of the well region 9, a drain region 6 and a pair of source regions 4 formed and spaced apart in the same layer direction (X direction) as the drain region 6 are formed by implanting N-type impurities to a high concentration. The drain region 6 and the source region 4 are formed in a rectangular shape when viewed in a plan view from the Z direction.

[0017] A high concentration region 8 is formed over the entire upper area of ​​the well region 9, including the channel region between the drain region 6 and the source region 4. This high concentration region 8 is formed by implanting a P-type impurity to a high concentration. A gate electrode 5 is formed on the upper side of the high concentration region 8 between the drain region 6 and the source region 4. The gate electrode 5 is formed by implanting P-type impurities into polycrystalline silicon to a high concentration. The gate electrode 5 is formed in a rectangular shape in a plan view. A gate insulating film 10 is formed between the gate electrode 5 and the high concentration region 8. The gate insulating film 10 is formed of an oxide film such as silicon dioxide, for example.

[0018] A peripheral wall 3 is formed around the drain region 6, the source region 4, and the gate electrode 5, separating the regions in which the transistors are formed. The peripheral wall 3 is formed by implanting a high concentration of P-type impurities into a portion of the upper portion A of the well region 9. An insulating film 2 is formed on the exposed portion on the upper surface of the high concentration region 8. The insulating film 2 is, for example, an oxide film such as silicon dioxide, and is formed from LOCOS or the like.

[0019] In this way, the off transistor 1a of the ESD protection circuit 1 has the high-concentration region 8 formed in the well region 9 at least near the corner R, which reduces the resistance in the path of the current that flows after the snapback operation, making it easier to pass the surge current. This allows the ESD protection circuit 1 to have a small external shape for the semiconductor device, and it can protect the internal circuitry from electrostatic discharge even against ESD with a short rise time for the surge voltage, such as CDM.

[0020] In this embodiment, the high concentration region is formed over the entire upper region of the well region, but the high concentration region only needs to be formed near at least the corners of the channel region, and may be formed over the entire channel region.

[0021] FIG. 4 illustrates an example of a circuit diagram of a semiconductor device including an ESD protection circuit using the off transistor illustrated in FIGS. As shown in FIG. 4, the semiconductor device D is not particularly limited as long as the ESD protection circuit 1 is connected in parallel to the internal circuit (protected circuit) C to be protected from electrostatic discharge, and can be appropriately selected depending on the purpose. The internal circuit C may include, for example, a reference voltage generator and a magnetic sensor.

[0022] As described above, the ESD protection circuit of this embodiment has an off-transistor formed in the upper part of the well region so as to be in contact with at least the drain region near the corner of the channel region, and including a high-concentration region of the second conductivity type whose impurity concentration is higher than the impurity concentration of the well region. As a result, the ESD protection circuit of this embodiment can protect the internal circuitry of a miniaturized semiconductor device even against ESD with a short rise time of surge voltage such as CDM.

[0023] Although one embodiment of the present invention has been described above, the present invention is not limited to the above embodiment and can be modified as appropriate without departing from the spirit of the present invention. Furthermore, within the spirit of the present invention, the components in the above embodiment can be replaced with well-known components as appropriate, and the above-described modified examples can be combined as appropriate. [Explanation of symbols]

[0024] 1 ESD protection circuit 1a Off transistor 2. Insulation layer 3 Peripheral wall part 4 Source Area 5. Gate electrode 6 Drain region 7. Semiconductor substrate 8 High concentration area 9 well area 10 Gate insulating film A Top of well area C Internal circuit (protected circuit) D. Semiconductor Devices R corner

Claims

1. A first-type conductive semiconductor substrate and A first conductivity type well region formed on the upper part of the semiconductor substrate, A drain region of second conductivity type is formed in the upper part of the well region and has an impurity concentration higher than that of the well region, A second conductivity type source region is formed above the well region, spaced apart from the drain region, and having an impurity concentration higher than that of the well region. A gate insulating film formed on the surface of the semiconductor substrate between the drain region and the source region, A gate electrode formed on the surface of the gate insulating film, In the upper part of the well region, a high-concentration region of a first conductivity type is formed so as to be in contact with the drain region at least near the corner of the channel region, and having an impurity concentration higher than that of the well region. An ESD protection circuit characterized by having an off-transistor equipped with [a specific feature].

2. The ESD protection circuit according to claim 1, wherein the high-concentration region is formed over the entire channel region.

3. The ESD protection circuit according to claim 1, wherein the high-concentration region is formed over the entire upper area of ​​the well region.

4. A semiconductor device characterized in that an ESD protection circuit according to any one of claims 1 to 3 and a protected circuit protected from electrostatic discharge by the ESD protection circuit are connected in parallel.

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