Semiconductor device

Abstract

To provide a semiconductor device that realizes inhibition of the leakage current during operation under a high-temperature environment.SOLUTION: A semiconductor device 10 comprises a substrate 100, a semiconductor stack structure 200, a source electrode 600S, a gate electrode 600G, a drain electrode 600D, and a gate insulating film 700. The semiconductor stack structure includes: a first semiconductor layer 300 comprising a first nitride semiconductor formed on the substrate; and a second semiconductor layer 400 formed on the first semiconductor layer and comprising a second nitride semiconductor having a larger band gap than the first nitride semiconductor. The gate leakage current at an operating temperature of 400 K is 2×10-5 A / mm or less when a reverse bias of 100 V is applied to between the gate electrode and the drain electrode.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] Nitride semiconductors have characteristics such as high saturated electron velocity and wide bandgap. For this reason, various studies have been conducted on applying nitride semiconductors to high-voltage and high-output semiconductor devices by utilizing these characteristics. In recent years, for device applications for high frequencies from several tens of GHz to several hundreds of GHz, the development of GaN-based high electron mobility transistors (HEMTs) (hereinafter sometimes referred to as "GaN-HEMTs") has been actively carried out. For example, Al x Ga 1-x N (0 < x < 1) is used as an electron supply layer, and in an AlGaN / GaN-HEMT, a two-dimensional electron gas (hereinafter sometimes referred to as "2DEG") is generated at the heterointerface of Al x Ga 1-x N (0 < x < 1) / GaN due to spontaneous polarization and piezoelectric polarization, and a sheet carrier concentration of 1 × 10 13 cm -2 or more can be obtained without doping anything. Thereby, high-frequency operation is realized (Patent Documents 1 and 2).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] When a semiconductor device is in the off state, an unintended current that flows between electrodes is called a leakage current. In particular, leakage current between the source electrode and drain electrode is called drain leakage current, and leakage current between the source electrode and gate electrode is called gate leakage current. The flow of a large leakage current in a semiconductor device is not only disadvantageous in terms of energy efficiency, but also poses a major problem in terms of safety. For this reason, suppressing leakage current is an important issue.

[0005] On the other hand, the need to use HEMT devices in high-temperature environments is increasing year by year. For example, high frequencies are required for communication in the space environment, but the environmental temperature is extremely high. Taking the surface of the moon as an example, the surface temperature during the day can reach over 100°C. For this reason, the development of HEMT devices that can withstand high-temperature operation is urgently needed.

[0006] Even if there are no problems with gate leakage current and drain leakage current during operation at room temperature, both leakage currents increase when the operating temperature is raised. This is thought to be because the doped layer in the carrier compensation layer in conventional HEMT devices, such as the GaN:Fe layer or AlN buffer layer, is the source of leakage, but the details are still unclear. As described above, a semiconductor device that realizes suppression of leakage current during operation in a high-temperature environment has not been obtained up to now.

[0007] SUMMARY OF THE PRESENT EMBODIMENTS Accordingly, an object of the present invention is to provide a semiconductor device that realizes suppression of leakage current during operation in a high temperature environment. [Means for solving the problem]

[0008] The inventors conducted intensive research into the above-mentioned problems and discovered that the above-mentioned problems can be solved by a semiconductor device in which the gate leakage current value or drain leakage current value during high temperature operation is equal to or less than a certain value, thereby completing the present invention.

[0009] That is, the gist of the present invention is as follows. [1] A semiconductor device comprising a substrate, a semiconductor laminate structure, a source electrode, a gate electrode, and a drain electrode, the semiconductor laminated structure includes a first semiconductor layer made of a first nitride semiconductor formed on the substrate, and a second semiconductor layer made of a second nitride semiconductor formed on the first semiconductor layer and having a band gap larger than that of the first nitride semiconductor; When a reverse bias of 100 V is applied between the gate electrode and the drain electrode, the gate leakage current value at an operating temperature of 400 K is 2×10 -5 A / mm or less. [2] When a reverse bias of 100 V is applied between the gate electrode and the drain electrode, the gate leakage current is 1×10 at an operating temperature of 500 K. -4 The semiconductor device according to [1], wherein the resistance of the semiconductor device is less than A / mm.

[0010] [3] A semiconductor device comprising a substrate, a semiconductor laminate structure, a source electrode, a gate electrode, and a drain electrode, the semiconductor laminated structure includes a first semiconductor layer made of a first nitride semiconductor formed on the substrate, and a second semiconductor layer made of a second nitride semiconductor formed on the first semiconductor layer and having a band gap larger than that of the first nitride semiconductor; When a reverse bias of 20 V is applied between the gate electrode and the drain electrode, the gate leakage current value at an operating temperature of 400 K is 1×10 -5 A / mm or less. [4] When a reverse bias of 20 V is applied between the gate electrode and the drain electrode, the gate leakage current is 4×10 at an operating temperature of 500 K. -5 The semiconductor device according to [3], wherein the resistance is 0.01 A / mm or less. [5] When a reverse bias of 20 V is applied between the gate electrode and the drain electrode, the gate leakage current is 1×10 at an operating temperature of 600 K. -4 The semiconductor device according to the above [3] or [4], wherein the electrical conductivity is less than A / mm.

[0011] [6] A semiconductor device comprising a substrate, a semiconductor laminate structure, a source electrode, a gate electrode, and a drain electrode, the semiconductor laminated structure includes a first semiconductor layer made of a first nitride semiconductor formed on the substrate, and a second semiconductor layer made of a second nitride semiconductor formed on the first semiconductor layer and having a band gap larger than that of the first nitride semiconductor; When a reverse bias of 10 V is applied between the gate electrode and the source electrode, and a forward bias of 100 V is applied between the source electrode and the drain electrode, the drain leakage current value at an operating temperature of 400 K is 5×10 -5 A semiconductor device having a capacitance of less than 1.0 A / mm. [7] When a reverse bias of 10 V is applied between the gate electrode and the source electrode, and a forward bias of 100 V is applied between the source electrode and the drain electrode, the drain leakage current value at an operating temperature of 500 K is 5×10 -4 The semiconductor device according to [6], wherein the resistance of the semiconductor device is less than A / mm. [8] When a reverse bias of 10 V is applied between the gate electrode and the source electrode, and a forward bias of 100 V is applied between the source electrode and the drain electrode, the drain leakage current value at an operating temperature of 600 K is 1×10 -3 The semiconductor device according to any one of [6] to [7], wherein the electrical conductivity is less than A / mm.

[0012] [9] A semiconductor device comprising a substrate, a semiconductor laminate structure, a source electrode, a gate electrode, and a drain electrode, the semiconductor laminated structure includes a first semiconductor layer made of a first nitride semiconductor formed on the substrate, and a second semiconductor layer made of a second nitride semiconductor formed on the first semiconductor layer and having a band gap larger than that of the first nitride semiconductor; When a reverse bias of 10 V is applied between the gate electrode and the source electrode, and a forward bias of 20 V is applied between the source electrode and the drain electrode, the drain leakage current value at an operating temperature of 400 K is 3×10 -5 A semiconductor device having a capacitance of less than 1.0 A / mm.

[10] When a reverse bias of 10 V is applied between the gate electrode and the source electrode, and a forward bias of 20 V is applied between the source electrode and the drain electrode, the drain leakage current value at an operating temperature of 500 K is 1.5×10 -4 A / mm or less, the semiconductor device according to [9] above.

[11] When a reverse bias of 10 V is applied between the gate electrode and the source electrode, and a forward bias of 20 V is applied between the source electrode and the drain electrode, the drain leakage current value at an operating temperature of 600 K is 1×10 -3 A / mm or less, the semiconductor device according to [9] or

[10] above.

[0013]

[12] The first nitride semiconductor contains GaN, The second nitride semiconductor is Al x Ga 1-x N (0 < x < 1), the semiconductor device according to any one of [1] to

[11] above.

[13] The substrate is a GaN substrate, the semiconductor device according to any one of [1] to

[12] above.

[14] The resistivity of the GaN substrate at 400 K is 1×10 7 Ωcm or more, the semiconductor device according to

[13] above.

[15] The resistivity of the GaN substrate at 500 K is 1×10 6 Ωcm or more, the semiconductor device according to

[13] or

[14] above.

[16] The resistivity of the GaN substrate at 600 K is 1×10 5 Ωcm or more, the semiconductor device according to any one of

[13] to

[15] above.

[17] The GaN substrate is a Mn-doped GaN substrate, the semiconductor device according to any one of

[13] to

[16] above. [Effect of the Invention]

[0014] The semiconductor device according to this embodiment effectively suppresses leakage current during operation in a high-temperature environment, making it highly suitable for use in environments requiring high-speed operation under high-temperature conditions. [Brief description of the drawings]

[0015] [Figure 1] FIG. 1 is a schematic cross-sectional view showing an example of a semiconductor device according to this embodiment. [Diagram 2] FIG. 2 is a graph showing the measurement results of the resistivity of the GaN substrates used in Example 1 and Comparative Example 1. [Diagram 3] FIG. 3 is a graph showing the results of two-terminal measurement of the semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a graph showing the results of three-terminal measurement of the semiconductor device according to the first embodiment. [Diagram 5] FIG. 5 is a graph showing the results of two-terminal measurement of the semiconductor device according to Comparative Example 1. In FIG. [Figure 6] FIG. 6 is a graph showing the results of three-terminal measurement of the semiconductor device according to the first comparative example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] The present invention will be described in detail below, but the present invention is not limited to the following embodiments and can be modified and practiced in various ways within the scope of the invention. In this specification, the crystal axis parallel to the

[0001] axis is called the c-axis, the crystal axis parallel to the <10-10> axis is called the m-axis, and the crystal axis parallel to the <11-20> axis is called the a-axis. The crystal plane perpendicular to the c-axis is called the c-plane. The Miller indices of the hexagonal crystal (hkil) are sometimes written in three digits as (hkl) because of the relationship h+k=-i. For example, (0004) is written in three digits as (004). In this specification, when a crystal axis, a crystal plane, a crystal orientation, etc. are mentioned, they respectively mean a crystal axis, a crystal plane, a crystal orientation, etc. in a substrate or a semiconductor layer, unless otherwise specified. In this specification, the Mn concentration and the Fe concentration at a specific position are both values ​​determined by the respective amounts detected using secondary ion mass spectrometry (SIMS). In this specification, when the expression "to" is used, it is used as an expression including the numerical value or physical property value before and after it. In other words, "A to B" means A or more and B or less. In this specification, the gate electrode and the semiconductor are a Schottky junction. Therefore, applying a voltage so that the gate electrode becomes positive is defined as a "forward bias", and applying a voltage so that the gate electrode becomes negative is defined as a "reverse bias". Between the source electrode and the drain electrode, applying a voltage so that the drain electrode becomes positive is defined as a "forward bias", following the general notation in the academic world.

[0017] [Semiconductor Devices] The semiconductor device according to the first embodiment includes a substrate, a semiconductor laminate structure, a source electrode, a gate electrode, and a drain electrode. The semiconductor laminate structure includes a first semiconductor layer made of a first nitride semiconductor formed on the substrate, and a second semiconductor layer made of a second nitride semiconductor having a larger band gap than the first nitride semiconductor formed on the first semiconductor layer. The semiconductor device has a gate leakage current of 2×10 at an operating temperature of 400 K when a reverse bias of 100 V is applied between the gate electrode and the drain electrode. -5 A / mm or less.

[0018] When a reverse bias of 100 V is applied between the gate electrode and the drain electrode, the gate leakage current at an operating temperature of 400 K is 2×10 -5 A / mm or less means that the gate leakage current in a high temperature environment is effectively suppressed when the semiconductor device is in the off state, which makes it possible to prevent a large gate leakage current from flowing and causing the device to break down when the semiconductor device is operated in a high temperature environment. In this specification, a high temperature environment refers to an environment of 50° C. or higher, and may be, for example, 100° C. or higher, or 150° C. or higher. There is no particular upper limit, but it is usually 500° C. or lower.

[0019] When a reverse bias of 100 V is applied between the gate electrode and the drain electrode, the gate leakage current at an operating temperature of 400 K is 2×10 -5 A / mm or less is sufficient, but from the viewpoint of reducing the risk of device failure due to gate leakage current, it is recommended to use a value of 1.5×10 -5 A / mm or less is preferable, and 1×10 -5 A / mm or less is more preferable. The smaller the gate leakage current is, the better. -8 A / mm or more.

[0020] It is also desirable for the semiconductor device to suppress the gate leakage current even in a higher temperature operating environment. From this viewpoint, it is desirable that the gate leakage current value at an operating temperature of 500 K when a reverse bias of 100 V is applied between the gate electrode and the drain electrode is 1×10 -4 A / mm is preferable, and 8×10 -5 A / mm or less is preferable, and 5×10 -5 A / mm or less is preferable, and 3×10 -5 A / mm or less is more preferable. If the gate leakage current at an operating temperature of 500K is in the above range, the risk of device failure due to the gate leakage current can be further reduced. The smaller the gate leakage current value, the more preferable it is. -8 A / mm or more.

[0021] The semiconductor device according to the second embodiment includes a substrate, a semiconductor laminate structure, a source electrode, a gate electrode, and a drain electrode. The semiconductor laminate structure includes a first semiconductor layer formed on the substrate and made of a first nitride semiconductor, and a second semiconductor layer formed on the first semiconductor layer and made of a second nitride semiconductor having a larger band gap than the first nitride semiconductor. The semiconductor device has a gate leakage current of 1×10 at an operating temperature of 400 K when a reverse bias of 20 V is applied between the gate electrode and the drain electrode. -5 A / mm or less.

[0022] When a reverse bias of 20 V is applied between the gate electrode and the drain electrode, the gate leakage current at an operating temperature of 400 K is 1×10 -5 A / mm or less means that the gate leakage current in a high temperature environment is effectively suppressed when the semiconductor device is in the off state, which makes it possible to prevent a large gate leakage current from flowing and causing the device to break down when the semiconductor device is operated in a high temperature environment.

[0023] When a reverse bias of 20 V is applied between the gate electrode and the drain electrode, the gate leakage current value at an operating temperature of 400 K is 1×10 -5 A / mm or less is sufficient, but from the viewpoint of reducing the risk of device failure due to gate leakage current, a value of 8×10 -6 A / mm or less is preferable, and 5×10 -6 A / mm or less is preferable, and 2×10 -6 A / mm or less is particularly preferable. The smaller the gate leakage current is, the more preferable it is. -8 A / mm or more.

[0024] It is also desirable for the semiconductor device to suppress the gate leakage current even in a higher temperature operating environment. From this perspective, it is desirable to suppress the gate leakage current value at an operating temperature of 500 K when a reverse bias of 20 V is applied between the gate electrode and the drain electrode. -5 A / mm or less is preferable, and 2×10 -5 A / mm or less is preferable, and 1×10 -5 A / mm or less is preferable, and 8×10 -6 A / mm or less is more preferable, and 5×10 -6A / mm or less is particularly preferable. If the gate leakage current at an operating temperature of 500K is in the above range, the risk of device failure due to the gate leakage current can be further reduced. The smaller the gate leakage current value, the more preferable it is, but it is usually less than 1.0×10 -8 A / mm or more.

[0025] From a similar perspective, it is desirable for the semiconductor device to suppress the gate leakage current even in a higher temperature operating environment. From this perspective, it is desirable that the gate leakage current value at an operating temperature of 600 K when a reverse bias of 20 V is applied between the gate electrode and the drain electrode is 1×10 -4 A / mm is preferable, and 9×10 -5 A / mm or less is preferable, and 8×10 -5 A / mm or less is more preferable. If the gate leakage current at an operating temperature of 600K is in the above range, the risk of device failure due to the gate leakage current can be further reduced. The smaller the gate leakage current value, the more preferable it is. -8 A / mm or more.

[0026] The semiconductor device according to the third embodiment includes a substrate, a semiconductor laminate structure, a source electrode, a gate electrode, and a drain electrode. The semiconductor laminate structure includes a first semiconductor layer made of a first nitride semiconductor formed on the substrate, and a second semiconductor layer made of a second nitride semiconductor having a larger band gap than the first nitride semiconductor formed on the first semiconductor layer. The semiconductor device has a drain leakage current of 5×10 at an operating temperature of 400 K when a reverse bias of 10 V is applied between the gate electrode and the source electrode, and a forward bias of 100 V is applied between the source electrode and the drain electrode. -5 A / mm.

[0027] When a reverse bias of 10 V is applied between the gate electrode and the source electrode, and a forward bias of 100 V is applied between the source electrode and the drain electrode, the drain leakage current value at an operating temperature of 400 K is 5×10 -5A drain leakage current of less than A / mm means that the drain leakage current in a high-temperature environment is effectively suppressed when the semiconductor device is in the off state, which prevents a large drain leakage current from flowing and causing the device to break down when the semiconductor device is operated in a high-temperature environment.

[0028] When a reverse bias of 10 V is applied between the gate electrode and the source electrode, and a forward bias of 100 V is applied between the source electrode and the drain electrode, the drain leakage current value at an operating temperature of 400 K is 5 × 10 -5 A / mm is sufficient, but from the viewpoint of reducing the risk of device failure due to drain leakage current, a value of 4×10 -5 A / mm or less is preferable, and 3×10 -5 A / mm or less is preferable, and 2×10 -5 A / mm or less is more preferable. The smaller the drain leakage current is, the more preferable it is. -8 A / mm or more.

[0029] It is also desirable for the semiconductor device to suppress the drain leakage current even in a higher temperature operating environment. From this viewpoint, it is desirable to suppress the drain leakage current value at an operating temperature of 500 K when a reverse bias of 10 V is applied between the gate electrode and the source electrode and a forward bias of 100 V is applied between the source electrode and the drain electrode. -4 A / mm is preferable, and 2×10 -4 A / mm or less is preferable, and 1×10 -4 A / mm or less is preferable, and 8×10 -5 A / mm or less is more preferable, and 6×10 -5 A / mm or less is particularly preferable. If the drain leakage current at an operating temperature of 500K is in the above range, the risk of device failure due to the drain leakage current can be further reduced. The smaller the drain leakage current value, the more preferable it is, but it is usually less than 1.0×10 -8 A / mm or more.

[0030] From a similar viewpoint, it is desirable that the drain leakage current of the semiconductor device be suppressed even in a higher temperature operating environment. From this viewpoint, when a reverse bias of 10 V is applied between the gate electrode and the source electrode, and a forward bias of 100 V is applied between the source electrode and the drain electrode, the drain leakage current value at an operating temperature of 600 K is 1×10 -3 A / mm is preferable, and 9×10 -4 A / mm or less is preferable, and 8×10 -4 A / mm or less is more preferable. If the drain leakage current at an operating temperature of 600K is in the above range, the risk of device failure due to the drain leakage current can be further reduced. The smaller the drain leakage current value, the more preferable it is. -8 A / mm or more.

[0031] The semiconductor device according to the fourth embodiment includes a substrate, a semiconductor stack, a source electrode, a gate electrode, and a drain electrode. The semiconductor stack includes a first semiconductor layer made of a first nitride semiconductor formed on the substrate, and a second semiconductor layer made of a second nitride semiconductor having a larger band gap than the first nitride semiconductor formed on the first semiconductor layer. The semiconductor device has a drain leakage current of 3×10 at an operating temperature of 400 K when a reverse bias of 10 V is applied between the gate electrode and the source electrode and a forward bias of 20 V is applied between the source electrode and the drain electrode. -5 A / mm.

[0032] When a reverse bias of 10 V is applied between the gate electrode and the source electrode, and a forward bias of 20 V is applied between the source electrode and the drain electrode, the drain leakage current value at an operating temperature of 400 K is 3×10 -5 A drain leakage current of less than A / mm means that the drain leakage current in a high-temperature environment is effectively suppressed when the semiconductor device is in the off state, which prevents a large drain leakage current from flowing and causing the device to break down when the semiconductor device is operated in a high-temperature environment.

[0033] When a reverse bias of 10 V is applied between the gate electrode and the source electrode, and a forward bias of 20 V is applied between the source electrode and the drain electrode, the drain leakage current value at an operating temperature of 400 K is 3 × 10 -5 A / mm is sufficient, but from the viewpoint of reducing the risk of device failure due to drain leakage current, a value of 1×10 -5 A / mm or less is preferable, and 8×10 -6 A / mm or less is preferable, and 6×10 -6 A / mm or less is more preferable. The smaller the drain leakage current is, the more preferable it is. -8 A / mm or more.

[0034] It is also desirable for the semiconductor device to suppress the drain leakage current even in a higher temperature operating environment. From this viewpoint, it is desirable to suppress the drain leakage current value at an operating temperature of 500 K when a reverse bias of 10 V is applied between the gate electrode and the source electrode and a forward bias of 20 V is applied between the source electrode and the drain electrode. -4 A / mm or less is preferable, and 1×10 -4 A / mm or less is preferable, and 8×10 -5 A / mm or less is preferable, and 5×10 -5 A / mm or less is more preferable, and 3×10 -5 A / mm or less is particularly preferable. If the drain leakage current at an operating temperature of 500K is in the above range, the risk of device failure due to the drain leakage current can be further reduced. The smaller the drain leakage current value, the more preferable it is, but it is usually less than 1.0×10 -8 A / mm or more.

[0035] From a similar viewpoint, it is desirable that the drain leakage current of the semiconductor device be suppressed even in a higher temperature operating environment. From this viewpoint, it is desirable that the drain leakage current value at an operating temperature of 600 K be 1×10 -3 A / mm is preferable, and 8×10 -4A / mm or less is preferable, and 5×10 -4 A / mm or less is preferable, and 3×10 -4 A / mm or less is particularly preferable. If the drain leakage current at an operating temperature of 600K is in the above range, the risk of device failure due to the drain leakage current can be further reduced. The smaller the drain leakage current value, the more preferable it is. -8 A / mm or more.

[0036] ·composition 1 is a schematic cross-sectional view showing an example of a semiconductor device according to this embodiment. In a semiconductor device 10, a semiconductor stack 200 is formed on a substrate 100. The semiconductor stack 200 includes a first semiconductor layer 300 and a second semiconductor layer 400, in that order, and optionally includes a cap layer 500. A source electrode 600S, a drain electrode 600D, and a gate electrode 600G are formed on the semiconductor laminate structure 200. Gate insulating films 700 are optionally formed between the source electrode 600S and the gate electrode 600G, and between the drain electrode 600D and the gate electrode 600G. The first semiconductor layer 300 is a layer made of a first nitride semiconductor, and is made of, for example, a C-containing GaN layer 301 and an i-GaN layer 302. The C-containing GaN layer 301 is preferably formed on the substrate 100, and the i-GaN layer 302 is preferably formed on the C-containing GaN layer 301. The second semiconductor layer 400 is a layer made of a second nitride semiconductor, and is preferably formed on the i-GaN layer 302 constituting the first semiconductor layer 300, for example. When the semiconductor stack 200 includes the cap layer 500, the cap layer 500 is preferably formed on the second semiconductor layer 400. A source electrode 600S, a drain electrode 600D, and a gate electrode 600G are formed on the cap layer 500, respectively.

[0037] ·substrate In any of the first to fourth embodiments of the present invention (these may be collectively referred to as "the present embodiment"), the semiconductor device includes a substrate. The substrate is not particularly limited, and may be, for example, a silicon substrate, a sapphire substrate, a SiC substrate, or a GaN substrate. Among them, the substrate is preferably a GaN substrate from the viewpoint of high crystal quality of the layer made of a nitride semiconductor epitaxially grown on the substrate and excellent device performance.

[0038] When the substrate is a GaN substrate, the resistivity at 400K is 1×10 7 More preferably, it is Ωcm or more. The inventors have found that the resistivity of the GaN substrate at 400 K is 1×10 7 It has been found that when the resistivity is Ωcm or more, the drain leakage current during high temperature operation of the semiconductor device is significantly suppressed. The reason for this is not yet clear, but it is believed to be as follows. In other words, in a HEMT structure, the spread of the depletion layer inhibits the drain leakage current, but in a high-temperature environment, the resistivity of the substrate decreases, causing the drain leakage current to flow via the substrate. Based on this knowledge, it is believed that by using a GaN substrate that has high resistivity even in a high-temperature environment for a semiconductor device, it will be possible to effectively suppress the drain leakage current during high-temperature operation of the semiconductor device.

[0039] In addition, the resistivity of the GaN substrate at 400K is 1×10 7 It has been found that when the resistivity is Ωcm or more, the gate leakage current during high temperature operation of the semiconductor device is also significantly suppressed. The cause of gate leakage current is said to be surface current between the source electrode and gate electrode, defects in the channel layer, etc., but the detailed mechanism is unknown. The mechanism of gate leakage current generation in this embodiment is also unknown, but since the change in resistivity of the substrate leads to a change in the gate leakage current, it is thought that the resistivity of the substrate affects the potential near the channel layer, and as a result, the depletion layer distribution changes, causing a change in the gate leakage current.

[0040] From the above viewpoint, the GaN substrate has a resistivity of 1×10 at 400K. 7 Ωcm or more is preferable, 1×1010 More preferably, Ωcm or more, 1×10 12 More preferably, Ωcm or more, 1×10 15 The resistivity at 400K is preferably as high as possible, and therefore there is no particular upper limit.

[0041] From a similar perspective, the resistivity of the GaN substrate at 500K is 1×10 6 It is also preferable that the resistance is 1×10 9 More preferably, Ωcm or more, 1×10 11 More preferably, Ωcm or more, 1×10 12 The resistivity at 500K is preferably as high as possible, and therefore there is no particular upper limit.

[0042] From a similar perspective, the resistivity of the GaN substrate at 600K is 1×10 5 It is also preferable that the resistance is 1×10 7 More preferably, Ωcm or more, 1×10 8 More preferably, Ωcm or more, 1×10 9 The resistivity at 600K is preferably as high as possible, and therefore there is no particular upper limit.

[0043] The substrate is also preferably a Mn-doped substrate, i.e., a GaN substrate having a Mn-doped layer, in which case the thickness of the Mn-doped layer in the c-axis direction does not need to match the thickness of the GaN substrate in the c-axis direction.

[0044] For example, when the thickness of the entire GaN substrate is 400 μm, the thickness of the Mn-doped layer is sufficient if it is 100 μm from the surface layer of the GaN substrate. Of course, the thickness of the Mn-doped layer is not limited to the above, and it does not exclude cases where it is thicker or thinner than that. In addition, the GaN substrate may be a GaN substrate in which the entire thickness direction is composed of the Mn-doped layer.

[0045] The Mn concentration in the Mn-doped layer of the GaN substrate is 1.0×10 16 atoms / cm 3Above 1.0×10 20 atoms / cm 3 The compensating impurity Mn contributes to high resistance, so the Mn concentration is preferably 1.0×10 16 atoms / cm 3 It is preferable from the viewpoint of increasing the resistance of the GaN crystal to 1.0×10 20 atoms / cm 3 It is preferable for the crystal quality of the GaN crystal to be good if it is not more than this value.

[0046] The Mn concentration in the Mn-doped layer of the GaN substrate is as follows, with the upper limit being 6.0×10 19 atoms / cm 3 Below, 5.0 x 10 19 atoms / cm 3 Below, 3.0 x 10 19 atoms / cm 3 Below, 1.0 x 10 19 atoms / cm 3 Below, 5.0 x 10 18 atoms / cm 3 The lower limit is preferably 1.0×10 16 atoms / cm 3 That's it, 3.0 x 10 16 atoms / cm 3 That's it, 5.0 x 10 16 atoms / cm 3 That's it, 1.0 x 10 17 atoms / cm 3 That's it, 3.0 x 10 17 atoms / cm 3 That's it, 5.0 x 10 17 atoms / cm 3 The combination of the upper and lower limits of the Mn concentration is arbitrary.

[0047] Semiconductor stacked structure The semiconductor device according to this embodiment has a semiconductor stack structure including a first semiconductor layer made of a first nitride semiconductor formed on a substrate, and a second semiconductor layer made of a second nitride semiconductor formed on the first semiconductor layer and having a larger band gap than the first nitride semiconductor.

[0048] First semiconductor layer The first semiconductor layer is a nitride semiconductor crystal layer formed on a substrate and made of a first nitride semiconductor. A suitable example of the first nitride semiconductor is GaN. When the first nitride semiconductor is GaN, the first semiconductor layer preferably includes a C-containing GaN layer containing carbon (C) and an i-GaN layer. The first semiconductor layer may be composed of one layer or two or more layers, and may further include a crystal phase made of GaN other than the C-containing GaN layer and the i-GaN layer.

[0049] ...C-containing GaN layer The first semiconductor layer has a carbon (C) concentration of 1×10 16 atoms / cm 3 It is preferable that the semiconductor device includes a C-containing GaN layer having the above structure. The C-containing GaN layer is a crystal layer made of epitaxially grown GaN and contains carbon (C) as an impurity. The presence of the C-containing GaN layer inhibits the migration of compensating impurities between the different regions defined by the C-containing GaN layer. For example, when the substrate is doped with Mn, the Mn in the substrate may move as a compensating impurity in the HEMT structure by thermal diffusion and reach the 2DEG region. When a compensating impurity such as Mn diffuses into the 2DEG, the movement of electrons in the 2DEG may be hindered, and the performance of the semiconductor device may be degraded. On the other hand, when a C-containing GaN layer is present, the movement of the compensating impurity is hindered, and the performance degradation of the semiconductor device can be suppressed.

[0050] The C concentration in the C-doped GaN layer is 1×10 16 atoms / cm 3 More preferably, from the viewpoint of more effectively inhibiting the movement of compensating impurities, 5×10 16 atoms / cm 3 More preferably, 1×10 17 atoms / cm 3 From the viewpoint of preventing the occurrence of defects such as threading dislocations, the C concentration in the C-containing GaN layer is preferably 1×1019 atoms / cm 3 Less than 1×10 is preferable. 18 atoms / cm 3 Less than 5×10 is preferable. 17 atoms / cm 3 Less than is even more preferred.

[0051] From the viewpoint of fabricating a normal device, the thickness of the C-containing GaN layer in the c-axis direction is preferably 50 nm or more, more preferably 100 nm or more, and even more preferably 200 nm or more. From the viewpoint of reducing leakage current, the thickness of the C-containing GaN layer is preferably 900 nm or less, more preferably 600 nm or less, and even more preferably 500 nm or less.

[0052] From the viewpoint of normal device fabrication, the thickness of the C-containing GaN layer in the c-axis direction is preferably 5% or more of the total thickness of the first semiconductor layer, more preferably 10% or more, and even more preferably 20% or more. From the same viewpoint, the thickness is preferably 90% or less of the total thickness of the first semiconductor layer, more preferably 80% or less, and even more preferably 70% or less. Note that, when the first semiconductor layer contains an i-GaN layer or the like described below in addition to the C-containing GaN layer, the total thickness of the first semiconductor layer refers to the total thickness in the c-axis direction including these layers.

[0053] i-GaN layer In this embodiment, when the first semiconductor layer includes the C-containing GaN layer, the first semiconductor layer preferably has an i-GaN layer in the

[0001] axial direction rather than the C-containing GaN layer, and more preferably the i-GaN layer is disposed directly on the C-containing GaN layer. Having an i-GaN layer in the <0001> axial direction from the C-containing GaN layer means that the i-GaN layer exists in the +c-axial direction from the C-containing GaN layer, that is, in the Ga polarity plane direction of the crystal.

[0054] The i-GaN layer is a crystalline layer made of GaN that is epitaxially grown without intentional doping with impurities, and is distinguished from the C-containing GaN layer by the C concentration. That is, the C concentration of the i-GaN layer is 1×10 16atoms / cm 3 is less than. The i-GaN layer functions as a so-called channel layer.

[0055] The thickness of the first semiconductor layer in the c-axis direction is preferably as thin as possible in order to reduce the drain leakage current during HEMT operation. From the perspective of normal device fabrication, the thickness of the i-GaN layer in the first semiconductor layer is preferably 50 nm or more, more preferably 100 nm or more, and even more preferably 200 nm or more. Also, from the perspective of reducing the leakage current, the thickness of the i-GaN layer is preferably 900 nm or less, more preferably 600 nm or less, and even more preferably 500 nm or less. The upper end surface of the i-GaN layer in the first semiconductor layer preferably coincides with the upper end surface of the first semiconductor layer.

[0056] ···Second semiconductor layer The second semiconductor layer is formed on the first semiconductor layer and is made of a second nitride semiconductor having a larger bandgap than the first nitride semiconductor. The second nitride semiconductor is not particularly limited as long as its bandgap is larger than that of the first nitride semiconductor. For example, when the first nitride semiconductor is GaN, the second nitride semiconductor is preferably Al x Ga 1-x N (0 < x < 1) or AlInGaN. The second semiconductor layer may consist of one layer or two or more layers.

[0057] A two-dimensional electron gas (2DEG) is formed at the hetero-junction interface between the first semiconductor layer and the second semiconductor layer. Specifically, when the first semiconductor layer has the above-mentioned i-GaN layer, a 2DEG is generated in the region sandwiched between the i-GaN layer and the second semiconductor layer. The second semiconductor layer functions as a so-called barrier layer or electron supply layer.

[0058] As a typical example, GaN (first semiconductor layer) / Al x Ga 1-xIn the hetero-structure of N(0 < x < 1) (the second semiconductor layer), due to spontaneous polarization and piezoelectric polarization, a 2DEG is generated at the hetero-interface, and a sheet carrier concentration of 1 × 10 13 cm -2 or more can be obtained, so high-frequency operation is realized.

[0059] From the perspective of normal device fabrication, the thickness of the second semiconductor layer in the c-axis direction is preferably 1 nm or more, more preferably 5 nm or more, and even more preferably 10 nm or more. Also, from the perspective of reducing leakage current, the thickness of the second semiconductor layer is preferably 50 nm or less, more preferably 40 nm or less, and even more preferably 30 nm or less. Note that when the second semiconductor layer is composed of layers made of two or more second nitride semiconductors, the above thickness is the total film thickness of the second semiconductor layer.

[0060] ·· Cap layer The semiconductor laminate structure includes a first semiconductor layer and a second semiconductor layer, but a cap layer may further be formed on the second semiconductor layer. The cap layer is preferably made of a nitride semiconductor different from the second nitride semiconductor. For example, when the second nitride semiconductor is Al x Ga 1-x N(0 < x < 1) or AlInGaN, it is preferably a cap layer made of GaN. The cap layer may consist of one layer or two or more layers.

[0061] From the perspective of normal device fabrication, the thickness of the cap layer in the c-axis direction is preferably 0.1 nm or more, more preferably 0.5 nm or more, and even more preferably 1 nm or more. Also, from the perspective of reducing leakage current, the thickness of the cap layer is preferably 10 nm or less, more preferably 8 nm or less, and even more preferably 5 nm or less. Note that when the cap layer is composed of two or more layers, the above thickness is the total film thickness of the cap layer.

[0062] · Electrode The semiconductor device according to the present embodiment includes a source electrode, a gate electrode, and a drain electrode, which are preferably formed above the semiconductor laminate structure.

[0063] The source electrode is, for example, a metal electrode, and specific examples thereof include a laminated structure containing titanium (Ti) and aluminum (Al), and a laminated structure containing molybdenum (Mo) and aluminum (Al).

[0064] The drain electrode is, for example, a metal electrode, and specific examples thereof include a laminated structure containing titanium (Ti) and aluminum (Al), and a laminated structure containing molybdenum (Mo) and aluminum (Al).

[0065] The source electrode and the drain electrode are preferably in ohmic contact with the semiconductor laminate structure, and the distance between the source electrode and the drain electrode is, for example, 5 μm or more and 30 μm or less.

[0066] The gate electrode is, for example, a metal electrode, and specifically, a laminated structure containing nickel (Ni) and gold (Au), a laminated structure containing platinum (Pt) and gold (Au), etc. The gate length is, for example, 1 μm or more and 15 μm or less. The gate electrode is preferably formed between the source electrode and the drain electrode. The distance between the gate electrode and the source electrode is, for example, 1 μm or more and 15 μm or less. The distance between the gate electrode and the drain electrode is, for example, 1 μm or more and 15 μm or less.

[0067] A gate insulating film may be provided between the gate electrode and the semiconductor laminate structure, that is, the gate electrode may be formed above the semiconductor laminate structure via the gate insulating film. Furthermore, a gate insulating film may be provided between the gate electrode and the source electrode, and between the gate electrode and the drain electrode.

[0068] The gate insulating film is, for example, an oxide or an oxynitride, such as silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, or aluminum oxynitride.

[0069] In one preferred embodiment, a source electrode, a gate electrode, and a drain electrode are formed on the cap layer, and more preferably, a gate insulating film is provided between the source electrode and the gate electrode, and between the gate electrode and the drain electrode. In another preferred embodiment, a source electrode and a drain electrode are formed on the second semiconductor layer, and a gate electrode is formed on the cap layer. In another preferred embodiment, a source electrode and a drain electrode are formed on the cap layer, and a gate electrode is formed on the gate insulating film.

[0070] ·Applications The semiconductor device according to this embodiment is capable of suppressing leakage current when high-speed operation in a high-temperature environment is required, and therefore can be suitably used for communications in high-temperature environments such as the desert or space.

[0071] [Method of manufacturing semiconductor device] The method for manufacturing the semiconductor device according to the present embodiment is not particularly limited, but one embodiment will be described below as an example. In addition, the preferred aspects of the semiconductor device obtained by this manufacturing method are the same as those described in the above-mentioned [Semiconductor device]. The manufacturing method of the semiconductor device according to the embodiment includes at least the steps of preparing a substrate, forming a semiconductor laminate structure on the substrate, and forming an electrode above the semiconductor laminate structure.

[0072] How to prepare the board The substrate used in the semiconductor device according to this embodiment is not particularly limited as described in the above [Semiconductor device], but is preferably a GaN substrate, and has a resistivity of 1×10 at 400 K or more. 7It is more preferable that the GaN substrate has a resistivity of Ωcm or more. Also, the GaN substrate may have a Mn-doped layer.

[0073] The above-mentioned substrate may be manufactured by a known method, or may be a commercially available product. In the case of manufacturing a GaN substrate, the step of preparing the above-mentioned substrate is a step of manufacturing the GaN substrate. Resistivity at 400K is 1×10 7 A GaN substrate with a resistivity of Ωcm or more can be obtained, for example, by growing a bulk GaN crystal on a seed while doping it with compensating impurities such as Mn using the HVPE (hydride vapor phase epitaxy) method, and then processing the crystal such as slicing, grinding, and polishing. The Mn-doped GaN substrate can be obtained, for example, by growing a Mn-doped bulk GaN crystal on a seed by the HVPE method, and then processing it by slicing, grinding, polishing, and the like.

[0074] -Method for forming semiconductor laminated structure The semiconductor laminated structure includes a first semiconductor layer made of a first nitride semiconductor formed on a substrate, and a second semiconductor layer made of a second nitride semiconductor having a larger band gap than the first nitride semiconductor formed on the first semiconductor layer. Thus, a method for forming the semiconductor laminated structure includes the steps of forming the first semiconductor layer on a substrate, and forming the second semiconductor layer on the first semiconductor layer.

[0075] The method for forming the first semiconductor layer on the substrate is not particularly limited, and various known methods can be adopted. Suitable examples include MOCVD (metal organic chemical vapor deposition) and molecular beam epitaxy (MBE). A method for forming a first semiconductor layer made of GaN will be specifically described below.

[0076] When the MOCVD method is used, the source gas is not particularly limited as long as it contains a Ga source and an N source for forming GaN, and any known source gas can be used.

[0077] When the first semiconductor layer is doped with C to form a C-containing GaN layer, the C concentration is 1×10 16 atoms / cm 3 As described in “Semiconductor stacked structure\··First semiconductor layer\···C-containing GaN layer” in the above [Semiconductor device], the thickness in the c-axis direction (height in the thickness direction) of the C-containing GaN layer is preferably 50 nm or more from the viewpoint of fabricating a normal device, and is preferably 900 nm or less from the viewpoint of reducing leakage current.

[0078] The C concentration in the C-doped GaN layer is 1×10 16 atoms / cm 3 The concentration should be 5×10 or more. 16 atoms / cm 3 That's it, 1×10 17 atoms / cm 3 The above may be possible.

[0079] The C concentration in the C-doped GaN layer was set to 1×10 in order to avoid a significant deterioration in crystal quality due to excessive doping. 19 atoms / cm 3 Less than 1×10 is preferable. 18 atoms / cm 3 Less than or 5 x 10 17 atoms / cm 3 It may be less than.

[0080] A conventionally known method can be used for doping C. For example, it is preferable to use the MOCVD method or the MBE method.

[0081] When using the MOCVD method, a hydrocarbon gas such as CH4 (methane) can be used as the source gas, but from the viewpoint of simplicity, it is preferable to use a source gas containing a Ga source and a N source for forming GaN. From this viewpoint, it is preferable to use trimethylgallium (TMG) or triethylgallium (TEG) as the source gas for C, and TMG is more preferable. It is further preferable to use a mixed gas of TMG and ammonia (NH3), or a mixed gas of TEG and NH3.

[0082] When a mixed gas of trimethylgallium (TMG) and ammonia (NH3) is used, the supply rate of TMG is preferably 100 μmol / min or more, more preferably 200 μmol / min or more, from the viewpoint of reducing the concentration of impurities such as Si, etc. Also, the supply rate of TMG is preferably 500 μmol / min or less, more preferably 300 μmol / min or less, from the viewpoint of film thickness controllability. Moreover, the supply rate ratio represented by TMG:NH3 is preferably 1:100 to 1:4000, more preferably 1:500 to 1:4000 or 1:100 to 1:2000, and further preferably 1:500 to 1:2000, from the viewpoint of controllability of the C concentration.

[0083] As described above, after forming a C-containing GaN layer as the first semiconductor layer, an i-GaN layer may be formed. The method for forming the i-GaN layer is the same as the method for forming the C-containing GaN layer, except that it is not doped with intentional impurities. Suitable examples include the MOCVD method and the MBE method.

[0084] When the MOCVD method is used to form the i-GaN layer, a hydrocarbon gas such as CH4 (methane) can be used as the source gas. From the viewpoint of simplicity, however, it is preferable to use a source gas that also contains a Ga source and a N source for forming GaN.

[0085] When using a mixed gas of trimethylgallium (TMG) and ammonia (NH3), from the perspective of reducing the impurity concentration such as Si, the supply rate of TMG is preferably 50 μmol / min or more, more preferably 100 μmol / min or more. Also, from the perspective of film thickness controllability, the supply rate of TMG is preferably 250 μmol / min or less, more preferably 150 μmol / min or less. Also, the ratio of the supply rates represented by TMG:NH3 is preferably 1:400 to 1:16000 from the perspective of reducing the C concentration, more preferably 1:400 to 1:1800 or 1:2000 to 1:16000, and even more preferably 1:2000 to 1:8000.

[0086] The thickness of the i-GaN layer in the c-axis direction in the first semiconductor layer is the same as that described in "[Semiconductor Layer Device]" under "·Semiconductor Stacked Structure\··First Semiconductor Layer\···i-GaN Layer", and it is preferably 50 nm or more from the perspective of normal device fabrication, and preferably 900 nm or less from the perspective of reducing leakage current.

[0087] ·Method for forming the second semiconductor layer After forming the above-mentioned first semiconductor layer, a second semiconductor layer is formed on the first semiconductor layer. The second nitride semiconductor constituting the second semiconductor layer is not particularly limited as long as its bandgap is larger than that of the first nitride semiconductor. For example, when the first nitride semiconductor is GaN, the second nitride semiconductor is preferably Al x Ga 1-x N (0 < x < 1) or AlInGaN. A 2DEG is generated in the region sandwiched between the first semiconductor layer and the second semiconductor layer.

[0088] The method for forming the second semiconductor layer is not particularly limited, and a conventionally known method may be adopted. Suitable examples include using the MOCVD method or the MBE method. The preferred thickness of the second semiconductor layer on the first semiconductor layer in the c-axis direction is the same as that described in "[Semiconductor Layer Device]" under "·Semiconductor Stacked Structure\··Second Semiconductor Layer".

[0089] When the second semiconductor layer is formed, a conventionally known layer such as a cap layer may be formed by a conventionally known method, if necessary.

[0090] Electrode formation method The method of forming the electrodes includes the steps of forming a source electrode, a gate electrode, and a drain electrode above a semiconductor laminate structure. The method for forming the electrodes is not particularly limited, and any conventionally known method may be used. A suitable example is photolithography.

[0091] The source electrode is, for example, a metal electrode, and specific examples thereof include a laminated structure containing titanium (Ti) and aluminum (Al), and a laminated structure containing molybdenum (Mo) and aluminum (Al). The drain electrode is, for example, a metal electrode, and specific examples thereof include a laminated structure containing titanium (Ti) and aluminum (Al), and a laminated structure containing molybdenum (Mo) and aluminum (Al). It is preferable that the source electrode and the drain electrode are in ohmic contact with the semiconductor laminate structure.

[0092] The gate electrode is, for example, a metal electrode, and specific examples thereof include a layered structure containing nickel (Ni) and gold (Au), and a layered structure containing platinum (Pt) and gold (Au). The gate electrode is preferably formed between the source electrode and the drain electrode. A gate insulating film may be provided between the gate electrode and the semiconductor laminated structure. That is, the gate electrode may be formed above the semiconductor laminated structure via the gate insulating film. A gate insulating film may be provided between the gate electrode and the source electrode and between the gate electrode and the drain electrode.

[0093] The gate insulating film is, for example, an oxide or an oxynitride, such as silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, or aluminum oxynitride. The method for forming the gate insulating film is not particularly limited, and any conventionally known method may be used. A suitable example is the plasma-enhanced chemical vapor deposition (PECVD) method. EXAMPLES

[0094] The present invention will be specifically described below with reference to examples, but the present invention is not limited to these.

[0095] [Example 1] A semiconductor multilayer structure was deposited by MOCVD on a c-plane GaN substrate with a Mn-doped layer obtained by HVPE to obtain a GaN epitaxial substrate with a HEMT structure. The thickness of the entire c-plane GaN substrate in the c-axis direction was 400 μm, of which the Mn-doped layer was present on the Ga polarity side with a thickness of approximately 100 μm. The Mn concentration of the Mn-doped layer was 8×10 17 atoms / cm 3 It was. The resistivity of a c-plane GaN substrate with a Mn-doped layer at 400 K is 1.0×10 12 Resistivity at 500K is 1.0×10 12 Ωcm, resistivity at 600K is 1.4×10 10 The resistivity was measured by the method described below.

[0096] Specifically, to form the first semiconductor layer, a c-plane GaN substrate was placed in an MOCVD apparatus and heated to 1090°C in a hydrogen / nitrogen mixed gas atmosphere at atmospheric pressure, and trimethylgallium (TMG) and NH3 gas were supplied. The gas supply rates were 410 μmol / min for TMG and 5 slm for NH3 gas. By growing the crystal for 2.7 minutes under these conditions, the C concentration in the first semiconductor layer reached 1×10 17 atoms / cm 3 The C-containing GaN layer was formed with a thickness of 300 nm. Next, an i-GaN layer with a thickness of 200 nm was grown on the obtained C-containing GaN layer while changing the supply rates of TMG and NH3 gases, the growth time, i.e., the gas supply amount.

[0097] As the formation of the second semiconductor layer, on the i-GaN layer formed above, Al x Ga 1-x N (0 < x < 1) layer was formed with a thickness of 18 nm. Next, a GaN cap layer was grown to a thickness of 2 nm to form a semiconductor laminated structure. Thus, a GaN epitaxial substrate having a HEMT structure with a substrate and a semiconductor layer laminated structure was obtained.

[0098] By means of photolithography, electrodes were formed on the GaN epitaxial substrate obtained above. The source electrode and the drain electrode were deposited by electron beam with Mo(7 nm) / Al(75 nm) / Mo(50 nm) / Au(120 nm), and the gate electrode was deposited by electron beam with Ni(36 nm) / Au(370 nm). The values in parentheses indicate the respective thicknesses. The gate length, the distance between the gate electrode and the source electrode, and the distance between the gate electrode and the drain electrode were 2 μm, 2 μm, and 5 μm, respectively, in this order. SiNx was formed as a gate insulating film with a thickness of 60 nm by PECVD method between the gate electrode and the source electrode, and between the gate electrode and the drain electrode, respectively. Thus, a semiconductor device having a HEMT structure (also referred to as a HEMT element) was obtained.

[0099] [Comparative Example 1] A semiconductor device having a HEMT structure (HEMT element) was obtained in the same manner as in Example 1 except that Fe was used instead of Mn as a compensation impurity to form a c-plane GaN substrate having an Fe-doped layer. The Fe-doped layer was present on the Ga-polarity plane side with a thickness of about 100 μm, and the Fe concentration in the Fe-doped layer was 3×10 18 atoms / cm 3 It was. The resistivity of the c-plane GaN substrate having an Fe-doped layer at 400 K was 3.2×10 6Ωcm, resistivity at 500K is 1.2×10 5 Ωcm, resistivity at 600K is 1.5×10 4 The resistivity was measured by the method described below.

[0100] [Measurement of substrate resistivity] A 30 nm Ti and 100 nm Au were successively vacuum-deposited on the surface of a c-plane GaN substrate, and Hall measurements were performed. The Hall measurements were performed using the four-terminal Van der Pauw method, and the resistivity (specific resistance) was measured while changing the measurement temperature. The measurement results of the resistivity in Example 1 are shown by "●" in Fig. 2, and the measurement results of the resistivity in Comparative Example 1 are shown by "▲" in Fig. 2. Note that the carrier type determined by the Hall measurement in each temperature range was p-type.

[0101] [Evaluation of semiconductor device] 2-terminal measurement In a semiconductor device with a HEMT structure, a reverse bias was applied between the gate electrode and the drain electrode to evaluate the two-terminal reverse breakdown voltage characteristics. The HEMT element was attached to a temperature variable stage by vacuum adsorption. The temperature of the temperature variable stage was changed to 300K, 400K, 500K, or 600K, and the two-terminal reverse breakdown voltage characteristics were evaluated at each temperature. The results of Example 1 are shown in FIG. 3, and the results of Comparative Example 1 are shown in FIG. 5. Vgd indicates the bias value between the gate electrode and the drain electrode, and -Ig indicates the gate leakage current. In the measurement, 1×10 -4 The cut-off current is the threshold value for determining whether the leakage current is good or bad, and is 1×10 -4 A value of A / mm or more indicates leakage. From the results of Figures 3 and 5, the -Ig value when Vgd is 100 V is shown in Table 1, and the -Ig value when Vgd is 20 V is shown in Table 2. In Tables 1 and 2, "leak" refers to a gate leakage current value of 1×10 -4 This means that the value was greater than or equal to A / mm.

[0102] 3-terminal measurement In a semiconductor device with a HEMT structure, a reverse bias of 10 V was applied between the gate electrode and the source electrode, and a forward bias was applied between the source electrode and the drain electrode to evaluate the three-terminal breakdown voltage characteristics. The HEMT element was attached to a temperature variable stage by vacuum adsorption. The temperature of the temperature variable stage was changed to 300 K, 400 K, 500 K, or 600 K, and the three-terminal breakdown voltage characteristics were evaluated at each temperature. The results of Example 1 are shown in FIG. 4, and the results of Comparative Example 1 are shown in FIG. 6. Vds indicates the bias value between the source electrode and the drain electrode, and Id indicates the drain leakage current. In the measurement, 1×10 -3 The cut-off current is the threshold value for determining whether the leakage current is good or bad, and is 1×10 -3 A value of A / mm or more indicates leakage. From the results of Fig. 4 and Fig. 6, the Id value when Vds is 100 V is shown in Table 3, and the Id value when Vds is 20 V is shown in Table 4. In Tables 3 and 4, "leak" means a drain leakage current value of 1×10 -3 This means that the value was greater than or equal to A / mm.

[0103] From the results in Table 1, when Vgd is 100 V and the operating temperature is 400 K, the gate leakage current value of the HEMT element of Comparative Example 1 is 2 × 10 -5 A / mm, whereas the gate leakage current of the HEMT element in Example 1 was 2×10 -5 A / mm or less, which is considerably smaller than that of Comparative Example 1. Furthermore, at operating temperatures of 500K and 600K, the gate leakage current value of the HEMT element of Comparative Example 1 exceeded the cutoff current value and was determined to be a leak, whereas the gate leakage current value of the HEMT element of Example 1 was 1×10 -4 The value was small, less than A / mm.

[0104] From the results in Table 2, when Vgd is 20 V and the operating temperature is 400 K, the HEMT element of Comparative Example 1 has a gate leakage current value of 1×10 -5 A / mm, whereas the HEMT element of Example 1 had a gate leakage current value of 1×10-5 At an operating temperature of 500 K, the gate leakage current of the HEMT element of Comparative Example 1 was 4×10 -5 A / mm, whereas the gate leakage current of the HEMT device in Example 1 was 4×10 -5 A / mm or less. At both operating temperatures of 400K and 500K, the gate leakage current value in the HEMT element of Example 1 was significantly larger than that in Comparative Example 1. At an operating temperature of 600K, the gate leakage current value of the HEMT element of Comparative Example 1 exceeded the cutoff current value and was determined to be a leak, whereas the HEMT element of Example 1 had a gate leakage current value of 1×10 -4 The value was small, less than A / mm.

[0105] From the results in Table 3, when Vds is 100 V and the operating temperature is 400 K, the drain leakage current value of the HEMT element of Comparative Example 1 is 5×10 -5 A / mm, whereas the drain leakage current of the HEMT element of Example 1 was 5×10 -5 A / mm, which is smaller than that of Comparative Example 1. At an operating temperature of 500 K, the HEMT element of Comparative Example 1 had a drain leakage current value of 5×10 -4 A / mm, whereas the drain leakage current of the HEMT device in Example 1 was 5×10 -4 A / mm, which is considerably smaller than that of Comparative Example 1. Furthermore, at an operating temperature of 600 K, the drain leakage current value of the HEMT element of Comparative Example 1 exceeded the cutoff current value and was determined to be a leak, whereas the drain leakage current value of the HEMT element of Example 1 was 1×10 -3 The value was small, less than A / mm.

[0106] From the results in Table 4, when Vds is 20 V, the drain leakage current value of Comparative Example 1 is 3×10 -5 A / mm, whereas the drain leakage current of the HEMT element of Example 1 was 3×10 -5A / mm, which is smaller than that of Comparative Example 1. At an operating temperature of 500 K, the HEMT element of Comparative Example 1 had a drain leakage current value of 1.5×10 -4 A / mm, whereas the drain leakage current of the HEMT device in Example 1 was 1.5×10 -4 A / mm, which is considerably smaller than that of Comparative Example 1. Furthermore, at an operating temperature of 600 K, the drain leakage current value of the HEMT element of Comparative Example 1 exceeded the cutoff current value and was determined to be a leak, whereas the drain leakage current value of the HEMT element of Example 1 was 1×10 -3 The value was small, less than A / mm.

[0107] [Table 1]

[0108] [Table 2]

[0109] [Table 3]

[0110] [Table 4]

Claims

1. A semiconductor device including a substrate, a semiconductor stack structure, a source electrode, a gate electrode, and a drain electrode, wherein the substrate is an Mn-doped GaN substrate, and the semiconductor stack structure includes a first semiconductor layer made of a first nitride semiconductor formed on the substrate, and a second semiconductor layer made of a second nitride semiconductor formed on the first semiconductor layer and having a larger bandgap than the first nitride semiconductor. When a reverse bias of 100 V is applied between the gate electrode and the drain electrode, the gate leakage current value at an operating temperature of 400 K is 2 × 10 －５ A / mm or less, a semiconductor device.

2. The gate leakage current value at an operating temperature of 500 K when a reverse bias of 100 V is applied between the gate electrode and the drain electrode is less than 1×10 －４ A / mm, and the semiconductor device according to claim 1.

3. A semiconductor device including a substrate, a semiconductor stack structure, a source electrode, a gate electrode, and a drain electrode, wherein the substrate is an Mn-doped GaN substrate, and the semiconductor stack structure includes a first semiconductor layer made of a first nitride semiconductor formed on the substrate, and a second semiconductor layer made of a second nitride semiconductor formed on the first semiconductor layer and having a larger bandgap than the first nitride semiconductor. When a reverse bias of 20 V is applied between the gate electrode and the drain electrode, the gate leakage current value at an operating temperature of 400 K is 1 × 10 －５ A / mm or less, semiconductor device.

4. When a reverse bias of 20 V is applied between the gate electrode and the drain electrode, the gate leakage current value at an operating temperature of 500 K is 4 × 10 －５ A / mm or less. The semiconductor device according to claim 3.

5. When a reverse bias of 20 V is applied between the gate electrode and the drain electrode, the gate leakage current value at an operating temperature of 600 K is less than 1×10 －４ A / mm, and the semiconductor device according to claim 3 or 4.

6. A semiconductor device including a substrate, a semiconductor stack structure, a source electrode, a gate electrode, and a drain electrode, wherein the substrate is an Mn-doped GaN substrate, and the semiconductor stack structure includes a first semiconductor layer made of a first nitride semiconductor formed on the substrate, and a second semiconductor layer made of a second nitride semiconductor formed on the first semiconductor layer and having a larger bandgap than the first nitride semiconductor. When a reverse bias of 10 V is applied between the gate electrode and the source electrode, and a forward bias of 100 V is applied between the source electrode and the drain electrode, the drain leakage current value at an operating temperature of 400 K is less than 5×10 －５ A / mm, semiconductor device.

7. When a reverse bias of 10 V is applied between the gate electrode and the source electrode and a forward bias of 100 V is applied between the source electrode and the drain electrode, the drain leakage current value at an operating temperature of 500 K is less than 5×10 －４ A / mm, and the semiconductor device according to claim 6.

8. When a reverse bias of 10 V is applied between the gate electrode and the source electrode and a forward bias of 100 V is applied between the source electrode and the drain electrode, the drain leakage current value at an operating temperature of 600 K is 1 × 10 －３ A semiconductor device according to claim 6 or 7, wherein the leakage current is less than A / mm.

9. A semiconductor device including a substrate, a semiconductor stack structure, a source electrode, a gate electrode, and a drain electrode, wherein the substrate is an Mn-doped GaN substrate, and the semiconductor stack structure includes a first semiconductor layer made of a first nitride semiconductor formed on the substrate, and a second semiconductor layer made of a second nitride semiconductor formed on the first semiconductor layer and having a larger bandgap than the first nitride semiconductor. When a reverse bias of 10 V is applied between the gate electrode and the source electrode, and a forward bias of 20 V is applied between the source electrode and the drain electrode, the drain leakage current value at an operating temperature of 400 K is 3×10 －５ A semiconductor device that is less than / mm.

10. When a reverse bias of 10 V is applied between the gate electrode and the source electrode and a forward bias of 20 V is applied between the source electrode and the drain electrode, the drain leakage current value at an operating temperature of 500 K is 1.5×10 －４ A semiconductor device according to claim 9, wherein the leakage current is 1.5×10 －４ A / mm or less.

11. When a reverse bias of 10 V is applied between the gate electrode and the source electrode, and a forward bias of 20 V is applied between the source electrode and the drain electrode, the drain leakage current value at an operating temperature of 600 K is 1×10 －３ A semiconductor device according to claim 9 or 10, wherein the leakage current is less than A / mm.

12. The first nitride semiconductor contains GaN. The second nitride semiconductor contains Al ｘ Ga １－ｘ N (0 < x < 1), and the semiconductor device according to claim 1, 3, 6, or 9.

13. The resistivity of the GaN substrate at 400 K is 1×10 ７ Ω·cm or more, the semiconductor device according to claim 1, 3, 6, or 9.

14. The resistivity of the GaN substrate at 500 K is 1 × 10 ６ Ω cm or more, and the semiconductor device according to claim 1, 3, 6, or 9.

15. The resistivity of the GaN substrate at 600 K is 1×10 ５ Ω cm or more, the semiconductor device according to claim 1, 3, 6, or 9.

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