Doping techniques
Patent Information
- Application Number
- JP2023193004
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2018-08-11
- Filing Date
- 2023-11-13
- Publication Date
- 2025-09-05
- Estimated Expiration
- 2039-08-09
AI Technical Summary
Existing methods of boron doping in semiconductor materials are limited to line-of-sight processes, lack conformality, and often dope both semiconductor and oxide materials, failing to selectively target semiconductor surfaces.
A method involving a non-line-of-sight pyrolysis process at controlled temperatures to deposit a conformal dopant film on semiconductor surfaces, followed by annealing to drive dopant atoms into the semiconductor material while minimizing dopant atoms in oxide materials.
Achieves conformal doping of semiconductor materials with high selectivity, ensuring minimal dopant atoms in oxide materials, thereby improving the quality and consistency of semiconductor devices.
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Abstract
Description
[Technical field]
[0001]
[0001] Embodiments of the present disclosure generally relate to methods for doping semiconductor materials, some embodiments of the present disclosure relate to methods for selectively doping semiconductor materials with respect to oxide materials, and some embodiments of the present disclosure relate to methods for conformally doping semiconductor materials. [Background technology]
[0002]
[0002] Controlling boron doping is important for p-type contact applications. Process control requires management of layer thickness, surface properties, thermal budget and etch selectivity.
[0003]
[0003] Additionally, existing methods of boron doping do not provide a method for conformally doping three-dimensional structures (e.g., FINFETs). These methods (e.g., implantation) are often line-of-sight limited or do not exhibit sufficient conformality.
[0004] Furthermore, existing methods of boron doping do not provide a method for doping only the semiconductor material: current technology often dopes both the semiconductor material and the adjacent oxide material.
[0005]
[0005] Therefore, there is a need for a method for conformally doping semiconductor materials, particularly a method that is selective to the surface of the semiconductor material. Summary of the Invention
[0006]
[0006] One or more embodiments of the present disclosure are directed to a method of forming an electronic device. The method includes selectively depositing a substantially conformal dopant film on a first surface including a semiconductor material relative to a second surface including an oxide material. The electronic device is annealed to drive dopant atoms from the dopant film into the semiconductor material such that the semiconductor material is conformally doped and substantially no dopant atoms are driven into the oxide material.
[0007]
[0007] A further embodiment of the present disclosure is directed to a method of forming an electronic device. The method includes providing a substrate having a first surface comprising a semiconductor material and a second surface comprising an oxide material. The first surface and the second surface are exposed to a boron precursor at a temperature ranging from about 700°C to about 800°C to selectively deposit a conformal dopant film by a non-line-of-sight pyrolysis process. The dopant film is deposited on the first surface and over the second surface. The dopant film comprises boron. The electronic device is annealed by a millisecond anneal at a temperature ranging from about 1150°C to about 1200°C to drive boron atoms from the dopant film into the semiconductor material such that the semiconductor material is conformally doped and substantially no dopant atoms are driven into the oxide material.
[0008]
[0008] A further embodiment of the present disclosure is directed to a method of forming an electronic device. The method includes forming an amorphous boron layer on a crystalline semiconductor material. An additional semiconductor material is deposited on the amorphous boron layer. The additional semiconductor material is substantially amorphous. The electronic device is annealed to crystallize the additional semiconductor material to form a boron-doped crystalline semiconductor material.
[0009]
[0009] So that the above-mentioned features of the present disclosure can be understood in detail, a more particular description of the present disclosure briefly summarized above can be made by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the present disclosure is open to other equally effective embodiments, and therefore the accompanying drawings merely illustrate typical embodiments of the present disclosure, and should not be considered as limiting the scope of the present disclosure. [Brief description of the drawings]
[0010] [Figure 1] 1 illustrates an exemplary substrate during processing in accordance with one or more embodiments of the present disclosure. [Diagram 2]
[0011] 1 illustrates an exemplary substrate during processing in accordance with one or more embodiments of the present disclosure. [Diagram 3]
[0012] 1 illustrates a system that can be used to process a substrate in accordance with one or more embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0011]
[0013] Before describing certain example embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description as the present disclosure is capable of other embodiments and of being practiced or carried out in various ways.
[0012]
[0014] As used herein and in the appended claims, the term "substrate" refers to a surface or a portion of a surface on which a process acts. Those skilled in the art will also understand that a reference to a substrate may refer to only a portion of the substrate, unless the context clearly indicates otherwise. Additionally, a reference to depositing on a substrate may refer to both a bare substrate and a substrate having one or more films or features deposited or formed thereon.
[0013]
[0015] As used herein, "substrate surface" refers to any substrate or material surface formed on a substrate on which a film treatment is performed during a manufacturing process. For example, substrate surfaces on which treatment may be performed include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers. Substrates may be exposed to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, e-beam cure, and / or bake the substrate surface. In addition to film treatment directly on the surface of the substrate itself, in the present disclosure, any of the disclosed film treatment steps may be performed on an underlayer formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include such underlayers as the context indicates. Thus, for example, when a film / layer or partial film / layer is being deposited on a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.
[0014]
[0016] Embodiments of the present disclosure relate to methods of forming electronic devices using methods including conformal and selective doping processes. Some embodiments of the present disclosure advantageously provide methods of conformally doping semiconductor materials. Some embodiments of the present disclosure advantageously provide methods for preferentially doping semiconductor materials over oxide materials. Some embodiments of the present disclosure advantageously provide methods of doping non-line-of-sight surfaces.
[0015]
[0017] As used herein and in the appended claims, phrases such as "selectively depositing a film on one surface over another surface" mean that a first amount of film is deposited on the first surface and a second amount of film is deposited on the second surface, where the second amount of film is less than the first amount of film or no film is deposited on the second surface. The term "over" as used in this regard does not refer to the physical orientation of one surface relative to the top surface of the other surface, but rather the relationship of the thermodynamic or kinetic properties of a chemical reaction with one surface relative to the other surface. For example, selectively depositing a cobalt film on a copper surface over a dielectric surface means that the cobalt film deposits on the copper surface and less or not at all on the dielectric surface, or that the formation of a cobalt film on the copper surface is thermodynamically or kinetically favored compared to the formation of a cobalt film on the dielectric surface.
[0016]
[0018] Referring to Figure 1, some embodiments relate to a method 100 of forming an electronic device. Figure 1 illustrates a cross-sectional view of an exemplary substrate for processing by method 100. Substrate 10 includes a first surface 20 that includes a semiconductor material 25 and a second surface 30 that includes an oxide material 35. In some embodiments, semiconductor material 25 includes or consists essentially of silicon.
[0017]
[0019] In some embodiments, the semiconductor material 25 is a source / drain extension region of a transistor. In some embodiments, the electronic device comprises a 3D NAND device comprising a plurality of alternating first surfaces 10 and second surfaces 20.
[0018]
[0020] As used herein and in the appended claims, phrases such as "consisting essentially of" mean that the subject film or composition is greater than about 95%, 98%, 99%, or 99.5% of the recited active material. For gas compositions (e.g., reactive gases), the phrase "consisting essentially of" refers to the active ingredients of the composition without diluents, carriers, or inert gases.
[0019]
[0021] In some embodiments, the method 100 begins by selectively depositing a substantially conformal dopant film 40 on the first surface 20 over the second surface 30. As used herein, a "substantially conformal" film refers to a film that is about the same thickness throughout (e.g., on the top, middle, and bottom of the sidewalls, and on the bottom of the gap). A substantially conformal film varies in thickness by no more than about 10%, 5%, 2%, 1%, or 0.5%.
[0020]
[0022] In some embodiments, the dopant film 40 has a thickness in the range of about 2 to about 10 monolayers.
[0021]
[0023] In some embodiments, selectively depositing the conformal film 40 is performed using a non-line-of-sight deposition process. Thus, in some embodiments, the dopant film 40 is conformally deposited on all exposed first surfaces, regardless of their "visibility." As shown in FIG. 1, the underside of a diamond fin would typically be difficult to dope since these surfaces are not "visible" to the line-of-sight process.
[0022]
[0024] In some embodiments, selectively depositing the dopant film 40 comprises a pyrolysis process. In some embodiments, the pyrolysis process comprises exposing the first surface and the second surface to a dopant precursor at a temperature in a range from about 600° C. to about 900° C. or a temperature in a range from about 700° C. to about 800° C.
[0023]
[0025] In some embodiments, the dopant precursor is a boron precursor and the dopant film comprises boron. In some embodiments, the boron precursor is borane (BH 3 ), diborane (B 2 H 6 ), Triborane (B 3 H 5 , B 3 H 7 ), tetraborane (B 4 H 6 , B 4 H 10 ), pentaborane (B 5 H 9 , B 5 H 11 ) or cyclic triborane (B 3 H 6 ) or cyclic tetraborane (B 4 H 8 ) . Further examples of suitable boron precursors include BCl 3 or alkyl-substituted boron compounds having the formula BHxR3-x, where each R is an independently selected C1 to C6 alkyl group and x is 0, 1 or 2. Specific examples of alkyl-substituted boron compounds include trimethyl boron and triethyl boron.
[0024]
[0026] In some embodiments, the dopant precursor is a phosphorus precursor and the dopant film comprises phosphorus. In some embodiments, the phosphorus precursor is phosphine (PH 3 ) or essentially PH 3 In some embodiments, the dopant precursor is an arsenic precursor and the dopant film comprises arsenic. In some embodiments, the arsenic precursor is arsine (AsH 3 ) or essentially AsH 3 It consists of:
[0025]
[0027] In some embodiments, the method 100 continues by annealing the electronic device to drive the dopant atoms from the dopant film 40 into the semiconductor material 25 such that the semiconductor material 25 is conformally doped and is substantially free of dopant atoms driven into the oxide material 35. As shown in Figure 1, the conformal doping of the semiconductor material 25 is indicated by the bold lines on the doped surface. As used herein, "substantially free of dopant atoms" means that the material surface of interest contains less than 5%, 2%, 1%, or 0.5% dopant atoms.
[0026]
[0028] In some embodiments, annealing the electronic device includes one or more of a spike anneal, a laser anneal, a rapid thermal anneal, a millisecond anneal, or a combination thereof, hi some embodiments, the annealing is performed at a temperature in the range of about 1000°C to about 1300°C, or in the range of about 1150°C to about 1200°C.
[0027]
[0029] In some embodiments, the dopant atoms are driven into the semiconductor material 25 to a depth of about 1 nm or more, about 2 nm or more, or about 5 nm or more. In some embodiments, a conformally doped semiconductor material has a depth of about 1 nm or more at the surface of the semiconductor material. 20 Atomic B / cm 3 That's about 2 20 Atomic B / cm 3 More than or about 5 20 Atomic B / cm 3 The dopant concentration is equal to or greater than 100%.
[0028]
[0030] Referring to Figure 2, some embodiments relate to a method 200 of forming an electronic device. Figure 2 illustrates a cross-sectional view of an exemplary substrate for processing by the method 200. The substrate 210 includes a crystalline semiconductor material 220.
[0029]
[0031] In some embodiments, the method 200 begins by forming an amorphous boron layer 230 on a crystalline semiconductor material 220. Formation of the amorphous boron layer may be performed by any suitable process, including but not limited to the process outlined above for depositing the dopant film 40.
[0030]
[0032] In some embodiments, the method 200 continues by depositing an additional semiconductor material 240 on the amorphous boron layer 230. In some embodiments, the additional semiconductor material 240 is substantially amorphous.
[0031]
[0033] In some embodiments, the method 200 continues by annealing the substrate 210 to crystallize the additional semiconductor material 240 and melt the amorphous boron layer 230 to form the boron doped crystalline semiconductor material 250. In some embodiments, the annealing process includes laser annealing. In some embodiments, the boron doped crystalline semiconductor material 250 has the same stoichiometry as the crystalline semiconductor material 220. In some embodiments not shown, the method continues by forming a silicide from the boron doped crystalline semiconductor material 250.
[0032]
[0034] In some embodiments, the crystalline semiconductor material 220 and the additional semiconductor material are composed of the same material. In some implementations, the semiconductor material comprises silicon. In some embodiments, the semiconductor material comprises silicon and germanium.
[0033]
[0035] With reference to FIG. 3, further embodiments of the present disclosure are directed to a processing tool 900 for performing the methods described herein. FIG. 3 illustrates a system 900 that can be used to process substrates according to one or more embodiments of the present disclosure. The system 900 may be referred to as a cluster tool. The system 900 includes a central transfer station 910 with a robot 912 therein. The robot 912 is illustrated as a single blade robot, but one of ordinary skill in the art will recognize that other robot 912 configurations are within the scope of the disclosure. The robot 912 is configured to move one or more substrates between chambers coupled to the central transfer station 910.
[0034]
[0036] At least one pre-clean / buffer chamber 920 is coupled to the central transfer station 910. The pre-clean / buffer chamber 920 may include one or more of a heater, a radical source, or a plasma source. The pre-clean / buffer chamber 920 may be used as a holding area for individual semiconductor substrates or for cassettes of wafers for processing. The pre-clean / buffer chamber 920 may perform a pre-clean process or pre-heat the substrate for processing or simply be a staging area for a process sequence. In some embodiments, there are two pre-clean / buffer chambers 920 coupled to the central transfer station 910.
[0035]
[0037] 9, the pre-clean chamber 920 may function as a pass-through chamber between the factory interface 905 and the central transfer station 910. The factory interface 905 may include one or more robots 906 for moving substrates from a cassette to the pre-clean / buffer chamber 920. A robot 912 may then move the substrate from the pre-clean / buffer chamber 920 to other chambers in the system 900.
[0036]
[0038] A first processing chamber 930 may be coupled to the central transfer station 910. The first processing chamber 930 may be configured as an anisotropic etch chamber and may be fluidly connected to one or more reactive gas sources to provide one or more flows of reactive gas to the first processing chamber 930. Substrates may be moved to and from the deposition chamber 930 by a robot 912 passing through an isolation valve 914.
[0037]
[0039] Processing chambers 940 may also be coupled to the central transfer station 910. In some embodiments, the processing chambers 940 comprise isotropic etch chambers and are fluidly coupled to one or more reactive gas sources to provide a flow of reactive gas to the processing chambers 940 to perform an isotropic etch process. Substrates may be moved to and from the deposition chambers 940 by a robot 912 passing through an isolation valve 914.
[0038]
[0040] Processing chamber 945 may also be coupled to the central transfer station 910. In some embodiments, processing chamber 945 is the same type of processing chamber 940 configured to perform the same process as processing chamber 940. This configuration may be useful when the process to be performed in processing chamber 940 takes much longer than the process in processing chamber 930.
[0039]
[0041] In some embodiments, a processing chamber 960 is coupled to the central transfer station 910 and configured to function as a selective epitaxial growth chamber. The processing chamber 960 can be configured to perform one or more different epitaxial growth processes.
[0040]
[0042] In some embodiments, the anisotropic etching process is performed in the same processing chamber as the isotropic etching process. In such embodiments, processing chamber 930 and processing chamber 960 may be configured to perform an etching process on two substrates simultaneously, and processing chamber 940 and processing chamber 945 may be configured to perform a selective epitaxial growth process.
[0041]
[0043] In some embodiments, each of the processing chambers 930, 940, 945, and 960 is configured to perform a different portion of a processing method. For example, processing chamber 930 may be configured to perform an anisotropic etching process, processing chamber 940 may be configured to perform an isotropic etching process, processing chamber 945 may be configured as a metrology station or to perform a first selective epitaxial growth process, and processing chamber 960 may be configured to perform a second epitaxial growth process. One skilled in the art will appreciate that the number and arrangement of individual processing chambers on a tool may vary, and that the embodiment shown in FIG. 9 represents only one possible configuration.
[0042]
[0044] In some embodiments, the processing system 900 includes one or more metrology stations. For example, the metrology station can be located in the pre-clean / buffer chamber 920, in the central transfer station 910, or within any of the individual processing chambers. The metrology station can be located anywhere in the system 900 that allows the recessed distance to be measured without exposing the substrate to an oxidizing environment.
[0043]
[0045] At least one controller 950 is coupled to one or more of the central transfer station 910, the pre-clean / buffer chamber 920, the processing chambers 930, 940, 945, or 960. In some embodiments, there is more than one controller 950 coupled to individual chambers or stations, with a main control processor coupled to each of the separate processors to control the system 900. The controller 950 can be one of any form of general purpose computer processor, microcontroller, microprocessor, etc. that can be used in an industrial environment to control the various chambers and sub-processors.
[0044]
[0046] At least one controller 950 may include a processor 952, a memory 954 coupled to the processor 952, input / output devices 956 coupled to the processor 952, and support circuits 958 for communication between different electronic components. The memory 954 may include one or more of a temporary memory (e.g., random access memory) and a non-transitory memory (e.g., storage).
[0045]
[0047] The processor's memory 954 or computer readable medium may be one or more of readily available memory such as random access memory (RAM), read only memory (ROM), a floppy disk, a hard disk, or any other form of digital storage, local or remote. The memory 954 may hold a set of instructions operable by the processor 952 to control parameters and components of the system 900. The support circuits 958 are coupled to the processor 952 for supporting the processor in a conventional manner. The circuits may include, for example, cache, power supplies, clock circuits, input / output circuits, subsystems, etc.
[0046]
[0048] The processes may generally be stored in memory as software routines that, when executed by a processor, cause the process chamber to perform the processes of the present disclosure. The software routines may also be stored and / or executed by a second processor (not shown) located remotely from the hardware being controlled by the processor. Some or all of the methods of the present disclosure may also be performed in hardware. Thus, the processes may be implemented in software and executed using a computer system, in hardware, for example as an application specific integrated circuit or other type of hardware implementation, or as a combination of software and hardware. The software routines, when executed by a processor, transform a general purpose computer into a specific purpose computer (controller) that controls the chamber operation so that the processes are performed.
[0047]
[0049] In some embodiments, the controller 950 has one or more configurations for executing individual processes or sub-processes to perform a method. The controller 950 may be coupled to and configured to operate intermediate components to perform the functions of a method. For example, the controller 950 may be connected to and configured to control one or more of gas valves, actuators, motors, slit valves, vacuum controls, etc.
[0048]
[0050] The controller 950 in some embodiments has one or more configurations selected from: moving substrates on a robot between multiple processing chambers and a metrology station; loading substrates into and / or out of the system; depositing a dopant film; annealing a substrate; and depositing a semiconductor material.
[0049]
[0051] Throughout this specification, references to "one embodiment," "a particular embodiment," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of phrases such as "in one or more embodiments," "a particular embodiment," "in one embodiment," or "in an embodiment" in various places throughout this specification do not necessarily refer to the same embodiment of the present disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.
[0050]
[0052] Although the disclosure of this specification has been described with reference to specific embodiments, those skilled in the art will understand that the described embodiments are merely illustrative of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed method and apparatus without departing from the spirit and scope of the present disclosure. Thus, the present disclosure may include modifications and variations that come within the scope of the appended claims and their equivalents.
Claims
1. 1. A method of forming an electronic device, comprising: forming an amorphous dopant layer on the crystalline semiconductor material; depositing an additional substantially amorphous semiconductor material on the amorphous dopant layer; annealing the electronic device to crystallize the additional semiconductor material to form a doped crystalline semiconductor material; A method comprising:
2. The method of claim 1 , wherein the crystalline semiconductor material comprises silicon.
3. The method of claim 1 , wherein the crystalline semiconductor material further comprises germanium.
4. The method of claim 1 , wherein annealing the electronic device comprises laser annealing.
5. The method of claim 1 , wherein the amorphous dopant layer comprises boron.
6. 6. The method of claim 5, wherein forming the amorphous dopant layer comprises exposing the crystalline semiconductor material to a boron precursor comprising one or more of borane, diborane, triborane, tetraborane, or pentaborane.
7. 7. The method of claim 6, wherein the boron precursor comprises one or more of cyclic triborane or cyclic tetraborane.
8. The method of claim 6 , wherein the boron precursor comprises a boron halide.
9. The method of claim 6 , wherein the boron precursor comprises an alkyl boron.
10. The method of claim 1 , wherein the amorphous dopant layer comprises phosphorus.
11. The method of claim 1 , wherein the amorphous dopant layer comprises arsenic.
12. The method of claim 1 , wherein the amorphous dopant layer has a thickness in the range of about 2 to about 10 monolayers.
13. The method of claim 1 , wherein the crystalline semiconductor material comprises silicon.
14. 10. The method of claim 1, wherein the crystalline semiconductor material is a source / drain extension region of a transistor.