Semiconductor device and bonding method

Abstract

To provide a semiconductor device with low electrical resistance, which prevents a semiconductor device defect caused by thermal expansion differences by laminating an Fe-Ni alloy metal layer directly or indirectly on the front or back electrode of a semiconductor element.SOLUTION: An Fe-Ni alloy metal layer 5 is deposited directly or indirectly on the front surface electrode and / or the back surface electrode of a semiconductor chip 2, a semiconductor chip and a conductor 4 are connected via the Fe-Ni alloy metal layer 5, and if necessary, the Ni weight % of the Fe-Ni alloy metal layer 5 is in the range of 36% or more and 45% or less, and the thickness of the Fe-Ni alloy metal layer 5 is 2 μm or more and 20 μm or less.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and the like that suppresses the difference in thermal expansion of objects to be joined by using an Fe-Ni alloy metal layer. [Background technology]

[0002] The mounting of semiconductor elements is based on fixing to the board, conductive connection of electrode terminals, and insulating protection of them. Semiconductors generate heat and expand due to the current flowing through the circuit. On the other hand, the thermal expansion coefficient of metals and insulating resins connected to semiconductors is generally about one order of magnitude larger. For example, the coefficient of thermal expansion (CTE) of silicon material is about 2.6 ppm / K, while the thermal expansion coefficient of copper, which is widely used as a wiring material and conductive material for boards, is about 16.5 ppm / K. When a silicon semiconductor is connected to copper, which is a conductive wiring material, the amount of strain caused by the difference in thermal expansion increases in proportion to the temperature and the length of the connection. The stress on the semiconductor element and the stress on the connection material due to this amount of strain are the cause of damage to semiconductor devices caused by thermal fatigue due to temperature cycles, and various countermeasures have been taken at present, but a fundamental solution has not been achieved. In particular, power devices through which large currents flow pose a large challenge in terms of this thermal stress.

[0003] To address these issues, ceramic substrates with a thermal expansion coefficient close to that of Si semiconductors have been used as substrate materials, with copper wiring formed on the ceramic substrate. For example, in the early days of CPU elements, which are logic devices, ceramic packages were widely used, but the high cost became a major issue. Currently, organic substrates are used, and measures are taken such as suppressing the amount of distortion caused by the difference in thermal expansion with sealing resins and underfill agents, but the heat resistance temperature is limited. Therefore, alumina and silicon nitride substrates, which have a thermal expansion coefficient close to that of Si and SiC semiconductors, are still widely used in high-output power devices.

[0004] In compound semiconductors such as SiC semiconductor devices, which have seen remarkable progress in practical application in recent years, the elements themselves can operate at higher temperatures than Si semiconductors and are also capable of high power density, so there is a demand for mounting technology that can suppress the thermal expansion difference and enable operation at high temperatures.

[0005] Fe-Ni alloy metal (for example, 42 alloy with 42% Ni by weight) is known as a material with a low thermal expansion coefficient and close to that of semiconductors, and is sometimes used for leads and lead frames of electronic components. Lead frames are generally made of copper with excellent electrical conductivity, and are often connected to Si semiconductor chips and SiC semiconductor chips using solder or paste containing resin components. Therefore, in the case of solder connection, the thermal stress caused by the difference in thermal expansion between the Si semiconductor or SiC semiconductor and the copper wiring due to temperature cycles causes the solder to plastically deform, and fatigue failure occurs due to repetition of this process. In addition, in the case of connection using paste, peeling of the paste material or at the interface can be a problem. Therefore, as mentioned above, the lead frame itself has been formed from 42 alloy, which has a thermal expansion coefficient close to that of the Si semiconductor or SiC semiconductor, to address the above problems, but Fe-Ni alloy metal is only used in a limited manner due to its low electrical conductivity and thermal conductivity compared to copper, and due to the cost of materials.

[0006] As a technique using Fe-Ni alloy metal, for example, the techniques shown in Patent Documents 2 to 4 are disclosed. The technique shown in Patent Document 2 uses a copper second connection lead with a thermal expansion coefficient of (1 to 6) × 10 -6 By connecting the first connection lead made of an iron-nickel alloy of 0.1% to 1.0% by welding or the like and fixing the tip of the first connection lead to the electrode pad with solder, the thermal stress applied to the electrode pad is reduced, and the thermal stress generated by the difference in thermal expansion between the electrode pad and the first connection lead is reduced, thereby preventing cracks from occurring in the solder or in the silicon below the electrode pad.In addition, by making the length of the first connection lead less than 40% of the combined length of the first connection lead and the second connection lead, the electrical resistance can be kept low and the cost of the connection conductor can be reduced.

[0007] The technology disclosed in Patent Document 3 is a semiconductor lead frame comprising a base material made of an iron-nickel alloy and a plating layer having a crystal grain size of 1 micron or less that is plated onto the base material. This makes it possible to minimize the crystal grain size and suppress the growth of whiskers when plating the base material made of an iron-nickel alloy (alloy 42) with tin.

[0008] In the technology shown in Patent Document 4, the low-expansion member has a plate member made of an iron-based material, and iron-nickel layers are formed on the surface layers of the upper and lower parts of the plate member, respectively. Here, the plate member has a large thermal expansion coefficient, but the iron-nickel layers formed on the surface layers of the upper and lower parts of the plate member have a small thermal expansion coefficient, so that the thermal expansion coefficient of the entire low-expansion member can be kept small. In addition, the plate member has high thermal conductivity, and the iron-nickel layers are formed thin relative to this plate member, so that the low-expansion member has high thermal conductivity in its thickness direction. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] International Publication No. 2015 / 053356 [Patent Document 2] JP 2012-38983 A [Patent Document 3] JP 2006-108666 A [Patent Document 4] JP 2004-103700 A Summary of the Invention [Problem to be solved by the invention]

[0010] However, the technologies shown in Patent Documents 1 and 2 are not sufficient as measures against defects caused by the difference in thermal expansion between a semiconductor and a conductor. In particular, the technology shown in Patent Document 2 relieves stress using a lead made of an Fe-Ni alloy metal, so even if the length of the first connection lead is made less than 40% of the combined length of the first connection lead and the second connection lead, it has the problem that the electrical conductivity and thermal conductivity are lower than those of copper, and it is not a technology that can be adequately addressed in terms of cost.

[0011] Furthermore, even if the techniques disclosed in Patent Documents 3 and 4 are used, the above problems cannot be solved.

[0012] The present invention has been made to solve the above problems, and aims to provide a semiconductor device that prevents defects in semiconductor elements caused by differences in thermal expansion by directly or indirectly laminating an Fe-Ni alloy metal layer on the front or back electrodes of the semiconductor element, while also reducing electrical resistance. [Means for solving the problem]

[0013] The semiconductor device of the present invention has an Fe-Ni alloy metal layer directly or indirectly deposited on a front or back electrode of a semiconductor element, and the semiconductor element and a conductor are connected via the Fe-Ni alloy metal layer.

[0014] In this manner, in the semiconductor device of the present invention, an Fe-Ni alloy metal layer is directly or indirectly applied to the front or back electrode of the semiconductor element, and the semiconductor element and the conductor are connected via the Fe-Ni alloy metal layer, thereby providing the effect of mitigating stress caused by the difference in thermal expansion between the semiconductor element and the conductor, thereby preventing damage to the semiconductor element. [Brief description of the drawings]

[0015] [Figure 1] FIG. 1 is a diagram showing the composition dependence of the linear thermal expansion coefficient of an Fe—Ni alloy. [Diagram 2]1A and 1B are diagrams showing a structure in which a lead frame is used in a semiconductor device; [Diagram 3] 1A and 1B are diagrams showing a bonding portion of a semiconductor chip in wire bonding; [Figure 4] 3 is a diagram showing a structure when flip-chip connection is performed in the semiconductor device according to the first embodiment. FIG. [Diagram 5] 3A to 3C are diagrams showing a flip-chip connection structure when the semiconductor device according to the first embodiment has Cu pillars. [Figure 6] 1 is a diagram showing a structure of a semiconductor device according to a first embodiment as a power device. [Figure 7] 1 is a diagram showing an example of a lead frame type power device structure in a semiconductor device according to a first embodiment. [Figure 8] 4 is a diagram showing an example of a power device structure when a Cu clip is used in the semiconductor device according to the first embodiment. FIG. [Figure 9] 2 is a diagram showing an example of an NMPB structure in the semiconductor device according to the first embodiment. FIG. [Figure 10] FIG. 4 is a diagram showing the measurement results of the linear expansion coefficient as a function of the heating temperature after plating of the Fe—Ni alloy metal layer in the semiconductor device according to the first embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Hereinafter, an embodiment of the present invention will be described. In addition, the same elements are denoted by the same reference numerals throughout the embodiment.

[0017] (First embodiment of the present invention) The semiconductor device according to the present embodiment will be described with reference to Figures 1 to 9. The semiconductor device according to the present embodiment has a connection structure in which an Fe-Ni alloy metal layer is directly or indirectly laminated on a front electrode or a back electrode of a semiconductor chip, and the semiconductor chip and a conductor are connected via the Fe-Ni alloy metal layer. In each of the following embodiments, the Fe-Ni alloy metal layer is a metal layer that contains at least an Fe-Ni alloy, and may contain a metal other than Fe-Ni.

[0018] The thermal expansion coefficient of Fe-Ni alloy metal can be controlled to a few ppm, which is close to that of Si semiconductors and SiC semiconductors. FIG. 1 is a diagram showing the composition dependency of the linear thermal expansion coefficient of Fe-Ni alloy. The horizontal axis shows the Ni composition, and the vertical axis shows the thermal expansion coefficient. As shown in the graph, the Ni composition has the smallest thermal expansion coefficient, and the Ni composition used conventionally as a lead frame material is 42%. In the semiconductor device according to this embodiment, the graph in FIG. 1 shows that an Ni weight percent concentration in the range of 30% to 45% is effective in suppressing the thermal expansion coefficient of the conductor.

[0019] The structure of the semiconductor device according to this embodiment will be specifically described below. Fig. 2 is a diagram showing a structure when a lead frame is used in a semiconductor device. Fig. 2(A) is a diagram showing a general semiconductor mounting structure when a lead frame is used, Fig. 2(B) is a first diagram showing a joint structure between a semiconductor element and a conductor when a lead frame is used in this embodiment, Fig. 2(C) is a second diagram showing a joint structure between a semiconductor element and a conductor when a lead frame is used in this embodiment, and Fig. 2(D) is a third diagram showing a joint structure between a semiconductor element and a conductor when a lead frame is used in this embodiment.

[0020] In FIG. 2, a Si semiconductor or a SiC semiconductor (hereinafter referred to as a semiconductor chip 2) is die-bonded to a die pad (island) 3a of a lead frame 3. The semiconductor chip 2 and the lead 3b of the lead frame 3 are connected by wires 8 and sealed with resin 6. In general, the semiconductor chip 2 is die-bonded to the die pad 3a with a paste containing solder 7 or a resin component, and the lead frame 3 is often made of copper, which has excellent electrical conductivity. In this case, as described above, the solder 7 is plastically deformed due to thermal stress caused by the difference in thermal expansion between the semiconductor chip 2 (Si or SiC) and the lead frame 3 (Cu) due to temperature cycles, and the solder 7 is broken by fatigue due to repetition of this, or peeled off at the paste material or its interface. Therefore, if the lead frame 3 itself is made of Fe-42%Ni material, which has a thermal expansion coefficient close to that of a semiconductor, there are problems with electrical conductivity and thermal conductivity as well as material costs, and the use of the solder 7 is limited.

[0021] The problem in the bonding between the semiconductor chip 2 and the conductor 4 (corresponding to the die pad 3a in FIG. 2), which is copper, is a problem in the interface between the semiconductor chip 2 and the conductor 4. Therefore, in the semiconductor device 1 according to this embodiment, it is useful to coat the surface of the die pad 3a, which is copper, with an Fe-Ni alloy metal layer 5 having a suppressed thermal expansion coefficient, as shown in FIG. 2(B). That is, the die pad 3a is coated with and stacked with the Fe-Ni alloy metal layer 5, and the Ti / Ni / Au film 2a of the semiconductor chip 2 is connected via the solder 7. In this way, by forming a layer (Fe-Ni alloy metal layer 5) of an Fe-Ni alloy composition having a thermal expansion coefficient close to that of the semiconductor chip 2 on the die pad 3a, it is possible to reduce the stress load on the solder 7 due to the thermal expansion of copper.

[0022] 2(C) shows a structure in which an Fe-Ni alloy metal layer 5, which has a relatively high strength and a thermal expansion coefficient close to that of a Si semiconductor or a SiC semiconductor, is deposited on the back surface (lower surface) of the semiconductor chip 2. In this example, the Fe-Ni alloy metal layer 5 is deposited and laminated on the surface of the Ti / Ni / Au film 2a of the semiconductor chip 2, and is joined to the conductor 4 via solder 7.

[0023] 2(D) shows a structure in which an Fe-Ni alloy metal layer 5 is applied to the rear surface (lower surface) of the semiconductor chip 2, and the Fe-Ni alloy metal layer 5 is formed as a bonding material. Here, the semiconductor chip 2 and the conductor 4 are bonded to each other by the Fe-Ni alloy metal layer 5 using nano-sized Ni particles as a binder on the surface of the Ti / Ni / Au film 2a of the semiconductor chip 2.

[0024] In addition, in Figures 2(B) to 2(D), the Ni weight percentage concentration of the Fe-Ni alloy metal layer 5 can be expected to be effective in the range of about 30% to 45%, and the thickness is effective at 2 μm or more, and preferably 5 μm or more.

[0025] In addition, in recent years, development of a joining technology that can handle high-temperature operation has been progressing in place of the joining by solder 7 as shown in Figs. 2(B) and (C). For example, in the case of Ag sintered material, Ni sintered material, or nickel micro-plated joining, which are die bonding materials with high adhesiveness and strength, there is no breakage in the connection material or peeling at the interface, but the stress on the semiconductor chip 2 increases, and defects such as current leakage due to cracks in the semiconductor chip 2 may be observed. As a countermeasure for such a case, in this embodiment, as shown in Fig. 2(D), the Fe-Ni alloy metal layer 5 is mixed with nano-sized Ni particles as a sintered material, thereby enabling strong joining with stress on the semiconductor chip 2 being relaxed. At this time, the Fe-Ni alloy metal layer 5 may further contain micro-sized Al particles. The inclusion of Al particles makes it possible to relax thermal stress due to the thermal expansion difference caused by Al (see, for example, JP 2020-35983 A).

[0026] When nano-sized Ni particles or micro-sized Al particles are included in the Fe-Ni alloy metal layer 5, the main component of the Fe-Ni alloy metal layer 5 is Fe-Ni alloy particles, but the linear expansion coefficient of the mixture changes according to the composition ratio of the mixture and the linear expansion coefficient shown in FIG. 1. That is, the mixture of Ni particles has a thermal expansion coefficient of Ni:100%, and the mixture of Al particles has a thermal expansion coefficient of Al:100%, so the linear expansion coefficient is determined by the Fe-Ni thermal expansion coefficient and their volume ratio. Therefore, it is desirable to adjust the composition ratio so that the linear expansion coefficient of the Fe-Ni alloy metal layer 5 is close to the thermal expansion coefficient of Si or SiC semiconductor. The nano-sized Ni particles are desirably 10 nm to 200 nm in size. In addition, nano-sized Ag particles or Cu particles having the same size and volume ratio may be used as the nano-sized particles other than Ni. Furthermore, the effect of the nano-sized Ni particles as a sintering material is desirably 15% or more in volume ratio, but considering the effect of the thermal expansion coefficient, it is desirably in the range of 60% or less.

[0027] Furthermore, the Fe-Ni alloy metal layer 5 can be deposited by methods such as cladding, physical vapor deposition, plating, thermal spraying, sintering, etc. When depositing the Fe-Ni alloy metal layer 5 on the conductor 4 as shown in Fig. 2(B), any of the above methods may be used. When depositing on the back side of the semiconductor chip 2 as shown in Fig. 2(C), physical vapor deposition or plating is used. In the case of Fig. 2(D), deposition and bonding are performed by sintering nano-sized Ni.

[0028] In particular, when the Fe-Ni alloy metal layer 5 is deposited by plating, it may be necessary to optimize the composition and rearrange the atoms in order to realize the thermal expansion coefficient of Fe-Ni as shown in FIG. 1. Specifically, in order to form the Fe-Ni alloy metal layer 5 of a desired composition by plating, it is desirable to perform a heat treatment at about 200°C to 350°C after the plating process. By performing the above-mentioned heat treatment after the plating process, a diffusion layer (for example, a layer in which the metals diffuse to each other at the interface of 0.01 μm=10 nm or more) is formed, and strong bonding can be realized. In addition, by performing the heat treatment after the plating process, a part of the Fe-Ni alloy metal layer is recrystallized, and strong bonding can be realized. That is, although the crystal after the plating process shows anisotropy due to the crystal growth direction, the heat treatment generates new crystal grains with different crystal orientations, and the Fe-Ni alloy metal layer 5 and the conductor 4 are bonded extremely strongly.

[0029] In addition, when the Fe-Ni alloy metal layer 5 is applied to the back side of the semiconductor chip 2 as shown in Fig. 2(C), it is preferable to apply the layer by plating before dicing the wafer. In other words, by performing plating processing on a wafer-by-wafer basis and then dicing, it is possible to very efficiently generate the semiconductor chip 2 having the Fe-Ni alloy metal layer 5 formed on the back side.

[0030] 2, the surface (upper surface side) of the semiconductor chip 2 is wire-bonded to the electrode metal to connect the surface electrode and the lead 3b, but no stress is applied between the wire 8 and the lead 3b because the wire 8 is flexible. On the other hand, although it is a small area, the difference in the thermal expansion coefficient between the material of the wire 8 and the semiconductor chip 2 may cause damage due to thermal stress to the semiconductor chip 2 in the wire-bonded portion.

[0031] The material of the wire 8 is generally aluminum, gold, copper, etc. In the case of ball bonding, the wire 8 material is melted once, and the area is relatively small, so there are few cases where thermal stress becomes a problem. However, in the case of power devices, wedge bonding is performed, so the diameter of the wire 8 is thick, about 50 μmφ to 500 μmφ, and it is work-hardened, so that plastic deformation of the material of the wire 8 does not progress during the thermal cycle, and stress is applied to the semiconductor chip 2 side. FIG. 3 is a diagram showing a bonding portion of a semiconductor chip in wire bonding. FIG. 3(A) shows a case where conventional wedge bonding is performed on an Al electrode 2b, and FIG. 3(B) shows a case where wedge bonding is performed on an Al / Fe-Ni / Au electrode in this embodiment. As described above, in the case of the conventional FIG. 3(A), plastic deformation of the material of the wire 8 does not progress during the thermal cycle, and stress is applied to the semiconductor chip 2 side. In contrast, in the present embodiment, as shown in FIG. 3(B), the surface of the Al electrode 2b of the semiconductor chip 2 is coated with an Fe-Ni alloy metal layer 5 having a thermal expansion coefficient lower than that of the material of the wire 8, thereby making it possible to solve the above-mentioned problem.

[0032] In this case, the composition of the Fe-Ni alloy metal layer 5 is set to a Ni weight percent concentration in the range of about 30% to 45%, and the thickness is set to 2 μm or more, preferably 5 μm to 20 μm. The Fe-Ni alloy metal layer 5 can be deposited by physical vapor deposition or plating. Usually, the electrode material is generally aluminum having a thickness of about 1 to 4 μm, but when the Fe-Ni alloy metal cannot be directly deposited, a pretreatment such as Zn substitution treatment (zincate) or Ni plating may be performed. Furthermore, as shown in FIG. 3(B), it is preferable to prevent oxidation of the Fe-Ni alloy metal layer 5 by depositing a plating layer 2c (e.g., Au, Ag, Al, etc.) on the layer of the Fe-Ni alloy metal layer 5.

[0033] Next, the flip chip structure will be described. FIG. 4 is a diagram showing a structure in which flip chip connection is performed in the semiconductor device according to this embodiment. FIG. 4 shows a flip chip structure in semiconductor mounting, in which the circuit surface of the semiconductor chip 2 is connected to the substrate electrode 4a (e.g., Cu electrode) of the substrate 9 in such a manner that it faces the substrate electrode 4a. The substrate electrode 4a and the semiconductor chip 2 are connected via a solder ball (solder 7), and are joined by melting the solder 7. Conventionally, a ceramic substrate has been used as the substrate 9 in order to reduce the thermal expansion difference with the semiconductor chip 2, but currently, organic substrates with a large thermal expansion coefficient are mainstream. This has been put into practical use by fixing the semiconductor chip 2 and the substrate 9 with an underfill, which is an insulating resin, to suppress deformation due to the thermal expansion difference, but when the semiconductor chip 2 is large in size or has high output, deformation due to the thermal expansion difference cannot be ignored.

[0034] Therefore, by forming a structure as shown in FIG. 4, it is possible to suppress deformation due to the difference in thermal expansion. In the case of FIG. 4(A), the Fe-Ni alloy metal layer 5 is attached to the connection surface of the semiconductor chip 2, and is connected to the conductor 4 (substrate electrode 4a of the substrate 9) via solder 7. On the other hand, in the case of FIG. 4(B), the Fe-Ni alloy metal layer 5 is attached to the surface of the conductor 4 (substrate electrode 4a of the substrate 9), and is connected to the connection surface of the semiconductor chip 2 via solder 7. In either case, a heat sink 21 for dissipating heat is disposed above the semiconductor chip 2. In FIG. 4, the Fe-Ni alloy metal layer 5 is formed between the semiconductor chip 2 and the substrate electrode 4a, so that it is possible to relieve stress caused by the difference in thermal expansion. In particular, the structure as shown in FIG. 4 is extremely effective when the electrode area is large, such as in a power device. In the case of the structure shown in FIG. 4(A), the Fe-Ni alloy metal layer 5 is formed by physical vapor deposition or plating, and in the case of the structure shown in FIG. 4(B), it is possible to use techniques such as cladding, physical vapor deposition, plating, spraying, and sintering.

[0035] 5 is a diagram showing a structure of flip-chip connection when a Cu pillar is included in the semiconductor device according to this embodiment. In FIG. 5, a Cu pillar 10, which is a conductor 4, is formed on the electrode side of the semiconductor chip 2, and is connected to the substrate electrode 4a by solder 7. An Fe-Ni alloy metal layer 5 is formed between the semiconductor chip 2 and the Cu pillar 10, which reduces the thermal expansion difference between the Cu pillar 10 and the semiconductor chip 2, and similarly to the above, it is possible to reduce the stress caused by the thermal expansion difference. The Fe-Ni alloy metal layer 5 in FIG. 5 is formed by physical vapor deposition or plating.

[0036] Next, the structure of the power device mounting will be described. FIG. 6 is a diagram showing the structure of the power device of the semiconductor device according to this embodiment. In mounting the power device, in addition to high output, a heat dissipation structure is important. Ceramics with a relatively small thermal expansion coefficient are often used as the insulating substrate 61 shown in FIG. 6, but the thermal expansion difference between the copper wiring (wiring 62 and heat dissipation substrate 63) that carries a large current and the semiconductor chip 2 may become a problem. For this reason, as shown in FIG. 6, an Fe-Ni alloy metal layer 5 is attached to the back side of the semiconductor chip 2. This makes it possible to relieve the stress caused by the thermal expansion difference, as in the past.

[0037] As shown in Fig. 6, it is desirable to also apply an Fe-Ni alloy metal layer 5 to the bonding portion of the semiconductor chip 2 in the wire bonding as described in Fig. 3. The Fe-Ni alloy metal layer 5 in Fig. 6 is formed by physical vapor deposition or plating.

[0038] Fig. 7 is a diagram showing an example of a lead connection type power device structure. The structure shown in Fig. 7 uses leads 3b, and the leads 3b, which are expected to have heat dissipation properties, are directly bonded to the front surface side of the semiconductor chip 2. Fe-Ni alloy metal layers 5 are formed between the copper wiring (leads 3b and heat dissipation substrate 63) on the front and back surfaces of the semiconductor chip 2, and are bonded to each other via solder 7. Fig. 8 is a diagram showing an example of a double-sided heat dissipation power device structure. In these structures, the electrodes on the front surface of the semiconductor chip 2 are directly bonded to the copper wiring (wiring 62, etc.), and the difference in thermal expansion coefficient becomes a problem.

[0039] As shown in Figures 7 and 8, the stress on the semiconductor chip 2 can be alleviated by inserting an Fe-Ni alloy metal layer 5 between the semiconductor chip 2 and the copper wiring. In particular, in the case of a double-sided heat dissipation mounting structure as shown in Figure 8, it is desirable to form an Fe-Ni alloy metal layer 5 on the front and back electrodes of the semiconductor chip 2. The Fe-Ni alloy metal layer 5 in Figures 7 and 8 is formed by physical vapor deposition or plating.

[0040] Next, the structure of nickel micro plating bonding (NMPB) developed by the inventors will be described. In the case of power devices, as shown in Figs. 6 to 8, connection is often made by solder 7, or Ag sintered materials are often used for high heat resistant devices. However, the solder 7 has a problem of low melting point, and the Ag sintered materials have problems such as Ag migration and high cost. Therefore, the inventors have developed a nickel micro plating bonding technology that connects the semiconductor chip 2 to the lead 3b or the substrate 9 (copper substrate) by plating with Ni through the edge (see, for example, Patent Document 1, International Publication No. 2017 / 154893, etc.). In this technology, the semiconductor chip 2 and the lead 3a are in contact or close to each other in a dot-like or linear manner at the edge portion of the tapered lead 3a, and the distance between the semiconductor chip 2 and the lead 3a gradually increases from the contact or close point toward the outside, and the semiconductor chip 2 and the lead 3a are connected by plating in a state where a plating solution of Ni is filled in the gap. The bond formed by the Ni plating is very strong and will not break due to thermal stress, but thermal stress on the semiconductor chip 2 may cause leakage on the semiconductor chip 2 side.

[0041] FIG. 9 is a diagram showing an example of the NMPB structure in the semiconductor device according to the present embodiment, in which FIG. 9(A) shows a structure in which plating bonding is performed with Ni, and FIG. 9(B) shows a structure in which plating bonding is performed with Fe-Ni alloy metal. In the case of FIG. 9(A), an Fe-Ni alloy metal layer 5 is formed on the connection surface where the semiconductor chip 2 is connected to the lead 3b, and the Fe-Ni alloy metal layer 5 and the edge of the lead 3b are in contact with each other and bonded with Ni plating 91. In this case, the Ni plating 91 may be formed by plating with an Fe-Ni alloy instead of Ni. The Fe-Ni alloy metal layer 5 here is formed by physical vapor deposition or plating. In the case of FIG. 9(B), the Fe-Ni alloy metal layer 5 is formed by plating with an Fe-Ni alloy in a state where the electrode of the semiconductor chip 2 and the edge of the lead 3b are in contact with each other, and the semiconductor chip 2 and the lead 3b are bonded via the edge. In either structure, the Fe-Ni alloy metal layer 5 is formed between the semiconductor chip 2 and the copper electrode, thereby alleviating the stress on the semiconductor chip 2 caused by the thermal expansion difference.

[0042] 9, in order to optimize the composition and rearrange atoms when Ni plating or Fe-Ni alloy plating is performed, it is desirable to perform heat treatment at about 200°C to 350°C after plating, as described above. This forms a diffusion layer at the interface between the plating metal and the conductor 4, making it possible to realize strong bonding. In addition, by performing heat treatment after plating, a part of the Fe-Ni alloy metal layer is recrystallized, making it possible to realize strong bonding.

[0043] A strong bond can be formed at the interface between the plated metal and the conductor 4 due to the diffusion layer and recrystallization. In addition, a similar phenomenon occurs at the interface where the growth surfaces of the opposing platings collide (interface 92 shown in Figure 9), making the plating bond even stronger.

[0044] Here, the effect of heat treatment after plating of the Fe-Ni alloy metal layer 5 conducted by the inventors is shown in FIG. 10. Here, the current density during plating was 2 A / dm 2 Or 4A / dm2 Then, a plating process was performed so that the composition of the Fe-Ni alloy metal layer 5 became Fe-(33 to 44)Ni (wt%), and then a heat treatment was performed at 0°C (unheated), 220°C, 250°C, 300°C, 350°C, 400°C, and 450°C. The linear expansion coefficient of the Fe-Ni alloy metal layer 5 heat-treated at each temperature was measured with a temperature change from 50°C to 250°C.

[0045] As shown in the measurement results in Fig. 10, it can be seen that the linear expansion coefficient changes depending on the heat treatment temperature. In other words, it is possible to adjust the linear expansion coefficient by heat treatment after plating depending on the usage environment and application of the semiconductor device 1. Specifically, by performing heat treatment at a temperature equal to or higher than the temperature at which the semiconductor device 1 is used, it is possible to prevent at least the linear expansion coefficient from changing significantly depending on the temperature, and the semiconductor device 1 can be used at a constant linear expansion coefficient.

[0046] As described above, in the semiconductor device of this embodiment, the Fe-Ni alloy metal layer 5 is directly or indirectly adhered to the front or back electrode of the semiconductor chip 2, and the semiconductor chip and the conductor are connected via the Fe-Ni alloy metal layer 5, thereby alleviating the stress caused by the difference in thermal expansion between the semiconductor chip 2 and the conductor, and preventing damage to the semiconductor chip 2.

[0047] Furthermore, by setting the Ni weight percentage of the Fe-Ni alloy metal layer in the range of 30% or more and 45% or less, and / or by setting the thickness of the Fe-Ni alloy metal layer to 2 μm or more and 20 μm or less, it is possible to minimize stress while keeping the thermal expansion coefficient as small as possible, thereby preventing damage to the semiconductor chip 2.

[0048] Furthermore, by forming the Fe-Ni alloy metal layer 5 by plating, it is possible to form it directly on the semiconductor chip 2, and it is possible to make it thicker than by sputtering, etc., so that it can be formed thick enough to withstand thermal expansion. [Explanation of symbols]

[0049] 1 Semiconductor device 2. Semiconductor chips 2a Ti / Ni / Au film 2b Al electrode 2c plating layer 3 Lead Frame 3a Die pad 3b Lead 4 Conductors 4a Substrate electrode 5 Fe-Ni alloy metal layer 6. Resin 7 Solder 8 Wire 9 Substrate 10 Cu pillar 21 Heat sink 61 Insulating substrate 62 Copper wiring 63 Heat dissipation board 91 Ni plating 92 Interface

Claims

1. an Fe—Ni alloy metal layer is formed directly or indirectly on a front electrode and / or a back electrode of a semiconductor element by plating, and the semiconductor element and a conductor are connected via the Fe—Ni alloy metal layer; A semiconductor device characterized in that the electrode surface, which is the front or back electrode of the semiconductor element, and the conductor are in contact or close proximity at the bonding surface in a point-like or linear manner, the distance between the electrode surface and the conductor at the bonding surface gradually increases outward from the point of contact or close proximity, and an Fe-Ni alloy metal is filled between the electrode surface and the conductor to form an Fe-Ni alloy metal layer.

2. The semiconductor element and the conductor are connected directly or indirectly to the front electrode and / or the back electrode of the semiconductor element via an Fe-Ni alloy metal layer formed by plating, The semiconductor device is characterized in that the Fe-Ni alloy metal layer is formed by heat-treating an Fe-Ni plating metal, and a diffusion layer is formed at the interface between the conductor and the Fe-Ni plating metal, or at the interface between the front electrode and / or back electrode of the semiconductor element and the Fe-Ni plating metal, or a part of the Fe-Ni plating metal is recrystallized.

3. An Fe-Ni alloy metal layer is directly or indirectly deposited on a front electrode and / or a back electrode of a semiconductor element, and the semiconductor element and a conductor are connected via the Fe-Ni alloy metal layer; The semiconductor device is characterized in that the Fe—Ni alloy metal layer is formed by sintering a powder of nano-sized metal particles and Fe—Ni alloy particles.

4. 4. The semiconductor device according to claim 3, The semiconductor device is characterized in that the powder contains micro-sized Al particles.

5. A joining method characterized by bringing an electrode surface, which is a front or back electrode of a semiconductor element, into contact with or close to a conductor in a point or line at the joining surface, filling the gap where the distance between the electrode surface and the conductor at the joining surface gradually increases outward from the point of contact or close proximity with Fe-Ni plating metal to form a plating bond, and then heat-treating the area.

6. A bonding material formed from a powder containing nano-sized metal particles and Fe-Ni alloy particles, and formed as an Fe-Ni alloy metal layer that is directly or indirectly deposited on the front electrode and / or back electrode of a semiconductor element.

7. A method for forming an Fe-Ni alloy metal layer by plating directly or indirectly onto a surface electrode and / or a back electrode of a semiconductor element, or onto a conductor electrically connected to the surface electrode and / or the back electrode of the semiconductor element, and then performing heat treatment at 220°C to 450°C.

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