Voltage regulator

Abstract

To provide a voltage regulator capable of suppressing current consumption in an unregulated condition with a simple circuit configuration held intact.SOLUTION: A voltage regulator 1A includes: an output transistor that outputs an output voltage in response to a control voltage; an error amplification circuit 25 that outputs an amplified signal obtained by amplifying a difference between a voltage based on the output voltage and a reference voltage; a source ground amplification circuit 20A that inputs the amplified signal and outputs the control voltage to the output transistor; and an unregulated condition detection circuit 30 that outputs a detection signal including a signal level corresponding to whether or not an unregulated condition is established, to the source ground amplification circuit. The source ground amplification circuit has a current control circuit 26A including a path 15 in a conducting state in the unregulated condition and a path 16 in an open state in the unregulated condition, which are plural parallel paths connecting a gate 24g serving as a control terminal of the output transistor and a GND terminal 12 serving as a first power terminal.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a voltage regulator. [Background technology]

[0002] A low dropout regulator (hereinafter referred to as "LDO"), which is an example of a voltage regulator, is a direct current (DC) linear voltage regulator that adjusts the output voltage VOUT based on the power supply voltage VDD. When the power supply voltage VDD is greater than a reference voltage VREF determined by the output voltage VOUT (hereinafter referred to as the "regulated state"), the LDO regulates the power supply voltage VDD to generate the output voltage VOUT. On the other hand, when the power supply voltage VDD is smaller than the reference voltage VREF (hereinafter referred to as the "unregulated state"), the current consumption of the LDO can increase significantly compared to when it is in the regulated state. This increase in current consumption can be tens, hundreds, or even thousands of times.

[0003] As a measure against the increase in current consumption in an unregulated state, an LDO equipped with a minimum dropout voltage circuit has been disclosed (see, for example, Patent Document 1). The minimum dropout voltage circuit prevents the LDO from going into an unregulated state by operating so that the reference voltage VREF is maintained at a value obtained by subtracting the minimum dropout voltage VMIN from the power supply voltage VDD. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US Patent Application Publication No. 2020 / 0278710 Summary of the Invention [Problem to be solved by the invention]

[0005] However, the conventional voltage regulator disclosed in Patent Document 1 has a huge and complicated circuit scale.

[0006] The present invention has been made in consideration of the above-mentioned circumstances, and has an object to provide a voltage regulator capable of suppressing current consumption in a non-regulated state while maintaining a simple circuit configuration. [Means for solving the problem]

[0007] The voltage regulator according to the present application comprises an output transistor having a control terminal for receiving a control voltage and outputting an output voltage, an error amplifier circuit for outputting an amplified signal obtained by amplifying a difference between a voltage based on the output voltage and a reference voltage, a source-grounded amplifier circuit for receiving the amplified signal and outputting the control voltage to the control terminal, and an unregulated state detection circuit for outputting a detection signal including a signal level corresponding to a regulated state or an unregulated state, respectively, to the source-grounded amplifier circuit, wherein the source-grounded amplifier circuit comprises a current control circuit having a plurality of parallel paths between the control terminal of the output transistor and a first power supply terminal supplying a first power supply voltage, the paths including a first path in a conductive state through which a current flows in the unregulated state, and a second path switched to the open state in the unregulated state. Effect of the Invention

[0008] According to the voltage regulator of the present application, it is possible to suppress current consumption in a non-regulated state while maintaining a simple circuit configuration. [Brief description of the drawings]

[0009] [Figure 1] 1 is a circuit diagram showing a configuration of a voltage regulator according to a first embodiment of the present invention. [Diagram 2] 1 is a circuit diagram illustrating an example of a non-regulation state detection circuit included in a voltage regulator according to an embodiment. [Diagram 3]FIG. 5 is a circuit diagram showing a configuration of a voltage regulator according to a second embodiment of the present invention. [Figure 4] 10 is a circuit diagram illustrating a configuration example of a switching circuit included in a voltage regulator according to a second embodiment. FIG. [Diagram 5] 4 is a circuit diagram showing a modification of the current control circuit included in the voltage regulator according to the first embodiment. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A voltage regulator according to an embodiment of the present invention will now be described with reference to the drawings.

[0011] [First embodiment] FIG. 1 is a circuit diagram showing a configuration of a voltage regulator 1A, which is an example of a voltage regulator according to a first embodiment of the present invention.

[0012] The voltage regulator 1A includes a grounded-source amplifier circuit 20A, an error amplifier circuit 25, a PMOS transistor 24 which is an example of a P-type field effect transistor, and a non-regulation state detection circuit 30. The voltage regulator 1A also includes a voltage divider circuit 50 which outputs a voltage (divided voltage) obtained by dividing the voltage of an output terminal 22 of the voltage regulator 1A relative to the voltage (hereinafter referred to as "power supply voltage GND") of a ground terminal (hereinafter referred to as "GND terminal") 12 serving as a first power supply terminal.

[0013] The grounded-source amplifier circuit 20A includes a current-voltage conversion circuit (hereinafter referred to as an "I / V conversion circuit") 21 and a current control circuit 26A. The error amplifier circuit 25 has a non-inverting input terminal (+) connected to the output terminal of the reference voltage circuit 23, an inverting input terminal (-) connected to the output terminal of the voltage divider circuit 50, and an output terminal. The PMOS transistor 24 serving as an output transistor includes a source connected to a VDD terminal 11 serving as a second power supply terminal, a drain connected to the output terminal 22, and a gate 24g serving as a control terminal connected to the current control circuit 26A.

[0014] The I / V conversion circuit 21 has, for example, a resistor including a PMOS transistor 211 and a resistor 212, one end of which is connected to a VDD terminal 11 that supplies a power supply voltage VDD as a second power supply voltage, and the other end of which is connected to a current control circuit 26A. The resistor illustrated in FIG. 1 is configured such that the drain of the PMOS transistor 211 is connected to one end of the resistor 212, and the gate of the PMOS transistor 211 is connected to the other end of the resistor 212. One end of the resistor is the source of the PMOS transistor 211, and is one end of the I / V conversion circuit 21. The other end of the resistor is the gate of the PMOS transistor 211 and the other end of the resistor 212, and is the other end of the I / V conversion circuit 21.

[0015] The current control circuit 26A has a plurality of parallel paths 15, 16 (16_1, ..., 16_n) (n is a natural number) connecting between the gate 24g and the GND terminal 12. Here, the path 15 as a first path has a current control transistor 27, and is at least one path that maintains a conductive state through which a current flows when the voltage regulator 1A is in a non-regulated state. The current control transistor 27 includes, for example, an NMOS transistor 27_1, which is an example of an N-type field effect transistor.

[0016] The path 16 as the second path is a path that connects between the gate 24g and the GND terminal 12 in a switchable manner between an open state and a closed state, and is configured to include n parallel paths 16_1, ..., 16_n. Each of the paths 16_1, ..., 16_n has NMOS transistors 28_1, ..., 28_n as the current control transistors 28 and NMOS transistors 29_1, ..., 29_n as the pass transistors 29, respectively, and is an n number of paths that are in an open state when the voltage regulator 1A is in a non-regulated state. That is, the current control circuit 26A includes an NMOS transistor 27_1 provided in the path 15, and NMOS transistors 28_1, ..., 28_n and NMOS transistors 29_1, ..., 29_n provided in the path 16.

[0017] The NMOS transistor 27_1 and the NMOS transistors 28_1, ..., 28_n are connected in parallel to each other between the gate 24g and the GND terminal 12. The current control transistor 27 is directly connected to the GND terminal 12 without passing through the NMOS transistors 29_1, ..., 29_n. On the other hand, the NMOS transistors 28_1, ..., 28_n are connected to the GND terminal 12 via the NMOS transistors 29_1, ..., 29_n, respectively.

[0018] In other words, the NMOS transistor 27_1 and the NMOS transistors 28_1, ..., 28_n each include a drain as a first terminal connected to the gate 24g, a gate as a control terminal for receiving an amplified signal output from the output terminal of the error amplifier circuit 25, and a second terminal as a source. The NMOS transistors 29_1, ..., 29_n each include a drain as a first terminal connected to the source of the NMOS transistor 28_1, ..., 28_n, a gate as a control terminal for receiving a detection signal output from the non-regulation state detection circuit 30, and a source as a second terminal connected to the GND terminal 12 that supplies the power supply voltage GND as a first power supply voltage.

[0019] The unregulated state detection circuit 30 has an input terminal 31i connected to a node N1 and an output terminal 31o connected to each control terminal of the NMOS transistors 29_1, ..., 29_n. Here, the node N1 is a connection point between the other end of the I / V conversion circuit 21, each drain of the NMOS transistor 27_1 and the NMOS transistors 28_1, ..., 28_n, and a gate 24g serving as a control terminal of the output transistor. The node N2 is a connection point between the output terminal of the error amplifier circuit 25 and the gate of the NMOS transistor 27_1. The node N3 is a connection point between the output terminal of the error amplifier circuit 25 and each gate of the NMOS transistors 28_1, ..., 28_n. The node N4 is a connection point between the output terminal 31o of the unregulated state detection circuit 30 and each gate of the NMOS transistors 28_1, ..., 28_n.

[0020] FIG. 2 is a circuit diagram of an unregulated state detection circuit 30, which is an example of the unregulated state detection circuit included in the voltage regulator according to the first embodiment.

[0021] The unregulated state detection circuit 30 includes a VDD terminal 11, a GND terminal 12, an input terminal 31i, an output terminal 31o, PMOS transistors 32, 34, and 35, NMOS transistors 36, 37, and 38, and a constant current source 39 that supplies a constant current I1. The PMOS transistors 32, 34, and 35 and the NMOS transistors 36 and 37 form a differential amplifier circuit. The NMOS transistor 38 and the constant current source 39 form an output inverter.

[0022] The differential amplifier circuit has a PMOS transistor 32 which is a sense transistor, PMOS transistors 34 and 35 which form a differential pair, and NMOS transistors 36 and 37 which form a current mirror which is an active load circuit. A predetermined reference voltage is applied to the gate of the PMOS transistor 34 which is the first input terminal of the differential pair from a reference voltage circuit 33. The gate of the PMOS transistor 35 which is the second input terminal of the differential pair is connected to the input terminal 31i and the gate of the PMOS transistor 32. The output terminal of the differential amplifier circuit is the connection point between the drain of the PMOS transistor 35 and the drain of the NMOS transistor 37.

[0023] The NMOS transistor 38 includes a drain connected to the output terminal 31o and serving as the output terminal of the output inverter, a gate connected to the input terminal of the output inverter and the output terminal of the differential amplifier circuit, and a source connected to the GND terminal 12. The constant current source 39 includes a first terminal connected to the VDD terminal 11, and a second terminal connected to the drain of the NMOS transistor 38 and the output terminal 31o.

[0024] Next, the operation of the voltage regulator 1A as the voltage regulator according to this embodiment will be described.

[0025] When the power supply voltage VDD is input to the VDD terminal 11, the voltage regulator 1A outputs an output voltage to the output terminal 22. The error amplifier circuit 25 receives a reference voltage from the reference voltage circuit 23 at a non-inverting input terminal (+) and receives a divided voltage as a voltage based on the output voltage at an inverting input terminal (-). The error amplifier circuit 25 outputs an amplified signal obtained by amplifying the difference between the reference voltage and the divided voltage to the gates of the NMOS transistor 27_1 and the NMOS transistors 28_1, ..., 28_n serving as the control terminals of the current control transistors 27, 28. The NMOS transistor 27_1 and the NMOS transistors 28_1, ..., 28_n convert the voltage received at each gate into a drain current and input it to the I / V conversion circuit 21. The I / V conversion circuit 21 converts the input current into a voltage based on the power supply voltage VDD and inputs it to the gate 24g of the PMOS transistor 24. The error amplifier circuit 25 and the common-source amplifier circuit 20A control the voltage of the gate 24g so that the output voltage approaches the reference voltage supplied to the non-inverting input terminal (+).

[0026] The unregulated state detection circuit 30 detects whether the voltage regulator 1A is in a regulated state (unregulated state) based on the voltage after current-voltage (I / V) conversion appearing at the other end of the I / V conversion circuit 21, i.e., the voltage at node N1. The unregulated state detection circuit 30 outputs a detection signal including a signal level corresponding to either the regulated state or the unregulated state as a detection result. When the power supply voltage VDD of the voltage regulator 1A is sufficiently high and the voltage regulator 1A is in a regulated state, the unregulated state detection circuit 30 illustrated in FIG. 2 outputs a high-level (hereinafter referred to as "H level") detection signal from an output terminal 31o.

[0027] When each gate of the NMOS transistors 29_1, ..., 29_n receives an H-level detection signal from the output terminal 31o, the NMOS transistors 29_1, ..., 29_n are turned on and closed. When the NMOS transistors 28_1, ..., 28_n are turned on, a current can flow through each of the paths 16_1, ..., 16_n of the path 16. Therefore, when the voltage regulator 1A is in a regulation state, a large current can flow through the current control transistors as a whole, and the output voltage is controlled to a desired voltage based on the reference voltage. At this time, the error amplifier circuit 25 and the source-grounded amplifier circuit 20A control the voltage of the gate 24g of the PMOS transistor 24 so that the divided voltage of the output voltage matches the reference voltage.

[0028] On the other hand, when the voltage regulator 1A is in a non-regulated state, the divided voltage of the output voltage is lower than the reference voltage, so the error amplifier circuit 25 fully turns on the NMOS transistor 27_1 and the NMOS transistors 28_1, ..., 28_n to pull down the gate voltage of the PMOS transistor 24 to 0 V, and attempts to draw the maximum support current from the power supply terminal 11. However, when the voltage regulator 1A is in a non-regulated state, the power supply voltage VDD is lower than the reference voltage, so no matter how much current the NMOS transistor 27_1 and the NMOS transistors 28_1, ..., 28_n draw, the divided voltage of the output voltage cannot be made to match the reference voltage.

[0029] Even though the divided voltage of the output voltage cannot be made equal to the reference voltage, the operation of the NMOS transistor 27_1 and the NMOS transistors 28_1, ..., 28_n to continue drawing the maximum support current does not provide an effect commensurate with the operation. Moreover, the operation of the NMOS transistor 27_1 and the NMOS transistors 28_1, ..., 28_n to continue drawing the maximum support current only increases the current consumption of the voltage regulator 1A, and when the voltage regulator is used in a battery-powered application, the battery is consumed rapidly.

[0030] Therefore, in order to suppress an increase in current consumption in the unregulated state, the voltage regulator 1A turns off the NMOS transistors 29_1, ..., 29_n in the unregulated state. When the NMOS transistors 29_1, ..., 29_n are turned off, the paths 16_1, ..., 16_n are switched to an open state. The unregulated state is detected by the unregulated state detection circuit 30 detecting that the voltage of the node N1 is lower than a predetermined voltage. When the power supply voltage VDD is insufficient and the voltage regulator 1A is in the unregulated state, the unregulated state detection circuit 30 illustrated in FIG. 2 outputs a low-level (hereinafter, referred to as "L level") detection signal from the output terminal 31o. When the NMOS transistors 29_1, ..., 29_n receive the L-level detection signal, the NMOS transistors 29_1, ..., 29_n are turned off, and the paths 16_1, ..., 16_n are switched to an open state.

[0031] As described above, the voltage regulator 1A includes the grounded-source amplifier circuit 20A having the path 16 that can be switched to an open state in the non-regulated state. The voltage regulator 1A including the grounded-source amplifier circuit 20A can turn off the NMOS transistors 29_1, ..., 29_n to cut off the current flowing through the paths 16_1, ..., 16_n when the voltage regulator 1A is in the non-regulated state. In this way, the voltage regulator 1A can switch at least one of the remaining paths 16_1, ..., 16_n to an open state while leaving the path 15 as at least one path that maintains a conductive state in the non-regulated state. Therefore, the voltage regulator 1A can suppress the current consumed in the grounded-source amplifier circuit 20A in the non-regulated state while maintaining a simple circuit configuration.

[0032] [Second embodiment] FIG. 3 is a circuit diagram showing a configuration of a voltage regulator 1B, which is an example of a voltage regulator according to the second embodiment.

[0033] Voltage regulator 1B differs from voltage regulator 1A in that it includes a grounded-source amplifier circuit 20B instead of grounded-source amplifier circuit 20A, but other components are substantially the same. Therefore, in the following description of this embodiment, the differences from voltage regulator 1A will be mainly described, and components that are substantially the same as those in voltage regulator 1A will be given the same reference numerals, and duplicate descriptions will be omitted.

[0034] The voltage regulator 1B includes a grounded-source amplifier circuit 20B, an error amplifier circuit 25, a PMOS transistor 24, and a non-regulation state detection circuit 30. The grounded-source amplifier circuit 20B includes an I / V conversion circuit 21 and a current control circuit 26B. The current control circuit 26B includes a switching circuit 40 capable of opening and closing between a node N2 and a node N3, instead of the NMOS transistors 29_1, ..., 29_n as the pass transistors 29 in the current control circuit 26A. That is, the current control circuit 26B includes a path 15 and n paths 16_1, ..., 16_n in which the NMOS transistors 29_1, ..., 29_n are omitted.

[0035] The switching circuit 40 has a first terminal connected to the node N2, a second terminal connected to the node N3, a third terminal connected to the GND terminal 12, and a control terminal that receives a detection signal output from the output terminal 31o. The switching circuit 40 is configured to be able to switch the connection destination of the second terminal between the first terminal and the third terminal according to the signal level of the signal supplied to the control terminal. When the voltage regulator 1B is in a regulated state, the switching circuit 40 connects the node N2 to the node N3. On the other hand, when the voltage regulator 1B is in a non-regulated state, the switching circuit 40 separates the node N2 from the node N3. In the switching circuit 40 illustrated in FIG. 3 and FIG. 4 described later, when the voltage regulator 1B is in a non-regulated state, the switching circuit 40 separates the node N2 from the node N3 and connects (pulls down) the node N3 to the GND terminal 12.

[0036] FIG. 4 is a circuit diagram showing an example of the configuration of the switching circuit 40. As shown in FIG.

[0037] The switching circuit 40 has a first terminal 41, a second terminal 42, a control terminal 43, a transistor pair 45, 46, and inverters 47, 48. The first terminal 41 is connected to a node N2. The second terminal 42 is connected to a node N3. The control terminal 43 is connected to an output terminal 31o. The transistor pair 45 as the first transistor pair is a pair of a PMOS transistor 45P and an NMOS transistor 45N. The transistor pair 46 as the second transistor pair is a pair of a PMOS transistor 46P and an NMOS transistor 46N.

[0038] The drain and source of the PMOS transistor 45P and the NMOS transistor 45N are connected to each other. The connection point 451 is a connection point between the source of the PMOS transistor 45P and the drain of the NMOS transistor 45N. The connection point 451 as a first end of the transistor pair 45 is connected to the first end 41 of the switching circuit 40. The connection point 452 is a connection point between the drain of the PMOS transistor 45P and the source of the NMOS transistor 45N. The connection point 452 as a second end of the transistor pair 45 is connected to the second end 42 of the switching circuit 40. The gates of the PMOS transistor 45P and the NMOS transistor 45N are connected via an inverter 47 as a first inverter. In the transistor pair 45 illustrated in FIG. 4, the inverter 47 has an input end connected to the gate of the NMOS transistor 45N and an output end connected to the gate of the PMOS transistor 45P.

[0039] The drain and source of the PMOS transistor 46P and the NMOS transistor 46N are connected to each other. The connection point 461 is a connection point between the drain of the PMOS transistor 46P and the source of the NMOS transistor 46N. The connection point 461 as the first end of the transistor pair 46 is connected to the GND terminal 12. The connection point 462 is a connection point between the source of the PMOS transistor 46P and the drain of the NMOS transistor 46N. The connection point 462 as the second end of the transistor pair 46 is connected to the second end 42. The gates of the PMOS transistor 46P and the NMOS transistor 46N are connected via an inverter 48 as a second inverter. In the transistor pair 46 illustrated in FIG. 4, the inverter 48 has an input terminal connected to the gate of the PMOS transistor 46P and an output terminal connected to the gate of the NMOS transistor 46N.

[0040] Here, the connection point of the input terminal of the inverter 47, the input terminal of the inverter 48, the gate of the NMOS transistor 45N, and the gate of the PMOS transistor 46P is referred to as a node N5. In the switching circuit 40 that receives an L-level detection signal in the non-regulated state of the voltage regulator 1B, an inverter 49 is connected between the control terminal 43 that receives the detection signal and the node N5. That is, the inverter 49 has an input terminal connected to the control terminal 43 and an output terminal connected to the node N5.

[0041] Next, the operation of the voltage regulator 1B as the voltage regulator according to this embodiment will be described.

[0042] In the regulated state and the non-regulated state, the voltage regulator 1B opens and closes the paths 16_1, ..., 16_n in the same manner as the voltage regulator 1A. When the voltage regulator 1B is in the regulated state, the switching circuit 40 switches the state between the node N2 and the node N3 to a closed state.

[0043] More specifically, the switching circuit 40 (see FIG. 4) receives an H-level detection signal output from the output terminal 31o through the control end 43. When the H-level detection signal is supplied from the control end 43, an H-level signal is supplied to each gate of the NMOS transistor 45N and the PMOS transistor 46P. Also, an L-level signal is supplied to the gate of the PMOS transistor 45P through an inverter 47. An L-level signal is supplied to the gate of the NMOS transistor 46N through an inverter 48. Therefore, when an H-level detection signal is supplied from the control end 43, both ends of the transistor pair 45 are conductive, while both ends of the transistor pair 46 are open.

[0044] When the voltage regulator 1B is in a non-regulated state, the switching circuit 40 connects the node N3 to the GND terminal 12. That is, the node N2 and the node N3 are opened, and the node N3 is pulled down.

[0045] More specifically, the switching circuit 40 (see FIG. 4) receives an L-level detection signal output from the output terminal 31o through the control end 43. When the L-level detection signal is supplied from the control end 43, an L-level signal is supplied to each gate of the NMOS transistor 45N and the PMOS transistor 46P. Also, an H-level signal is supplied to the gate of the PMOS transistor 45P through an inverter 47. An L-level signal is supplied to the gate of the NMOS transistor 46N through an inverter 48. Therefore, when an L-level detection signal is supplied from the control end 43, both ends of the transistor pair 45 are open, while both ends of the transistor pair 46 are conductive.

[0046] As described above, the voltage regulator 1B includes the grounded-source amplifier circuit 20B having the path 16 that can be switched to an open state in the non-regulated state. According to the voltage regulator 1B including the grounded-source amplifier circuit 20B, when the voltage regulator 1B is in the non-regulated state, the switching circuit 40 connects the node N3 to the GND terminal 12. By connecting the node N3 to the GND terminal 12, the NMOS transistors 28_1, ..., 28_n receive the power supply voltage GND at their gates and turn off. In this way, in the non-regulated state, the voltage regulator 1B can switch at least one remaining path 16_1, ..., 16_n to an open state while leaving the path 15 as at least one path that maintains a conductive state. Therefore, the voltage regulator 1B can suppress the current consumed in the grounded-source amplifier circuit 20B in the non-regulated state while maintaining a simple circuit configuration.

[0047] The present invention is not limited to the above-described embodiment, and can be implemented in various forms other than the above-described embodiment at the implementation stage, and various omissions, additions, substitutions, or modifications can be made without departing from the spirit of the invention. For example, the voltage regulators 1A and 1B shown in Figs. 1 and 3 include a voltage divider circuit 50, but the voltage divider circuit 50 may be omitted and the output terminal 22 may be connected to the inverting input terminal (-) of the error amplifier circuit 25. Also, the voltage regulator 1A may include a current control circuit 26C instead of the current control circuit 26A.

[0048] FIG. 5 is a circuit diagram showing a configuration of a current control circuit 26C which is a modified example of the current control circuit 26A.

[0049] The current control circuit 26C differs from the current control circuit 26A in that it has a pass transistor 60 instead of the pass transistor 29, but is otherwise substantially the same. The pass transistor 60 is configured by aggregating into one or more numbers that are less than the number n of NMOS transistors 28_1, …, 28_n as the current control transistors 28.

[0050] The current control circuit 26C is an example in which the pass transistor 60 is aggregated into m (m is a natural number satisfying 1 ≤ m < n) NMOS transistors 60_1, …, 60_m that are fewer in number than the number n of NMOS transistors 28_1, …, 28_n. The current control circuit 26C includes at least one configuration in which the drain of the NMOS transistor 28_2 provided in the path 16_2 as the third path is connected to the node N6, which is the connection point between the drain of the NMOS transistor 28_1 provided in the path 16_1 as the second path and the drain of the NMOS transistor 60_1. That is, in the current control circuit 26C, the paths 16 (16_1, …, 16_n) are aggregated into m paths 65_1, …, 65_m that are the same number as the number of NMOS transistors 60_1, …, 60_m that make up the pass transistor 60 at the part of the pass transistor 60.

[0051] Also, in the voltage regulators 1A and 1B described above, an example was described in which the non-regulation state detection circuit 30 outputs a detection signal of H level from the output terminal 31o when in the regulation state, but the present invention is not limited to this example. The non-regulation state detection circuit 30 may be configured to output a detection signal of H level from the output terminal 31o when in the non-regulation state. In this case, if an inverter is interposed in the subsequent stage of the non-regulation state detection circuit 30, it can operate in the same manner as the voltage regulators 1A and 1B when outputting a detection signal of H level from the output terminal 31o.

[0052] The I / V conversion circuit 21 is not limited to the circuit illustrated in FIG. 1 and the like, and may include a resistor. The resistor may include at least one of a resistor, a diode element, and a transistor having a gate and a drain connected (so-called diode connection). For example, the resistor may be composed of only a resistor 212, or may be composed of only a PMOS transistor 211 having a gate and a drain connected, or may be composed of a PMOS transistor 211 having a gate and a drain connected, and a resistor 212 connected in series with the PMOS transistor 211. Also, a diode element may be used instead of the PMOS transistor 211 having a gate and a drain connected.

[0053] The MOS transistors used in the present embodiment are examples of field effect transistors (FETs) and are not limited to MOSFETs. For example, field effect transistors other than MOSFETs, such as MIS-FETs and junction FETs (JFETs), may also be used.

[0054] These embodiments and their variations are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0055] 1A,1B Voltage Regulator 11 VDD terminal (second power supply terminal) 12 GND terminal (first power supply terminal) 15 Route (1st Route) 16(16_1~16_n) Route (2nd route, 3rd route) 20A, 20B Source grounded amplifier circuit 21 Current-to-voltage (I / V) conversion circuit 24 PMOS transistor (output transistor) 25 Error amplifier circuit 26A, 26B, 26C Current control circuit 27,28 Current-controlled transistor 29,60 Pass transistor 30 Unregulated state detection circuit 40 Switching circuit 45 Transistor pair (first transistor pair) 46 Transistor pair (second transistor pair) 47 Inverter (first inverter) 48 Inverter (Second inverter)

Claims

1. an output transistor having a control terminal for receiving a control voltage and for outputting an output voltage; an error amplifier circuit that outputs an amplified signal obtained by amplifying the difference between a voltage based on the output voltage and a reference voltage; a source-grounded amplifier circuit to which the amplified signal is input and which outputs the control voltage to the control terminal; an unregulated state detection circuit that outputs a detection signal including a signal level corresponding to a regulated state or an unregulated state to the source ground amplifier circuit; the source-grounded amplifier circuit includes a current control circuit having a plurality of parallel paths each of which is switchably connected between the control terminal of the output transistor and a first power supply terminal that supplies a first power supply voltage and which is open or closed depending on the signal level of the detection signal; The voltage regulator, wherein the paths include a first path in a conductive state through which a current flows in the unregulated state, and a second path that is switched to the open state in the unregulated state.

2. the current control circuit includes current control transistors provided in the plurality of parallel paths, each current control transistor having a first terminal connected to the control terminal of the output transistor, a control terminal receiving the amplified signal, and a second terminal; a pass transistor including a first terminal connected to a second terminal of the current control transistor provided in the second path, a second terminal connected to the first power supply terminal, and a control terminal for receiving the detection signal, the pass transistor being switchable between an open state and a closed state in accordance with the signal level of the detection signal; 2. The voltage regulator of claim 1, wherein the pass transistor is switched to the open state in the unregulated state.

3. 3. The voltage regulator according to claim 2, wherein the number of paths that are switched to the open state in the non-regulated state is two or more, including the second path.

4. the paths switched to the open state in the unregulated state include the second path and a third path; 3. The voltage regulator according to claim 2, wherein a second terminal of the current control transistor provided in the second path is connected to a second terminal of the current control transistor provided in the third path.

5. the current control circuit further includes a third path that is switched to the open state in the unregulated state; the current control circuit includes the plurality of current control transistors, each of which is provided in the plurality of parallel paths and includes a first terminal connected to the control terminal of the output transistor, a control terminal receiving the amplified signal, and a second terminal; a first pass transistor including a first terminal connected to a second terminal of the current control transistor provided in the second path, a second terminal connected to the first power supply terminal, and a control terminal for receiving the detection signal, the first pass transistor being switchable between an open state and a closed state in accordance with the signal level of the detection signal; a second pass transistor including a first terminal connected to a second terminal of the current control transistor provided in the third path, a second terminal connected to the first power supply terminal, and a control terminal for receiving the detection signal, the second pass transistor being switchable between an open state and a closed state in accordance with the signal level of the detection signal; 2. The voltage regulator of claim 1, wherein the first pass transistor and the second pass transistor are switched to the open state in the unregulated state.

6. the current control circuit includes the plurality of current control transistors connected in parallel between the control terminal of the output transistor and the first power supply terminal, the control terminal receiving the amplified signal; a switching circuit that is capable of switching between an open state in which a control terminal of the current control transistor provided on the second path is disconnected from the error amplifier circuit and a closed state in which a control terminal of the current control transistor provided on the second path is connected to the error amplifier circuit, in accordance with the signal level of the detection signal; The voltage regulator of claim 1 , wherein the switching circuit is switched to the open state in the unregulated state.

7. 7. The voltage regulator according to claim 6, wherein the switching circuit is configured to be able to switch a connection destination of the control terminal of the current control transistor provided in the second path, and in the closed state, the connection destination is switched to the error amplifier circuit, while in the open state, the connection destination is switched to the first power supply terminal.

8. The switching circuit a first terminal connected to the error amplifier circuit; a second terminal connected to a control terminal of the current control transistor provided in the second path; a control terminal for receiving the detection signal; a first transistor pair consisting of a first PMOS transistor and a first NMOS transistor, the first transistor pair having a first end connected to the first end of the switching circuit and a second end connected to the second end of the switching circuit; a second transistor pair including a second PMOS transistor and a second NMOS transistor, the second transistor pair having a first end connected to the first power supply terminal and a second end connected to a second end of the switching circuit and a second end of the first transistor pair; a first inverter connected between the gate of the first PMOS transistor and the gate of the first NMOS transistor; 8. The voltage regulator according to claim 6, further comprising: a second inverter connected between the gate of the second PMOS transistor and the gate of the second NMOS transistor.

9. the current control circuit includes the plurality of current control transistors, each of which is provided in the plurality of parallel paths and includes a first terminal connected to the control terminal of the output transistor, a control terminal receiving the amplified signal, and a second terminal; 2. The voltage regulator according to claim 1, wherein the source-grounded amplifier circuit has a current-voltage conversion circuit having one end connected to a second power supply terminal that supplies a second power supply voltage and another end connected to first terminals of the plurality of current control transistors and the control terminal of the output transistor.

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