Analog / digital converter
Patent Information
- Application Number
- JP2022160982
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2022-10-05
- Publication Date
- 2025-08-19
- Estimated Expiration
- 2042-10-05
AI Technical Summary
Existing successive approximation type A/D converters face challenges in suppressing glitches and reducing power consumption due to the use of delay circuits for timing adjustments and complex circuit configurations in D flip-flops with set/reset.
The use of conditional passability latches in the data register section of the A/D converter to accurately reflect comparison signals without requiring timing adjustments, thereby eliminating the need for delay circuits and simplifying the circuit configuration.
This approach effectively suppresses glitches and reduces power consumption in the D/A converter, avoiding increases in circuit area and power consumption associated with delay circuits.
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Abstract
Description
[Technical field]
[0001] The present disclosure relates to analog-to-digital converters. [Background technology]
[0002] 2. Description of the Related Art As one type of analog-to-digital converter (hereinafter also referred to as "A / D converter"), a successive approximation type A / D converter is known which does not use an operational amplifier and therefore consumes less power.
[0003] For example, Japanese Patent Laid-Open Publication No. 2009-17085 (Patent Document 1) discloses a successive approximation type A / D converter including a comparator that compares an analog input voltage with a reference voltage, a successive approximation register consisting of multiple bits that stores the comparison result of the comparator and generates a comparison code based on the comparison result, and a digital / analog (hereinafter abbreviated as D / A) converter that generates a reference voltage to be compared next based on the comparison code.
[0004] Patent document 1 describes that in order to detect abnormal operation of the successive approximation register, the successive approximation register further includes a detection circuit that outputs an abnormal conversion detection signal when the value of any bit among the multiple bits of the successive approximation register changes during a period in which the successive approximation register must hold data. [Prior art documents] [Patent documents]
[0005] [Patent Document 1] JP 2009-17085 A Summary of the Invention [Problem to be solved by the invention]
[0006] In a successive approximation A / D converter, it is necessary to adjust the generation timing of the signal that reflects the comparison result of the comparator and is supplied to the D / A converter so as not to cause glitches in the D / A converter. For example, by arranging a delay circuit to create a time difference between the timing at which the register holds the comparison result of the comparator and the timing at which the signal that is supplied to the D / A converter is generated based on the output signal of the register, it is possible to adjust the timing so that no momentary change in value occurs in the signal that is supplied to the D / A converter. However, there is a concern that the placement of the delay circuit may result in extra power consumption.
[0007] Patent Document 1 describes a configuration in which a signal to be supplied to a D / A converter is generated by receiving a comparison result of a comparator using a set-reset D flip-flop instead of a reset D flip-flop. As a result, the successive approximation A / D converter of Patent Document 1 does not need to place a delay for timing adjustment on the path of a multi-bit signal supplied to the D / A converter.
[0008] However, in Patent Document 1, a delay circuit is used to generate a short pulse as a set signal for the set-reset D flip-flop, which raises concerns that it may be difficult to reduce power consumption.In addition, the set-reset D flip-flop has a relatively complicated circuit configuration, which raises concerns that power consumption and area may increase.
[0009] The present disclosure has been made to solve such problems, and an object of the present disclosure is to provide a successive approximation type analog-to-digital converter that can suppress glitches in the D / A converter while reducing power consumption. [Means for solving the problem]
[0010] In one aspect of the present disclosure, an analog-to-digital converter includes a digital-to-analog conversion circuit, a comparator, and a successive approximation register circuit. The digital-to-analog conversion circuit holds an analog input voltage and outputs a differential voltage between the analog input voltage and a voltage corresponding to an analog-converted value of a multi-bit control signal. The comparator outputs a comparison signal that is a digital signal based on the differential voltage and a reference voltage. The successive approximation register circuit has a data register section for holding the comparison signal, and generates multiple bits of the control signal based on output signals of the data register section at multiple timings corresponding to the multiple bits respectively. The data register section has conditional pass latches arranged corresponding to each of the multiple bits. The conditional pass latch has a function of determining whether to pass or hold the value of the input comparison signal to the output signal. Effect of the Invention
[0011] According to the present disclosure, by using a conditional pass latch, changes in a comparison signal can be accurately reflected in a multi-bit control signal without the need for timing adjustment using a delay circuit, so it is possible to provide a successive approximation type analog-to-digital converter that can simultaneously suppress glitches and reduce power consumption when D / A converting the multi-bit control signal. [Brief description of the drawings]
[0012] [Figure 1] 1 is a schematic block diagram illustrating a configuration of an analog-to-digital converter according to an embodiment of the present invention. [Diagram 2] 2 is a block diagram illustrating a configuration example of a successive approximation register circuit shown in FIG. 1. [Diagram 3] 3 is a circuit diagram of a D flip-flop with a reset used as a comparative example in the data register unit shown in FIG. 2. [Figure 4] 3 is a timing chart illustrating a comparative example of the operation of the successive approximation register circuit illustrated in FIG. 2; [Diagram 5] 2 is a circuit diagram of a reset-enabled D latch constituting a data register unit in the analog-to-digital converter according to the first embodiment. FIG. [Figure 6] 5 is a timing chart illustrating an operation of the successive approximation register circuit in the analog-to-digital converter according to the present embodiment. [Figure 7] 2 is a block diagram illustrating a configuration example of a successive approximation register circuit of the analog-to-digital converter according to the first embodiment. FIG. [Figure 8] FIG. 8 is a circuit diagram of the gated SR latch shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0013] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following, the same or corresponding parts in the drawings are denoted by the same reference characters, and their description will not be repeated in principle.
[0014] Embodiment 1 FIG. 1 is a schematic block diagram illustrating the configuration of an analog-to-digital converter 100, which is a successive approximation type A / D converter according to this embodiment.
[0015] 1, an analog-to-digital converter 100 includes a D / A conversion circuit 11, a comparator 15, and a successive approximation register circuit 20. The D / A conversion circuit 11 includes a comparator 15 and a successive approximation register circuit 20. The successive approximation register circuit 20 includes a digital-to-analog converter (D / A converter) 15 and a digital-to-digital converter (D / A converter).
[0016] The D / A conversion circuit 11 includes a sample-and-hold circuit 12, a D / A converter 13, and a subtractor 14. The sample-and-hold circuit 12 has a switch 12a and a capacitor 12b.
[0017] The switch 12a is turned on at the sampling timing of the analog input voltage Vin. The capacitor 12b holds the analog input voltage Vin transmitted when the switch 12a is on as a sampling voltage Vsmp.
[0018] The D / A converter 13 receives a D / A control signal D, which is a (n+1)-bit (n: natural number) digital signal, from the successive approximation register circuit 20. <0> ~D <n>The D / A conversion circuit 11 outputs a voltage Vcv which is a D / A converted value of the sampling voltage Vsmp. The subtractor 14 generates a differential voltage Vo between the sampling voltage Vsmp and the voltage Vcv as an output voltage of the D / A conversion circuit 11 (Vo=Vsmp-Vcv).
[0019] The comparator 15 generates a comparison signal cmp, which is a digital signal based on the differential voltage Vo from the D / A conversion circuit 11, at the rising or falling timing of the clock signal clk. As an example, the comparison signal cmp is a digital signal that compares the differential voltage Vo with a reference voltage and indicates the comparison result. The reference voltage can be, for example, a common voltage that corresponds to the intermediate voltage of the voltage range that is the target of A / D conversion of the analog input voltage Vin, but can be determined arbitrarily.
[0020] In addition, if the comparator 15 includes a reset function, a latch circuit (not shown) may be built in the comparator 15 so that the output value does not change due to the reset operation. In addition, if the analog input voltage Vin is input as positive and negative differential signals, the D / A conversion circuit 11 is provided corresponding to each. In this case, the output Vop of the D / A conversion circuit 11 with the analog input voltage Vin being a positive voltage and the output Von of the D / A conversion circuit 11 with the analog input voltage Vin being a negative voltage are input to the comparator 15, and Vop and Von are compared.
[0021] The successive approximation register circuit 20 receives a start signal Str from the outside, determines the D / A conversion order of the D / A conversion circuit 11, holds the comparison signal cmp from the comparator 15, and outputs a D / A control signal D according to the comparison signal cmp. <0> ~D <n>Generate.
[0022] In addition, the successive approximation register circuit 20 may generate a clock (clk) for operating the comparator 15 and the successive approximation register circuit 20 in response to the comparison signal cmp from the comparator 15. The A / D conversion result by the successive approximation type analog-to-digital converter 100 is output from the successive approximation register circuit 20.
[0023] Fig. 2 is a block diagram for explaining a configuration example of the successive approximation register circuit 20 shown in Fig. 1. In the following, in order to simplify the explanation, the resolution of the A / D conversion is explained as 3 bits (i.e., in Fig. 1, n=2). However, as will become clear from the following explanation, the present disclosure can be applied to a resolution of any number of bits.
[0024] 2, the successive approximation register circuit 20 includes a shift register section 21, a D / A conversion pulse generating section 22, a data register section 23, and a D / A control signal generating section 24. In order to simplify the explanation, a circuit that receives an external start signal and a circuit that performs a reset operation are not shown in FIG.
[0025] The shift register section 21 is composed of (n+1) flip-flops that commonly receive a reset signal rst and a clock signal clk. After reset is released when the reset signal changes from a logical high level (H level) to a logical low level (L level), the (n+1) flip-flops output a signal that rises from an L level to an H level in response to a rising edge of the clock signal clk from an L level to an H level, starting from the left flip-flop. Therefore, a time difference of one clock of the clock signal clk is sequentially provided between the rising timings of the output signals from the (n+1) flip-flops.
[0026] The D / A conversion pulse generating unit 22 generates (n+1) D / A conversion pulses P <0> ~P <n>Each D / A conversion pulse is a pulse signal having an L level period of one pulse of the clock signal clk. Furthermore, the D / A conversion pulse P <0> ~P <n>In the example of FIG. 2, since n=2 (3-bit resolution), the D / A conversion pulse generating unit 22 generates the D / A conversion pulse P <0> ~P <2> will be output.
[0027] The data register unit 23 receives the D / A conversion pulse P The comparison signal cmp (comparator 15) at the transition timing (rising time) from L level to H level of (i: an integer from 0 to n) is As a result, the data register unit 23 outputs a D / A conversion pulse P <0> ~P <n>(n+1) data signals C having the value (H / L level) of the comparison signal cmp at the rising edge of <0> ~C <n>In the example of FIG. 2 where n=2, the data register unit 23 outputs the data signal C <0> ~C <2> will be output.
[0028] The D / A control signal generator 24 generates the D / A control signal D <0> ~D <n>Each NAND gate has (n+1) NAND gates that generate a data signal C and the inverted signal of D / A conversion pulse P The result of the NAND operation with the D / A control signal D As a result, the D / A control signal generator 24 outputs (n+1) D / A control signals D <0> ~D <n>In the example of FIG. 2 where n=2, the D / A control signal generator 24 outputs the D / A control signal D <0> ~D <2> Generate.
[0029] The D / A control signal D from the D / A control signal generator 24 <0> ~D <n>As shown in FIG. 1, the D / A converter 13 receives the sampling voltage Vsmp (analog input voltage Vin) and the difference voltage Vo is input to the comparator 15. Through such feedback, the D / A control signal D <0> ~D <n>Finally, it converges to a value equivalent to the A / D conversion value of the sampling voltage Vsmp (analog input voltage Vin).
[0030] First, as a comparative example, the operation of the successive approximation register circuit 20 when the data register section 23 is configured with a reset D flip-flop 40 shown in FIG. 3 will be described.
[0031] 3, in the reset D flip-flop 40, when an H level is input to the R terminal (reset terminal) for resetting, the output of the NOR gate is forcibly changed to the L level, so that the output signal of the Q terminal is fixed to the L level. A reset signal rst common to the shift register section 21 can be input to the R terminal (reset terminal).
[0032] During the non-reset period when an L level is input to the R terminal, the timing of change of one of the inputs of the NOR gate is controlled by an inverter that operates in response to the input clock CK to the CK terminal (clock terminal) or its inverted signal CKb. This causes the reset-equipped D flip-flop 40 to capture and hold the signal level of the D terminal at the rising edge of the input clock CK, and output it from the Q terminal.
[0033] As shown in FIG. 2, the CK terminal of the i-th reset D flip-flop 40(i) receives a D / A conversion pulse P is input to the D terminal, and a comparison signal cmp from the comparator 15 is input to the D terminal. Furthermore, a data signal C is input from the Q terminal. will be output.
[0034] Fig. 4 is a timing chart illustrating a comparative example of the operation of the successive approximation register circuit 20. In Fig. 4, the operation when the comparison signal cmp from the comparator 15 is at H level is indicated by a solid line, while the operation when the comparison signal cmp is at L level is indicated by a dotted line.
[0035] In the reset D flip-flop 40, as described above, the D / A conversion pulse P is input to the CLK terminal, the D / A conversion pulse P The level of the comparison signal cmp at time t0 when the comparison signal cmp rises from the L level to the H level is captured.
[0036] At this time, the D / A control signal D is output to the Q terminal. 4 occurs due to the time required for the internal processing of the reset D flip-flop 40 until the level of the comparison signal cmp received from the D terminal is reflected in the D / A control signal D According to the above, the D / A control signal D is generated.
[0037] As a result, when the comparison signal cmp is at the L level, the following problem occurs.
[0038] In the reset D flip-flop 40, the D / A conversion pulse P In response to the rising edge of At time t1 when the delay time due to the internal processing of the reset D flip-flop 40 has elapsed, the D / A control signal D In the period from time t0 to time t1, a momentary pulse is generated due to a temporary change in value. This causes a glitch to occur in the output of the D / A converter 13, and the D / A control signal D As the time it takes for the D / A conversion value to converge to the correct value increases, there are concerns that D / A conversion errors may occur, the D / A conversion speed may decrease, and power consumption may increase.
[0039] As shown by the solid line in FIG. 4, when the comparison signal cmp is at the L level, the data signal C Since the D / A control signal D is maintained at the L level at time t1, Therefore, the above-mentioned problem does not occur.
[0040] For example, in the conventional method, in order to prevent the above-mentioned glitch from occurring, a delay circuit having a delay amount equivalent to the delay time generated by the reset D flip-flop 40 is inserted between the D / A conversion pulse generating unit 22 and the D / A control signal generating unit 24, so that the D / A control signal D However, the power consumption and area increase accordingly due to the placement of the delay circuit.
[0041] Alternatively, in Patent Document 1, the data register unit 23 is configured with a set-reset D flip-flop, and the D / A control signal generator 24 is not arranged, so that the D / A control signal D However, as described above, the configuration of Patent Document 1 requires the placement of a delay circuit to generate a set signal for the above-mentioned set-reset D flip-flop. This causes the above-mentioned problems of increased power consumption and circuit area.
[0042] Therefore, in this embodiment, the data register unit 23 is configured with a conditional pass latch that has a function of determining whether to pass or hold (non-pass) a change in the input signal at the D terminal to the output signal at the Q terminal when the change occurs. In the first embodiment, the data register unit 23 in FIG. 2 is configured using (n+1) reset-enabled D latches 50 shown in FIG. 5.
[0043] As shown in FIG. 5, the reset-enabled D latch 50 has a configuration in which a part of the reset-enabled D flip-flop 40 shown in FIG.
[0044] The clocked inverter 51 operates during an H level period of an inverted signal CKb of an input clock CK to a clock terminal CK (an L level period of CK), and inverts and outputs the value (H / L level) of the D terminal. On the other hand, during an H level period of the input clock CK, the output of the clocked inverter 51 is floating.
[0045] On the other hand, the clocked inverter 52 operates during the H level period of the input clock CK. That is, during the L level period of the input clock CK, the output of the clocked inverter 52 is floating.
[0046] The output of the clocked inverter 51 is connected to one of two inputs of a NOR gate 53. The input of the clocked inverter 52 is connected to the output of the NOR gate 53, and the output of the clocked inverter 52, like the output of the clocked inverter 51, is connected to one of the two inputs of the NOR gate 53.
[0047] An R terminal (reset terminal) is connected to the other of the two inputs of the NOR gate 53. The buffer 54 outputs the output signal of the NOR gate 53 to a Q terminal. A reset signal rst common to the shift register section 21 can also be input to the R terminal (reset terminal) of the reset-equipped D latch 50.
[0048] Therefore, when the reset D latch 50 is reset by inputting an H level to the R terminal (reset terminal), the output of the NOR gate is forcibly changed to an L level, and the output signal of the Q terminal is reset to an L level.
[0049] On the other hand, during the non-reset period when an L level is input to the R terminal, while the input clock CK is at a H level, the value (H / L level) of the D terminal captured at the rising edge of the input clock CK is held and output from the Q terminal.
[0050] Regarding the (n+1) reset-enabled D latches 50 constituting the data register unit 23, the D / A conversion pulse P is input to the D terminal, and a comparison signal cmp from the comparator 15 is input to the D terminal. Furthermore, a data signal C is input from the Q terminal. will be output.
[0051] Fig. 6 is a timing chart for explaining the operation of the successive approximation register circuit in the analog-to-digital converter according to this embodiment. That is, Fig. 6 shows a timing chart when the data register section 23 is configured using the reset-equipped D latch 50 of Fig. 5. In Fig. 6, as in Fig. 4, the operation when the comparison signal cmp from the comparator 15 is at H level is shown by a solid line, while the operation when the comparison signal cmp is at L level is shown by a dotted line.
[0052] The reset-equipped D latch 50 receives a D / A conversion pulse P corresponding to the input clock CK. During the L level period of the D terminal, the comparison signal cmp is passed. Therefore, when the comparator 15 executes a comparison at the falling edge of the input clock CK in the successive approximation register circuit 20, the D / A conversion pulse P During the L level period, the comparison signal cmp from the comparator 15 passes through the clocked inverter 51 and is taken in, and the data signal C Therefore, the D / A conversion pulse P By the time t0 when the comparison signal cmp rises, the value of the comparison signal cmp is passed to the data signal C can be reflected in.
[0053] On the other hand, as shown in FIG. 2, the D / A control signal generator 24 is composed of a NAND gate, so that the D / A conversion pulse P Until the time t0 when the data signal C Even if the value of The value of does not change to H level. Therefore, the reference voltage Vcv output from the D / A converter 13 does not change erroneously and the D / A conversion circuit 11 does not operate.
[0054] Next, at time t0, the D / A conversion pulse P When the signal C goes high, the comparison signal cmp is reflected in the data signal C has already been input to the D / A control signal generating section 24, the D / A control signal generating section 24 instantly D / A control signal based on D Then, the D / A conversion pulse P is maintained at H level until the flip-flop constituting the shift register section 21 is reset. Therefore, even if the comparison signal cmp from the comparator 15 fluctuates, it is not captured by the reset-equipped D latch 50, and the data signal C and D / A control signal D is immutable.
[0055] In FIG. 6, the (n+1)-bit D / A control signal D corresponds to one embodiment of a "multiple-bit control signal", and time t0 corresponds to "multiple timings" corresponding to each of the (n+1) bits. Furthermore, the (n+1)-bit D / A conversion pulse P corresponds to one embodiment of the "pulse signal that defines a plurality of timings", and its L level corresponds to the "first level" and its H level corresponds to the "second level". Also, the D / A conversion pulse P The L level period corresponds to "a certain period before each of the multiple timings."
[0056] From the above, in the analog-to-digital converter according to the first embodiment, by configuring the data register unit 23 with the reset D latch 50, the effect of the delay time due to the internal processing of the data register unit 23 can be suppressed, and therefore it is possible to avoid the occurrence of glitches in the output of the D / A converter 13 without disposing a delay circuit as in Patent Document 1, etc. As a result, it is possible to avoid increases in power consumption and circuit area due to the placement of a delay circuit, and it is possible to achieve both suppression of glitches in the D / A converter and low power consumption.
[0057] It is also understood that the reset-enabled D latch 50 (FIG. 5) used in the first embodiment can be configured with about half the number of elements compared to the reset-enabled D flip-flop 40 in the comparative example of FIG. 3. Therefore, by replacing the reset-enabled D flip-flop 40 with the reset-enabled D latch 50, the power consumption and circuit area can be further reduced.
[0058] Embodiment 2 In the second embodiment, another example of a conditionally passable latch constituting a data register section in a sequential register circuit will be described.
[0059] 7 is a block diagram illustrating a configuration example of a successive approximation register circuit 20x according to embodiment 2. The analog-to-digital conversion circuit according to embodiment 2 is configured by replacing the successive approximation register circuit 20 with a successive approximation register circuit 20x in the analog conversion device according to embodiment 1 described with reference to FIGS.
[0060] Comparing Fig. 7 with Fig. 2, the successive approximation register circuit 20x according to the second embodiment differs from the successive approximation register circuit 20 (Fig. 2) according to the first embodiment in that a data register unit 23X is arranged instead of the data register unit 23. The data register unit 23X includes (n+1) gated SR latches 80 instead of the reset-equipped D latch 50 in the data register unit 23. The configuration of other parts in Fig. 7 is similar to that in Fig. 2, and therefore detailed description will not be repeated. That is, Fig. 7 also shows a configuration example when the resolution of A / D conversion is 3 bits (n=2).
[0061] FIG. 8 shows a circuit diagram of the gated SR latch 80 shown in FIG.
[0062] 8, the gated SR latch 80 has an internal latch 81 and an input gate 82. The internal latch 81 receives a signal at an R terminal (reset terminal) and an output signal of the input gate 82. The internal latch 81 can be configured with a NOR gate as shown in FIG. 8, but can also be configured with a NAND gate.
[0063] The input gate 82 has two inputs, the signals of the terminal E and the terminal S. For example, the input gate 82 can be configured as a NOR gate having two inputs, the signal of the terminal E and the inverted signal of the terminal S.
[0064] At the time of reset when an H level is input to the R terminal (reset terminal) of the gated SR latch 80, the output signal of the Q terminal is fixed to an L level. A reset signal rst common to the shift register unit 21 can also be input to the R terminal (reset terminal) of the gated SR latch 80.
[0065] On the other hand, during non-reset when an L level is input to the R terminal (reset terminal), if the input signal to the E terminal is at L level, the input signal to the S terminal passes through input gate 82 (NOR gate) and is input to internal latch 81. Because the R terminal is at L level, the output signal of input gate 82 is passed and immediately transmitted to the Q terminal. That is, the value of the output signal of the Q terminal changes instantly according to the value of the signal at the S terminal.
[0066] Furthermore, when the input signal to the E terminal is at H level during non-reset (when the R terminal is at L level), the input signal to the S terminal is blocked by the input gate 82 and is not input to the internal latch 81. For this reason, the output signal to the Q terminal holds the value of the input signal to the S terminal that was captured by the internal latch 81 when the signal at the E terminal rose.
[0067] From the above, it can be understood that if the input clock CK in Fig. 3 is input to the E terminal, the gated SR latch 80 operates in the same manner as the reset-equipped D latch 50 described in Fig. 3. Therefore, as shown in Fig. 7, the i-th gated SR latch 80 outputs a D / A conversion pulse P 6. That is, the i-th gated SR latch 80 receives a data signal C similar to that of FIG. 6 from its Q terminal. can be output.
[0068] Therefore, the data register section 23X in FIG. 7 can operate in the same manner as the data register section 23 described in the first embodiment. That is, the D / A conversion pulse P During the L level period, the comparison signal cmp from the comparator 15 passes through the input gate 82 and is taken in, and the data signal C Therefore, the D / A conversion pulse P When goes high (time t0 in FIG. 6), the D / A control signal generator 24 instantly generates the data signal C D / A control signal based on D can be generated.
[0069] As a result, the analog-to-digital converter according to the second embodiment, which includes the data register unit 23X configured with the gated SR latch 80, can also avoid occurrence of glitches in the output of the D / A converter 13 without disposing a delay circuit as in Patent Document 1 etc. As a result, as in the first embodiment, it is possible to avoid increases in power consumption and circuit area due to the placement of a delay circuit, and therefore it is possible to achieve both suppression of glitches and low power consumption in the D / A converter.
[0070] Moreover, the gated SR latch 80 (FIG. 8) used in the second embodiment has a simpler circuit configuration than the reset-enabled D flip-flop 40 in the comparative example of FIG. 3, and therefore, by replacing the reset-enabled D flip-flop 40 with the gated SR latch 80, it is possible to further enjoy the effects of reducing power consumption and circuit area.
[0071] Although the gated SR latch 80 (FIG. 8) has a larger circuit area due to its constituent elements than the reset-added D latch 50 (FIG. 6), it has the advantage that wiring for the input clock CK is not required internally.
[0072] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]
[0073] 11 D / A conversion circuit, 12 sample hold circuit, 12a switch, 12b capacitor, 13 converter, 14 subtractor, 15 comparator, 20, 20x comparison register circuit, 21 shift register section, 22 conversion pulse generating section, 23, 23X data register section, 24 control signal generating section, 40 reset D flip-flop, 50 reset D latch, 80 gated SR latch, 81 internal latch, 82 input gate, 100 analog-to-digital converter, C <0> ~C <2> ,C Data signal, CK Clock terminal (input clock), D <0> ~D <2> ,D D / A control signal, P <0> ~P <2> ,P D / A conversion pulse, SR gated, Str start signal, Vcv reference voltage, Vo output voltage, Vsmp sampling voltage, clk clock signal, cmp comparison signal. < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>
Claims
1. a digital-to-analog conversion circuit that holds an analog input voltage and outputs a differential voltage between the analog input voltage and a voltage corresponding to an analog-converted value of a multi-bit control signal; a comparator that outputs a comparison signal that is a digital signal based on the differential voltage and a reference voltage; a successive approximation register circuit having a data register section for holding the comparison signal, and generating the plurality of bits of the control signal based on output signals of the data register section at a plurality of timings respectively corresponding to the plurality of bits; an analog-to-digital converter, wherein the data register unit is configured with conditional pass latches arranged corresponding to each of the plurality of bits and having the function of determining whether to pass or hold the value of the input comparison signal to the output signal.
2. 2. The analog-to-digital converter according to claim 1, wherein the conditionally passable latch is a D latch that receives the comparison signal at a D terminal and generates the output signal at a Q terminal.
3. 3. The analog-to-digital converter according to claim 2, wherein the D latch is configured to capture the signal at the D terminal when a pulse signal that defines the plurality of timings by transitioning from a first level to a second level is at the first level.
4. 2. The analog-to-digital converter according to claim 1, wherein the conditionally passable latch is a gated SR latch that receives the comparison signal at an S terminal and a pulse signal defining each of the plurality of timings at an E terminal, and generates the output signal at a Q terminal.
5. The gated SR latch comprises: an input gate to which the signals of the S terminal and the E terminal are input; 5. The analog-to-digital converter according to claim 4, further comprising an internal latch that receives a reset signal input to an R terminal and the output signal of said input gate, and outputs said output signal to said Q terminal.