Vertical semiconductor device

Abstract

To provide a vertical semiconductor device capable of improving the avalanche tolerance.SOLUTION: The vertical semiconductor device includes a semiconductor substrate 10 having a cell region 1 in which a semiconductor element is formed and an outer peripheral region 2 surrounding the cell region 1. Defining an area where an impurity layer 14 is formed as cell area 1, a trench gate structure extends from the cell area 1 to the outer peripheral area 2. A base layer 13 extends from the cell region 1 to the outer peripheral region 2, A contact hole 20a extends from the cell area 1 to the outer peripheral area 2. An upper electrode 21 is also connected to the base layer 13 via the contact hole 20a in the outer peripheral region 2.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a vertical semiconductor device having a trench gate structure. [Background technology]

[0002] Conventionally, a vertical semiconductor device having a trench gate structure has been proposed (for example, see Patent Document 1). Specifically, this vertical semiconductor device is configured by forming a MOSFET (short for metal oxide semiconductor field effect transistor). More specifically, the vertical semiconductor device is configured by forming an n + On the drain region of the n - A p-type drift layer is formed on the n-type base layer. + A source layer of a type is formed, and a trench gate structure is formed to penetrate the source layer and the base layer and reach the drift layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2013-84905 A Summary of the Invention [Problem to be solved by the invention]

[0004] Such a vertical semiconductor layer usually includes a cell region where a MOSFET element is formed and a peripheral region surrounding the cell region, and the trench gate structure may be extended from the cell region to the peripheral region so as to reduce the electric field in the peripheral region.

[0005] However, in the vertical semiconductor device described above, a parasitic bipolar transistor is formed by the drift layer, the base layer, and the source layer. According to the study by the present inventors, when the trench gate structure is extended to the peripheral region, it has been confirmed that the parasitic bipolar transistor is likely to operate around the trench gate structure arranged in the peripheral region. For this reason, it is desired to improve the avalanche resistance so that the parasitic bipolar transistor is less likely to operate.

[0006] In view of the above, an object of the present invention is to provide a vertical semiconductor device capable of improving the avalanche resistance. [Means for solving the problem]

[0007] In claim 1 for achieving the above object, a vertical semiconductor device having a semiconductor element having a trench gate structure is provided, the vertical semiconductor device comprising a semiconductor substrate (10) having a cell region (1) in which the semiconductor element is formed and an outer periphery region (2) surrounding the cell region, the cell region comprising a drift layer (12) of a first conductivity type, a base layer (13) of a second conductivity type formed on the drift layer, an impurity layer (14) of the first conductivity type formed in a surface layer portion of the base layer and having a higher impurity concentration than the drift layer, a trench gate structure in which a gate electrode (18) is disposed via a gate insulating film (17) in a trench (16) extending along a surface direction of the semiconductor substrate, penetrating the impurity layer and the base layer to reach the drift layer, and a gate insulating film (17) formed on the opposite side of the base layer with the drift layer in between. The semiconductor device has a high-concentration layer (11) of a first or second conductivity type having a higher impurity concentration than the drift layer, an interlayer insulating film (20) formed on one surface (10a) of the semiconductor substrate and having a contact hole (20a) exposing the base layer and the impurity layer, a first electrode (21) electrically connected to the impurity layer and the base layer through the contact hole, and a second electrode (22) electrically connected to the high-concentration layer, the region in which the impurity layer is formed is defined as a cell region, the trench gate structure extends from the cell region to the peripheral region, the base layer extends from the cell region to the peripheral region, the contact hole extends from the cell region to the peripheral region, and the first electrode is connected to the base layer through the contact hole even in the peripheral region.

[0008] According to this, when the vertical semiconductor device performs an avalanche operation, carriers (e.g., holes) are easily extracted from the first electrode through the base layer in the peripheral region, which improves the avalanche resistance and suppresses the operation of a parasitic bipolar transistor.

[0009] Note that the reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and specific components described in the embodiments described below. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a plan view of a vertical semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view taken along line II-II in FIG. [Diagram 3] FIG. 2 is a cross-sectional view taken along line III-III in FIG. [Figure 4] 2 is a schematic diagram showing a circuit configuration of the vertical semiconductor device shown in FIG. [Diagram 5] FIG. 13 is a diagram showing the relationship between the adjustment distance and the avalanche resistance. [Figure 6] FIG. 11 is a cross-sectional view of a vertical semiconductor device according to a second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be denoted by the same reference numerals.

[0012] (First embodiment) A vertical semiconductor device according to a first embodiment will be described with reference to the drawings. The vertical semiconductor device according to the present embodiment is preferably mounted on a vehicle such as an automobile and used as a device for driving various electronic devices for the vehicle.

[0013] As shown in FIG. 1, the vertical semiconductor device of this embodiment has a cell region 1 and a peripheral region 2. As will be described later in detail, the vertical semiconductor device of this embodiment is configured by forming an n-channel MOSFET element having a source layer 14 as a semiconductor element. In this embodiment, the cell region 1 and the peripheral region 2 are divided depending on whether the source layer 14 is formed or not, and the part where the source layer 14 is formed is the cell region 1. In other words, the part that actually functions as a MOSFET element is the cell region 1, and the part that does not function as a MOSFET element is the peripheral region 2. In FIG. 1, an interlayer insulating film 20 and an upper electrode 21, which will be described later, are omitted. Although FIG. 1 is not a cross-sectional view, a gate insulating film 17 and a gate electrode 18, which will be described later, are hatched to make it easier to understand.

[0014] As shown in FIG. 2 and FIG. 3, the vertical semiconductor device of the present embodiment has a high impurity concentration. + The semiconductor substrate 10 has a substrate 11 made of a silicon substrate or the like. On the surface of the substrate 11, a n-type - In this embodiment, the substrate 11 functions as a drain region and corresponds to a high concentration layer.

[0015] A p-type base layer 13 having a relatively low impurity concentration is formed in a surface layer of the drift layer 12. The base layer 13 is formed, for example, by ion-implanting p-type impurities into the drift layer 12, and functions as a channel layer that forms a channel region. In this embodiment, the base layer 13 includes a base region 13a located on the drift layer 12 side, and a base contact region 13b having a higher impurity concentration than the base region 13a and formed on the base region 13a. The base layer 13 in this embodiment is formed from the cell region 1 to the outer periphery region 2.

[0016] In addition, the surface layer of the base layer 13 is provided with an n-type impurity layer having a higher impurity concentration than the drift layer 12.+ A source layer 14 of a type is formed in the trench 16. The source layer 14 is formed between a plurality of trenches 16 described later so as to be in contact with the side surface of the trench 16. The base contact region 13b is formed so as to be located on the opposite side of the trench 16 described later with the source layer 14 interposed therebetween.

[0017] In this embodiment, the region where the source layer 14 is formed is defined as the cell region 1. The base contact region 13b may be formed to coincide with the source layer 14 in the longitudinal direction (i.e., extension direction) of the trench 16 described later, or may be formed to protrude slightly from the cell region 1 to the outer periphery region 2. In this embodiment, the source layer 14 corresponds to the impurity layer. The semiconductor substrate 10 has the substrate 11 side defined as the other surface 10b and the base layer 13 and source layer 14 side defined as the first surface 10a.

[0018] In the semiconductor substrate 10, a plurality of trenches 16 are formed so as to penetrate the base layer 13 and the source layer 14 from the one surface 10a side to reach the drift layer 12. The plurality of trenches 16 are formed so as to be arranged along a direction intersecting one direction in the surface direction of the semiconductor substrate 10 as a longitudinal direction. More specifically, the plurality of trenches 16 are arranged in parallel at equal intervals to form a stripe-like layout. In FIG. 1, the trenches 16 are arranged so as to extend along the left-right direction of the paper as a longitudinal direction, and are arranged along the up-down direction of the paper. In addition, each trench 16 is formed so that both ends in the longitudinal direction protrude from the cell region 1 to the outer peripheral region 2.

[0019] The inner wall surface of the trench 16 is covered with a gate insulating film 17. A gate electrode 18 made of doped polysilicon is disposed in the trench 16 with the gate insulating film 17 interposed therebetween.

[0020] An interlayer insulating film 20 made of an oxide film or the like is formed on one surface 10a of the semiconductor substrate 10 so as to cover the gate electrode 18. In the interlayer insulating film 20, contact holes 20a are formed to expose the source layer 14 and the base layer 13.

[0021] Here, the contact hole 20a in this embodiment is formed so as to protrude beyond the source layer 14 in the longitudinal direction of the trench 16. In other words, the contact hole 20a is formed so as to also expose the base layer 13 located in the peripheral region 2. However, the contact hole 20a is formed so as to terminate closer to the cell region 1 side than the end of the trench 16 in the longitudinal direction. Note that the contact hole 20a is indicated by a dotted line in FIG. 1. That is, the region surrounded by the dotted line in FIG. 1 is the region exposed from the interlayer insulating film 20.

[0022] An upper electrode 21 corresponding to a source electrode is formed on the interlayer insulating film 20. Specifically, the upper electrode 21 is formed in the cell region 1 so as to be connected to the source layer 14 and the base contact region 13b (i.e., the base layer 13) through the contact hole 20a. The upper electrode 21 is also formed in the outer periphery region 2 so as to be connected to the base layer 13 through the contact hole 20a. In this embodiment, the upper electrode 21 corresponds to a first electrode.

[0023] A lower electrode 22 corresponding to a drain electrode is formed on the other surface 10b side of the substrate 11. In this embodiment, the lower electrode 22 corresponds to a second electrode.

[0024] The above is the configuration of the vertical semiconductor device in this embodiment. - type, n type, n + The type corresponds to the first conductivity type, and p type, p + The type corresponds to the second conductivity type. In this embodiment, as described above, the semiconductor substrate 10 is configured to include the substrate 11, the drift layer 12, the base layer 13, the source layer 14, and the like.

[0025] Next, the operation and effects of the vertical semiconductor device will be described. First, in the vertical semiconductor device as described above, a voltage equal to or higher than the threshold voltage in the insulated gate structure is applied to the gate electrode 18, whereby a channel region is formed in the base layer 13 in contact with the trench 16, and a current flows between the source and drain, thereby turning the device into an ON state. When the voltage applied to the gate electrode 18 becomes lower than the threshold voltage, the channel region formed in the base layer 13 disappears, and the current is cut off, turning the device into an OFF state.

[0026] The vertical semiconductor device as described above has a circuit configuration as shown in Fig. 4. That is, the vertical semiconductor device in this embodiment has a circuit configuration including a MOS transistor MTr, a parasitic bipolar transistor PTr formed by a drift layer 12, a base layer 13, and a source layer 14, a depletion capacitance DC, and an internal resistance R of the base layer 13. In the vertical semiconductor device as described above, when the device is switched from an on state to an off state, avalanche breakdown may occur, causing an excessive current to flow between the source and drain.

[0027] Therefore, in this embodiment, the contact hole 20a is extended to the peripheral region 2, and the base layer 13 is electrically connected to the upper electrode 21 in the peripheral region 2. As a result, when the vertical semiconductor device performs an avalanche operation, holes are easily extracted from the upper electrode 21 through the base layer 13 in the peripheral region 2. In other words, the region where the internal resistance R of the base layer 13 is small increases. Therefore, the avalanche resistance can be improved, and the operation of the parasitic bipolar transistor PTr can be suppressed.

[0028] Here, as shown in FIG. 4, the length of the contact hole 20a protruding from the cell region 1 to the peripheral region 2 is set as the adjustment distance d. That is, the length of the contact hole 20a protruding from the source layer 14 to the peripheral region 2 is set as the adjustment distance d. In other words, the length of the base layer 13 connected to the upper electrode 21 in the peripheral region 2 along the longitudinal direction of the trench 16 is set as the adjustment distance d. In this case, the longer the adjustment distance d, the easier it is to extract holes from the upper electrode 21. However, according to the study by the present inventors, as shown in FIG. 5, it was confirmed that the avalanche resistance is almost unchanged when the adjustment distance d is 0.1 μm or more. Therefore, in this embodiment, the adjustment distance d is set to 0.1 μm or more.

[0029] In addition, in FIG. 5, the substrate 11 is 1×10 18 ~1×10 20 cm -3 , drift layer 12 is 1×10 16 ~1×10 18 cm -3 , the base region 13a is 1×10 13 cm -3 , the base contact region 13b is 1×10 15 ~1×10 16 cm -3 About 1×10 13 cm -3 The results show the extent to which

[0030] As described above, in this embodiment, the contact hole 20a extends from the cell region 1 to the peripheral region 2, and the upper electrode 21 is connected to the base layer 13 also in the peripheral region 2. Therefore, when the vertical semiconductor device performs an avalanche operation, holes are easily extracted from the upper electrode 21 through the base layer 13 in the peripheral region 2. This makes it possible to improve the avalanche resistance and suppress the operation of the parasitic bipolar transistor PTr.

[0031] (1) In this embodiment, the adjustment distance is set to 0.1 μm or more, which makes it possible to sufficiently increase the avalanche resistance.

[0032] Second embodiment A second embodiment will be described. This embodiment differs from the first embodiment in that a trench contact is formed. As the rest is the same as the first embodiment, a description thereof will be omitted here.

[0033] 6, in the present embodiment, a contact trench 23 is formed in the semiconductor substrate 10 so as to communicate with the contact hole 20a formed in the interlayer insulating film 20. More specifically, the contact trench 23 is formed so as to coincide with the contact hole 20a in the normal direction to the one surface 10a of the semiconductor substrate 10. That is, the contact trench 23 has an adjustment distance d from the cell region 1 of 0.1 μm or more, similar to the contact hole 20a.

[0034] The source layer 14 in this embodiment has a source region 14a located on the gate insulating film 17 side, and a source contact region 14b having a higher impurity concentration than the source layer 14 and formed so as to be in contact with the side surface of the contact trench 23. The base contact region 13b is formed so as to be in contact with the bottom surface of the contact trench 23.

[0035] According to the present embodiment described above, the contact hole 20a extends from the cell region 1 to the peripheral region 2, and the upper electrode 21 is connected to the base layer 13 also in the peripheral region 2. Therefore, the same effects as those of the first embodiment can be obtained.

[0036] Here, for example, it is also possible to form a configuration in which the contact hole 20a and the contact trench 23 are not extended to the peripheral region 2, but a separate contact hole is formed in the peripheral region 2 to connect the upper electrode 21 to the base layer 13 in the peripheral region 2. However, in this configuration, the process of forming the contact trench 23 and the contact hole 20a and the process of forming the separate contact hole must be performed separately, which increases the number of manufacturing steps. In other words, the vertical semiconductor device of this embodiment can obtain the same effects as the first embodiment while suppressing an increase in the number of manufacturing steps.

[0037] (1) In this embodiment, a contact trench 23 is formed in the semiconductor substrate 10, and the source contact region 14b and the base contact region 13b are formed to be in contact with the contact trench 23. This makes it easier to ensure the connection area with the upper electrode 21, and shortens the length between adjacent trenches 16. This allows the on-resistance to be reduced, and the vertical semiconductor device to be miniaturized.

[0038] (Other embodiments) Although the present disclosure has been described based on the embodiment, it is understood that the present disclosure is not limited to the embodiment or structure. The present disclosure also encompasses various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure.

[0039] For example, in each of the above embodiments, an n-channel type trench gate structure MOSFET in which the first conductivity type is n-type and the second conductivity type is p-type has been described as an example. However, the vertical semiconductor device may be configured by forming a p-channel type trench gate structure MOSFET in which the conductivity types of each component are inverted with respect to the n-channel type. Furthermore, the vertical semiconductor device may be configured by forming an IGBT of a similar structure in addition to the MOSFET. In the case of an IGBT, the n-channel type MOSFET in each of the above embodiments may be formed by forming a p-channel type trench gate structure MOSFET in which the conductivity types of each component are inverted with respect to the n-channel type. + The substrate 11 is + Except for the change to a collector layer of the type described above, this embodiment is similar to the vertical MOSFET described in the first embodiment.

[0040] In addition, in each of the above embodiments, the semiconductor substrate 10 is a silicon substrate. However, the semiconductor substrate 10 may be a silicon carbide substrate or a gallium nitride substrate.

[0041] In each of the above embodiments, the base contact region 13b may not be formed, and the base layer 13 may be directly connected to the upper electrode 21. In the above first embodiment, the source contact region 14b may be formed so as to be connected to the upper electrode 21, and in the above second embodiment, the source contact region 14b may not be formed. [Explanation of symbols]

[0042] 1 cell area 2 Outer area 10a one side 11 Substrate (high concentration layer) 12 Drift Layer 13 Base Layer 14 Source layer (impurity layer) 16 Trench 17 Gate insulating film 18 Gate electrode 20 Interlayer insulating film 20a Contact Hole 21 Upper electrode (1st electrode) 22 Lower electrode (second electrode)

Claims

1. A vertical semiconductor device having a semiconductor element having a trench gate structure, The semiconductor substrate (10) includes a cell region (1) in which the semiconductor element is formed, and an outer periphery region (2) surrounding the cell region, The cell region is A drift layer (12) of a first conductivity type; a base layer (13) of a second conductivity type formed on the drift layer; a first conductivity type impurity layer (14) formed in a surface layer portion of the base layer and having a higher impurity concentration than the drift layer; the trench gate structure in which a gate electrode (18) is disposed through a gate insulating film (17) in a trench (16) extending along a surface direction of the semiconductor substrate, the trench (16) penetrating the impurity layer and the base layer to reach the drift layer; a high-concentration layer (11) of a first conductivity type or a second conductivity type, which is formed on the opposite side of the drift layer from the base layer and has a higher impurity concentration than the drift layer; an interlayer insulating film (20) formed on one surface (10a) of the semiconductor substrate and having contact holes (20a) for exposing the base layer and the impurity layer; a first electrode (21) electrically connected to the impurity layer and the base layer through the contact hole; A second electrode (22) electrically connected to the high concentration layer, a region in which the impurity layer is formed is defined as the cell region; the trench gate structure extends from the cell region to the periphery region, The base layer extends from the cell region to the outer periphery region, the contact hole extends from the cell region to the outer periphery region, the first electrode is connected to the base layer through the contact hole even in the peripheral region; A vertical semiconductor device in which the length of the contact hole along the extension direction of the trench in the peripheral region is an adjustment distance (d), and the adjustment distance is 0.1 μm or more (excluding 5 μm or more).

2. A contact trench (23) communicating with the contact hole is formed in the semiconductor substrate, the impurity layer is formed in contact with a side surface of the contact trench, 2. The vertical semiconductor device according to claim 1, wherein the base layer is formed in contact with a bottom surface of the contact trench.

Images