Silicon carbide substrate, silicon carbide wafer, and silicon carbide semiconductor device

Abstract

To suppress the generation of wrapping.SOLUTION: In a silicon carbide substrate, a Young ratio to be measured by a resonance method becomes 475 GPa or more at 500°C.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a SiC substrate made of silicon carbide (hereinafter also referred to as SiC), and a SiC wafer and a SiC semiconductor device using the same. [Background technology]

[0002] Conventionally, a SiC semiconductor device has been proposed in which an epitaxial layer of SiC is grown on a substrate made of SiC to form a SiC wafer, and a semiconductor element such as a MOSFET is formed using this SiC wafer (see, for example, Non-Patent Document 1). Note that MOSFET is an abbreviation for metal oxide semiconductor field effect transistor.

[0003] The above-mentioned SiC semiconductor device has, for example, the following configuration. That is, the SiC semiconductor device has an n-type substrate, an n-type drift layer arranged on the substrate, a p-type base layer arranged on the drift layer, and an n-type source region formed in a surface layer portion of the base layer. The SiC semiconductor device also has a trench gate structure formed to penetrate the source region and reach the drift layer, a first electrode electrically connected to the base layer and the source region, and a second electrode connected to the substrate.

[0004] Such a SiC semiconductor device is manufactured as follows. First, an n-type epitaxial layer is arranged on a substrate to form a SiC wafer. Next, ion implantation and activation annealing are performed to form a base layer, source region, etc., and a trench gate structure. After that, the SiC wafer is divided into chips to manufacture the device. [Prior art documents] [Non-patent literature]

[0005] [Non-Patent Document 1] S.Harada et al, First Demonstration of Dynamic Characteristics for SiC Superjunction MOSFET Realized using Multi-epitaxial Growth Method IEEE International Electron Devices Meeting (IEDM), pp. 8.2.1, Dec. 2018. Summary of the Invention [Problem to be solved by the invention]

[0006] Meanwhile, according to the study by the present inventors, it has been confirmed that, when manufacturing the above-mentioned SiC semiconductor device, warping may occur in the SiC wafer during ion implantation, activation annealing, etc. If each manufacturing step is performed in a warped state, this may cause the SiC wafer to crack or cause characteristic defects of the SiC semiconductor device.

[0007] In view of the above, an object of the present invention is to provide a SiC substrate capable of suppressing the occurrence of warping, and a SiC wafer and a SiC semiconductor device using the same. [Means for solving the problem]

[0008] Claim 1 for achieving the above object is a SiC substrate, the Young's modulus of which, as measured by a resonance method, is 475 GPa or more at 500°C.

[0009] According to this, when a SiC wafer is constructed by growing an epitaxial layer on a SiC substrate and a semiconductor device is manufactured using this SiC wafer, warping of the SiC wafer can be suppressed.

[0010] Claim 5 provides a SiC wafer, comprising the SiC substrate according to claim 1 and an epitaxial layer (20) formed on the SiC substrate, the epitaxial layer having a thickness of 4 to 40 μm.

[0011] According to this, since the SiC wafer is constructed using the above-mentioned SiC substrate, warping of the SiC wafer can be suppressed when a semiconductor device is manufactured using the SiC wafer.

[0012] Claim 8 is a SiC semiconductor device comprising the substrate according to claim 1 and an epitaxial layer (20) formed on the SiC substrate, and a semiconductor element is formed that passes a current along the stacking direction of the substrate and the epitaxial layer.

[0013] According to this, since the SiC semiconductor device is configured using the above-mentioned SiC substrate, the occurrence of characteristic fluctuations can be suppressed.

[0014] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and specific components described in the embodiments described below. [Brief description of the drawings]

[0015] [Figure 1] 1 is a cross-sectional view of a SiC semiconductor device in a first embodiment. [Diagram 2] FIG. 1 is a cross-sectional view of a SiC wafer. [Diagram 3] FIG. 11 is a diagram showing the relationship between each manufacturing process and the amount of warping. [Figure 4] FIG. 13 is a diagram for explaining the amount of warping. [Diagram 5] FIG. 1 is a diagram showing the relationship between temperature and Young's modulus. [Figure 6] FIG. 1 is a diagram showing contaminants in a substrate. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be denoted by the same reference numerals.

[0017] (First embodiment) A SiC semiconductor device according to a first embodiment will be described with reference to FIG. 1. In this embodiment, a SiC semiconductor device in which a MOSFET is formed as a semiconductor element will be described as an example. Although not shown in the figure, the SiC semiconductor device according to this embodiment has a cell region and an outer peripheral region formed to surround the cell region. The MOSFET shown in FIG. 1 is formed in the cell region of the SiC semiconductor device.

[0018] The SiC semiconductor device is a n-type + The present embodiment is configured using a substrate 10 of a type. An epitaxial layer 20 made of SiC is disposed on the surface of the substrate 10. The epitaxial layer 20 of the present embodiment is an n - Buffer layer 21, n - In the epitaxial layer 20 of this embodiment, a p-type drift layer 22, a p-type base layer 23, and a p-type base layer 23 are arranged in this order. The epitaxial layer 20 of this embodiment has a thickness of about 4 to 40 μm, and an impurity concentration of 1.0×10 15 ~1.0×10 19 cm -3 The configuration has a portion as described above.

[0019] The surface layer of the base layer 23 is + A source region 24 of a type is formed. Note that the base layer 23 and the source region 24 of this embodiment are formed by ion implantation.

[0020] The substrate 10 has, for example, a resistivity of 30 mΩ·cm or less, a (0001) Si surface, and an off angle of 0.5 to 5° with respect to the (0001) Si surface. 18 ~1.0×10 20 cm -3 The substrate 10 has a thickness of, for example, 300 to 600 μm. In this embodiment, the substrate 10 corresponds to a silicon carbide substrate. In this embodiment, the substrate 10 constitutes a drain layer in a MOSFET.

[0021] The buffer layer 21 has an n-type impurity concentration of, for example, 1.0×10 18 ~1.0×10 19 cm -3 The drift layer 22 has an n-type impurity concentration of, for example, 1.0×10 15 ~5.0×10 16 cm -3 It is said that.

[0022] The base layer 23 is a portion where a channel region is formed, and has a p-type impurity concentration of, for example, 3.0×10 17 cm -3 The source region 24 has a higher impurity concentration than the drift layer 22. For example, the n-type impurity concentration in the surface layer is 2.5×10 18 ~1.0×10 19 cm -3 The thickness is about 0.5 to 2 μm. The film thicknesses of the drift layer 22, the base layer 23 and the source region 24 are arbitrary and are not limited to the above.

[0023] Further, a trench 30 is formed so as to penetrate the base layer 23 and the source region 24 and reach the drift layer 22. The base layer 23 and the source region 24 are disposed so as to contact the side surface of the trench 30. Although only one trench 30 is illustrated in FIG. 1, the actual trench 30 is formed in a stripe shape with a plurality of trenches 30 disposed at equal intervals in the left-right direction of the page.

[0024] A gate insulating film 31 is formed on the inner wall surface of the trench 30. A gate electrode 32 made of doped poly-Si is formed on the surface of the gate insulating film 31. The trench 30 is completely filled with the gate insulating film 31 and the gate electrode 32. In this embodiment, a trench gate structure is configured in this manner.

[0025] On the epitaxial layer 20, an upper electrode 41 is disposed as a source electrode insulated from the gate electrode 32 and connected to the base layer 23 and the source region 24. Although omitted in FIG. 1, an interlayer insulating film is actually formed on the epitaxial layer 20, and the upper electrode 41 is connected to the base layer 23 and the source region 24 through a contact hole formed in the interlayer insulating film. The upper electrode 41 of this embodiment is made of a plurality of metals such as Ni / Al. Among the plurality of metals, a portion that contacts a portion that constitutes n-type SiC (i.e., the source region 24) is made of a metal that can make ohmic contact with n-type SiC. Among the plurality of metals, a portion that contacts at least p-type SiC (i.e., the base layer 23) is made of a metal that can make ohmic contact with p-type SiC.

[0026] A lower electrode 42 is formed on the back surface side of the substrate 10 as a drain electrode electrically connected to the substrate 10. In this embodiment, this structure constitutes an n-channel type inversion type trench gate structure MOSFET. A cell region is constituted by arranging a plurality of such MOSFETs.

[0027] The above is the basic configuration of the SiC semiconductor device in this embodiment. In such a SiC semiconductor device, when a predetermined gate voltage is applied to the gate electrode 32, an inversion layer is formed in the portion of the base layer 23 that contacts the trench 30, and a current flows between the upper electrode 41 and the lower electrode 42. In other words, a current flows along the stacking direction of the substrate 10 and the epitaxial layer 20.

[0028] The above-described SiC semiconductor device is manufactured as follows.

[0029] That is, first, as shown in FIG. 2, a wafer-shaped substrate 10 is prepared, and an epitaxial layer 20 is grown on the substrate 10 to form a SiC wafer 50. The wafer-shaped substrate 10 is, for example, a 6-inch one, but an 8-inch one may also be used. Next, although not shown in detail, ion implantation and activation annealing are performed on the epitaxial layer 20 to form a base layer 23, a source region 24, etc., and a trench gate structure is also formed. Thereafter, an interlayer insulating film, an upper electrode 41, a lower electrode 42, etc. are formed, and the SiC wafer 50 is divided into chip units to manufacture the above-mentioned SiC semiconductor device.

[0030] Here, according to the study by the present inventors, it has been confirmed that even if the manufacturing process such as ion implantation is performed under the same conditions, the amount of warpage may differ depending on the SiC wafer 50 (i.e., the substrate 10) used, as shown in FIG. 3. Note that "received" in FIG. 3 indicates that the SiC wafer 50 having the epitaxial layer 20 arranged on the substrate 10 is placed in the manufacturing device. Also, FIG. 3 shows the results of preparing three samples of the SiC wafer 50, namely, SiC wafer A, SiC wafer B, and SiC wafer C. Furthermore, FIG. 3 shows the results of performing multiple ion implantations (i.e., the first to seventh ion implantations in FIG. 3) when forming the base layer 23 and the source region 24.

[0031] Furthermore, the results in FIG. 3 confirm that when the manufacturing process was performed using SiC wafer A, the amount of warpage was larger than when the manufacturing process was performed using SiC wafer B or SiC wafer C.

[0032] The amount of warpage here is what is called BOW. More specifically, the amount of warpage is as follows. That is, as shown in FIG. 4, a plane passing through the center of the thickness t of the SiC wafer 50 (i.e., t / 2) is defined as a reference plane RP. Also, a plane connecting the centers of the thickness t of the SiC wafer 50 (i.e., t / 2) at both sides of the center C in the surface direction of the side surface of the SiC wafer 50 is defined as a virtual plane VP. In this embodiment, the distance between the reference plane RP at the center C and the virtual plane VP is defined as the amount of warpage when the SiC wafer 50 is held without vacuum suction.

[0033] In this case, it is currently desired to keep the amount of warpage in each manufacturing process to 200 μm or less. Therefore, in the results shown in Figure 3, the current requirements can be met when SiC wafer B and SiC wafer C are used.

[0034] Furthermore, the inventors of the present invention have conducted extensive research into the amount of warpage and obtained the results shown in Figs. 5 and 6. First, as shown in Fig. 5, Young's modulus was measured by the resonance method, and it was confirmed that SiC wafer A, which has a large amount of warpage, has a smaller Young's modulus than SiC wafer B and SiC wafer C, which have a small amount of warpage. Measuring Young's modulus by the resonance method is a method of measuring the resonant frequency while maintaining the sample at a constant temperature and deriving Young's modulus based on the measured resonant frequency. Also, in Fig. 5, Young's modulus is measured in the state of SiC wafer 50.

[0035] As shown in FIG. 6, it was confirmed that SiC wafer A, which has a small Young's modulus, has more contaminating impurities than SiC wafer B and SiC wafers, which have a large Young's modulus. In other words, it is confirmed from FIG. 5 and FIG. 6 that the more contaminating impurities contained in the substrate 10, the smaller the Young's modulus becomes. Note that FIG. 6 shows the results of a SIMS analysis, and the lower detection limit is a small amount that cannot be detected by the SIMS analysis. Also, the contaminating impurities are impurities that may be mixed in when preparing the substrate 10, and currently, the main impurities include aluminum (Al), boron (B), titanium (Ti), and vanadium (V).

[0036] As described above, SiC wafer B and SiC wafer C can satisfy the current requirements. Therefore, from FIG. 5, it is sufficient for substrate 10 to have a Young's modulus of 475 GPa or more at 500° C. Also, it is sufficient for substrate 10 to have a Young's modulus of 465 GPa or more at 1000° C. Furthermore, from FIG. 6, it is sufficient for substrate 10 to have a total amount of contaminants of 1.0×10 16 atoms / cm 3 It is sufficient if the temperature is equal to or lower than the above. Therefore, the substrate 10 of this embodiment satisfies these requirements. Note that 500°C is a temperature that is maintained so as to reduce crystal damage when ion implantation is performed on the SiC wafer 50. 1000°C is the upper limit temperature at which measurement accuracy is guaranteed in measuring Young's modulus using the current resonance method.

[0037] Here, the substrate is usually obtained by cutting a SiC ingot. Specifically, the SiC ingot is obtained by a high-temperature CVD (short for chemical vapor deposition) method or a sublimation method. More specifically, when manufacturing a SiC ingot by a high-temperature CVD method, a seed substrate made of SiC is placed in a chamber, and while controlling the temperature in the chamber by a heating device arranged around the chamber, a reaction gas such as silane or propane is introduced into the chamber to grow an epitaxial layer on the seed substrate. When manufacturing a SiC ingot, contaminant impurities in the chamber may be taken in. For this reason, when manufacturing a SiC ingot by a high-temperature CVD method, it is preferable to use a high-purity gas or to make each member such as the chamber out of a high-purity material.

[0038] Furthermore, when manufacturing a SiC ingot by sublimation, a seed substrate made of SiC is placed in a chamber, and SiC powder is sublimated to grow an epitaxial layer on the seed substrate. When manufacturing a SiC ingot, contaminant impurities in the chamber and in the powder may be introduced. For this reason, when manufacturing a SiC ingot by sublimation, it is preferable to use high-purity powder and to make each member such as the chamber out of a high-purity material. As a result, the total amount of contaminant impurities contained in the substrate 10 is reduced to 1.0×10 16 atoms / cm 3 This becomes easier as follows.

[0039] In manufacturing a SiC semiconductor device, by using a substrate 10 having a Young's modulus of 475 GPa or more at 500° C. as measured by a resonance method, warping of the SiC wafer 50 during the manufacturing process can be suppressed.

[0040] The Young's modulus of the substrate 10 is preferably measured before growing the epitaxial layer 20. However, in this embodiment, the substrate 10 has a thickness of about 300 μm to 600 μm, and the epitaxial layer has a thickness of about 4 to 40 μm. Therefore, the influence of the epitaxial layer 20 is sufficiently small compared to the influence of the substrate 10 and can be ignored, so the Young's modulus may be measured after growing the epitaxial layer 20. FIG. 5 shows the result after growing the epitaxial layer 20.

[0041] Furthermore, in order to suppress warping due to the Twyman effect, the substrate 10 may have one surface on which the epitaxial layer 20 is grown and the other surface opposite to the one surface polished by CMP (short for Chemical Mechanical Polishing) or the like. Furthermore, the thickness of the substrate 10 is set to 300 to 600 μm, but it may be made thicker in the range of 300 to 600 μm (for example, about 500 μm) so as to be more resistant to warping.

[0042] According to the present embodiment described above, the substrate 10 has a Young's modulus of 475 GPa or more at 500° C. This makes it possible to suppress warping of the SiC wafer 50 during manufacturing of the SiC semiconductor device. This makes it possible to suppress cracking of the SiC wafer 50 and fluctuations in the characteristics of the SiC semiconductor device.

[0043] (1) In this embodiment, the substrate 10 has a Young's modulus of 465 GPa or more at 1000° C., which can further prevent the SiC wafer 50 from warping during the high-temperature manufacturing process.

[0044] (2) In this embodiment, the substrate 10 has a contaminant impurity concentration of 1×10 16 atoms / cm 3 It is set as follows. Therefore, when manufacturing a SiC semiconductor device, it is possible to suppress warping of the SiC wafer 50. Therefore, it is possible to suppress cracking of the SiC wafer 50 and occurrence of fluctuations in the characteristics of the SiC semiconductor device.

[0045] (3) In this embodiment, the thickness of the substrate 10 is set to 300 to 600 μm, the resistivity of the substrate 10 is set to 30 mΩcm or less, and the n-type impurity concentration is set to 5.0×10 18 ~1.0×10 20 cm -3 The epitaxial layer 20 has a thickness of 4 to 40 μm and an impurity concentration of 1.0×10 15 ~1.0×10 19 cm -3 The buffer layer has a portion where the n-type impurity concentration is 1.0×10 18 ~1.0×10 19 cm -3 The drift layer 22 has an n-type impurity concentration of 1.0×10 15 ~5.0×10 16 cm -3 For this reason, it is possible to obtain a MOSFET having the currently desired characteristics.

[0046] (Other embodiments) Although the present disclosure has been described based on the embodiment, it is understood that the present disclosure is not limited to the embodiment or structure. The present disclosure also encompasses various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure.

[0047] For example, in each of the above embodiments, a SiC semiconductor device is described in which a MOSFET having an n-channel type trench gate structure in which the first conductivity type is n-type and the second conductivity type is p-type is formed. However, for example, a SiC semiconductor device may be formed in which a MOSFET having a p-channel type trench gate structure in which the conductivity types of each component are inverted with respect to the n-channel type is formed.

[0048] In addition, in each of the above embodiments, a SiC semiconductor device including a MOSFET has been described. However, the SiC semiconductor device may include a Schottky diode, a pn diode, or an IGBT.

[0049] (Features of the present invention)

[0050] [Claim 1] A silicon carbide substrate, A silicon carbide substrate with a Young's modulus of 475 GPa or more at 500°C, as measured by the resonance method.

[0051] [Claim 2] 2. The silicon carbide substrate according to claim 1, having a Young's modulus of 465 GPa or more at 1000° C. as measured by a resonance method.

[0052] [Claim 3] Containing contaminants of 1×10 16 atoms / cm 3 3. The silicon carbide substrate according to claim 1, wherein:

[0053] [Claim 4] The thickness is set to 300 to 600 μm, the resistivity is set to 30 m·Ω cm or less, and the n-type impurity concentration is set to 5.0×10 18 ~1.0×10 20 cm -3 4. The silicon carbide substrate according to claim 1, wherein:

[0054] [Claim 5] A silicon carbide wafer, A silicon carbide substrate according to any one of claims 1 to 4; an epitaxial layer (20) formed on the silicon carbide substrate; The epitaxial layer is a silicon carbide wafer having a thickness of 4 to 40 μm.

[0055] [Claim 6] The epitaxial layer has an impurity concentration of 1.0×10 15 ~1.0×10 19 cm -3 6. The silicon carbide wafer according to claim 5, comprising a portion having:

[0056] [Claim 7] The epitaxial layer has a buffer layer (21) located on the silicon carbide substrate side, and a drift layer (22) located on the buffer layer, The buffer layer has an n-type impurity concentration of 1.0×10 18 ~1.0×10 19 cm -3 It is said that, The drift layer has an n-type impurity concentration of 1.0×10 15 ~5.0×10 16 cm -3 7. The silicon carbide wafer according to claim 6, wherein:

[0057] [Claim 8] 1. A silicon carbide semiconductor device, comprising: A silicon carbide substrate according to any one of claims 1 to 4; an epitaxial layer (20) formed on the silicon carbide substrate; a silicon carbide semiconductor device including a semiconductor element formed therein, the semiconductor element passing a current along a stacking direction of the silicon carbide substrate and the epitaxial layer; [Explanation of symbols]

[0058] 10 Substrate 20 Epitaxial layer

Claims

1. A silicon carbide substrate, A silicon carbide substrate having a Young's modulus of 475 GPa or more at 500° C. as measured by a resonance method.

2. 2. The silicon carbide substrate according to claim 1, having a Young's modulus of 465 GPa or more at 1000° C. as measured by a resonance method.

3. The contaminant impurities contained are 1.0 x 10 １６ atoms / cm ３ The silicon carbide substrate according to claim 1 , wherein:

4. The thickness is set to 300 to 600 μm, the resistivity is set to 30 mΩcm or less, and the n-type impurity concentration is set to 5.0×10 １８ ~1.0 x 10 ２０ cm －３ The silicon carbide substrate according to claim 1 .

5. A silicon carbide wafer, A silicon carbide substrate according to claim 1 ; An epitaxial layer (20) formed on the silicon carbide substrate, The epitaxial layer is a silicon carbide wafer having a thickness of 4 to 40 μm.

6. The epitaxial layer has an impurity concentration of 1.0×10 １５ ~1.0 x 10 １９ cm －３ The silicon carbide wafer according to claim 5 , comprising a portion having:

7. The epitaxial layer has a buffer layer (21) located on the silicon carbide substrate side, and a drift layer (22) located on the buffer layer, The buffer layer has an n-type impurity concentration of 1.0×10 １８ ~1.0 x 10 １９ cm －３ It is said that, The drift layer has an n-type impurity concentration of 1.0×10 １５ ~5.0 x 10 １６ cm －３ The silicon carbide wafer according to claim 6 .

8. 1. A silicon carbide semiconductor device, comprising: A silicon carbide substrate according to claim 1 ; An epitaxial layer (20) formed on the silicon carbide substrate, a silicon carbide semiconductor device including a semiconductor element formed therein, the semiconductor element passing a current along a stacking direction of the silicon carbide substrate and the epitaxial layer;

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