Semiconductor device

Abstract

To provide a transistor including an oxide semiconductor with excellent electric characteristics by achieving miniaturization.SOLUTION: A transistor 120 includes, on an oxide insulating layer 106 provided on a substrate 100 with an insulating surface, an oxide semiconductor layer 108, source and drain electrode layers 110a, b, an insulating layer 112 covering the source and drain electrode layers and having an opening, a gate insulating layer 114 in contact with a part of the oxide semiconductor layer, and a gate electrode layer 116 overlapping with the oxide semiconductor layer and source and drain electrodes through the gate insulating layer. The widths of the source and drain electrode layers in a channel width direction are made smaller than the width of the oxide semiconductor layer and the overlap between the gate electrode layer and the source and drain electrode layers is reduced so as to reduce the parasitic capacitance. The source and drain electrode layers include, at a lower end part, a region protruding to a channel length direction, so that the electric field concentration is relieved. By the provision of the insulating layer 112, the parasitic capacitance between the source and drain electrode layers and the gate electrode layer is reduced.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The invention disclosed in this specification relates to a semiconductor device and a manufacturing method thereof.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This generally refers to electro-optical devices, light-emitting display devices, semiconductor circuits, and electronic devices, all of which are semiconductor devices. be. [Background technology]

[0003] A technology to construct transistors using semiconductor thin films formed on substrates with insulating surfaces The transistor is being used in integrated circuits (ICs) and image display devices (simply called display devices). It is widely used in semiconductor electronic devices such as transistors. Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used for this purpose, but other materials include Oxide semiconductors are attracting attention.

[0004] For example, zinc oxide or In-Ga-Zn oxide is used as the oxide semiconductor to produce a transistor. Techniques for producing a transistor have been disclosed (see Patent Documents 1 and 2).

[0005] In addition, Patent Document 3 discloses a source electrode and a drain electrode in contact with an oxide semiconductor layer, A gate electrode overlapping the semiconductor layer, and a gate electrode provided between the oxide semiconductor layer and the gate electrode. and an insulating layer, and the source electrode and the drain electrode are formed on the first conductive layer and on the edge of the first conductive layer. A transistor structure having a second conductive layer having a region extending in a channel length direction from the first conductive layer. It has been disclosed. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A [Patent Document 3] JP 2011-171721 A Summary of the Invention [Problem to be solved by the invention]

[0007] In order to achieve high-speed operation of transistors, miniaturization of transistors is required. When a transistor is miniaturized, the transistor, particularly the source electrode layer and the drain electrode layer, Since the electric field applied to the edge increases, a transistor structure with an electric field relaxation is required.

[0008] In order to operate a transistor at high speed, a gate electrode layer and a source electrode layer or a drain electrode layer are It is necessary to reduce the parasitic capacitance that can occur between the electrode layers.

[0009] In view of the above, one embodiment of the present invention is a semiconductor device including a source electrode layer and a drain electrode layer. To provide a transistor structure that realizes the mitigation of electric field concentration that may occur at the edge of a layer. This is one of the challenges.

[0010] Further, one embodiment of the present invention is a semiconductor device including a gate electrode layer and a source electrode layer or a drain electrode layer. To provide a transistor structure capable of reducing parasitic capacitance that may occur between a semiconductor device and an insulator layer. One of the objectives of the project is to

[0011] Another embodiment of the present invention is a transistor including an oxide semiconductor that is miniaturized and has excellent electrical characteristics. One object is to provide a transistor.

[0012] One embodiment of the invention disclosed in this specification achieves at least one of the above objects. be. [Means for solving the problem]

[0013] In one embodiment of the present invention, a source electrode layer and a drain electrode layer sandwiching a channel formation region are The source electrode layer and the drain electrode layer have a region protruding in the channel length direction. A transistor having an insulating layer provided between the gate electrode layer and the gate insulating layer. The transistor has a source electrode layer and a drain electrode layer in a channel width direction. By making the width of the gate electrode layer and the source electrode layer smaller than the width of the oxide semiconductor layer, The overlap with the drain electrode layer is reduced to reduce parasitic capacitance. The electrode layer and the drain electrode layer have a region protruding in the channel length direction at the lower end thereof, The electric field concentration can be alleviated, and the presence of the insulating layer makes it possible to The parasitic capacitance between the gate electrode layer and the gate electrode layer can be reduced. For example, the following configuration may be used.

[0014] One embodiment of the present invention is a single-layer insulating film provided on and in contact with an island-shaped oxide semiconductor layer. A source electrode layer and a drain electrode layer each made of a conductive layer a gate insulating layer provided over the insulating layer and in contact with a part of the oxide semiconductor layer; A gate insulating layer, an oxide semiconductor layer, a source electrode layer, and a drain electrode layer are formed on the oxide semiconductor layer through the gate insulating layer. a gate electrode layer overlapping the source electrode layer and the drain electrode layer; The source electrode layer has a region protruding in a channel length direction and overlaps with the gate electrode layer. The lower ends of the source electrode layer and the drain electrode layer are located on the oxide semiconductor layer, and The width of the opening in the insulating layer is greater than the distance between the source electrode layer and the drain electrode layer. The width of the opening of the insulating layer in the channel width direction is smaller than the width of the gate electrode layer. The width of the gate electrode layer is smaller than that of the drain electrode layer.

[0015] In the above semiconductor device, the thickness of the oxide semiconductor layer in the region in contact with the gate insulating layer is The thickness of the gate electrode layer is smaller than that of a region that overlaps with the gate electrode layer and is in contact with the source electrode layer or the drain electrode layer. It is preferable that the size is small.

[0016] In the above semiconductor device, the oxide semiconductor layer is provided below the oxide semiconductor layer. It is preferable that an oxide insulating layer containing one or more metal elements selected from the following is provided in contact with the oxide insulating layer. In addition, the oxide insulating layer is preferably an oxide insulating layer containing gallium oxide. In addition, a conductive layer overlapping with the oxide semiconductor layer with the oxide insulating layer interposed therebetween is preferably provided. stomach.

[0017] In the above semiconductor device, the gate insulating layer is made of an element selected from the constituent elements of the oxide semiconductor layer. It is preferable that the oxide insulating layer contains one or more metal elements.

[0018] In this specification, the term "substantially the same" is used in a sense that does not require strict agreement. For example, the expression "substantially the same" refers to a pattern obtained by etching multiple layers using the same mask. The term includes the degree of agreement in the shapes obtained. Effect of the Invention

[0019] According to one embodiment of the present invention, a source electrode layer and a drain electrode layer each including an oxide semiconductor It is possible to provide a transistor structure that alleviates electric field concentration that may occur in the .

[0020] According to one embodiment of the present invention, a gate electrode layer and a source electrode layer or The present invention provides a transistor structure capable of reducing parasitic capacitance that may occur between a drain electrode layer and the transistor. can be provided.

[0021] According to one embodiment of the present invention, an oxide semiconductor having excellent electrical characteristics can be obtained by miniaturization. A transistor including the [Brief description of the drawings]

[0022] [Figure 1] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Diagram 2] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Diagram 3] FIG. 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 4] 1A to 1C illustrate an example of a method for manufacturing a semiconductor device. [Diagram 5] 1A to 1C illustrate an example of a method for manufacturing a semiconductor device. [Figure 6] 1A and 1B are a cross-sectional view and a circuit diagram illustrating one embodiment of a semiconductor device. [Figure 7] 1A and 1B are a circuit diagram and a perspective view illustrating one embodiment of a semiconductor device. [Figure 8] 1A and 1B are a cross-sectional view and a circuit diagram illustrating one embodiment of a semiconductor device. [Figure 9] 1A and 1B are a block diagram and a partial circuit diagram illustrating one embodiment of a semiconductor device. [Figure 10] 1A to 1C are diagrams illustrating electronic devices. [Figure 11] 1A to 1C are diagrams illustrating electronic devices. [Figure 12] 1A to 1C are diagrams illustrating electronic devices. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] Hereinafter, the embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and various modifications in form and details are possible by those skilled in the art. Therefore, the present invention should not be construed as being limited to the following description of the embodiments. It is not something that can be achieved.

[0024] In the configuration of the present invention described below, the same parts or parts having similar functions are The same reference numerals are used in common between different drawings, and the repeated explanations are omitted. When referring to a part having the same function, the hatch pattern is the same and no particular symbol is attached. There are cases.

[0025] In each figure described in this specification, the size, thickness, or area of ​​each component is not clearly indicated. The figures may be exaggerated for illustrative purposes and are not necessarily limited to scale.

[0026] In this specification, the ordinal numbers such as 1st, 2nd, etc. are used for convenience. It does not indicate the order of steps or the order of layers. It does not indicate a specific name for the purpose of reference.

[0027] (Embodiment 1) In this embodiment mode, one embodiment of a semiconductor device and a manufacturing method thereof will be described with reference to FIGS. In this embodiment, a semiconductor device having an oxide semiconductor layer will be described as an example. A transistor is shown.

[0028] 1A to 1C show examples of a structure of a transistor 120. FIG. 1B is a plan view of the resistor 120, and FIG. 1B is a cross-sectional view taken along the dashed line X1-Y1 in FIG. 1(C) is a cross-sectional view taken along the dashed line V1-W1 in FIG. 1(A).

[0029] As shown in FIG. 1B, the transistor 120 is provided on a substrate 100 having an insulating surface. An island-shaped oxide semiconductor layer 108 is formed on the oxide insulating layer 106. A source electrode layer 110a and a drain electrode layer 110b are provided in contact with the source electrode layer An insulating layer 112 having an opening and covering the drain electrode layer 110a and the drain electrode layer 110b; a gate insulating layer 114 provided on the gate insulating layer 12 and in contact with a part of the oxide semiconductor layer 108; The oxide semiconductor layer 108, the source electrode layer 110a, and the drain electrode layer 110b are formed with the insulating layer 114 interposed therebetween. The gate electrode layer 116 overlaps the layer 110b. An insulating layer 118 disposed over 116 may be added to the component.

[0030] In the transistor 120, the source electrode layer 110a and the drain electrode layer 110b are formed by a single The channel is made of a metal layer with multiple etching processes during the fabrication process. The lower end of the channel 111a and the lower end of the channel 111b are in contact with the channel forming region. The gate insulating layer 114 is formed between the region 111a and the region 111b and the oxide semiconductor layer 10. It is provided so as to be in contact with a part of 8.

[0031] Generally, the gate insulating layer of a top-gate transistor is a source electrode layer and a drain electrode layer. In the region covering the end of the electrode layer, there is a step caused by the film thickness of the electrode layer, and in the step portion The film thickness is locally smaller than other regions. In such a thin region, Because the dielectric breakdown voltage is low, the electric field is concentrated in the region, causing the transistor to break down. Also, gate leakage may occur from the thin film area. As the size of the gate electrodes decreases, the difference in thickness between the wiring layer and the gate insulating layer becomes larger, and this problem becomes more serious. becomes more pronounced.

[0032] However, in the transistor 120, the source electrode layer 110a and the drain electrode In the layer 110b, a protruding region (11 1a, 111b) are provided to gradually reduce the thickness of the film at the periphery, and a gate is provided to cover the region. The insulating layer 114 is formed. By providing the region, the gate insulating layer 114 is locally It is possible to prevent the formation of areas with a small thickness in certain places, which reduces the concentration of electric field. As a result, the dielectric breakdown voltage of the transistor 120 can be improved, and In addition, the coverage of the gate insulating layer 114 is improved, and the occurrence of breaks is prevented. This can prevent connection problems.

[0033] The regions 111a and 111b of the source electrode layer 110a and the drain electrode layer 110b are In the process of forming the source electrode layer 110a and the drain electrode layer 110b, etching is performed multiple times. The source electrode layer 110a and The drain electrode layer 110b also has a lower end portion in the channel width direction that protrudes in the channel width direction. In this way, adjacent regions (regions 111c and 111d shown in FIG. 1B) are formed.

[0034] The insulating layer 112 is provided to cover the source electrode layer 110a and the drain electrode layer 110b. The insulating layer 112 has an opening in a region overlapping with the channel formation region. Parasitic between the source electrode layer 110a and the drain electrode layer 110b and the gate electrode layer 116 As shown in FIG. 1(A), the capacitance can be reduced. The width of the portion is greater than the distance between the source electrode layer 110a and the drain electrode layer 110b, and and is smaller than the width of the gate electrode layer 116. In addition, the width of the opening in the channel width direction is It is smaller than the width of the source electrode layer 110a and the drain electrode layer 110b.

[0035] As shown in FIG. 1A, the source electrode layer 1 The width of the drain electrode layer 110a and the drain electrode layer 110b in the channel width direction is That is, in the region overlapping with the gate electrode layer 116, The bottom ends of the source electrode layer 110a and the drain electrode layer 110b are formed on the oxide semiconductor layer 108. By adopting such an arrangement, the gate electrode layer 116 and the source electrode layer 1 The overlap between the drain electrode layer 110a and the drain electrode layer 110b can be reduced, and the occurrence of parasitic capacitance can be reduced. This can be further suppressed.

[0036] In the oxide semiconductor layer 108 included in the transistor 120, The thickness of the region in contact with the source electrode layer 110a and the drain electrode layer 110b is The region with a small thickness is smaller than the thickness of the source electrode layer 110a and the drain electrode layer 1 When processing the conductive film that becomes 10b, a part of the conductive film is etched, or the source electrode The exposed area of ​​the oxide semiconductor layer 108 after forming the layer 110a and the drain electrode layer 110b. The thin film region is formed by etching the transistor. This region functions as a channel forming region of the transistor 120. By reducing the resistance of the region in contact with the source electrode layer 110a and the drain electrode layer 110b, Therefore, the source electrode layer 110a and the channel formation region can be reduced in the This makes it possible to reduce the contact resistance with the drain electrode layer 110b.

[0037] The structure of the oxide semiconductor layer will be described below.

[0038] The oxide semiconductor layer is roughly classified into a single crystal oxide semiconductor layer and a non-single crystal oxide semiconductor layer. The single-crystal oxide semiconductor layer includes an amorphous oxide semiconductor layer, a microcrystalline oxide semiconductor layer, a polycrystalline oxide semiconductor layer, and a physical semiconductor layer, CAAC-OS (C Axis Aligned Crystalline This refers to films such as oxide semiconductor films.

[0039] The amorphous oxide semiconductor layer is an oxide semiconductor layer in which the atomic arrangement in the film is irregular and which does not have a crystalline component. The layer is a compound semiconductor layer. It does not have any crystalline parts even in a microscopic area, and the entire film has a completely amorphous structure. A typical example is an oxide semiconductor layer.

[0040] The microcrystalline oxide semiconductor layer is, for example, a microcrystal having a size of 1 nm or more and less than 10 nm (nanocrystal). Therefore, the microcrystalline oxide semiconductor layer has a lower atomic number than the amorphous oxide semiconductor layer. Therefore, the microcrystalline oxide semiconductor layer has a higher molecular weight than the amorphous oxide semiconductor layer. Also, the defect level density is low.

[0041] The CAAC-OS film is one of the oxide semiconductor layers having multiple crystal parts. The crystal part is so large that it fits inside a cube with one side less than 100 nm. The crystals contained in the S film are in the form of cubes with sides of less than 10 nm, 5 nm, or 3 nm. The CAAC-OS film has a smaller defect density than the microcrystalline oxide semiconductor layer. The CAAC-OS film has a low density of recessed states. .

[0042] The CAAC-OS film was observed under a transmission electron microscope (TEM). When observed under a quartz microscope, clear boundaries between the crystals were observed. It is not possible to confirm the grain boundary. It can be said that the AC-OS film is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0043] The CAAC-OS film was observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM observation ) It can be confirmed that the metal atoms are arranged in layers in the crystal part. Each layer has a surface on which the CAAC-OS film is formed (also called a surface on which the film is formed) or a top surface having irregularities. The shape of the CAAC-OS film reflects this, and the CAAC-OS film is aligned parallel to the surface on which the film is formed or the top surface.

[0044] On the other hand, the CAAC-OS film was observed by TEM from a direction roughly perpendicular to the sample surface (planar TEM). When the metal atoms were observed, they were found to be arranged in triangular or hexagonal shapes in the crystals. However, no regularity was observed in the arrangement of metal atoms between different crystal parts. stomach.

[0045] Cross-sectional and planar TEM observations revealed that the crystals in the CAAC-OS film had an orientation. It is clear that there are

[0046] X-ray diffraction (XRD) was performed on the CAAC-OS film. For example, a CAAC-OS film with InGaZnO4 crystals was In the out-of-plane analysis, a peak was observed at a diffraction angle (2θ) of approximately 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. This indicates that the crystals in the CAAC-OS film have a c-axis orientation, and the c-axis is generally aligned on the surface on which the film is formed or on the upper surface. It can be seen that it is oriented in a substantially vertical direction.

[0047] On the other hand, in-plane X-ray irradiation is performed on the CAAC-OS film in a direction perpendicular to the c-axis. In the analysis by the ane method, a peak may appear at 2θ around 56°. This peak is This is attributed to the (110) plane of the InGaZnO4 crystal. For a semiconductor layer, 2θ is fixed at around 56°, and the normal vector of the sample surface is taken as the axis (φ axis). When the sample is rotated and analyzed (φ scan), the crystal plane equivalent to the (110) plane is In contrast, in the case of the CAAC-OS film, the 2θ is set to 5 Even when the φ is fixed at around 6° and scanned, no clear peak appears.

[0048] From the above, it is considered that the a-axis and b-axis orientations are inconsistent between different crystal regions in the CAAC-OS film. The crystal is regular, but has a c-axis orientation, and the c-axis is parallel to the normal vector of the surface on which the crystal is formed or the upper surface. Therefore, the layered arrangement confirmed by the cross-sectional TEM observation mentioned above is consistent with the above. Each layer of aligned metal atoms is a plane parallel to the ab plane of the crystal.

[0049] The crystalline portion is formed when the CAAC-OS film is formed or when a crystallization process such as a heat treatment is performed. As described above, the c-axis of the crystal is aligned along the surface on which the CAAC-OS film is formed or along the surface on which the CAAC-OS film is formed. The orientation of the CAAC-OS film is parallel to the normal vector of the top surface. When the shape of the CAAC-OS film is changed by etching, the c-axis of the crystal is aligned with the surface on which the CAAC-OS film is formed. Or it may not be parallel to the normal vector of the upper surface.

[0050] In addition, the degree of crystallinity in the CAAC-OS film may not be uniform. When the crystal part of the CAAC-OS film is formed by crystal growth from the vicinity of the top surface, The adjacent regions may have a higher degree of crystallinity than the regions adjacent the surface to be formed. When impurities are added to a C-OS film, the crystallinity of the region to which the impurities are added changes, resulting in partial In some cases, regions of differing crystallinity may be formed.

[0051] In addition, the out-of-plane method of CAAC-OS film with InGaZnO4 crystals In the analysis by , in addition to the peak at 2θ near 31°, a peak also appeared at 2θ near 36°. The peak at 2θ of around 36° may be due to the c-axis orientation in some parts of the CAAC-OS film. The CAAC-OS film contains crystals that do not have a 2θ of around 31°. It is preferred that the spectrum exhibits a peak and does not exhibit a peak at 2θ of around 36°.

[0052] The electrical characteristics of transistors using CAAC-OS films change when exposed to visible or ultraviolet light. Therefore, the transistor has high reliability.

[0053] Note that the oxide semiconductor layer 108 may have any of the above structures. For example, The semiconductor layer may include two or more of a crystalline oxide semiconductor layer, a microcrystalline oxide semiconductor layer, and a CAAC-OS film. It may be a laminated film.

[0054] In this specification, "parallel" means that the angle between two straight lines is between -10° and 10°. Therefore, it includes the case where the angle is between -5° and 5°. "Straight" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. This also includes cases where the angle is between 85° and 95°.

[0055] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. .

[0056] The insulating layers in contact with the oxide semiconductor layer 108 (the oxide insulating layer 106 and the gate insulating layer 114) The region containing oxygen in excess of the stoichiometric composition (hereinafter, also referred to as the oxygen excess region) is included. When the insulating layer in contact with the oxide semiconductor layer 108 includes an oxygen excess region, It is possible to supply oxygen to the oxide semiconductor layer 108. It is possible to prevent oxygen from being released from 8 and to compensate for oxygen vacancies. To suppress a negative shift in the threshold voltage of the transistor 120 and improve reliability. can be done.

[0057] In addition, the insulating layer in contact with the oxide semiconductor layer 108 (the oxide insulating layer 106 and the gate insulating layer 11 4) one or more metal elements selected from the constituent elements of the oxide semiconductor layer 108 It is preferable to use an oxide insulating layer containing gallium oxide (GaO x Also written as (Note that x is not necessarily a natural number and includes non-natural numbers), gallium zinc oxide film (Ga2Z n x O y (also written as x=1~5), Ga2O3 (Gd2O3) film, containing gallium Insulating In-Ga-Zn oxide films with a large amount and low indium content It is preferable to use an oxide insulating layer containing gallium.

[0058] For example, the oxide semiconductor layer 108 may be a gallium oxide semiconductor layer such as an In-Ga-Zn-based oxide semiconductor layer. A semiconductor layer containing gallium is used, and the oxide semiconductor layer is sandwiched between two semiconductor layers containing gallium. When an oxide insulating layer (e.g., a gallium oxide film) is used, the oxide insulating layers arranged above and below the Since it contains the same constituent material as the oxide semiconductor layer, it has a good interface with the oxide semiconductor layer. Therefore, stable electrical characteristics can be imparted to the transistor. In addition, the oxide semiconductor layer is sandwiched between the upper and lower electrodes, and the oxide semiconductor layer is sandwiched between the upper and lower electrodes. By providing an oxide insulating layer containing one or more metal elements, Blocks the intrusion of impurities that may affect the layer, such as nitrogen and metal elements, by diffusion. Therefore, the oxide semiconductor layer can be sandwiched between the insulating layers or the insulating layers can be used to surround the oxide semiconductor layer. By providing the oxide insulating layer so as to surround the oxide semiconductor layer, the composition and It is possible to realize a semiconductor device having a constant purity and stable electrical characteristics.

[0059] FIG. 2 illustrates a configuration example of a transistor 122 according to this embodiment. 2(B) is a plan view of the resistor 122, and FIG. 2(B) is a cross-sectional view taken along the dashed line X2-Y2 in FIG. 2(A). 2(C) is a cross-sectional view taken along the dashed line V2-W2 in FIG. 2(A).

[0060] The transistor 122 shown in FIG. 2 has an oxide semiconductor layer between the oxide insulating layer 106 and the substrate 100. a conductive layer 102 overlapping with the conductor layer 108; and an insulating layer 103 provided over the conductive layer 102; The transistor 102 differs from the transistor 120 in that it includes an insulating layer 104 in which the conductive layer 102 is buried. The other configuration is similar to that of the transistor 120, so a detailed description will be omitted.

[0061] In the transistor 122, the conductive layer 102 is an electrode layer that functions as a so-called back gate. The potential can be set appropriately. The gate voltage applied to the back gate is By controlling this, the threshold voltage of the transistor 122 can be controlled. It can be of the Marioff type.

[0062] 3A to 3D show other configuration examples of the transistor of this embodiment.

[0063] The difference between the transistor 124 shown in FIG. 3A and the transistor 122 shown in FIG. 2 is that the transistor 124 has an oxide The shape of the oxide insulating layer in contact with the lower layer of the oxide semiconductor layer 108. The oxide insulating layer 107 is formed in an island shape. The oxide semiconductor layer 106 can be formed using the same material and the same manufacturing method as the edge layer 106. The oxide insulating layer may include one or more metal elements selected from the constituent elements of 108. The oxide insulating layer 107 is preferably formed in the same form as the oxide semiconductor layer 108 when the oxide semiconductor layer 108 is processed into an island shape. The etching process can be performed using a mask, and the pattern shape seen from a plane (not shown) ) has substantially the same shape as the oxide semiconductor layer. In comparison, the structure shown in FIG. 3A can be obtained without increasing or decreasing the number of masks. In the transistor 24, the structure other than the oxide insulating layer 107 is similar to that of the transistor 122. , detailed explanation will be omitted.

[0064] The difference between the transistor 126 illustrated in FIG. 3B and the transistor 122 illustrated in FIG. 2 is that In the transistor 126, the gate insulating layer 117 is in the form of a patterned The gate insulating layer 117 is formed to cover the entire surface of the insulating layer 112 without forming a gate insulating layer. The insulating layer 114 can be formed using a similar material and a similar manufacturing method. In the transistor 122 shown in FIG. 2, the gate insulating layer 114 is the same as the gate electrode layer 116. Transistor 122 is patterned using the same photomask as transistor 1. The number of masks is the same as that of the gate insulating layer 117 of the transistor 126. The other configuration is similar to that of the transistor 122, so a detailed description will be omitted.

[0065] The difference between the transistor 128 in FIG. 3C and the transistor 120 in FIG. 1 is that the transistor 128 has an acid The transistor 128 has an oxide semiconductor layer in contact with the oxide insulating layer 106. The oxide semiconductor layer 108a and the oxide semiconductor layer 108b in contact with the oxide semiconductor layer 108a In the transistor 128, the oxide semiconductor layer 108a and the oxide The configuration other than the organic semiconductor layer 108b is the same as that of the transistor 120, and therefore a detailed description thereof will not be given. Omitted.

[0066] The oxide semiconductor layer 108a and the oxide semiconductor layer 108b are formed using metal oxides having different compositions. For example, the oxide semiconductor layer 108a may be formed using an oxide of a ternary metal. For example, the oxide semiconductor layer 108a may be made of an oxide of a binary metal. The oxide semiconductor layer 108b may be an oxide of a ternary metal. The organic semiconductor layer 108a and the oxide semiconductor layer 108b are made of the same elements, and have different compositions. Note that the oxide semiconductor layer may have a stacked structure of three or more layers.

[0067] The oxide semiconductor layer 108b is formed by using a semiconductor material containing a small amount of indium (In) and gallium (Ga). It is preferable to use an oxide semiconductor containing at least In and having a content of In≦Ga. Since a has a larger oxygen vacancy formation energy than In, it is difficult for oxygen vacancies to occur. Oxides with a composition of In≦Ga have more stable characteristics than oxides with a composition of In>Ga. By using such materials, the reliability of transistors can be improved. .

[0068] The oxide semiconductor layer 108a contains at least In and Ga, and the content of these elements is It is preferable to use an oxide semiconductor in which In>Ga. The s orbital of In contributes to carrier conduction, and by increasing the In content, the s orbital Since there is a tendency for overlap to increase, oxides with a composition of In>Ga are In≦Ga. It has a higher mobility than an oxide having the composition

[0069] In the case where the oxide semiconductor layer has a stacked structure, a step of thinning the channel formation region (thinning Patterning or subsequent etching of the source electrode layer 110a and the drain electrode layer 110b. The lower layer of the stack (the oxide semiconductor layer 108a in FIG. 3C) is not exposed by the etching process. The oxide semiconductor layer is formed in this manner.

[0070] The difference between the transistor 130 in FIG. 3D and the transistor 122 in FIG. 2 is that the transistor 130 has an acid The transistor 130 has a structure in which the oxide insulating layer 106 is in contact with the oxide semiconductor layer. The oxide semiconductor layer 108a and the oxide semiconductor layer 108b in contact with the oxide semiconductor layer 108a The transistor 130 includes a layer other than the oxide semiconductor layer. Since the transistor 122 is the same as the oxide semiconductor layer 10, detailed description thereof will be omitted. The structures of the oxide semiconductor layer 8a and the oxide semiconductor layer 108b can be similar to those of the transistor 128. do.

[0071] Note that the transistors illustrated in FIGS. 1, 2, and 3A to 3D are partially different from each other. However, one embodiment of the present invention is not particularly limited, and various combinations are possible. For example, the patterned oxide insulating layer 107 shown in FIG. 3(A) and the patterned oxide insulating layer 107 shown in FIG. A transistor having a stacked structure of the oxide semiconductor layer 108a and the oxide semiconductor layer 108b, A transistor configuration may also be used.

[0072] An example of a method for manufacturing the transistor 122 will be described below with reference to FIGS.

[0073] First, a conductive layer 102 is formed on a substrate 100 having an insulating surface.

[0074] There is no significant restriction on the substrate that can be used for the substrate 100 having an insulating surface. In either case, it is necessary to have heat resistance sufficient to withstand subsequent heat treatment. For example, barium Glass substrates such as borosilicate glass and aluminoborosilicate glass, ceramic substrates, and quartz substrates A single crystal substrate such as silicon or silicon carbide can also be used. Crystalline semiconductor substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI A substrate or the like can be used, and a substrate having a semiconductor element provided thereon is called a substrate 100. It may also be used as.

[0075] The material of the conductive layer 102 is molybdenum, titanium, tantalum, tungsten, aluminum, Metallic materials such as copper, chromium, neodymium, scandium, etc., or alloy materials whose main components are these The conductive layer 102 can be formed by doping with an impurity element such as phosphorus. Semiconductor films, such as polycrystalline silicon films, and silicide films, such as nickel silicide, are The conductive layer 102 may have a single layer structure or a stacked layer structure. The shape 102 may be tapered, for example, with a taper angle of 30° to 70°. Here, the taper angle is the angle between the side surface of a layer having a tapered shape and the bottom surface of the layer. Point.

[0076] The material of the conductive layer 102 is indium oxide, tin oxide, or indium oxide containing tungsten oxide. Indium oxide, indium zinc oxide with tungsten oxide, indium zinc oxide with titanium oxide Indium tin oxide, indium oxide zinc oxide, silicon oxide Alternatively, a conductive material such as indium tin oxide doped with silicon may be used.

[0077] At least the surface of the conductive layer 102 that is in contact with the insulating layer 103 is in contact with the oxide semiconductor layer 108 in work function. A material having a work function greater than 1 eV, preferably greater than 1 eV. It is desirable to use a material having the following properties. For example, the material is In-G a-Zn-O film, nitrogen-containing In-Sn-O film, nitrogen-containing In-Ga-O film, nitrogen-containing In-Zn-O film containing nitrogen, Sn-O film containing nitrogen, In-O film containing nitrogen, metal nitride film (nitrogen Indium nitride film, zinc nitride film, tantalum nitride film, tungsten nitride film, etc. These films have a work function of 5 eV or more and are The voltage can be made positive, making it possible to realize a normally-off switching transistor. For example, when an In-Ga-Zn-O film containing nitrogen is used, at least the oxide semiconductor layer An In-Ga-Zn-O film containing nitrogen at a concentration higher than 108 may be used.

[0078] Next, an insulating layer 103 is formed on the conductive layer 102 so as to cover the conductive layer 102. 03: Silicon oxide and silicon oxynitride are produced by CVD, sputtering, etc. , aluminum oxide, aluminum oxynitride, hafnium oxide, gallium oxide, zinc oxide A single layer or multilayer structure of films containing gallium or a mixture of these materials may be provided.

[0079] The insulating layer 103 is a layer that is processed later and is in contact with the oxide insulating layer 106. Since the oxide insulating layer 106 in contact with the conductor layer 108 preferably includes an oxygen excess region, A film having a barrier property against oxygen is applied to the insulating layer 103, and the oxide insulating layer 106 It is preferable to prevent the desorption of oxygen. Specifically, a film having a lower permeability to oxygen than the oxide insulating layer 106 may be used. For example, the aluminum oxide film or nitride film, the magnesium-added aluminum film, aluminium oxide film or nitride film, titanium-added aluminium oxide film or Nitride film, magnesium oxide film or nitride film, or titanium oxide film or nitride film The insulating layer 103 may be formed of a single layer or a stacked layer of an oxide film. In addition to providing a barrier against impurities, the membrane has low permeability to impurities such as hydrogen and moisture. As such a film, an aluminum oxide film can be preferably used. By using an aluminum oxide film as the insulating layer 103, it is possible to prevent oxygen from being released. The electrical characteristics of the transistor 122 may be affected by impurities such as hydrogen and moisture. This can suppress the inflow of

[0080] Next, the insulating layer 105 is formed over the insulating layer 103 (see FIG. 4A). Reflecting the shape of the conductive layer 102, the surface has protrusions.

[0081] The insulating layer 105 is formed by depositing silicon oxide, oxynitride, or the like by a CVD method, a sputtering method, or the like. Silicon, aluminum oxide, aluminum oxide nitride, hafnium oxide, gallium oxide, It can be formed using zinc gallium oxide, zinc oxide, or a mixture of these materials. The border layer 105 may be a single layer or a laminate.

[0082] Next, a planarization process is performed to remove the protrusions on the upper surface of the insulating layer 105, and the insulating layer 104 is formed. The planarization process is not particularly limited, but may be a polishing process (e.g., chemical mechanical polishing). , dry etching, plasma treatment, etc., can be used, and these can be combined to By this planarization treatment, a part of the insulating layer 103 (which overlaps with the conductive layer 102) may be area) is exposed.

[0083] In addition, the insulating layer 104 is made in a state in which impurities such as hydrogen (including water and hydroxyl groups) are reduced. In order to achieve this, hydrogen or a hydrogen compound is removed from the insulating layer 104 (or the insulating layer 105 before the planarization process). A heat treatment may be carried out to remove the hydrogen (dehydration or dehydrogenation).

[0084] Next, an oxide insulating layer 106 is deposited on the insulating layer 104 and the exposed insulating layer 103 by MOCV. D(Metal Organic Chemical Vapor Depositio The insulating film is formed by a CVD method such as a CVD method (see FIG. 4B), or a sputtering method.

[0085] The oxide insulating layer 106 is made of a material selected from the constituent elements of an oxide semiconductor layer to be formed later. It is preferable to provide an oxide insulating layer containing one or more metal elements. For example, gallium oxide gallium oxide film, zinc gallium oxide film, gallium gadolinium oxide film, high gallium content and In addition, insulating films such as In-Ga-Zn oxide films with low indium content are used. It is preferable that

[0086] In order to reduce impurities, the particle size is reduced compared to the sputtering method. It is preferable to form the oxide insulating layer 106 using an MOCVD method in which generation of oxide is suppressed. For example, when a gallium oxide film is formed as the oxide insulating layer 106 by MOCVD, Methylgallium or the like can be used as the material.

[0087] The oxide insulating layer 106 preferably has reduced impurities such as hydrogen. A heat treatment may be carried out to remove hydrogen or a hydrogen compound (dehydration or dehydrogenation). This heat treatment can also serve as a dehydration or dehydrogenation treatment for the insulating layer 104.

[0088] In addition, the oxide insulating layer 106 is a layer that is in contact with the oxide semiconductor layer 108 to be formed later. Therefore, it is preferable that the oxide insulating layer 106 has an oxygen excess region. For example, the oxide insulating layer 106 may be formed in an oxygen atmosphere. Even if oxygen is introduced into the oxide insulating layer 106 to form an oxygen excess region in the oxide insulating layer 106, good.

[0089] In this embodiment, the oxide insulating layer 106 is formed by adding oxygen (at least oxygen radicals, oxygen The oxygen-excess region is formed by introducing oxygen into the material. The methods include ion implantation, ion doping, plasma immersion ion implantation, A plasma treatment or the like can be used.

[0090] For the oxygen introduction process, a gas containing oxygen can be used. Nitrogen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide, etc. can be used. In the oxygen introduction process, a rare gas may be contained in the oxygen-containing gas.

[0091] Depending on the treatment conditions, oxygen introduction treatment may be performed not only on the layer directly exposed to oxygen, but also on the layer provided below the layer. In other words, oxygen can be introduced into the oxide insulating layer 106. Therefore, oxygen can also be introduced into the insulating layers 104 and 103 .

[0092] Next, an oxide semiconductor layer is formed over the oxide insulating layer 106, and an island-shaped oxide semiconductor layer 108 After processing the oxide semiconductor layer 108, a conductive film 110 is formed to cover the oxide semiconductor layer 108 (see FIG. 4C). see).

[0093] The oxide semiconductor layer is formed by sputtering, MBE (Molecular Beam Induction), or the like. m Epitaxy, CVD, pulsed laser deposition, ALD (Atomic Laser Deposition), A suitable method for this purpose may be the layer deposition method.

[0094] When the oxide semiconductor layer is formed, the hydrogen concentration in the oxide semiconductor layer is reduced as much as possible. In order to reduce the hydrogen concentration, for example, a sputtering method is used for film formation. When performing the above, hydrogen, water, etc. are used as the atmospheric gas to be supplied to the deposition chamber of the sputtering device. A high-purity rare gas (typically argon) from which impurities such as hydroxyl groups or hydrides have been removed. , oxygen, and a mixed gas of a rare gas and oxygen are appropriately used.

[0095] In addition, the residual moisture in the film formation chamber is removed and a sputtering gas from which hydrogen and moisture have been removed is introduced. By forming the oxide semiconductor layer in this manner, the hydrogen concentration in the formed oxide semiconductor layer can be reduced. To remove residual moisture in the deposition chamber, an adsorption type vacuum pump, such as a cryopump, is used. It is preferable to use a turbo pump, an ion pump, or a titanium sublimation pump. A molecular pump with a cold trap may be used. A cryopump is, for example, Hydrogen molecules, water (H2O), and other compounds that contain hydrogen atoms (preferably compounds that contain carbon atoms) Since the pumping capacity of the film deposition chamber is high, the film deposition chamber is pumped using a cryopump. The concentration of impurities contained in the oxide semiconductor layer can be reduced.

[0096] In addition, when the oxide semiconductor layer is formed by a sputtering method, the metal oxide ter used for the film formation is The relative density (filling rate) of the get is 90% or more and 100% or less, preferably 95% or more and 99.9% or less. By using a metal oxide target with a high relative density, the oxide film formed This allows the semiconductor layer to be a dense film.

[0097] In addition, the oxide semiconductor layer can be formed while the substrate 100 is maintained at a high temperature. This is effective in reducing the concentration of impurities that may be contained in the semiconductor layer. The substrate temperature is preferably 200° C. or higher and 300° C. or lower. In addition, by heating the substrate at a high temperature during film formation, the crystalline oxide semiconductor A conductor layer can be formed.

[0098] In the case where a CAAC-OS film is used as the oxide semiconductor layer 108, the CAAC-OS film is As a method for this, for example, a deposition temperature is set to 200° C. or more and 450° C. or less to form an oxide semiconductor film. Alternatively, a method of forming a thin oxide semiconductor film and aligning the c-axis approximately perpendicular to the surface may be used. After the film is formed, it is heat-treated at 200°C to 700°C, and the c-axis orientation is roughly perpendicular to the surface. Alternatively, after forming a thin film as the first layer, heat the film at 200°C to 700°C. The second layer may be formed by carrying out the heat treatment described below, and the c-axis may be oriented approximately perpendicular to the surface.

[0099] The oxide semiconductor used for the oxide semiconductor layer 108 contains at least indium (In). In particular, it is preferable that the oxide semiconductor contains indium and zinc (Zn). As a stabilizer to reduce the variation in the electrical characteristics of the transistors used, In addition to gallium (Ga), it is preferable to use tin ( Sn), hafnium (Hf), aluminum (Al), or zirconium (Zr) It is preferable to have one or more types.

[0100] Other stabilizers include the lanthanides lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Ho, Erbium, Thulium, Ytterbium, Ru It may have one or more of tetraethynyl phosphate (Pt) and tetraethynyl phosphate (Tb).

[0101] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and oxides of binary metals. The In-Zn oxide, In-Mg oxide, In-Ga oxide, and ternary metal oxides are Oxides such as In-Ga-Zn oxides, In-Al-Zn oxides, and In-Sn-Zn In-Hf-Zn oxide, In-La-Zn oxide, In-Ce-Zn oxide Oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm-Zn oxide oxides, In-Eu-Zn oxides, In-Gd-Zn oxides, In-Tb-Zn oxides In-Dy-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide , In-Tm-Zn oxide, In-Yb-Zn oxide, In-Lu-Zn ​​oxide, In-Sn-Ga-Zn oxides and In-Hf-Ga-Zn oxides, which are oxides of quaternary metals Oxide, In-Al-Ga-Zn oxide, In-Sn-Al-Zn oxide, In-S n-Hf-Zn oxide and In-Hf-Al-Zn oxide can be used.

[0102] For example, In-Ga-Zn oxide is an oxide having In, Ga, and Zn as the main components. The ratio of In, Ga, and Zn does not matter. Metal elements may also be included.

[0103] In addition, as an oxide semiconductor, InMO3(ZnO) m (m>0 and m is not an integer) In addition, M may be selected from Ga, Fe, Mn, and Co. The metal element or elements are also shown. In2SnO 5(ZnO) n A material expressed as (n>0, and n is an integer) may be used.

[0104] For example, In:Ga:Zn=1:1:1(=1 / 3:1 / 3:1 / 3), In:Ga:Z n=2:2:1 (=2 / 5:2 / 5:1 / 5), or In:Ga:Zn=3:1:2 In-Ga-Zn oxide with an atomic ratio of (=1 / 2:1 / 6:1 / 3) and its neighboring compositions Alternatively, the oxide of In:Sn:Zn=1:1:1 (=1 / 3: 1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3:1 / 6:1 / 2) or In-Sn with an atomic ratio of In:Sn:Zn=2:1:5 (=1 / 4:1 / 8:5 / 8) It is preferable to use -Zn-based oxides or oxides having a composition close to that.

[0105] However, a transistor using an oxide semiconductor containing indium is not limited to these. The appropriate composition is selected according to the required electrical characteristics (field effect mobility, threshold value, variation, etc.). In addition, the carrier concentration and impurity concentration can be adjusted to obtain the required electrical characteristics. The degree of crystallization, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density, etc. must be appropriate. is preferred.

[0106] For example, it is relatively easy to obtain high current transistors using In-Sn-Zn oxide semiconductors. However, in the case of transistors using In-Ga-Zn oxide semiconductors, In transistors, the field effect mobility can also be increased by reducing the bulk defect density. Cut.

[0107] For example, the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c(a+b+ The composition of the oxide with the atomic ratio of In:Ga:Zn=A:B:C (A+B+C = 1), a, b, and c are in the vicinity of the oxide composition (aA) 2 +(bB) 2 + (cC) 2 ≦r 2 It means that the following condition is satisfied. For example, r can be set to 0.05. The same is true for other oxides.

[0108] In addition, the oxide semiconductor layer 108 is heated to a temperature at which excess hydrogen (water or It is preferable to carry out a heat treatment for removing (dehydrating or dehydrogenating) the organic compound (including hydroxyl groups). The temperature of the heat treatment is 300°C to 700°C, or less than the distortion point of the substrate. This heat treatment can be performed under high pressure or in a nitrogen atmosphere. Hydrogen, which is an impurity that contributes to the oxidation of the oxide semiconductor, can be removed from the oxide semiconductor.

[0109] Note that the heat treatment for dehydration or dehydrogenation can be performed after the formation of the oxide semiconductor layer. This may be performed at any time during the process of producing the star 122. The heat treatment for curing may be carried out multiple times, or may be carried out in combination with other heat treatments.

[0110] Note that the heat treatment for dehydration or dehydrogenation is performed before the oxide semiconductor layer is processed into an island shape. By using the above-mentioned method, oxygen contained in the oxide insulating layer 106 can be prevented from being released by heat treatment. This is preferable because it allows

[0111] In heat treatment, nitrogen or rare gases such as helium, neon, argon, water, hydrogen, etc. It is preferable that the nitrogen, helium, or neon introduced into the heat treatment device is not included. The purity of rare gas such as argon should be 6N (99.9999%) or more, preferably 7N (99. 99999%) or more (i.e. impurity concentration is 1 ppm or less, preferably 0.1 ppm or less) It is preferable to do so.

[0112] After the oxide semiconductor layer 108 is heated by the heat treatment, the heating temperature is maintained or the heating temperature is increased. While slowly cooling from the beginning, high purity oxygen gas, high purity dinitrogen monoxide gas, or ultra-dry air was added to the same furnace. The dew point was measured using a CRDS (Cavity Ring Down Laser Spectroscopy) type dew point meter. In this case, the moisture content is 20 ppm or less (-55°C in terms of dew point), preferably 1 ppm or less, more preferably Preferably, air of 10 ppb or less may be introduced. It is preferable that the oxygen gas or the like introduced into the heat treatment device does not contain water, hydrogen, etc. The purity of the dinitrogen monoxide gas is 6N or more, preferably 7N or more (i.e., oxygen gas or dinitrogen monoxide gas). It is preferable to keep the impurity concentration in the nitrogen gas at 1 ppm or less, preferably 0.1 ppm or less. It is preferable that the action of oxygen gas or nitrous oxide gas is used to remove impurities caused by dehydration or dehydrogenation treatment. The main component material of the oxide semiconductor that was reduced at the same time by the process of removing the pure material. By supplying oxygen, the oxide semiconductor layer is highly purified and made to be i-type (intrinsic). can be done.

[0113] In addition, oxygen, which is a main component material of an oxide semiconductor, can be removed by the dehydration or dehydrogenation treatment. Since there is a risk that the amount of The compound semiconductor layer is doped with oxygen (at least one of oxygen radicals, oxygen atoms, and oxygen ions). ) may be introduced to supply oxygen into the film.

[0114] Oxygen is introduced into the oxide semiconductor layer that has been subjected to dehydration or dehydrogenation treatment to supply oxygen into the film. By this, the oxide semiconductor layer can be highly purified and made to be i-type (intrinsic). A transistor having a purified i-type (intrinsic) oxide semiconductor has low fluctuation in electrical characteristics. It is controlled and electrically stable.

[0115] When oxygen is introduced into the oxide semiconductor layer 108, oxygen may be directly introduced into the oxide semiconductor layer 108. Alternatively, oxygen may be introduced into the oxide semiconductor layer 108 through an insulating layer that is formed later. When introducing the material through a membrane, ion implantation, ion doping, plasma imaging, etc. are used. A direct ion implantation method or the like may be used. When oxygen is introduced, plasma treatment or the like can be used in addition to the above methods.

[0116] For example, when oxygen ions are implanted into the oxide semiconductor layer 108 by an ion implantation method, the dose 1×10 13 ions / cm 2 5×10 or more 16 ions / cm 2 The following would suffice.

[0117] Or, an insulating layer in contact with the oxide semiconductor layer (the oxide insulating layer 106 or the gate insulating layer 114) The insulating layer is formed into a layer including an oxygen excess region, and heat treatment is performed in a state where the insulating layer and the oxide semiconductor layer are in contact with each other. By this, the oxygen contained in the insulating layer in excess is diffused into the oxide semiconductor layer, and the oxide semiconductor The heat treatment may be performed in a similar manner to other heat treatments in the fabrication process of the transistor 122. It can also be used for processing.

[0118] The timing of supplying oxygen to the oxide semiconductor layer is not particularly limited as long as it is after the oxide semiconductor layer is formed. In addition, oxygen may be introduced into the oxide semiconductor layer several times.

[0119] The oxide insulating layer 106 and the oxide semiconductor layer 108 are successively formed without exposure to the air. When the oxide insulating layer 106 and the oxide semiconductor layer 108 are formed in succession, This can prevent impurities such as hydrogen and moisture from being adsorbed on the surface of the oxide insulating layer 106. .

[0120] The conductive film 110 is made of a material selected from the group consisting of Al, Cr, Cu, Ta, Ti, Mo, and W. Metal films containing the elements, or metal nitride films containing the above elements (titanium nitride film, nitride A single-layer structure such as a molybdenum film or a tungsten nitride film can be used. This allows for efficient manufacturing and reduces the cost of the semiconductor device. The conductive film 110 may be made of a conductive metal oxide. The materials are indium oxide (In2O3), tin oxide (SnO2), and zinc oxide (ZnO). , Indium oxide tin oxide (In2O3-SnO2), Indium oxide zinc oxide (In2 O3-ZnO) or materials containing silicon oxide in these metal oxide materials. It may also have a layered structure.

[0121] The conductive film 110 may be an In-Ga-Zn-O film containing nitrogen, an In-Sn- O film, In-Ga-O film containing nitrogen, In-Zn-O film containing nitrogen, Sn-O film containing nitrogen A single-layer structure of a metal nitride film such as a metal oxide film containing nitrogen, or an In-O film, can be used. Since the film contains one or more metal elements selected from the constituent elements of the oxide semiconductor layer 108, In this way, the interface with the oxide semiconductor layer 108 can be stabilized.

[0122] Next, a resist mask 170a is formed over the conductive film 110, and the conductive film 110 is The conductive film 110 is half-etched (i.e., the conductive film 110 covers the oxide semiconductor layer 108). The etching is stopped at this state), resulting in a conductive film 110 having a recess (see FIG. 4(D)).

[0123] Next, the resist mask 170a is retracted (reduced) to form a resist mask 170b. To reduce the resist mask, oxygen plasma ashing is used. After that, the conductive film 110 is etched using the resist mask 170b. Thus, the source electrode layer 110a and the drain electrode layer 110b are formed (see FIG. 4E). In addition, a part of the conductive film 110 exposed from the resist mask 170b is etched. As a result, the source electrode layer 110a and the drain electrode layer 110b have a small thickness and protrude from the periphery. In addition, the regions 111a, 111b, 111c, and 111d are formed. 11a, 111b, 111c, and 111d have approximately the same width and approximately the same thickness. is.

[0124] In addition, the etching using the resist mask 170a and the retreat (shrinkage) of the resist mask 170a (small) and etching using resist mask 170b are performed successively in the same chamber. In this embodiment, the resist mask 170a is once recessed (reduced) before use. However, the present invention is not limited to this embodiment. Two or more recession (reduction) processes may be performed to A multi-step shape may be formed on the periphery of the electrode layer 110a and the drain electrode layer 110b. .

[0125] In addition, part of the oxide semiconductor layer 108 is simultaneously etched by this etching treatment. A thin region is formed between the source electrode layer 110a and the drain electrode layer 110b. Alternatively, after the source electrode layer 110a and the drain electrode layer 110b are formed, The exposed oxide semiconductor layer 108 is subjected to etching treatment (for example, wet etching treatment). By performing this process, a region with a small film thickness may be formed.

[0126] Next, the source electrode layer 110a, the drain electrode layer 110b, and the exposed oxide semiconductor layer 1 An insulating layer 112 is formed to cover 08 (see FIG. 5A).

[0127] The insulating layer 112 may be a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an oxide Aluminum nitride film, silicon nitride film, aluminum nitride film, silicon oxynitride film, nitrogen The insulating layer 112 is a gate insulating layer formed later. A material different from that of 114 is used, and a material with a high etching selectivity is applied. It is preferable that

[0128] Next, a resist mask 180 is formed on the insulating layer 112, and the insulating layer 1 12 is etched to form an opening 150 (see FIG. 5(B)). According to this theory, the oxide semiconductor layer 108, the source electrode layer 110a, and the drain electrode layer 110b A part of it is exposed.

[0129] Next, the insulating layer 112, the exposed oxide semiconductor layer 108, the source electrode layer 110a and the drain electrode layer 110b are A gate insulating film 113 is formed to cover the gate electrode layer 110b (see FIG. 5(C)). The insulating film 113 can be formed in a similar manner to the oxide insulating layer 106 .

[0130] The source electrode layer 110a and the drain electrode layer 110b have a small thickness at the periphery and a protruding region. By having the region, the film thickness at the end portion is gradually reduced, and the gate insulating film formed on the electrode layer is Therefore, the coverage of the gate insulating film 113 (or the gate insulating film 113) can be improved. In the edge layer 114), it is possible to suppress the formation of a region with a locally small thickness. Therefore, the electric field concentration between the source electrode layer 110a and the drain electrode layer 110b can be reduced. In addition, disconnection and connection failure can be prevented.

[0131] Thereafter, a conductive layer (a wiring formed in the same layer) that will become a gate electrode layer is formed on the gate insulating film 113. A gate insulating layer 114 and a gate electrode layer 115 are formed by selectively etching the gate insulating layer 114 and the gate electrode layer 115. In this etching process, the insulating layer 112 is formed (see FIG. 5(D)). The insulating film functions as a protective layer for the source electrode layer 110a and the drain electrode layer 110b.

[0132] The gate electrode layer 116 can be formed using a material and a method similar to those of the conductive layer 102. As the gate electrode layer 116, a layer in contact with at least the gate insulating layer 114 can be formed. The surface is preferably made of a material having a work function larger than that of the oxide semiconductor layer 108. It is preferable to use a material having a work function larger than the above by at least 1 electron volt.

[0133] In this manner, the transistor 122 of this embodiment can be formed.

[0134] Note that an insulating layer 118 may be formed over the gate electrode layer 116 (see FIG. 5E). The layer 118 can be formed using a similar material and method to the insulating layer 103. The insulating layer 118 prevents oxygen from being released from the oxide semiconductor layer 108 or an insulating layer in contact with the oxide semiconductor layer 108. It is preferable that the layer has a function as a barrier layer (protective layer) for preventing the adhesion.

[0135] The transistor described in this embodiment has source and drain electrodes sandwiching a channel formation region of an oxide semiconductor layer. By forming a region protruding in the channel length direction at the lower end of the electrode layer and the drain electrode layer, The coverage of the gate insulating layer provided in contact with the electrode layer is improved. There is no localized thin area in the insulating layer, and the thin area This makes it possible to prevent breakdown of the transistor caused by electric field concentration.

[0136] In addition, a gate insulating layer is provided between the source and drain electrode layers and the gate electrode layer. By including the insulating layer provided in the source electrode layer and the drain electrode layer, the gate electrode layer The parasitic capacitance can be reduced.

[0137] Therefore, the transistor described in this embodiment can be miniaturized and has excellent electrical characteristics. It may be a transistor.

[0138] As described above, the configurations, methods, etc. described in this embodiment mode may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0139] (Embodiment 2) In this embodiment, as an example of a semiconductor device to which the transistor described in Embodiment 1 is applied, It is possible to retain memory contents even when power is not supplied, and there is no limit to the number of times it can be written. The semiconductor device without the above-mentioned structure will be described with reference to the drawings.

[0140] FIG. 6 shows an example of the configuration of a semiconductor device. FIG. 6(A) shows a cross-sectional view of the semiconductor device, and FIG. FIG. 1B) shows a circuit diagram of the semiconductor device.

[0141] The semiconductor device shown in FIG. 6A includes a transistor 160 using a first semiconductor material in a lower portion. The transistor 162 is made of a second semiconductor material. The transistor according to one embodiment of the present invention described in Embodiment 1 is used as the transistor 162. In this embodiment, a transistor having a similar configuration to the transistor 122 can be used. Use the .

[0142] Here, the first and second semiconductor materials have different bandgaps. For example, it is preferable that the first semiconductor material is a semiconductor material other than an oxide semiconductor (silicon The second semiconductor material may be an oxide semiconductor. Transistors using oxide semiconductors can easily operate at high speed. The transistor's characteristics enable it to retain electric charge for a long period of time.

[0143] It should be noted that the above transistors are all n-channel transistors. However, it goes without saying that a p-channel transistor can be used. In order to hold the transistor, a transistor using an oxide semiconductor as described in Embodiment 1 is used. In addition to being used as a resistor 162, materials used in semiconductor devices and the structure of semiconductor devices, etc. The specific configuration of the conductor device need not be limited to those shown here.

[0144] The transistor 160 in FIG. 6A includes a semiconductor material (e.g., silicon). A channel forming region 216 is provided on the substrate 200, and a pair of semiconductor layers are provided on the substrate 200 so as to sandwich the channel forming region 216. The impurity region 214 and the high-concentration impurity region 220 (collectively referred to as simply impurity) are provided in the The intermetallic compound region 224 is in contact with the high concentration impurity region 220. A gate insulating layer 208 is provided on the panel forming region 216, and a gate insulating layer 208 is provided on the gate insulating layer 208. A gate electrode layer 210 is formed on the insulating layer 210. A sidewall insulating film is formed on the side of the gate electrode layer 210. It has an edge layer 218, an electrode layer 212a, and an electrode layer 212b.

[0145] Note that the electrode layer 212a and the electrode layer 212b function as a source electrode layer or a drain electrode layer. The contact hole is provided in the insulating layer 228 on the gate electrode layer 210. The insulating layer 228 is electrically connected to the intermetallic compound region 224 through a via. The insulating film may have a laminated structure, and may be a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, etc. Aluminum oxide nitride film, silicon nitride film, aluminum nitride film, silicon oxide nitride film For example, an inorganic insulating film such as an aluminum nitride oxide film or an aluminum oxide film can be used.

[0146] An element isolation insulating layer 206 is provided on the substrate 200 so as to surround the transistor 160. do.

[0147] The transistor 160 using a single crystal semiconductor substrate can operate at high speed. By using this transistor as a read transistor, data can be read at high speed. can be carried out.

[0148] A transistor 162 illustrated in FIG. 6A is a transistor in which an oxide semiconductor is used for a channel formation region. A transistor that uses an oxide semiconductor for the channel formation region is extremely small. Note that the oxide semiconductor included in the transistor 162 can achieve excellent off-state characteristics. The layer is preferably a highly purified oxide semiconductor. This makes it possible to obtain the transistor 162 with better off-state characteristics.

[0149] Since the off-state current of the transistor 162 is small, the use of the transistor 162 enables long-term recording. The contents of the memory can be retained, i.e., no refresh operation is required, or Therefore, it is possible to realize a semiconductor memory device in which the frequency of refresh operations is extremely low. Power consumption can be reduced sufficiently.

[0150] The transistor 162 is formed by sandwiching a channel formation region of the oxide semiconductor layer 244 between electrode layers 268a The electrode layer 268b has a region protruding in the channel length direction at the lower end thereof, and the electrode layer and the The insulating layer 263 is provided between the gate electrode layer 262 and the gate insulating layer 260. The transistor 162 has an electrode layer 268a and an electrode layer 268b arranged along the channel length at the bottom end. By having a region protruding in the direction, electric field concentration can be alleviated, and the insulating layer 263 is effectively By this, the parasitic capacitance between the electrode layer 268a and the gate electrode layer 262 and between the electrode layer 268b and the gate electrode layer 262 is reduced. The transistor 162 is also oxidized through the gate insulating layer 260. In addition to the gate electrode layer 262 overlapping the organic semiconductor layer 244, the insulating layer 203 and the insulating layer 204 are and a conductive layer 202b overlapping with the oxide semiconductor layer 244 with the insulating layer 205 interposed therebetween. The conductive layer 202b can be used as a so-called back gate electrode. By applying a bias voltage to the transistor 162, the threshold voltage of the transistor 162 is increased in the positive direction. It is possible to vary it.

[0151] The insulating layer 203 and the insulating layer 204 may be formed of silicon oxide, silicon oxynitride, or aluminum oxide. aluminum oxide nitride, hafnium oxide, gallium oxide, zinc gallium oxide, Alternatively, a film containing a mixture of these materials may be used. An oxide insulating layer containing one or more metal elements selected from the constituent elements of the conductor layer 244 is used. In addition, the insulating layer 205 preferably includes an oxygen excess region.

[0152] When a film having a barrier property against oxygen is used as the insulating layer 203, the insulating layer 20 This is preferable since it is possible to prevent the release of oxygen from 5.

[0153] In addition, when the conductive layer 202b and the electrode layer 202a have a tapered shape, the insulating layer 203 The taper angle is preferably 30° or more and 70° or less. It is preferable to set the above.

[0154] An insulating layer 232 and an insulating layer 235 are provided over the transistor 162 as a single layer or a stacked layer. The insulating layer 232 or the insulating layer 235 may be formed of the same material as the insulating layer 203 or the insulating layer 204. If necessary, after forming the insulating layer 235, a film containing a C The surface of the insulating layer 235 may be planarized by performing a planarization process such as MP processing. As the insulating layer 235, a planarizing insulating film is formed to reduce surface irregularities caused by the transistor. Alternatively, an inorganic insulating film and a planarizing insulating film may be laminated. By using organic materials such as polyimide resin, acrylic resin, and benzocyclobutene resin, Alternatively, in addition to the above organic materials, low-dielectric constant materials (low-k materials) can be used. This can be done.

[0155] A wiring layer 256 is provided on the insulating layer 235. The wiring layer 256 is connected to the transistor 162. The wiring layer 256 is provided to connect other transistors. An electrode layer is formed through a contact hole formed in the edge layer 232 and the gate insulating layer 260. In addition, a separate electrode layer is formed in the contact hole, and the electrode The wiring layer 256 and the electrode layer 268b may be electrically connected via a layer.

[0156] In addition, a region overlapping with the electrode layer 268a of the transistor 162 with the gate insulating layer 260 interposed therebetween A conductive layer 253 is provided in the region, and the electrode layer 268a, the gate insulating layer 260, and the conductive layer 253 are provided in the region. The capacitor 164 is formed by the conductive layer 253. The electrode layer 268a functions as one electrode of the capacitor 164, and the conductive layer 253 functions as one electrode of the capacitor 164. It should be noted that when capacitance is not required, the capacitance element 164 can be omitted. Alternatively, the capacitor 164 may not be provided. It may be provided above.

[0157] In this embodiment, the conductive layer 253 has the same structure as the gate electrode layer 262 of the transistor 162. It can be formed in a single manufacturing process.

[0158] The electrode layer 268a is electrically connected to the electrode layer 202a formed in the same layer as the conductive layer 202b. The electrode layer 202a is connected to the insulating layer 234 through a contact hole. Although not shown in FIG. 6A, the electrode layer 222 a is electrically connected to the gate electrode layer 210 of the transistor 160. The electrode layer 268a of the transistor 162 is electrically connected to the gate electrode layer 210 of the transistor 160. is connected to.

[0159] The structures of the insulating layer 230 and the insulating layer 234 can be similar to that of the insulating layer 228. If necessary, the insulating layers 228, 230, and 234 may be subjected to a planarization process. In addition, the electrode layer 268a of the transistor 162 and the gate electrode layer 268b of the transistor 160 The electrical connection with 210 is not limited to the configuration shown in FIG. 6(A), and may be made by connecting an electrode layer (or The configuration of the wiring layer and the insulating layer can be set appropriately. A separate electrode layer may be provided between the electrode layer 268a and the gate electrode layer 21. 0 may be directly connected.

[0160] In FIG. 6A, the electrode layer 202a is connected to the insulating layer 204 through a contact hole. The electrode layer 268a is electrically connected to the conductive layer 202b of the transistor 162. The electrode layer 222a is electrically connected to a wiring layer 222b provided in the same layer as the electrode layer 222a.

[0161] In FIG. 6A, the transistor 160 and the transistor 162 are at least partially In addition, the transistor 162 and the capacitor 164 are provided so as to overlap each other. It is preferable that the second insulating layer 140 is provided so as to overlap at least a part of the transistor 160. For example, the conductive layer 253 of the capacitor 164 is slightly different from the gate electrode layer 210 of the transistor 160. By adopting such a planar layout, This allows the area occupied by the semiconductor device to be reduced, thereby enabling high integration. .

[0162] Next, an example of a circuit configuration corresponding to FIG. 6(A) is shown in FIG. 6(B).

[0163] In FIG. 6B, the first wiring (1st Line) and the source voltage of the transistor 160 The electrode layer is electrically connected to the second wiring (2nd Line) and the transistor 160. The drain electrode layer is electrically connected to the third wiring (3rd Line). and one of the source electrode layer and the drain electrode layer of the transistor 162 are electrically connected to each other. The fourth wiring (4th Line) and the gate electrode layer of the transistor 162 are electrically connected to each other. The gate electrode layer of the transistor 160 and the gate electrode layer of the transistor 16 The other of the source electrode layer or the drain electrode layer of the second capacitor is electrically connected to one of the electrodes of the capacitor 164. , and the fifth wiring (5th Line) and the other electrode of the capacitor element 164 are electrically is connected to

[0164] In the semiconductor device illustrated in FIG. 6B, the potential of the gate electrode layer of the transistor 160 can be held. By taking advantage of this feature, it is possible to write, retain, and read information as follows: .

[0165] The writing and holding of data will be described. First, the potential of the fourth wiring is set to The transistor 162 is turned on by applying a potential to the transistor 162. The potential of the third wiring is applied to the gate electrode layer of the transistor 160 and the capacitor 164. That is, a predetermined charge is applied to the gate electrode layer of the transistor 160. (Write). Here, the charges that give two different potential levels (hereafter, low-level charges) Then, the fourth wiring The potential of the transistor 162 is set to a potential at which the transistor 162 is turned off. By setting the transistor 160 in the ON state, the charge applied to the gate electrode layer of the transistor 160 is held. (retain).

[0166] Since the off-state current of the transistor 162 is extremely small, the gate electrode layer of the transistor 160 The charge is retained for a long time.

[0167] Next, the reading of information will be explained. A state in which a predetermined potential (constant potential) is applied to the first wiring When an appropriate potential (read potential) is applied to the fifth wiring, the gate of the transistor 160 Depending on the amount of charge held in the electrode layer, the second wiring has a different potential. If the transistor 160 is an n-channel type, a high level is applied to the gate electrode layer of the transistor 160. The apparent threshold voltage V for a given charge th_H The gate of transistor 160 The apparent threshold voltage V when a low-level charge is applied to the gate electrode layer th_L twist Here, the apparent threshold voltage is the voltage at which the transistor 160 is turned on. The term "potential of the fifth wiring" refers to the potential of the fifth wiring required to achieve the "state". The potential of V th_H and V th_L By setting the potential V0 between the For example, in writing, the charge applied to the gate electrode layer of the If a Bell charge is applied, the potential of the fifth wire is V0 (>V th_H ) Then When a low level charge is applied, the transistor 160 is in the "on state." The potential of the fifth wire is V0( <V th_L ), transistor 160 is "off" Therefore, by observing the potential of the second wiring, the stored information It can be read out.

[0168] When memory cells are arranged in an array, only the information in a desired memory cell can be read. In memory cells that do not read information, the state of the gate electrode layer The potential at which transistor 160 is in the “off state” regardless of the state of the th_ H Alternatively, a smaller potential may be applied to the fifth wiring. First, the potential at which transistor 160 is in the "on" state, i.e., V th_L Greater than A potential can be applied to the fifth wiring.

[0169] In the semiconductor device described in this embodiment, an off-state current is low when an oxide semiconductor is used for a channel formation region. By using extremely small transistors, memory contents can be retained for an extremely long period of time. In other words, the refresh operation is unnecessary or the refresh operation is possible. This allows the frequency of operation to be reduced significantly, resulting in a significant reduction in power consumption. In addition, when there is no power supply (however, it is preferable that the potential is fixed), Even if the transistor is turned on, the stored contents can be retained for a long period of time. By making 62 a normally-off transistor, when there is no power supply, the transistor The gate (gate electrode layer 262) of the transistor 162 is configured to receive a ground potential. Thus, when there is no power supply, the transistor 162 is in an off state. can be maintained, and the memory contents can be retained.

[0170] In addition, the semiconductor device described in this embodiment does not require a high voltage for writing data. There is no problem with degradation of the capacitance. For example, unlike conventional non-volatile memory, the floating gate Since there is no need to inject electrons into the floating gate or extract electrons from the floating gate, The problem of deterioration of the gate insulating layer does not occur at all. The device does not have the limit on the number of times it can be rewritten, which is a problem with conventional non-volatile memory, and is reliable. Furthermore, the on and off states of transistors allow the Since writing is performed, high speed operation can be easily achieved.

[0171] As described above, a semiconductor device that realizes miniaturization and high integration and is endowed with high electrical characteristics is provided. It is possible to provide a semiconductor device and a method for manufacturing the semiconductor device.

[0172] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0173] (Embodiment 3) In this embodiment mode, the transistor described in Embodiment 1 is used, and a A semiconductor device that can retain memory contents even in a difficult situation and has no limit on the number of times it can be written to. Regarding the configuration, differences from the configuration shown in the second embodiment will be described with reference to FIG.

[0174] FIG. 7(A) shows an example of a circuit configuration of a semiconductor device, and FIG. 7(B) shows an example of the semiconductor device. First, the semiconductor device shown in FIG. 7(A) will be described, followed by the semiconductor device shown in FIG. The semiconductor device shown in FIG.

[0175] In the semiconductor device shown in FIG. 7A, the bit line BL and the source electrode of the transistor 162 The gate electrode layer or drain electrode layer of the transistor 162 is electrically connected to the word line WL. The source electrode layer or the drain electrode layer of the transistor 162 is electrically connected to the and a first terminal of the capacitance element 254 are electrically connected to each other.

[0176] Next, data is written and stored in the semiconductor device (memory cell 250) shown in FIG. The case where the above is performed will be explained.

[0177] First, the potential of the word line WL is set to a potential at which the transistor 162 is turned on. This causes the potential of the bit line BL to change to the potential of the capacitor 254. The potential of the word line WL is then applied to the first terminal of the transistor 1 By setting the potential at which the transistor 62 is turned off, the transistor 162 is turned off. The potential of the first terminal of the quantum element 254 is held (held).

[0178] The transistor 162 including an oxide semiconductor has an extremely low off-state current. For this reason, when the transistor 162 is turned off, the first The potential of the terminal (or the charge stored in the capacitance element 254) is kept constant for an extremely long period of time. In addition, the transistor 162 can be a normally-off transistor. By this, when no power is supplied, the gate of the transistor 162 is at ground potential. In this way, when there is no power supply, the The transistor 162 can be maintained in the off state, and the memory contents can be maintained. .

[0179] Next, the reading of information will be described. When the transistor 162 is turned on, The bit line BL and the capacitance element 254 are electrically connected to each other. As a result, the potential of the bit line BL changes. The amount of change in the potential is determined by the potential of the first terminal of the capacitance element 254 (or the potential stored in the capacitance element 254). It takes on different values ​​depending on the charge.

[0180] For example, the potential of the first terminal of the capacitance element 254 is V, the capacitance of the capacitance element 254 is C, and the bit line The capacitance component of BL (hereinafter also referred to as bit line capacitance) is CB, If the potential of the bit line BL is VB0, the potential of the bit line BL after the charge is redistributed is (CB×VB0+C×V) / (CB+C). Therefore, the state of memory cell 250 is In this case, the potential of the first terminal of the capacitance element 254 is assumed to be in two states, V1 and V0 (V1>V0). Then, the potential of the bit line BL when the potential V1 is held is (=(CB×VB0+C×V1 ) / (CB+C)) is the potential of the bit line BL when the potential V0 is held (=(CB × VB0+C×V0) / (CB+C)).

[0181] Then, by comparing the potential of the bit line BL with a predetermined potential, information can be read out. do.

[0182] As described above, in the semiconductor device illustrated in FIG. 7A, the off-state current of the transistor 162 is extremely small. Due to its small size, the charge stored in the capacitance element 254 can be held for a long time. In other words, refresh operations are not required or the frequency of refresh operations can be reduced. Since it is possible to extremely reduce the power consumption, Even if there is no power supply, the memory contents can be retained for a long period of time. do.

[0183] Next, the semiconductor device shown in FIG.

[0184] The semiconductor device shown in FIG. 7B has the memory cell 2 shown in FIG. 7A as a memory circuit in the upper portion. 50, and the memory cell arrays 251a and 251b are provided at the bottom. The peripheral circuits required to operate the array 251 (memory cell arrays 251a and 251b) The peripheral circuit 258 is electrically connected to the memory cell array 251. It is being done.

[0185] By configuring as shown in FIG. 7B, the peripheral circuit 258 is connected to the memory cell array 251 ( Since the memory cell arrays 251a and 251b can be provided directly under the It is possible to achieve miniaturization.

[0186] The transistors provided in the peripheral circuit 258 are made of a different semiconductor material from the transistor 162. It is more preferable to use silicon, germanium, silicon germanium, etc. Silicon carbide, gallium arsenide, or the like can be used, and a single crystal semiconductor can be used. In addition, organic semiconductor materials may be used. The transistor is capable of sufficiently high speed operation. It is possible to realize various circuits (logic circuits, driver circuits, etc.) that require operation in an optimal manner. do.

[0187] In the semiconductor device shown in FIG. 7B, two memory cell arrays 251 (memory cell In the above embodiment, the memory cell array 251a and the memory cell array 251b are stacked. The number of memory cell arrays to be stacked is not limited to this. This may also be a configuration.

[0188] As described above, a semiconductor device that realizes miniaturization and high integration and is endowed with high electrical characteristics is provided. It is possible to provide a semiconductor device and a method for manufacturing the semiconductor device.

[0189] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0190] (Embodiment 4) In this embodiment, as another example of a semiconductor device using the transistor described in this specification, A NOR circuit and a NAND circuit, which are logic circuits, are shown in FIGS. 8(A) to 8(C). FIG. 8(B) is a NOR type circuit, and FIG. 8(C) is a NAND type circuit. FIG. 8(A) is a B) A cross-sectional view showing the structure of transistor 802 and transistor 803 in a NOR type circuit. FIG.

[0191] In the NOR and NAND circuits shown in FIGS. 8B to 8C, p-channel transistors are used. The transistors 801, 802, 811, and 814 are the same as those shown in the second embodiment. In this embodiment, the n-type conductivity type is A p-type is added to a substrate 800 (for example, an n-type single crystal silicon substrate) using a semiconductor material having the above structure. The impurity elements that contribute to the formation of the gallium oxide include boron (B), aluminum (Al), and gallium (Ga). is introduced to form a p-channel transistor having a p-type impurity region.

[0192] In addition, the transistors 803, 804, 812, and 813, which are n-channel transistors, In the case where a channel formation region has a structure similar to that of any of the transistors described in Embodiment 1, A transistor including an oxide semiconductor film is used.

[0193] In the NOR type circuits and NAND type circuits shown in FIGS. The transistors 803, 804, 812, and 813 are semiconductor devices that sandwich a channel formation region of the oxide semiconductor layer. The source electrode layer and the drain electrode layer have a region protruding in the channel length direction at the lower end. Therefore, the electric field concentration between the electrode layers can be alleviated, and the source electrode layer and the drain electrode layer can be formed in a thin film. The gate insulating layer may include an insulating layer provided between the gate electrode layer and the gate electrode layer. Therefore, the parasitic capacitance between the electrode layer and the gate electrode layer can be reduced. A first gate electrode layer and a second gate electrode layer are provided to sandwich the oxide semiconductor layer. One of the gate electrode layers is used as a so-called back gate to appropriately control the potential. For example, By connecting the transistors 803, 804, 812, and 813 to GND, the threshold voltages of the transistors 803, 804, 812, and 813 are It can be made a positive transistor and a normally-off transistor.

[0194] In this embodiment, in the NOR circuit, the transistor 803 and the transistor 8 The gate electrode layers that can function as back gates are electrically connected to each other, and N In the AND circuit, a transistor 812 and a transistor 813 are provided with a back An example in which gate electrode layers functioning as gates are electrically connected to each other is shown. However, this is not limited to this. The gate electrode layers functioning as back gates are electrically controlled independently. The structure may be such that

[0195] The semiconductor device shown in FIG. 8A uses a single crystal silicon substrate as a substrate 800. A transistor 802 is formed on a silicon substrate, and an oxide semiconductor layer is formed on the transistor 802. This is an example in which a transistor 803 is stacked in a channel formation region. An element isolation insulating layer 806 is provided to surround the transistor 802 .

[0196] The electrode layer 841b electrically connected to the gate electrode layer 841a of the transistor 803 is a gate The insulating layer 843, the insulating layer 839, the oxide insulating layer 838, and the insulating layer 837 are Through the contact hole, the electrode layer 83, which is an electrode layer provided in the same layer as the conductive layer 840, The electrode layer 835 is provided on the insulating layer 836 and the insulating layer 833. The wiring layer 832 is electrically connected to the contact hole. Although not shown, the wiring layer 832 is formed by a contact provided on the insulating layer 830 and the insulating layer 826. The gate electrode layer 821 of the transistor 802 is electrically connected to the gate electrode layer 821 through a tact hole. Therefore, the gate electrode layer 841a of the transistor 803 is the same as the gate It is electrically connected to the electrode layer 821 .

[0197] Although not explicitly shown in FIG. 8A, the electrode layer 825 of the transistor 802 is The wiring layer 834 is electrically connected to the transistor through the electrode layer 831. The electrode layer 845 of the transistor 802 is electrically connected to the electrode layer 845 of the transistor 803. The transistor 803 is electrically connected to an electrode layer 845 of the transistor 803 .

[0198] Note that the electrode layer (or gate electrode layer) of the transistor 802 and the electrode The electrical connection between the layer (or gate electrode layer) is not limited to the configuration shown in FIG. The configurations of the electrode layer (or wiring layer) and insulating layer can be set appropriately.

[0199] As shown in FIG. 8A, a transistor 802 and a transistor 803 may be stacked. By this, the area occupied by the semiconductor device can be reduced, and therefore high integration can be achieved. In addition, the transistor 802 can be a transistor that can be normally off. Therefore, the logic circuit can be controlled accurately.

[0200] As described above, a semiconductor device that realizes miniaturization and high integration and is endowed with high electrical characteristics is provided. It is possible to provide a semiconductor device and a method for manufacturing the semiconductor device.

[0201] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0202] (Embodiment 5) In this embodiment, the transistor disclosed in the first embodiment is used as an example of a semiconductor device. CPU (Central Processing Unit) that uses at least a part of This article explains:

[0203] Fig. 9A is a block diagram showing a specific configuration of a CPU. On a substrate 1190, an ALU 1191 (ALU: Arithmetic logic unit, arithmetic circuit), ALU controller 1192, instruction decoder 11 93, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface 1198 (Bus I / F), rewritable ROM 1199, and ROM interface 1189 (ROM The substrate 1190 may be a semiconductor substrate, an SOI substrate, a glass substrate, etc. The ROM 1199 and the ROM interface 1189 may be provided on a separate chip. Of course, the CPU shown in FIG. 9(A) is merely an example showing a simplified configuration. Actual CPUs have a wide variety of configurations depending on their applications.

[0204] The instructions input to the CPU via the bus interface 1198 are The signal is input to the decoder 1193, decoded, and then passed to the ALU controller 1192, the interface Rupture Controller 1194, Register Controller 1197, Timing Controller Entered into 1195.

[0205] ALU controller 1192, interrupt controller 1194, register controller The controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates signals for the CPU program. During system execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and mask. The register controller 1197 determines the address of the register 1196 and processes it. It generates addresses and reads and writes to register 1196 depending on the state of the CPU.

[0206] The timing controller 1195 also includes the ALU 1191 and the ALU controller 119 2, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal that controls the operation timing of the register controller 1197. The timing controller 1195 generates an internal clock signal C based on the reference clock signal CLK1. The internal clock signal CLK2 is generated by the internal clock generator 100. Supply to the seed circuit.

[0207] In the CPU shown in FIG. 9A, a register 1196 is provided with a memory cell. The memory cells of the first 1196 are the same as those disclosed in the second or third embodiment. Good too.

[0208] In the CPU shown in FIG. 9A, the register controller 1197 According to the instruction from the register 1196, the holding operation is selected. In the memory cell of 1196, data is held by a logic element that inverts the logical value. The logic value is inverted, or the data is held by a capacitive element. If the element is selected to retain data, When data retention in the capacitive element is selected, the capacitive element is turned on. The data is rewritten to the element, and the supply of the power supply voltage to the memory cell in the register 1196 is stopped. Payment may be stopped.

[0209] Regarding the power supply stop, as shown in FIG. 9(B) or FIG. 9(C), the memory cell group and the power supply A switching element is provided between nodes to which the potential VDD or the power supply potential VSS is applied. The circuits in Figures 9(B) and 9(C) will be described below.

[0210] In FIG. 9B and FIG. 9C, a switching element that controls the supply of a power supply potential to a memory cell is shown. An example of the structure of a memory circuit including the transistor disclosed in Embodiment 1 is shown as an element.

[0211] The memory device shown in FIG. 9B includes a switching element 1141 and a plurality of memory cells 1142. Specifically, each memory cell 1142 has a real The memory cells described in the second or third embodiment can be used. Each memory cell 1142 of the semiconductor memory device 43 is connected to a high level through a switching element 1141. The power supply potential VDD of each memory cell is supplied to the memory cell group 1143. The cell 1142 is supplied with the potential of the signal IN and the potential of the low-level power supply potential VSS. There are.

[0212] In FIG. 9B, the transistor disclosed in the first embodiment is used as the switching element 1141. The transistor is driven by a signal SigA applied to its gate electrode layer. This provides better control over switching.

[0213] In FIG. 9B, the switching element 1141 has only one transistor. However, there is no particular limitation and a plurality of transistors may be included. When the element 1141 has a plurality of transistors functioning as switching elements, The plurality of transistors may be connected in parallel or in series. Alternatively, the circuits may be connected in series and parallel in combination.

[0214] In FIG. 9B, the switching element 1141 switches the memory cell group 1143. The supply of a high-level power supply potential VDD to each memory cell 1142 is controlled. The supply of the low-level power supply potential VSS is controlled by the switching element 1141. Good too.

[0215] In addition, in FIG. 9C, each memory cell 1142 included in the memory cell group 1143 is A memory device to which a low-level power supply potential VSS is supplied via a switching element 1141. The switching element 1141 switches each memory cell in the memory cell group 1143. The supply of the low-level power supply potential VSS to the recell 1142 can be controlled.

[0216] A switch is provided between the memory cell group and a node to which the power supply potential VDD or the power supply potential VSS is applied. When a switching element is installed to temporarily stop the CPU operation and cut off the supply of power voltage It is possible to retain data even in this state, and power consumption can be reduced. Specifically, for example, a user of a personal computer inputs information to an input device such as a keyboard. You can stop the CPU from operating while you are no longer entering information, which reduces power consumption. Power consumption can be reduced.

[0217] Here, we have taken the CPU as an example, but the same can also be said for DSP (Digital Signal Processor). processor), custom LSI, FPGA (Field Programmable Gauge It can also be applied to LSIs such as MOSFET's (MOSFET gate arrays).

[0218] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0219] In addition, spin-transfer magnetoresistive random access memory (MRAM), also known as a spintronics device, Table 1 shows a comparison between MRAM and memories that use oxide semiconductors.

[0220] [Table 1]

[0221] Combining oxide semiconductor transistors and silicon transistors As shown in Table 1, compared to spintronics devices, the drive method and writing principle of the The theory and materials are very different.

[0222] In addition, a transistor using an oxide semiconductor and a transistor using silicon can be combined. As shown in Table 1, the memory that is used has advantages over spintronics devices such as heat resistance and 3D (Three or more layered structure), magnetic field resistance, and other advantages. The overhead power is the power consumed to write data to the memory in the processor. This refers to the power consumed by the head.

[0223] Thus, oxide semiconductor-based metal-oxide semiconductor devices have many advantages over spintronics devices. By using memory, it is possible to reduce CPU power consumption.

[0224] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0225] (Embodiment 6) The semiconductor device disclosed in this specification can be applied to various electronic devices (including game machines). The electronic devices include televisions, monitors and other display devices, lighting devices, desktop Or notebook type personal computer, word processor, DVD (Digital Playing still or moving images stored on a recording medium such as a Versatile Disc image reproduction devices, portable CD players, radios, tape recorders, headphone stereos Audio, stereos, cordless telephone handsets, transceivers, portable radios, mobile phones, car phones , portable game consoles, calculators, personal digital assistants, electronic organizers, electronic books, electronic translators, voice input devices appliances, video cameras, digital still cameras, electric shavers, microwave ovens and other high-frequency heating equipment Electric rice cookers, electric washing machines, vacuum cleaners, air conditioners and other air conditioning equipment, tableware Washing machines, dish dryers, clothes dryers, futon dryers, electric refrigerators, electric freezers, electric refrigerators These include medical equipment such as refrigerators, freezers for storing DNA, smoke detectors, radiation detectors, and dialysis machines. In addition, it is used in emergency exit lights, traffic lights, conveyor belts, elevators, escalators, industrial Examples include industrial equipment such as robots and power storage systems. In addition, oil-based engines and Vehicles propelled by electric motors using power from non-aqueous secondary batteries are also included in the category of electrical equipment. The above-mentioned moving body includes, for example, an electric vehicle (EV), an internal combustion engine, and Hybrid electric vehicles (HEV) and plug-in hybrid electric vehicles (PHEV) These tires and wheels are converted into tracks, and motorized vehicles including electric-assisted bicycles Bicycles, motorcycles, electric wheelchairs, golf carts, small or large boats, submarines, helicopters Examples of spacecraft include microcomputers, aircraft, rockets, satellites, space probes, interplanetary rovers, and spacecraft. Specific examples of these electronic devices are shown in FIG.

[0226] FIG. 10A shows a table 9000 having a display section. The table 9000 includes: A display unit 9003 is incorporated in a housing 9001, and an image is displayed on the display unit 9003. In addition, the configuration in which the housing 9001 is supported by four legs 9002 is shown. The housing 9001 also includes a power cord 9005 for power supply.

[0227] The transistor described in Embodiment 1 can be used in the display portion 9003 and can be used in electronic devices. This can provide high reliability to the device.

[0228] The display unit 9003 has a touch input function, and the display unit 9003 of the table 9000 By touching the displayed display button 9004 with a finger or the like, the screen can be operated or information can be input. It can also communicate with other home appliances or control them, making the screen It may also be used as a control device to control other home appliances by operation. For example, an image sensor If a semiconductor device having a sensor function is used, the display portion 9003 can have a touch input function. This can be done.

[0229] In addition, the screen of the display unit 9003 can be vertically supported on the floor by a hinge provided on the housing 9001. It can also be set upright and used as a television set. If you install a large screen television, the free space will be narrowed, but if you put it on a table, If the display unit is built in, the space in the room can be used more effectively.

[0230] FIG. 10B shows a portable music player. The main body 3021 has a display unit 3023 and an earphone. A fixing part 3022 for attaching the device to the computer, a speaker, an operation button 3024, and an external memory slot 3 025, etc. are provided. The memory and logic circuit shown are applied to the memory and CPU built into the main body 3021. This makes it possible to make a portable music player (PDA) more energy efficient.

[0231] Furthermore, the portable music player shown in FIG. 10(B) may be equipped with an antenna, a microphone function, and a wireless function. By linking it to a mobile phone, you can enjoy wireless hands-free driving while driving a car. Conversation is also possible.

[0232] FIG. 10C shows a computer, which includes a main body 9201 including a CPU, a housing 9202, a display unit 9203, keyboard 9204, external connection port 9205, pointing device 92 The computer displays a semiconductor device manufactured using one embodiment of the present invention. By using the CPU shown in the fifth embodiment, This makes it possible to realize a computer with reduced power consumption.

[0233] Figures 11(A) and 11(B) show a tablet-type terminal that can be folded in two. Figure 11(A) 9 shows the tablet terminal in an open state. The tablet terminal includes a housing 9630, a display unit 9631a, and a display unit 9631b, display mode switch 9034, power switch 9035, power saving mode It has a mode changeover switch 9036, a fastener 9033, and an operation switch 9038.

[0234] In the portable devices shown in FIG. 11(A) and FIG. 11(B), image data is temporarily stored. For example, in the second embodiment, an SRAM or a DRAM is used as a memory. The semiconductor device described in the above embodiment can be used as a memory. By adopting this semiconductor device in memory, writing and reading of information can be performed at high speed. This allows long-term storage and reduces power consumption.

[0235] In addition, a part of the display unit 9631a can be used as a touch panel area 9632a. By touching the operation keys 9638 shown on the display, data can be input. In the example of 9631a, half of the area has a display function, and the other half The display area has a touch panel function, but is not limited to this. The entire area of ​​9631a may have a touch panel function. The entire surface of the display section 9631a is used as a touch panel by displaying keyboard buttons, and the display section 9631b can be used as a display screen.

[0236] In addition, in the display unit 9631b, as in the display unit 9631a, The area 9632b of the touch panel can be used as the keyboard of the touch panel. By touching the area where the display switch button 9639 is displayed with your finger or a stylus, A keyboard button can be displayed on the display portion 9631b.

[0237] In addition, the touch panel area 9632a and the touch panel area 9632b can be touched simultaneously. You can also input the character.

[0238] A display mode changeover switch 9034 is used to change the display orientation between portrait and landscape. You can switch between black and white and color display. The 9036 tablet device is equipped with a light sensor that detects external light during use. The display brightness can be optimized according to the amount of light. In addition, it also incorporates other detection devices such as gyros, acceleration sensors, and other sensors that detect tilt. It may be stored.

[0239] FIG. 11A shows an example in which the display area of ​​the display portion 9631b is the same as that of the display portion 9631a. However, there is no particular limitation, and one size may be different from the other size. For example, one display panel may have a higher resolution than the other. It is also possible to use the following.

[0240] FIG. 11B shows the tablet terminal in a closed state. The tablet terminal includes a housing 9630 and a solar cell 96 33, a charge / discharge control circuit 9634, a battery 9635, and a DCDC converter 9636 In addition, in FIG. 11B, a battery 9635 is used as an example of the charge and discharge control circuit 9634. , a configuration having a DC-DC converter 9636 is shown.

[0241] In addition, since the tablet device can be folded in half, the housing 9630 can be folded when not in use. Therefore, the display portions 9631a and 9631b can be protected, and thus the durability can be improved. This makes it possible to provide a tablet terminal that is highly durable and reliable even for long-term use.

[0242] In addition, the tablet terminals shown in Figs. 11(A) and 11(B) can store various information. Functions for displaying information (still images, videos, text images, etc.), calendars, dates, or times, etc. A function to display information on the display unit, and a function to operate or edit the information displayed on the display unit by touch input. It has the function of inputting information, the function of controlling processing by various software (programs), etc. This can be done.

[0243] The solar cell 9633 attached to the surface of the tablet device supplies power to the touch panel, The solar cell 9633 can be provided to a display unit, a video signal processor, or the like. The battery 9635 can be efficiently charged by providing a light emitting diode (LED) on one or both sides of the body 9630. The battery 9635 may be a lithium-ion battery. The use of such a structure has the advantage of enabling miniaturization.

[0244] The configuration and operation of the charge / discharge control circuit 9634 shown in FIG. ) shows a block diagram and explains the device. In FIG. 11(C), a solar cell 9633, a battery 96 35, DC-DC converter 9636, converter 9637, switches SW1 to SW3, The figure shows a display unit 9631, a battery 9635, and a DC-DC converter 9636. The converter 9637 and the switches SW1 to SW3 constitute a charge / discharge control circuit shown in FIG. This corresponds to route 9634.

[0245] First, an example of operation in which power is generated by the solar cell 9633 using external light will be described. The power generated by the solar cell 9633 becomes the voltage for charging the battery 9635. The voltage is increased or decreased by the DC-DC converter 9636. When power is used from the solar cell 9633 for operation, switch SW1 is turned on and the converter The voltage is increased or decreased by the power supply 9637 to a voltage required for the display unit 9631. When you do not want to display anything on the display unit 9631, turn SW1 off and SW2 on to turn on the battery. It is sufficient to configure it to charge the Lee 9635.

[0246] The solar cell 9633 is shown as an example of a power generating means, but is not limited thereto. Batteries using other power generation methods such as piezoelectric elements and thermoelectric conversion elements For example, the device may be configured to transmit and receive power wirelessly (contactlessly). A configuration that combines a non-contact power transmission module that charges by connecting the device to the power source and other charging methods. It is also possible to use the following.

[0247] In FIG. 12A, a television set 8000 includes a housing 8001 and a display unit 8002. It displays images on a display unit 8002 and outputs audio from a speaker unit 8003. The transistor described in Embodiment 1 is used in the display portion 8002. It is possible to use.

[0248] The display unit 8002 is a light-emitting device having light-emitting elements such as a liquid crystal display device or an organic EL element in each pixel. Device, electrophoretic display device, DMD (Digital Micromirror Device e) and PDP (Plasma Display Panel), It can be used.

[0249] The television device 8000 may include a receiver, a modem, and the like. The device 8000 can receive general television broadcasts using a receiver and also has a modem. By connecting to a wired or wireless communication network via to communicate information to a single person (i.e., a single person), or two-way (i.e., between a sender and a receiver, or between receivers themselves) It is also possible.

[0250] The television device 8000 also includes a CPU and a memory for performing information communication. The television device 8000 may include the memory described in any one of the second to fifth embodiments. It is possible to use a logic circuit or a CPU.

[0251] In FIG. 12A, an air conditioner having an indoor unit 8200 and an outdoor unit 8204 is shown. The indoor unit 8200 is an example of an electrical device using the CPU of the fifth embodiment. The electronic device includes a housing 8201, an air outlet 8202, a CPU 8203, and the like. In the illustrated example, the CPU 8203 is provided in the indoor unit 8200. 203 may be provided in the outdoor unit 8204. Alternatively, the indoor unit 8200 and the outdoor unit 82 The CPU 8203 may be provided in both the CPU 8204 and the CPU 8205. Because the CPU uses oxide semiconductors, it has excellent heat resistance and is a highly reliable air conditioner. A conditioner can be realized.

[0252] In FIG. 12A, an electric refrigerator-freezer 8300 includes a CPU using an oxide semiconductor. Specifically, the electric refrigerator-freezer 8300 includes a housing 8301, a refrigerator compartment, 12A, the C The PU 8304 is provided inside the housing 8301. By using it for the CPU 8304 of an electric refrigerator-freezer 8300, power saving can be achieved.

[0253] FIG. 12B shows an example of an electric vehicle, which is an example of an electric device. 0 is equipped with a secondary battery 9701 (FIG. 12(C)). The output of the control circuit 9702 is adjusted and supplied to the driver 9703. The circuit 9702 is controlled by a processing unit 9704 having a ROM, RAM, CPU, etc. (not shown). By using the CPU shown in the fifth embodiment as the CPU of the electric vehicle 9700, This allows for power saving.

[0254] The driving device 9703 is a DC motor or an AC motor alone, or a combination of a motor and an internal combustion engine. The processing device 9704 is configured in combination with the electric vehicle 9700. (acceleration, deceleration, stopping, etc.) and driving information (uphill and downhill slopes, etc., load on the drive wheels) Based on input information (such as shipment information), the control circuit 9702 outputs a control signal. 702 is a secondary battery 9701 supplied with electric energy by a control signal from a processing device 9704. It adjusts the energy and controls the output of the drive unit 9703. Although not shown, an inverter for converting direct current to alternating current is also built in.

[0255] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination. [Explanation of symbols]

[0256] 100 Substrates 102 Conductive layer 103 Insulating layer 104 Insulating layer 105 Insulating layer 106 Oxide insulating layer 107 Oxide insulating layer 108 Oxide semiconductor layer 108a Oxide semiconductor layer 108b Oxide semiconductor layer 110 Conductive film 110a source electrode layer 110b Drain electrode layer 111a area 111b area 111c area 111d area 112 Insulating layer 113 Gate insulating film 114 Gate Insulation Layer 116 Gate electrode layer 117 Gate Insulation Layer 118 Insulating Layer 120 Transistor 122 Transistor 124 Transistor 126 Transistor 128 Transistors 130 Transistor 150 Opening 160 Transistors 162 Transistor 164 Capacitive element 170a Resist mask 170b resist mask 180 Resist Mask 200 boards 202a Electrode layer 202b Conductive layer 203 Insulating layer 204 Insulating layer 205 Insulating layer 206 Element isolation insulating layer 208 Gate Insulation Layer 210 Gate electrode layer 212a Electrode layer 212b Electrode layer 214 Impurity region 216 Channel formation region 218 Sidewall insulating layer 220 High concentration impurity region 222a Electrode layer 222b wiring layer 224 Intermetallic compound area 228 Insulating Layer 230 Insulating layer 232 Insulating layer 234 Insulating layer 235 Insulating Layer 244 Oxide semiconductor layer 250 memory cells 251 Memory Cell Array 251a Memory Cell Array 251b Memory Cell Array 253 Conductive Layer 254 Capacitive element 256 wiring layer 258 Peripheral Circuits 260 Gate Insulation Layer 262 Gate electrode layer 263 Insulating Layer 268a Electrode layer 268b Electrode layer 800 boards 801 Transistors 802 Transistor 803 Transistor 804 Transistor 806 Element isolation insulating layer 811 Transistor 812 Transistor 813 Transistor 814 Transistor 821 Gate electrode layer 825 Electrode layer 826 Insulating layer 830 Insulating layer 831 Electrode layer 832 Wiring layer 833 Insulation Layer 834 Wiring layer 835 Electrode layer 836 Insulating layer 837 Insulating layer 838 Oxide insulating layer 839 Insulating layer 840 Conductive Layer 841a Gate electrode layer 841b Electrode layer 843 Gate Insulation Layer 845 Electrode layer 1141 Switching element 1142 Memory Cell 1143 Memory Cell Group 1189 ROM Interface 1190 Board 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Registers 1197 Register Controller 1198 Bus Interface 1199 ROM 3021 Main unit 3022 Fixed part 3023 Display section 3024 Operation button 3025 External Memory Slot 8000 Television Equipment 8001 Case 8002 Display section 8003 Speaker section 8200 indoor unit 8201 Case 8202 Ventilator 8203 CPU 8204 Outdoor unit 8300 Electric refrigerator-freezer 8301 Case 8302 Refrigerator door 8303 Freezer door 8304 CPU 9000 Table 9001 Case 9002 Legs 9003 Display section 9004 Display button 9005 Power Cord 9033 Fastener 9034 Switch 9035 Power Switch 9036 Switch 9038 Operation switch 9201 Main unit 9202 Case 9203 Display section 9204 Keyboard 9205 External connection port 9206 Pointing Device 9630 Case 9631 Display section 9631a Display section 9631b Display section 9632a area 9632b area 9633 Solar Cells 9634 Charge / discharge control circuit 9635 Battery 9636 DC-DC Converter 9637 Converter 9638 Operation key 9639 Button 9700 Electric Vehicle 9701 Secondary battery 9702 Control circuit 9703 Drive unit 9704 Processing Equipment

Claims

1. A first transistor; a first insulating layer having a region overlying the first transistor; a second transistor above the first insulating layer; a capacitance element electrically connected to the first transistor and the second transistor, The first transistor is a first channel formation region having silicon; a first gate insulating layer having a region located above the first channel forming region; a first gate electrode layer having a region located above the first gate insulating layer; The second transistor is a second gate electrode layer over the first insulating layer; a second gate insulating layer having a region located above the second gate electrode layer; an oxide semiconductor layer having a region located above the second gate insulating layer; a third gate insulating layer having a region located above the oxide semiconductor layer; a third gate electrode having a region located above the third gate insulating layer; a first conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as one of a source electrode layer and a drain electrode layer; the first conductive layer is electrically connected to the first gate electrode layer; the first conductive layer has a region that functions as a first electrode of the capacitor element, a second conductive layer above the first conductive layer; the second conductive layer functions as a second electrode of the capacitor; the second conductive layer has a region overlapping with the first gate electrode layer.

2. A first transistor; a first insulating layer having a region overlying the first transistor; a second transistor above the first insulating layer; a capacitance element electrically connected to the first transistor and the second transistor, The first transistor is a first channel formation region having silicon; a first gate insulating layer having a region located above the first channel forming region; a first gate electrode layer having a region located above the first gate insulating layer; the first insulating layer comprises Si and N; The second transistor is a second gate electrode layer over the first insulating layer; a second gate insulating layer having a region located above the second gate electrode layer; an oxide semiconductor layer having a region located above the second gate insulating layer; a third gate insulating layer having a region located above the oxide semiconductor layer; a third gate electrode having a region located above the third gate insulating layer; a first conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as one of a source electrode layer and a drain electrode layer; the first conductive layer is electrically connected to the first gate electrode layer; the first conductive layer has a region that functions as a first electrode of the capacitor element, a second conductive layer above the first conductive layer; the second conductive layer functions as a second electrode of the capacitor.

3. A first transistor; a first insulating layer having a region overlying the first transistor; a second transistor above the first insulating layer; a capacitance element electrically connected to the first transistor and the second transistor, The first transistor is a first channel formation region having silicon; a first gate insulating layer having a region located above the first channel forming region; a first gate electrode layer having a region located above the first gate insulating layer; the first insulating layer comprises Si and N; The second transistor is a second gate electrode layer over the first insulating layer; a second gate insulating layer having a region located above the second gate electrode layer; an oxide semiconductor layer having a region located above the second gate insulating layer; a third gate insulating layer having a region located above the oxide semiconductor layer; a third gate electrode having a region located above the third gate insulating layer; a first conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as one of a source electrode layer and a drain electrode layer; the first conductive layer is electrically connected to the first gate electrode layer; the first conductive layer has a region that functions as a first electrode of the capacitor element, a second conductive layer above the first conductive layer; the second conductive layer functions as a second electrode of the capacitor; the second conductive layer has a region overlapping with the first gate electrode layer.

4. In any one of claims 1 to 3, the oxide semiconductor layer does not have a region overlapping with the first channel formation region.

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