Semiconductor device, control method for semiconductor device, and manufacturing method for semiconductor device

Abstract

To expand an acceptable range of a time difference between the transition of a first signal and the transition of a second signal.SOLUTION: A semiconductor device includes a semiconductor substrate, a first semiconductor layer and a second semiconductor layer that are positioned exclusively on a surface layer of the semiconductor substrate, a third semiconductor layer positioned on the opposite side of the semiconductor substrate with respect to the first semiconductor layer and the second semiconductor layer, a fourth semiconductor layer and a fifth semiconductor layer that are positioned exclusively on the opposite side of the semiconductor substrate with respect to the third semiconductor layer, and a first electrode, a second electrode, and a third electrode whose surfaces have an insulating property. The first electrode extends to reach the first semiconductor layer through the first semiconductor layer, the second semiconductor layer, the fifth semiconductor layer, and the third semiconductor layer. The second electrode extends to reach the semiconductor substrate through the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer, or through the second semiconductor layer, the third semiconductor layer, and the fifth semiconductor layer. The third electrode extends to reach the semiconductor substrate through the fourth semiconductor layer and the third semiconductor layer, separates the first semiconductor layer from the second semiconductor layer, and has the second semiconductor layer held between the third electrode and the second electrode.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The technology disclosed in this specification relates to a semiconductor device. [Background technology]

[0002] Insulated gate bipolar transistors (hereinafter referred to as "IGBTs") are well known as semiconductor devices. In an IGBT, for example, an impurity layer is provided on the upper surface of a semiconductor substrate. For example, trenches penetrating the impurity layer are provided periodically. An insulating layer is provided on the side and bottom of the trench. A conductor is provided in the trench and surrounded by the insulating layer. For example, the impurity layer functions as a channel layer, and the semiconductor substrate functions as a drift layer.

[0003] An IGBT may employ two types of trenches with different depths (see, for example, Patent Document 1). For example, the deep trench reaches the semiconductor substrate as the drift layer, and the shallow trench does not reach the drift layer.

[0004] Signals for controlling the operation of the semiconductor device are provided separately to the conductor in the deep trench and the conductor in the shallow trench, and these signals control the carrier concentration in the channel layer around each trench. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2016-154218 A Summary of the Invention [Problem to be solved by the invention]

[0006] As an example of the operation when an IGBT having the above-mentioned configuration is turned off, the following sequence is assumed, where a first signal is applied to the conductor provided in the shallow trench and a second signal is applied to the conductor provided in the deep trench: the OFF transition of the second signal is earlier than the OFF transition of the first signal. Here, the "OFF transition" is the voltage transition acting in the direction of reducing the carrier concentration as described above.

[0007] With this sequence, the carrier concentration on the impurity layer side of the semiconductor substrate is first reduced by the OFF transition of the second signal, and then the semiconductor device is turned off by the OFF transition of the first signal. This sequence shortens the time it takes to turn off the semiconductor device, and reduces the turn-off loss after the OFF transition of the first signal. On the other hand, the reduction in the carrier concentration of the semiconductor substrate increases the forward voltage of the semiconductor device, and the forward conduction loss from the OFF transition of the second signal to the OFF transition of the first signal increases.

[0008] It is envisioned that the increase in forward conduction losses may exceed the decrease in turn-off losses following the OFF transition of the first signal, in which case the total amount of losses following the OFF transition of the second signal may increase compared to the case where the OFF transition of the first signal and the OFF transition of the second signal occur in parallel.

[0009] One possible technique for minimizing the total amount is to optimize the time difference between the OFF transition of the second signal and the OFF transition of the first signal. However, the allowable range of the time difference is narrow, which may cause problems such as variations in the total amount of the above-mentioned losses and difficulty in controlling the OFF transition to obtain the optimal time difference.

[0010] The technology disclosed in this specification has been made in consideration of such problems, and aims to expand the permissible range of the time difference between the transition of a first signal and the transition of a second signal. [Means for solving the problem]

[0011] A semiconductor device according to a first aspect of the technology disclosed herein includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type located on a surface layer of the semiconductor substrate, a second semiconductor layer of the first conductivity type located exclusively with the first semiconductor layer on the surface layer of the semiconductor substrate and having a peak value of impurity concentration higher than that of the semiconductor substrate, a third semiconductor layer of a second conductivity type located on the opposite side of the semiconductor substrate with respect to the first semiconductor layer and the second semiconductor layer, a fourth semiconductor layer of a second conductivity type located selectively on the opposite side of the semiconductor substrate with respect to the third semiconductor layer and having a peak value of impurity concentration higher than that of the third semiconductor layer, a fifth semiconductor layer of a first conductivity type located exclusively with the fourth semiconductor layer on the opposite side of the semiconductor substrate with respect to the third semiconductor layer and having a peak value of impurity concentration higher than that of the second semiconductor layer, and a sixth semiconductor layer of a second conductivity type located on the opposite side to both of the body layers; a first electrode penetrating the fifth semiconductor layer and the third semiconductor layer, extending to reach the first semiconductor layer farther from the sixth semiconductor layer than a boundary between the second semiconductor layer and the semiconductor substrate, and having an insulating surface; a second electrode penetrating the second semiconductor layer, the fourth semiconductor layer, and the third semiconductor layer, or penetrating the second semiconductor layer, the fifth semiconductor layer, and the third semiconductor layer, extending to reach the semiconductor substrate, being closer to the sixth semiconductor layer than both of the first semiconductor layer and the second semiconductor layer, and having an insulating surface; and a third electrode penetrating the fourth semiconductor layer and the third semiconductor layer, extending to reach the semiconductor substrate, being closer to the sixth semiconductor layer than both of the first semiconductor layer and the second semiconductor layer, separating the first semiconductor layer from the second semiconductor layer, sandwiching the second semiconductor layer together with the second electrode, and having an insulating surface.

[0012] A second aspect of the technology disclosed herein is a method for controlling a semiconductor device, wherein a first signal is provided to the first electrode and a second signal is provided to the second electrode, and when both the first signal and the second signal are transitioned to turn off the semiconductor device, the first signal transitions with a delay relative to the second signal. Effect of the Invention

[0013] According to the semiconductor device and the control method thereof according to the present disclosure, the allowable range of the delay time between the OFF transition of the first signal applied to the first electrode and the OFF transition of the second signal applied to the second electrode is expanded.

[0014] Objects, features, aspects and advantages associated with the technology disclosed herein will become more apparent from the detailed description set forth below and the accompanying drawings. [Brief description of the drawings]

[0015] [Figure 1] 1 is a cross-sectional view showing an example of a configuration of a semiconductor device according to a first embodiment. [Diagram 2] 4 is a cross-sectional view showing another example of the configuration of the semiconductor device according to the first embodiment. FIG. [Diagram 3] 4 is a cross-sectional view showing another example of the configuration of the semiconductor device according to the first embodiment. FIG. [Figure 4] 1 is a circuit diagram illustrating a circuit for applying two types of gate voltages to an IGBT. [Diagram 5] FIG. 2 is a waveform diagram illustrating a sequence of two gate voltages. [Figure 6] 4 is a waveform diagram illustrating the operation of turning off an IGBT. FIG. [Figure 7] 1 is a cross-sectional view illustrating a configuration of a semiconductor device according to a comparative example; [Figure 8] 13 is a graph showing the dependency of the total loss on the time difference. [Figure 9] 11 is a waveform diagram illustrating an operation of turning off an IGBT in the comparative example. [Figure 10] 10 is an enlarged waveform diagram showing a region R10 in FIG. 9. FIG. [Figure 11] 10 is an enlarged waveform diagram showing a region R11 in FIG. 9. [Figure 12] 4 is a waveform diagram illustrating an operation of turning off an IGBT in the embodiment. [Figure 13] 13 is an enlarged waveform diagram showing a region R13 in FIG. 12. FIG. [Figure 14] 13 is an enlarged waveform diagram showing a region R14 in FIG. 12. FIG. [Figure 15] 1 is a graph showing the dependence of the total loss amount on the saturation voltage. [Figure 16] FIG. 11 is a waveform diagram showing another example of a sequence of two types of gate voltages. [Figure 17] FIG. 2 is a waveform diagram illustrating the on-transition of two types of gate voltages. [Figure 18] FIG. 2 is a waveform diagram illustrating the on-transition of two types of gate voltages. [Figure 19] 4 is a waveform diagram illustrating an operation when the semiconductor device according to the first embodiment is turned on. FIG. [Figure 20] 4 is a waveform diagram illustrating an operation when the semiconductor device according to the first embodiment is turned on. FIG. [Figure 21] FIG. 11 is a cross-sectional view illustrating the configuration of a semiconductor device according to a second embodiment. [Figure 22] 11 is a waveform diagram illustrating an operation when the semiconductor device according to the second embodiment is turned on. FIG. [Figure 23] FIG. 11 is a cross-sectional view illustrating the configuration of a semiconductor device according to a third embodiment. [Figure 24] FIG. 11 is a cross-sectional view illustrating the configuration of a semiconductor device according to a fourth embodiment. [Diagram 25] 1 is a graph illustrating the relationship between the withstand voltage of a semiconductor device and the distance between trench electrodes. [Figure 26] 1A to 1C are cross-sectional views illustrating a part of a first manufacturing method of the semiconductor device according to the first embodiment in order of steps. [Figure 27] 1A to 1C are cross-sectional views illustrating a part of a first manufacturing method of the semiconductor device according to the first embodiment in order of steps. [Figure 28] 1A to 1C are cross-sectional views illustrating a part of a first manufacturing method of the semiconductor device according to the first embodiment in order of steps. [Figure 29] 1A to 1C are cross-sectional views illustrating a part of a first manufacturing method of the semiconductor device according to the first embodiment in order of steps. [Diagram 30] 1A to 1C are cross-sectional views illustrating a part of a first manufacturing method of the semiconductor device according to the first embodiment in order of steps. [Diagram 31] 1A to 1C are cross-sectional views illustrating a part of a first manufacturing method of the semiconductor device according to the first embodiment in order of steps. [Diagram 32] 1A to 1C are cross-sectional views illustrating a part of a first manufacturing method of the semiconductor device according to the first embodiment in order of steps. [Diagram 33] 1A to 1C are cross-sectional views illustrating a part of a first manufacturing method of the semiconductor device according to the first embodiment in order of steps. [Diagram 34] 1A to 1C are cross-sectional views illustrating a part of a first manufacturing method of the semiconductor device according to the first embodiment in order of steps. [Diagram 35] 1A to 1C are cross-sectional views illustrating a part of a first manufacturing method of the semiconductor device according to the first embodiment in order of steps. [Diagram 36] 1A to 1C are cross-sectional views illustrating a part of a first manufacturing method of the semiconductor device according to the first embodiment in order of steps. [Figure 37] 1A to 1C are cross-sectional views illustrating a part of a first manufacturing method of the semiconductor device according to the first embodiment in order of steps. [Figure 38] 5A to 5C are cross-sectional views illustrating a part of a second manufacturing method for the semiconductor device according to the first embodiment in order of steps. [Figure 39] 5A to 5C are cross-sectional views illustrating a part of a second manufacturing method for the semiconductor device according to the first embodiment in order of steps. [Diagram 40] 5A to 5C are cross-sectional views illustrating a part of a second manufacturing method for the semiconductor device according to the first embodiment in order of steps. [Diagram 41] 5A to 5C are cross-sectional views illustrating a part of a second manufacturing method for the semiconductor device according to the first embodiment in order of steps. [Diagram 42] 1 is a graph illustrating the relationship between trench depth and mask opening width. [Diagram 43] 11A to 11C are cross-sectional views illustrating a part of a first manufacturing method of a semiconductor device according to a fourth embodiment in the order of steps. [Diagram 44]11A to 11C are cross-sectional views illustrating a part of a first manufacturing method of a semiconductor device according to a fourth embodiment in the order of steps. [Diagram 45] 11A to 11C are cross-sectional views illustrating a part of a first manufacturing method of a semiconductor device according to a fourth embodiment in the order of steps. [Diagram 46] 11A to 11C are cross-sectional views illustrating a part of a first manufacturing method of a semiconductor device according to a fourth embodiment in the order of steps. [Figure 47] 11A to 11C are cross-sectional views illustrating a part of a first manufacturing method of a semiconductor device according to a fourth embodiment in the order of steps. [Figure 48] 13A to 13C are cross-sectional views illustrating a part of a second manufacturing method of a semiconductor device according to a fourth embodiment. [Figure 49] FIG. 13 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a fifth embodiment. [Figure 50] FIG. 13 is a cross-sectional view showing another example of the configuration of the semiconductor device according to the fifth embodiment. [Figure 51] FIG. 13 is a cross-sectional view showing another example of the configuration of the semiconductor device according to the fifth embodiment. [Figure 52] FIG. 13 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a sixth embodiment. [Diagram 53] FIG. 13 is a cross-sectional view showing another example of the configuration of the semiconductor device according to the sixth embodiment. [Figure 54] FIG. 23 is a cross-sectional view showing another example of the configuration of the semiconductor device according to the sixth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Hereinafter, embodiments will be described with reference to the accompanying drawings. In the following embodiments, detailed features are shown for the purpose of explaining the technology, but they are merely examples and are not necessarily essential features for enabling the embodiments to be implemented.

[0017] In the description provided in this specification, terms indicating specific positions or directions, such as "top," "bottom," "left," "right," "side," "bottom," "front," or "back," may be used, but these terms are used for convenience to facilitate understanding of the contents of the embodiments and do not relate to the positions or directions in which the embodiments are actually implemented.

[0018] The presence or absence of a "+" or "-" symbol to the right of the symbols "N" and "P" indicating the conductivity type of a semiconductor indicates the relative level of impurity concentration, for example, the peak value of the impurity concentration. For example, an N+ type semiconductor has a higher N-type impurity concentration than an N-type semiconductor, and an N-type semiconductor has a higher N-type impurity concentration than an N-type semiconductor. A P+ type semiconductor has a higher P-type impurity concentration than a P-type semiconductor, and a P-type semiconductor has a higher P-type impurity concentration than a P-type semiconductor. Such high and low impurity concentrations are relative, and for example, even if different semiconductors are described as all N-type semiconductors, it does not mean that the impurity concentrations of those semiconductors are equal to each other.

[0019] <Embodiment 1> Fig. 1 is a cross-sectional view illustrating a configuration of a semiconductor device 100A according to embodiment 1. Fig. 2 is a cross-sectional view illustrating an example of the configuration of the semiconductor device 100A, and Fig. 3 is a cross-sectional view illustrating another example of the configuration of the semiconductor device 100A.

[0020] The cross section shown in Fig. 2 and the cross section shown in Fig. 3 appear when viewed from the direction of the arrow at position QQ in Fig. 1. The cross section shown in Fig. 1 is also a cross section when viewed from the direction of the arrow at position JJ in Fig. 2, and is also a cross section when viewed from the direction of the arrow at position KK in Fig. 3. The configuration shown in Fig. 2 contributes to suppressing the multi-layering of wiring using, for example, polysilicon, and ultimately to improving productivity.

[0021] The semiconductor device 100A includes a semiconductor substrate 1, semiconductor layers 2, 31, 32, 41, 42, 5, 10, and 11, and trench electrodes 81, 82, and 9. "Trench electrode" is a provisional name for an electrode extending in a groove shape in the thickness direction of the semiconductor substrate 1, and its specific configuration will be described later.

[0022] The semiconductor substrate 1 is realized by, for example, N-type silicon. The semiconductor device 100A is typically an IGBT, and the semiconductor substrate 1 functions as, for example, a drift layer.

[0023] The semiconductor layers 31 and 32 are located exclusively on the surface layer of the semiconductor substrate 1. The semiconductor layers 31 and 32 are realized by, for example, N-type silicon. The semiconductor layers 31 and 32 function as, for example, carrier accumulation layers. For example, in this embodiment, the semiconductor layers 31 and 32 have the same peak value of impurity concentration.

[0024] In a third embodiment described later, a case will be described in which the impurity concentration of the semiconductor layer 31 is equal to the impurity concentration of the semiconductor substrate 1, and the semiconductor layer 31 is considered to be a part of the semiconductor substrate 1. In a fourth embodiment described later, a case will be described in which the peak value of the impurity concentration of the semiconductor layer 31 is lower than the peak value of the impurity concentration of the semiconductor layer 32.

[0025] The semiconductor layer 2 is located on the opposite side of the semiconductor layers 31 and 32 to the semiconductor substrate 1. The semiconductor layer 2 has a conductivity type opposite to that of the semiconductor substrate 1 and the semiconductor layers 31 and 32, and is realized by, for example, P-type silicon. The semiconductor layer 2 functions as, for example, a channel layer of an IGBT.

[0026] The semiconductor layer 5 is selectively located on the opposite side of the semiconductor layer 2 from the semiconductor substrate 1. The semiconductor layer 5 has the same conductivity type as the semiconductor layer 2 and a higher peak value of the impurity concentration than the semiconductor layer 2, and is realized by, for example, P+ type silicon. For example, the semiconductor layer 5 functions as an emitter layer of an IGBT.

[0027] The semiconductor layers 41 and 42 are located exclusively with the semiconductor layer 5 on the opposite side of the semiconductor substrate 1 with respect to the semiconductor layer 2. The semiconductor layers 41 and 42 each have the same conductivity type as the semiconductor substrate 1 and the semiconductor layers 31 and 32, and have a higher peak value of impurity concentration than the semiconductor layer 32, and are realized, for example, by N+ type silicon. For example, the semiconductor layers 41 and 42 function as emitter layers of an IGBT.

[0028] The semiconductor layer 11 is located on the opposite side of the semiconductor substrate 1 to the semiconductor layers 2, 31, 32, 41, 42, and 5. The semiconductor layer 11 has the same conductivity type as the semiconductor layer 2, and is realized by, for example, P-type silicon. For example, the semiconductor layer 11 functions as a collector layer of an IGBT. The semiconductor layer 11 is electrically connected to a collector electrode C of the IGBT by, for example, a structure not shown.

[0029] The semiconductor layer 10 is located between and in contact with the semiconductor substrate 1 and the semiconductor layer 11. The semiconductor layer 10 has the same conductivity type as the semiconductor substrate 1 and a higher peak value of the impurity concentration than the semiconductor substrate 1, and is realized by, for example, N-type silicon. For example, the semiconductor layer 10 functions as a buffer layer of the IGBT.

[0030] The trench electrode 81 penetrates the semiconductor layers 41, 2 and extends to reach the semiconductor layer 31 farther from the semiconductor layer 11 than the boundary between the semiconductor layer 32 and the semiconductor substrate 1 (away toward the upper side of the paper in FIG. 1). The trench electrode 81 has an insulating surface, specifically, a surface facing the semiconductor layers 41, 2, 31. The trench electrode 81 is electrically connected to the gate electrode G1 of the IGBT by, for example, a structure not shown.

[0031] The trench electrode 82 extends through the semiconductor layers 2, 42, and 32 to reach the semiconductor substrate 1. The trench electrode 82 is closer to the semiconductor layer 11 than either of the semiconductor layers 31 and 32. The trench electrode 82 has an insulating surface, specifically, a surface facing the semiconductor substrate 1 and the semiconductor layers 42, 2, and 32. The trench electrode 82 is electrically connected to the gate electrode G2 of the IGBT by, for example, a structure not shown.

[0032] The trench electrode 9 extends through the semiconductor layers 5 and 2 to the semiconductor substrate 1. When the semiconductor layers 31 and 32 are regarded as a single body, it can be said that the trench electrodes 9 and 82 both penetrate the semiconductor layers 31 and 32. The trench electrode 9 is closer to the semiconductor layer 11 than either of the semiconductor layers 31 and 32. The trench electrode 9 separates the semiconductor layer 31 from the semiconductor layer 32. The trench electrode 9 and the trench electrode 82 sandwich the semiconductor layer 32. The trench electrode 9 has an insulating surface, specifically, a surface facing the semiconductor substrate 1 and the semiconductor layers 2, 31, 32, and 5. The trench electrode 9 is electrically connected to the emitter electrode E of the IGBT together with the semiconductor layers 41, 42, and 5, for example. The trench electrode 9 is not connected to either of the gate electrodes G1 and G2, and can be regarded as a dummy electrode from the viewpoint of not functioning as a gate.

[0033] Each of the trench electrodes 81, 82, and 9 has an insulating film 6 and a conductor 7. The conductor 7 is realized, for example, from polysilicon. The insulating film 6 provides the above-mentioned insulating properties of the trench electrodes 81, 82, and 9, and is realized, for example, from silicon oxide. Although each of the trench electrodes 81, 82, and 9 is surrounded by the insulating film 6 inside the trench, it can be considered as an electrode that can be electrically connected to the outside.

[0034] The trench electrodes 81, 82, and 9 are positioned periodically when viewed along the thickness direction of the semiconductor substrate 1. For example, the trench electrodes 81 and 82 are positioned alternately along one direction, and the trench electrode 9 is positioned between the trench electrodes 81 and 82 (see FIG. 2). For example, the trench electrodes 81 and 82 are positioned alternately along two directions, and the trench electrodes 9 are positioned in a lattice pattern between the trench electrodes 81 and 82 (see FIG. 3).

[0035] The semiconductor layer 41 may be formed continuously around the trench electrode 81 as illustrated in Fig. 3, or may be formed discontinuously. The semiconductor layer 42 may be formed continuously around the trench electrode 82 as illustrated in Fig. 3, or may be formed discontinuously.

[0036] 4 is a circuit diagram illustrating a circuit for applying two types of gate voltages to the IGBT 100. The semiconductor device 100A can be employed as the IGBT 100 having gate electrodes G1 and G2, an emitter electrode E, and a collector electrode C.

[0037] The on / off of the IGBT 100 is controlled by two types of gate voltages. The gate electrode G1 is connected to a signal source 102 via a delay circuit 101 and a resistor. This resistor may be realized as being included in the signal source 102 or may be realized as being included in the delay circuit 101.

[0038] The gate electrode G2 is connected to the signal source 102 via a resistor. This resistor may be realized as being included in the signal source 102.

[0039] 5 is a waveform diagram illustrating the sequence of the two types of gate voltages. With the potential of the emitter electrode E as a reference, the voltage applied to the gate electrode G1 (hereinafter tentatively referred to as the "first gate voltage": corresponding to the above-mentioned first signal) transitions between the value Vg1 (>0) and the value (-Vg1), and the voltage applied to the gate electrode G2 (hereinafter tentatively referred to as the "second gate voltage": corresponding to the above-mentioned second signal) transitions between the value Vg2 (>0) and the value (-Vg2). The falling edge of the first gate voltage and the falling edge of the second gate voltage both correspond to the OFF transition.

[0040] The delay circuit 101 has at least a function of delaying the fall of the first gate voltage with respect to the fall of the second gate voltage by a time difference dt. For example, the second gate voltage is input to the delay circuit 101, and the first gate voltage is obtained from the delay circuit 101. Alternatively, the delay circuit 101 is omitted, and the first gate voltage and the second gate voltage are obtained from the signal source 102.

[0041] Since the first gate voltage is applied to the gate electrode G1, it can be said that a first signal is applied to the trench electrode 81. Since the second gate voltage is applied to the gate electrode G2, it can be said that a second signal is applied to the trench electrode 82. As a method of controlling turning off the semiconductor device 100A employed as the IGBT 100, both the first gate voltage and the second gate voltage are transitioned, with the first gate voltage transitioning with a delay relative to the second gate voltage. The same applies to the control of the semiconductor devices 100B, 100C, and 100D described below.

[0042] Fig. 6 is a waveform diagram illustrating the operation of turning off the IGBT 100. In Fig. 6, the vertical axis on the left side indicates the collector current Ic [A], and the vertical axis on the right side indicates the collector voltage Vce [V] based on the emitter potential. The horizontal axis indicates time [s]. Waveform H20 indicates the waveform of the collector current Ic, and waveform H21 indicates the waveform of the collector voltage Vce.

[0043] The second gate voltage makes an OFF transition at time t2, and the first gate voltage makes an OFF transition at time t1. The difference between times t1 and t2 is the above-mentioned time difference dt. At time t0, the collector current Ic stops flowing. The total amount of loss in the IGBT 100 during the period from time t2 to time t0 is hereinafter referred to as the total loss Eoff.

[0044] 7 is a cross-sectional view illustrating the structure of a semiconductor device 100Z as a comparative example to be compared with the semiconductor device 100A. The structure of the semiconductor device 100Z is roughly different from that of the semiconductor device 100A in the order in which the trench electrodes 81, 82, and 9 are arranged. In the semiconductor device 100A, the trench electrode 9 is interposed between the trench electrodes 81 and 82, but in the semiconductor device 100Z, the trench electrode 9 is not interposed between the trench electrodes 81 and 82, and the trench electrodes 81 and 82 are sandwiched between the trench electrodes 9.

[0045] More specifically, in both of the semiconductor devices 100A and 100Z, if the semiconductor layers 31 and 32 are regarded as a single unit, it can be said that the trench electrodes 82 and 9 penetrate the semiconductor layers 31 and 32. In both of the semiconductor devices 100A and 100Z, it can be said that the trench electrode 81 penetrates the semiconductor layer 41 and extends to reach the semiconductor layers 31 and 32.

[0046] In the semiconductor device 100Z, similar to the semiconductor device 100A, the trench electrode 82 faces the semiconductor substrate 1 and the semiconductor layers 42, 2, and 32. In the semiconductor device 100Z, the trench electrode 82 also faces the semiconductor layer 31, and the surface facing the semiconductor layer 31 has insulating properties.

[0047] In the semiconductor device 100Z, similar to the semiconductor device 100A, the trench electrode 81 faces the semiconductor layers 41, 2. In the semiconductor device 100Z, the trench electrode 81 also faces the semiconductor layer 32, and the surface facing the semiconductor layer 32 has insulating properties.

[0048] In the semiconductor device 100Z, similar to the semiconductor device 100A, the trench electrode 9 faces the semiconductor substrate 1 and the semiconductor layers 31 and 2. However, the trench electrode 9 in the semiconductor device 100A faces the semiconductor layer 5, whereas the trench electrode 9 in the semiconductor device 100Z does not face the semiconductor layer 5.

[0049] In the semiconductor device 100Z, the semiconductor layers 41, 42, and 5 are arranged between the trench electrodes 81 and 82 without a trench electrode 9 therebetween.

[0050] 8 is a graph showing the dependency of the total loss amount Eoff [%] on the time difference dt. The total loss amount Eoff is shown as a percentage, with the value when the time difference dt is zero being 100%. The percentage white circles show the comparative example, specifically the data when the semiconductor device 100Z is used in the IGBT 100, and are connected by a dashed line. The black circles show the present embodiment, specifically the data when the semiconductor device 100A is used in the IGBT 100, and are connected by a solid line.

[0051] In the comparative example, as the time difference dt increases, the total loss Eoff tends to decrease once and then increase again. Specifically, when the time difference dt is around 20 μs, the total loss Eoff reaches a minimum value.

[0052] In the case of the embodiment, as the time difference dt increases, the total loss amount Eoff tends to decrease almost monotonically, and when the time difference dt is longer than about 35 μs, the total loss amount Eoff tends to become almost stable.

[0053] From the above graph, it can be seen that the permissible range of the time difference dt for reducing losses, in other words, the permissible range of the time difference dt by which the off transition of the first gate voltage is delayed from the off transition of the second gate voltage, is wider in the present embodiment than in the comparative example.

[0054] FIG. 9 is a waveform diagram illustrating the operation of turning off the IGBT 100 in the comparative example. In FIG. 9, the vertical axis on the left side indicates the collector current Ic [A], and the vertical axis on the right side indicates the collector voltage Vce [V] based on the emitter potential. The horizontal axis indicates time [s]. The dashed waveform indicates the collector current Ic, and the solid waveform indicates the collector voltage Vce. For both the collector current Ic and the collector voltage Vce, cases are shown in which the time difference dt takes values ​​of 0 μs, 18 μs, and 60 μs. For each time difference dt, the first gate voltage makes an OFF transition at a time of 100 μs (labeled as "1.0E-04" in the diagram).

[0055] Fig. 10 is a waveform diagram showing an enlarged view of region R10 in Fig. 9. Fig. 11 is a waveform diagram showing an enlarged view of region R11 in Fig. 9.

[0056] Waveforms H31, H32, and H33 shown by solid lines each represent the waveform of collector voltage Vce in the comparative example, and waveforms H41, H42, and H43 shown by dashed lines each represent the waveform of collector current Ic in the comparative example.

[0057] Waveforms H31 and H41 both show the case where the time difference dt has a value of 0 μs. Waveforms H32 and H42 both show the case where the time difference dt has a value of 18 μs. Waveforms H33 and H43 both show the case where the time difference dt has a value of 60 μs.

[0058] FIG. 12 is a waveform diagram illustrating an operation of turning off the IGBT 100 in this embodiment. In FIG. 12, the vertical axis on the left side indicates the collector current Ic [A], and the vertical axis on the right side indicates the collector voltage Vce [V] based on the emitter potential. The horizontal axis indicates time [s]. The dashed waveform indicates the collector current Ic, and the solid waveform indicates the collector voltage Vce. For both the collector current Ic and the collector voltage Vce, cases are shown in which the time difference dt takes values ​​of 0 μs, 18 μs, and 60 μs. For each time difference dt, the first gate voltage makes an OFF transition at a time of 100 μs (marked as "1.0E-04" in the diagram).

[0059] Fig. 13 is a waveform diagram showing an enlarged view of region R13 in Fig. 12. Fig. 14 is a waveform diagram showing an enlarged view of region R14 in Fig. 12.

[0060] Waveforms H51, H52, and H53 shown by solid lines each represent the waveform of the collector voltage Vce in the embodiment, and waveforms H61, H62, and H63 shown by dashed lines each represent the waveform of the collector current Ic in the embodiment.

[0061] Waveforms H51 and H61 both show the case where the time difference dt has a value of 0 μs. Waveforms H52 and H62 both show the case where the time difference dt has a value of 18 μs. Waveforms H53 and H63 both show the case where the time difference dt has a value of 60 μs.

[0062] 10 and 13, it can be seen that the increase in the collector voltage Vce after the second gate voltage makes an OFF transition is suppressed more in this embodiment than in the comparative example. The increase in the collector voltage Vce increases the loss during conduction of the IGBT 100. The increase in the total loss Eoff in the comparative example with the increase in the time difference dt shown in FIG. 8 is believed to be due to the increase in the collector voltage Vce.

[0063] 11 and 14, it can be seen that the rising speed of the collector voltage Vce is suppressed more in this embodiment than in the comparative example. When the time difference dt is large, distortion occurs in the waveform of the collector voltage Vce in the comparative example.

[0064] In both the semiconductor devices 100A and 100Z, the semiconductor layers 2, 31, 32, and 5 are considered to be emitter regions of the IGBTs. In both the semiconductor devices 100A and 100Z, the current flowing therein during operation passes through the emitter regions.

[0065] The electrons accumulated in the semiconductor layers 31 and 32 due to the potential of the trench electrode 82 are reduced by the second gate voltage turning off. This reduction leads to a reduction in the electrons injected from the semiconductor layers 31 and 32 to the semiconductor substrate 1, and ultimately leads to a reduction in carriers on the semiconductor layer 31 and 32 side of the semiconductor substrate 1. This reduction causes a depletion layer extending from the boundary between the semiconductor substrate 1 and the semiconductor layers 31 and 32 to expand.

[0066] In the semiconductor device 100Z, the trench electrodes 81 and 82 are adjacent to each other, and the emitter region is shared between them. In the semiconductor device 100Z, the hole current flows only through the depletion layer. The resistance component of the depletion layer is high, and the expansion of the depletion layer leads to an increase in the voltage that turns on the semiconductor device 100Z. The longer the time difference dt, the longer the depletion layer extends, and the greater the forward conduction loss.

[0067] The longer the time difference dt is (the earlier the second gate voltage's OFF transition is than the first gate voltage's OFF transition), the greater the collector voltage Vce (see waveforms H31, H32, and H33 in FIG. 10). At the time the first gate voltage makes the OFF transition, the depletion layer has already expanded in the emitter region, and the collector voltage Vce rises faster (see waveforms H32 and H33 in FIG. 11).

[0068] In the semiconductor device 100A, the emitter region is not shared between the trench electrodes 81 and 82. Specifically, the semiconductor layer 31 to which the trench electrode 81 faces and the semiconductor layer 32 to which the trench electrode 82 faces are separated by the trench electrode 9.

[0069] Even if the depletion layer extending from the semiconductor layer 32 in the semiconductor substrate 1 expands as a result of the second gate voltage being turned off, almost no depletion layer exists at the boundary between the semiconductor layer 31 facing the trench electrode 81 and the semiconductor substrate 1 until the first gate voltage is turned off. The emitter region including the semiconductor layers 2, 31, and 5, where almost no depletion layer exists, has a smaller resistance component than the emitter region including the semiconductor layers 2, 32, and 5, where the depletion layer expands. In the semiconductor device 100A, the hole current flows through the latter.

[0070] These two types of emitter regions are parallel in the semiconductor device 100A, and the voltage that turns on the semiconductor device 100A is almost independent of the time difference dt (see waveforms H51, H52, and H53 in FIG. 13). At the time when the first gate voltage makes the OFF transition, there is still almost no depletion layer near the boundary between the semiconductor layer 31 and the semiconductor substrate 1, and the rate of increase of the collector voltage Vce is suppressed (see waveforms H51, H52, and H53 in FIG. 14).

[0071] 15 is a graph illustrating the dependence of the total loss Eoff on the saturation voltage Vce(sat) for the collector voltage Vce. In FIG. 15, the vertical axis represents the total loss Eoff [mJ], and the horizontal axis represents the saturation voltage Vce(sat) [V].

[0072] The white circles represent data for a comparative example, specifically when the semiconductor device 100Z is used in the IGBT 100, and are connected by a dashed line. The black circles represent data for this embodiment, specifically when the semiconductor device 100A is used in the IGBT 100, and are connected by a solid line. For the data of the comparative example, the total loss Eoff that is the minimum value for the time difference dt is used.

[0073] In both the comparative example and this embodiment, a trade-off relationship is observed between the saturation voltage Vce(sat) and the total loss amount Eoff. It is observed that there is a tendency for the saturation voltage Vce(sat) to increase when the total loss amount Eoff is reduced.

[0074] There exists a range of saturation voltage Vce(sat) (hereinafter tentatively referred to as the "low speed side") in which the comparative example and this embodiment show an approximately equal trade-off relationship. There exists a range of saturation voltage Vce(sat) (hereinafter tentatively referred to as the "high speed side") in which the present embodiment has a smaller total loss amount Eoff than the comparative example. The saturation voltage Vce(sat) is higher on the high speed side than on the low speed side.

[0075] In both the comparative example and this embodiment, that is, in both the semiconductor devices 100A and 100Z, the carrier concentration in the semiconductor substrate 1 is lower on the high-speed side than on the low-speed side. In the comparative example, the larger the time difference dt, the more likely the depletion layer expands on the emitter region side of the semiconductor substrate 1, and the greater the forward conduction loss from when the second gate voltage makes the OFF transition to when the first gate voltage makes the OFF transition, making it difficult to suppress the total loss Eoff. In the present embodiment, the increase in forward conduction loss due to the extension of the depletion layer is suppressed, and the total loss Eoff is suppressed more than in the comparative example.

[0076] <Example of range of peak value of impurity concentration> The peak values ​​of the impurity concentrations employed in the semiconductor substrate 1 and the semiconductor layers 2, 31, 32, 41, 42, and 5 are exemplified as follows.

[0077] The peak value of the impurity concentration in the semiconductor substrate 1 is, for example, 1×10 12 cm -3is the lower limit, 1×10 14 cm -3 It is preferable that the peak value of the impurity concentration in the semiconductor substrate 1 satisfies the upper and lower limits, in terms of the semiconductor device 100A having a large breakdown voltage, compared to a case in which it does not satisfy these limits.

[0078] The peak value of the impurity concentration in the semiconductor layer 2 is, for example, 1×10 16 cm -3 is the lower limit, 1×10 17 cm -3 is the upper limit. It is preferable that the peak value of the impurity concentration in the semiconductor layer 2 satisfies the upper limit, in terms of the semiconductor device 100A having a large turn-off interruption capability, compared to when it does not satisfy the upper limit. It is preferable that the peak value of the impurity concentration in the semiconductor layer 2 satisfies the lower limit, in terms of the semiconductor device 100A having a large interruption capability during a short circuit, in comparison to when it does not satisfy the lower limit.

[0079] The peak values ​​of the impurity concentrations in the semiconductor layers 31 and 32 are, for example, 1×10 16 cm -3 It is preferable that the peak values ​​of the impurity concentrations in the semiconductor layers 31 and 32 satisfy this upper limit, in terms of the semiconductor device 100A having a large breakdown voltage, compared to a case in which this upper limit is not satisfied.

[0080] The peak values ​​of the impurity concentrations in the semiconductor layers 41, 42, and 5 are, for example, 1×10 18 cm -3 It is preferable that the peak values ​​of the impurity concentrations in the semiconductor layers 41, 42, and 5 satisfy this lower limit, in terms of lower contact resistance in each of the layers, compared to a case in which the peak values ​​do not satisfy this lower limit.

[0081] <Another example of the second gate voltage> Fig. 16 is a waveform diagram showing another example of the sequence of two types of gate voltages. The first gate voltage transitions between the value Vg1 and the value (-Vg1) in the same manner as in the example of Fig. 5. The second gate voltage transitions between the value 0 and the value (-Vg2) unlike the example of Fig. 5. The second gate voltage transitions at a potential below zero.

[0082] In the semiconductor device 100A, the conductivity types of the semiconductor layers 31, 32 and the semiconductor layers 41, 42 are all N-type, and the conductivity type of the semiconductor layer 2 is P-type, so that two types of N-channel type MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors) are configured. Specifically, a MOSFET (hereinafter tentatively referred to as a "first MOSFET") configured by the semiconductor layers 41, 2, 31 and a MOSFET (hereinafter tentatively referred to as a "second MOSFET") configured by the semiconductor layers 42, 2, 32 are connected in parallel in the semiconductor device 100A.

[0083] The first MOSFET is turned on when the first gate voltage exceeds a predetermined positive value, and the second MOSFET is turned on when the second gate voltage exceeds a predetermined positive value.

[0084] 5 rise above a predetermined positive value, and the semiconductor device 100A is turned on. If the turn-on of the second MOSFET is delayed from the turn-on of the first MOSFET, the waveform of the current (collector current Ic) that flows when the semiconductor device 100A is turned on is distorted.

[0085] Figures 17 and 18 are waveform diagrams illustrating the ON transition of two types of gate voltages. In both Figures 17 and 18, the vertical axis indicates the gate voltage Vge [V] commonly used for both the first and second gate voltages, and the horizontal axis indicates time [s]. Waveform H71 indicates the first gate voltage, and waveform H72 indicates the second gate voltage. Both Figures 17 and 18 illustrate the case where the rise of the second gate voltage is 0.15 μs slower than the rise of the first gate voltage.

[0086] Fig. 17 illustrates an example in which the second gate voltage also transitions from -15V to 15V like the first gate voltage, and corresponds to the two gate voltage sequences illustrated in Fig. 5 except for the rising delay. Fig. 18 illustrates an example in which the first gate voltage transitions from -15V to 15V and the second gate voltage transitions from 0V to 15V, and corresponds to the two gate voltage sequences illustrated in Fig. 16 except for the rising delay.

[0087] Fig. 19 is a waveform diagram illustrating the operation of the semiconductor device 100A when the transition illustrated in Fig. 17 occurs and the semiconductor device 100A is turned on. Fig. 20 is a waveform diagram illustrating the operation of the semiconductor device 100A when the transition illustrated in Fig. 18 occurs and the semiconductor device 100A is turned on. In both Fig. 19 and Fig. 20, the left vertical axis indicates the collector current Ic [A], and the right vertical axis indicates the collector voltage Vce [V] based on the emitter potential. The horizontal axis indicates time [s].

[0088] The waveform of the collector current Ic shown in Fig. 19 is distorted to have a peak near its maximum value. Such distortion does not appear in the waveform of the collector current Ic shown in Fig. 20. When the second gate voltage shown in Fig. 16 is used, the second gate voltage does not reach a predetermined positive value even if it transitions, and the second MOSFET does not turn on. In this case, the second MOSFET does not turn on after the first MOSFET turns on, so the above-mentioned distortion does not appear in the waveform of the collector current Ic.

[0089] When the conductivity type of the semiconductor substrate 1 and the semiconductor layers 31, 32, 41, and 42 is N-type, the distortion of the collector current Ic flowing through the semiconductor device 100A is suppressed by the second gate voltage transitioning at a voltage equal to or less than zero as described above. When the conductivity type of the semiconductor substrate 1 and the semiconductor layers 31, 32, 41, and 42 is P-type, the distortion of the collector current Ic flowing through the semiconductor device 100A is suppressed by the second gate voltage transitioning at a voltage equal to or greater than zero.

[0090] <Embodiment 2> As described in "Another Example of the Second Gate Voltage" above, not turning on the second MOSFET contributes to suppressing distortion in the collector current Ic. For example, not forming the second MOSFET contributes to suppressing distortion in the collector current Ic.

[0091] 21 is a cross-sectional view illustrating a configuration of a semiconductor device 100B according to embodiment 2. In comparison with the semiconductor device 100A, the semiconductor device 100B does not include the semiconductor layer 42, and the semiconductor layers 2, 5, and 32 are provided between the trench electrodes 82 and 9.

[0092] The trench electrode 82 in the semiconductor device 100A extends through the semiconductor layers 2, 42, and 32 to reach the semiconductor substrate 1. The trench electrode 82 in the semiconductor device 100B extends through the semiconductor layers 2, 5, and 32 to reach the semiconductor substrate 1. The surface of the trench electrode 82, specifically, the surface facing the semiconductor layers 5, 2, and 31, is insulating.

[0093] The semiconductor device 100B does not have the semiconductor layer 42 that the semiconductor device 100A has, and therefore does not include a second MOSFET.

[0094] Fig. 22 is a waveform diagram illustrating the operation when the semiconductor device 100B is turned on when the transition illustrated in Fig. 17 occurs. In Fig. 22, the vertical axis on the left side indicates the collector current Ic [A], and the vertical axis on the right side indicates the collector voltage Vce [V] based on the emitter potential. The horizontal axis indicates time [s].

[0095] Even if the second gate voltage applied to the semiconductor device 100B transitions between positive and negative values ​​as illustrated in FIG. 17 and rises after the first gate voltage, no distortion appears in the collector current Ic, as in the case where the transition is below zero as illustrated in FIG. 18.

[0096] In the semiconductor device 100B, as in the semiconductor device 100A, the trench electrode 9 separates the semiconductor layer 31 from the semiconductor layer 32, so that the allowable range of the time difference dt that delays the OFF transition of the first gate voltage from the OFF transition of the second gate voltage is expanded.

[0097] <Embodiment 3> When the impurity concentration of the semiconductor layer 31 is equal to the impurity concentration of the semiconductor substrate 1, the semiconductor layer 31 can be considered as part of the semiconductor substrate 1, and a part of the semiconductor substrate 1 on the semiconductor layer 2 side can also be considered as the semiconductor layer 31.

[0098] 23 is a cross-sectional view illustrating a configuration of a semiconductor device 100C according to the third embodiment. A region of the semiconductor substrate 1 in the semiconductor device 100C, which corresponds to a region where the semiconductor layer 31 existed in the semiconductor device 100A, is virtually separated and illustrated as a semiconductor layer 31. In the semiconductor device 100C, the impurity concentration of the semiconductor layer 31 and the impurity concentration of the semiconductor substrate 1 can be said to be equal.

[0099] The cross section shown in Fig. 2 and the cross section shown in Fig. 3 appear when viewed from the direction of the arrow at position LL in Fig. 23. It can be said that Fig. 2 is a cross-sectional view showing an example of the configuration of the semiconductor device 100C, and Fig. 3 is a cross-sectional view showing another example of the configuration of the semiconductor device 100C.

[0100] It can be seen that the semiconductor device 100C has a lower peak value of the impurity concentration in the semiconductor layer 31 than the semiconductor device 100A. The reduction in the peak value of the impurity concentration in the semiconductor layer 31 increases the saturation voltage Vce(sat) and contributes to a reduction in the total loss Eoff (see FIG. 15). As can be understood from the explanation given using the comparative example in the first embodiment, the total loss Eoff is significantly affected by the operation of the first MOSFET including the semiconductor layer 31, and is less affected by the operation of the second MOSFET. Therefore, the semiconductor device 100C has an improved trade-off relationship between the saturation voltage Vce(sat) and the total loss Eoff than the semiconductor device 100A.

[0101] <Fourth embodiment> As described in the third embodiment, the reduction in the peak value of the impurity concentration in the semiconductor layer 31 contributes to improving the trade-off relationship between the saturation voltage Vce(sat) and the total loss amount Eoff. For example, the peak value of the impurity concentration in the semiconductor layer 31 is higher than the peak value of the impurity concentration in the semiconductor substrate 1 in the semiconductor device 100A and is lower than the peak value of the impurity concentration in the semiconductor layer 32.

[0102] Fig. 24 is a cross-sectional view illustrating a configuration of a semiconductor device 100D according to embodiment 4. Both the cross-section shown in Fig. 2 and the cross-section shown in Fig. 3 appear when viewed from the direction of the arrow at position MM in Fig. 24. It can be said that Fig. 2 is a cross-sectional view illustrating an example of the configuration of the semiconductor device 100D, and Fig. 3 is a cross-sectional view illustrating another example of the configuration of the semiconductor device 100D.

[0103] In the semiconductor device 100A, the peak value of the impurity concentration in the semiconductor layer 31 is approximately the same as the peak value of the impurity concentration in the semiconductor layer 32. In the semiconductor device 100D, the peak value of the impurity concentration in the semiconductor layer 31 is lower than the peak value of the impurity concentration in the semiconductor layer 32. Compared to the semiconductor device 100A, the semiconductor device 100D has an improved trade-off relationship between the saturation voltage Vce(sat) and the total loss Eoff.

[0104] <Positional Relationship Between Depth of Trench Electrodes 81, 82, 9 and Bottom of Semiconductor Layers 31, 32> In Fig. 24, depths d1, d2, d9, d31, and d32 defined in the semiconductor device 100D are shown. Similarly, depths d1, d2, d9, d31, and d32 are shown in the semiconductor devices 100A (see Fig. 1) and 100B (see Fig. 21). Similarly, depths d1, d2, d9, and d32 are shown in the semiconductor device 100C (see Fig. 23) (depth d31 is not shown in the semiconductor device 100C because the semiconductor layer 31 is part of the semiconductor substrate 1).

[0105] The surface of the semiconductor layers 41, 42, and 5 that is farther from the semiconductor layer 11 (hereinafter tentatively referred to as the "semiconductor device surface") is used as the reference position for the depths d1, d2, d9, d31, and d32 (hereinafter tentatively referred to as the "reference position"). For example, the semiconductor device surfaces of the semiconductor layers 41, 42, and 5 are located substantially on the same plane. For example, the position of the semiconductor device surface of the semiconductor layer 5 is used as the reference position.

[0106] As described below, the semiconductor layers 41, 42, and 5 are formed on one main surface of the semiconductor substrate 1, and the semiconductor substrate 1 remains closer to the semiconductor layer 11 than the semiconductor layers 41, 42, and 5. As described above, the trench electrodes 81, 82, and 9 penetrate either of the semiconductor layers 41, 42, and 5, and therefore their openings can be said to be located on the surface of the semiconductor device as the ends opposite the respective semiconductor layers 11 (ends opposite the "bottoms" described below).

[0107] Depth d1 is the depth of the bottom of trench electrode 81 (the portion closest to semiconductor layer 11: the same applies below), depth d2 is the depth of the bottom of trench electrode 82, and depth d9 is the depth of the bottom of trench electrode 9. For example, the fact that depth d2 and depth d9 are the same allows trenches used for trench electrodes 82 and 9 to be formed in parallel in the manufacturing process (described later), which contributes to simplifying the formation process.

[0108] In the direction in which the trench electrode 82 extends (the thickness direction of the semiconductor substrate 1), the trench electrode 82 can be seen as protruding from the semiconductor layer 32 to the semiconductor substrate 1. In the direction in which the trench electrode 9 extends (the thickness direction of the semiconductor substrate 1), the trench electrode 9 can be seen as protruding from the semiconductor layer 32 to the semiconductor substrate 1.

[0109] For example, the length by which trench electrode 82 protrudes from semiconductor layer 32 in the direction in which it extends is equal to the length by which trench electrode 9 protrudes from semiconductor layer 32 in the direction in which it extends. When the protruding lengths are equal and the semiconductor device surfaces of semiconductor layers 41, 42, and 5 are positioned substantially on the same plane, depth d2 and depth d9 are equal.

[0110] The depth d31 is the depth of the bottom of the semiconductor layer 31, and the depth d32 is the depth of the bottom of the semiconductor layer 32. In the semiconductor devices 100A and 100B, as illustrated in FIGS. 1 and 21, respectively, for example, the depths d31 and d32 are equal.

[0111] As described above, the semiconductor layers 31 and 32 function as carrier accumulation layers. It can be said that the depths d31 and d32 indicate the positions of the boundaries on the collector layer side of the carrier accumulation layers.

[0112] The trench electrode 81 reaches and extends from the semiconductor layer 11 farther than the boundary between the semiconductor layer 32 and the semiconductor substrate 1 to the semiconductor layer 31. From the viewpoint that the semiconductor layer 31 functions as a carrier accumulation layer in the first MOSFET, for example, the trench electrode 81 does not penetrate the semiconductor layer 31. This positional relationship is expressed as d1 < d32 using the depths d1 and d32. Further, in the semiconductor devices 100A, 100B, and 100D, there is a positional relationship expressed as d1 < d31 using the depth d31.

[0113] In the semiconductor device 100D, for example, further, there is a relationship of d31 < d32, and the semiconductor layer 31 is thinner than the semiconductor layer 32. Such a relationship contributes to the simplification of the process for obtaining the semiconductor layers 31 and 32, specifically, the process of diffusing impurities in the manufacturing process (described later).

[0114] The trench electrodes 9 and 82 extending to the semiconductor substrate 1 on the semiconductor layer 11 side from the semiconductor layers 31 and 32 (d31 < d2, d32 < d2, d31 < d9, d32 < d9) relieve the concentration of the electric field in the semiconductor layers 31 and 32 when the semiconductor devices 100A, 100B, and 100D operate, contributing to the improvement of the breakdown voltage.

[0115] The trench electrodes 9 and 82 extending to the semiconductor substrate 1 on the semiconductor layer 11 side from the semiconductor layer 32 (d32 < d2, d32 < d9) relieve the concentration of the electric field in the semiconductor layer 32 when the semiconductor device 100C operates, contributing to the improvement of the breakdown voltage.

[0116] <Spacing between trench electrodes 81, 82, and 9> FIG. 25 is a graph illustrating the relationship between the withstand voltage of the semiconductor devices 100A, 100B, 100C, and 100D and the distance between the trench electrodes 81, 82, and 9. In FIG. 25, the vertical axis indicates the withstand voltage BV [V] at 25° C., and the horizontal axis indicates the trench distance [μm]. The trench distance here corresponds to the distance between the adjacent trench electrodes 82 and 9 along the direction in which the trench electrodes 82 and 9 are aligned. The trench electrodes 9 are located on both sides of the trench electrodes 81 in the direction in which the trench electrodes 9 and 81 are aligned (see FIGS. 1, 21, 23, and 24). The distance between the adjacent trench electrodes 9 across the trench electrode 81 also corresponds to the trench distance.

[0117] 25, the larger the trench interval, the lower the withstand voltage. For example, when the peak value of the impurity concentration of the semiconductor layers 31 and 32 is the same as that of the semiconductor substrate 1 and the trench interval is 15 μm, the withstand voltage is about 90% of the target withstand voltage.

[0118] The narrow trench spacing strengthens the field plate effect between the trench electrodes 9 and 82, and reduces the concentration of the electric field near the bottom surface of the trench electrode 82, which in turn contributes to improving the withstand voltage.

[0119] The fact that the peak value of the impurity concentration of the semiconductor layers 31 and 32 is higher than the peak value of the impurity concentration of the semiconductor substrate 1 makes the dependency of the withstand voltage on the trench interval prominent. The above-mentioned semiconductor devices 100A, 100B, 100C, and 100D all have an N-type semiconductor substrate 1 and an N-type semiconductor layer 32. In this case, narrowing the trench interval to less than 15 μm contributes to making the withstand voltage of the semiconductor devices 100A, 100B, 100C, and 100D 90% or more of the target withstand voltage.

[0120] <First Manufacturing Method of Semiconductor Device 100A> 26 to 37 are cross-sectional views illustrating a part of the first manufacturing method of the semiconductor device 100A according to the first embodiment, particularly, the manufacturing steps of the trench electrodes 81, 82, and 9 in order of steps.

[0121] 26 illustrates a process of introducing an N-type impurity into a structure in which semiconductor layers 25 and 3 have already been formed using a semiconductor substrate 1. The semiconductor layer 3 will later become semiconductor layers 31 and 32. The semiconductor layers 2 and 5 are collectively shown as a semiconductor layer 25.

[0122] The configuration of the semiconductor substrate 1 on the side opposite the semiconductor layer 25, 3 is omitted. For example, the semiconductor substrate 1 already has the semiconductor layers 10, 11 provided on the side opposite the semiconductor layer 25, 3. In both the description of the manufacturing method described here and the manufacturing method described later, the semiconductor layers 10, 11 are not illustrated.

[0123] Before the N-type impurity is introduced, the semiconductor substrate 1, the semiconductor layers 3 and 25, the insulating film 400, and the mask 501 are stacked in this order along a direction from the bottom to the top of the paper in FIG.

[0124] The insulating film 400 is realized, for example, by an oxide film obtained by oxidizing the semiconductor substrate 1 before the semiconductor layers 25 and 3 are provided. When silicon is used as the material for the semiconductor substrate 1, the insulating film 400 is, for example, a silicon oxide film.

[0125] The mask 501 has openings 501a and 501b. The openings 501a and 501b are formed in the mask 501 in correspondence with positions where the semiconductor layers 41 and 42 (see FIG. 1) are to be formed, respectively. For example, a patterned photoresist film is used for the mask 501. The openings 501a and 501b are formed by, for example, photolithography of the photoresist film.

[0126] As the N-type impurity, for example, arsenic (As) is introduced. Fig. 26 shows an example in which ion implantation using arsenic ions (As+: the symbol "+" here does not indicate the magnitude of the impurity concentration but indicates that it is a positive ion) is adopted for the introduction of the N-type impurity. The symbol "x" in the semiconductor layer 25 typically indicates the location where the N-type impurity is introduced.

[0127] After the N-type impurities are introduced, the mask 501 is removed by a known technique to expose the insulating film 400. After the insulating film 400 is exposed, at least the vicinity of the semiconductor layer 25, for example, the entire structure is heated to diffuse the introduced N-type impurities (so-called "drive-in"). This diffusion forms the semiconductor layers 41 and 42 as illustrated in FIG. 27. When the insulating film 400 is a silicon oxide film, for example, the drive-in increases the thickness of the insulating film 400 to become the insulating film 401.

[0128] A mask 502 is provided on the insulating film 401 on the side opposite to the semiconductor substrate 1 (FIG. 28). An opening 502a is formed in the mask 502. The opening 502a is formed in the mask 502 at a position corresponding to the position where the trench electrode 81 (see FIG. 1) is to be formed. For example, a patterned photoresist film is used for the mask 502. The opening 502a is formed by, for example, photolithography of the photoresist film. By etching the insulating film 401 through the mask 502, a hole corresponding to the opening 502a is formed in the insulating film 401, and the semiconductor layer 41 is partially exposed.

[0129] Using the mask 502 and the insulating film 401 with the opening as described above as a mask, the semiconductor layers 41, 25, and 3 are selectively etched to form a trench 801 that penetrates the semiconductor layers 41 and 25 and reaches the semiconductor layer 3 (FIG. 29). The position of the trench 801 corresponds to the position where the trench electrode 81 is to be provided.

[0130] The insulating film 401 is removed by a known technique, for example, etching. An insulating film 601 is formed on the semiconductor layers 41, 25, and 3 exposed on the inner wall of the trench 801 and on the semiconductor layers 41, 42, and 25 exposed by the removal (FIG. 30). The insulating film 601 in the trench 801 will later become the insulating film 6 that provides insulation on the surface of the trench electrode 81. The insulating film 601 is formed by, for example, thermal oxidation.

[0131] A conductor 701 is provided on the insulating film 601, including inside the trench 801, on the side opposite to the semiconductor substrate 1 (FIG. 31). The trench 801 is filled with the insulating film 601 and the conductor 701. For example, polysilicon doped with a high impurity concentration is used for the conductor 701.

[0132] The conductor 701 is etched from the side opposite to the semiconductor substrate 1, remaining only in the trench 801 (so-called "etch back") and exposed as the conductor 7 (FIG. 32). Thereafter, the surface of the conductor 7 exposed in the trench 801 is oxidized by, for example, an oxidation process to obtain the trench electrode 81. The oxidation process increases the thickness of the insulating film 601 to obtain the insulating film 602. In view of the above-mentioned manufacturing process, it can be said that the trench electrode 81 is embedded in the trench 801.

[0133] A mask 503 is provided on the insulating film 602 on the side opposite to the semiconductor substrate 1 (FIG. 33). The mask 503 has openings 503a and 503b. The openings 503a and 503b are formed in the mask 503 corresponding to the positions where the trench electrodes 9 and 82 (see FIG. 1) are to be formed, respectively. For example, a patterned photoresist film is used for the mask 503. The openings 503a and 503b are formed by, for example, photolithography on the photoresist film. By etching the insulating film 602 through the mask 503, holes corresponding to the openings 503a and 503b are formed in the insulating film 602, and the semiconductor layer 42 is partially exposed.

[0134] Using the mask 503 and the insulating film 602 with the opening as described above as a mask, the semiconductor layers 25 and 3 and the semiconductor substrate 1 are selectively etched to form trenches 90 and 802 (FIG. 34).

[0135] The position of trench 90 corresponds to the position where trench electrode 9 is provided. Trench 90 penetrates semiconductor layers 25 and 3 to reach semiconductor substrate 1. The position of trench 802 corresponds to the position where trench electrode 81 is provided. Trench 802 penetrates semiconductor layers 42, 25, and 3 to reach semiconductor substrate 1. By forming trenches 90 and 802, semiconductor layer 3 is divided into semiconductor layers 31 and 32.

[0136] An insulating film 6 is formed on the semiconductor layers 31, 32, 42, 25 and the semiconductor substrate 1 exposed on the inner walls of the trenches 90 and 802 (FIG. 35). The insulating film 6 in the trench 802 will later provide insulation for the surface of the trench electrode 82. The insulating film 6 in the trench 90 will later provide insulation for the surface of the trench electrode 9. The insulating film 6 is formed by, for example, thermal oxidation.

[0137] A conductor 702 is provided on the insulating film 6 and the insulating film 602 in the trenches 90, 802 on the side opposite to the semiconductor substrate 1 (FIG. 36). Both the trenches 90, 802 are filled with the insulating film 6 and the conductor 702. For example, polysilicon doped with a high impurity concentration is used for the conductor 702.

[0138] The conductor 702 remains only in the trenches 90, 802 by etching back from the side opposite to the semiconductor substrate 1, and is exposed as the conductor 7 (FIG. 37). Thereafter, the surfaces of the conductor 702 exposed in the trenches 90, 802 are oxidized by, for example, an oxidation process, to obtain the corresponding trench electrodes 9, 82. In view of the above-mentioned manufacturing process, it can be said that the trench electrode 82 is embedded in the trench 802, and the trench electrode 9 is embedded in the trench 90.

[0139] The trenches 90, 802 are formed in a parallel process (see FIG. 34). The fact that the bottom position of the trench electrode 82 (e.g., depth d2) and the bottom position of the trench electrode 9 (e.g., depth d9) coincide with each other contributes to the adoption of such a process. The adoption of such a parallel process contributes to the simplification of the formation of the trench electrodes 82, 9, and thus to the simplification of the manufacturing process of the semiconductor device 100A. The simplification of the manufacturing process contributes to the reduction of the manufacturing cost of the semiconductor device 100A.

[0140] The formation of the trenches 802, 90 described above can be explained as follows: prior to the formation of either of the trench electrodes 82, 9, the trench 802 for filling the trench electrode 82 and the trench 90 for filling the trench electrode 9 are formed in parallel by selective etching using a mask 503 having openings 503a, 503b.

[0141] The formation of trenches 90 and 802 may precede the formation of trench 801. The formation of trench 801 may precede the formation of semiconductor layer 41. The formation of trenches 90 and 802 may precede the formation of semiconductor layer 42.

[0142] <Second Manufacturing Method of Semiconductor Device 100A> 38 to 41 are cross-sectional views illustrating a part of the second manufacturing method of the semiconductor device 100A, particularly the manufacturing steps of the trench electrodes 81, 82, and 9 in order of steps.

[0143] 27 is obtained, a mask 502 is provided on the insulating film 401 on the side opposite to the semiconductor substrate 1 (FIG. 38). The mask 502 has openings 502a, 502b, and 502c. The openings 502a, 502b, and 502c are formed in the mask 502 in correspondence with the positions where the trench electrodes 81, 9, and 82 (see FIG. 1) are to be formed, respectively. By etching the insulating film 401 through the mask 502, holes corresponding to the openings 502a, 502b, and 502c are formed in the insulating film 401, and the semiconductor layers 41 and 42 are partially exposed.

[0144] Using the mask 502 and the insulating film 401 with the openings as described above as a mask, the semiconductor layers 25, 3, 41, 42 and the semiconductor substrate 1 are selectively etched to form trenches 801, 90, 802 (FIG. 39).

[0145] The position of trench 801 corresponds to the position where trench electrode 81 is provided. Trench 801 penetrates semiconductor layers 41 and 25 to reach semiconductor layer 3. The position of trench 802 corresponds to the position where trench electrode 82 is provided. Trench 802 penetrates semiconductor layers 42, 25, and 3 to reach semiconductor substrate 1. The position of trench 90 corresponds to the position where trench electrode 9 is provided. Trench 90 penetrates semiconductor layers 25 and 3 to reach semiconductor substrate 1.

[0146] By forming the trenches 90 and 802, the semiconductor layer 3 is divided into the semiconductor layers 31 and 32.

[0147] The trenches 90 and 802 are used to form the trench electrodes 9 and 82, respectively. The insulating film 6 used for surface insulation in the trench electrodes 9, 81, and 82 functions as a so-called gate insulating film, and therefore the thicknesses thereof are approximately equal in the trenches 90, 801, and 802. Since the trench electrodes 9 and 82 are formed deeper than the trench electrode 81, the trenches 90 and 802 are also formed deeper than the trench 801.

[0148] This parallel formation of deep trenches 90, 802 and shallow trench 801 is facilitated by having trenches 90, 802 have wider openings than trench 801. For example, the wider the openings in the mask used in the selective etch, the wider the resulting trench openings and the faster the etch rate.

[0149] Fig. 42 is a graph illustrating the relationship between the trench depth and the mask opening width when a trench is formed by selective etching using a mask with an opening. The horizontal axis indicates the minimum width of the opening provided in the mask as the opening width [nm]. For example, when the opening is rectangular, the length of the short side of the rectangle is used as the opening width. The vertical axis indicates the trench depth [μm].

[0150] 42, the larger the opening width of the mask, the deeper the trench that is formed. Since trench electrodes 81, 82, and 9 are embedded in trenches 801, 802, and 90, respectively, the depths of trenches 801, 802, and 90 can be substantially treated as depths d1, d2, and d9, respectively.

[0151] The fact that the openings 502b and 502c are wider than the opening 502a contributes to forming the deep trenches 90 and 802 and the shallow trench 801 in parallel, which in turn contributes to simplifying the process of forming the trench electrodes 81, 82, and 9.

[0152] For example, widths w2 and w3 of trench electrodes 82 and 9 that extend deeper than trench electrode 81 are both greater than width w1 of trench electrode 81 (see FIG. 1). Widths w1, w2, and w3 are the sizes of trench electrodes 81, 82, and 9 in a direction (left-right direction on the paper in FIG. 1) perpendicular to the direction in which trench electrodes 81, 82, and 9 extend (up-down direction on the paper in FIG. 1).

[0153] Generally, the larger the opening width of the mask, the wider the width of the formed trench. Since trench electrodes 81, 82, and 9 are embedded in trenches 801, 802, and 90 respectively, the widths of trenches 801, 802, and 90 can be substantially treated as widths w1, w3, and w3 respectively. The formation of trench electrodes 81, 82, and 9 having the above-described relationship regarding width (w1 < w2, w1 < w3) contributes to the formation of deep trench 90, 802 and shallow trench 801 in parallel, and thus contributes to the above-described simplification and, consequently, to the suppression of manufacturing costs. The same also holds true for semiconductor devices 100B, 100C, 100D and their manufacturing methods (see FIGS. 21, 23, and 24).

[0154] The formation of trenches 801, 802, and 90 described above can be explained as follows: Prior to the formation of any of trench electrodes 81, 82, and 9, trench 801 for embedding trench electrode 81, trench 802 for embedding trench electrode 82, and trench 90 for embedding trench electrode 9 are formed in parallel by selective etching using mask 502 provided with openings 502a, 502b, and 502c. The openings 502b for the etching to form trench 802 and the openings 502c for the etching to form trench 90 are wider than the opening 502a used for the etching to form trench 801.

[0155] An insulating film 6 is formed on the semiconductor layers 41, 25, 31 exposed on the inner wall of trench 801 and on the semiconductor substrate 1 and semiconductor layers 42, 25, 31, 32 exposed on the inner walls of trenches 802 and 90 (FIG. 40). For the formation of such insulating film 6, for example, thermal oxidation is utilized.

[0156] A conductor 703 is provided on the side opposite to the semiconductor substrate 1 on the insulating film 6 and the insulating film 401 in trenches 90, 801, and 802 (FIG. 41). All of trenches 90, 801, and 802 are filled with the insulating film 6 and the conductor 703. For the conductor 703, for example, polysilicon doped with a high impurity concentration is employed.

[0157] The conductor 703 remains as the conductor 7 only in the trenches 90, 801, and 802 by etching back from the side opposite to the semiconductor substrate 1. Thereafter, the surface of the conductor 703 exposed in each of the trenches 90, 801, and 802 is oxidized by, for example, an oxidation process to obtain the trench electrodes 9, 81, and 82. This provides a structure in which the insulating film 602 in FIG. 37 is replaced with the insulating film 401. In view of these manufacturing steps, it can be said that the trenches 801, 802, and 90 are filled with the trench electrodes 81, 82, and 9, respectively.

[0158] In the second manufacturing method, the formation of the trenches 90, 801, and 802 may precede the formation of the semiconductor layers 41 and .

[0159] <Manufacturing Method of Semiconductor Device 100B> The semiconductor device 100B according to the second embodiment differs from the semiconductor device 100A in that the semiconductor layer 42 is not present. The manufacturing method of the semiconductor device 100B differs from the first manufacturing method of the semiconductor device 100A in that the opening 501b is not formed in the mask 501. Since the opening 501b is not formed, when the N-type impurity is introduced and drive-in is performed, the semiconductor layer 41 is formed but the semiconductor layer 42 is not formed.

[0160] <First Manufacturing Method of the Semiconductor Device 100D> 43 to 47 are cross-sectional views illustrating a part of the first manufacturing method of the semiconductor device 100D according to the fourth embodiment, in particular, the manufacturing steps of the semiconductor layers 31 and 32 in order of steps. As described later, the description of the manufacturing method can also be applied to the description of the manufacturing methods of the semiconductor device 100A according to the first embodiment, the semiconductor device 100B according to the second embodiment, and the semiconductor device 100C according to the third embodiment.

[0161] 43 to 47, the semiconductor layer 31 is formed on the left side of the broken line, and the semiconductor layer 32 is formed on the right side of the broken line.

[0162] An insulating film 410 is provided on the main surface of the semiconductor substrate 1 (FIG. 43). For example, when silicon is used for the semiconductor substrate 1, the insulating film 410 is realized by a silicon oxide film obtained by oxidizing the main surface of the semiconductor substrate 1.

[0163] A mask 511 selectively covers the insulating film 410 (FIG. 44). The mask 511 avoids a region where the semiconductor layer 32 will be formed later, and covers the insulating film 410 in a region where the semiconductor layer 31 will be formed later. It can also be said that the insulating film 410 is covered by the mask 511 that has an opening in a region where the semiconductor layer 32 will be formed later.

[0164] For example, a patterned photoresist film is used as the mask 511. N-type impurities are introduced into the semiconductor substrate 1 through the insulating film 410 and the mask 511 with the openings as described above. For example, phosphorus (P) is introduced as the N-type impurity.

[0165] FIG. 44 illustrates an example in which ion implantation using phosphorus ions (P+: where the symbol "+" does not indicate the magnitude of the impurity concentration but indicates that the ions are positive ions) is used to introduce N-type impurities.

[0166] The symbol "x" in the semiconductor substrate 1 typically indicates a location where an N-type impurity has been introduced. A region 302 where an N-type impurity has been introduced is shown in FIG.

[0167] After the mask 511 is removed by a known technique, a mask 512 selectively covers the insulating film 410 (FIG. 45). The mask 512 avoids the region where the semiconductor layer 31 will be formed later, and covers the insulating film 410 in the region where the semiconductor layer 32 will be formed later. It can also be said that the insulating film 410 is covered by the mask 512 that has an opening in the region where the semiconductor layer 31 will be formed later.

[0168] For example, a patterned photoresist film is also used for the mask 512. N-type impurities are introduced into the semiconductor substrate 1 through the insulating film 410 and the mask 512 with the opening as described above. For example, phosphorus (P) is introduced as the N-type impurity.

[0169] Fig. 45 illustrates a case where ion implantation using phosphorus ions is adopted for the introduction of N-type impurities. In Fig. 45, a region 301 into which N-type impurities have been introduced is shown.

[0170] In the semiconductor device 100D, the peak value of the impurity concentration of the semiconductor layer 31, for example, the peak concentration, is lower than the peak value of the impurity concentration of the semiconductor layer 32. As a method for obtaining the semiconductor layers 31 and 32 having different peak values ​​of the impurity concentrations, N-type impurities are introduced into the regions 302 and 301, respectively, by using the masks 511 and 512 as described above.

[0171] In FIG. 45, the peak value of the N-type impurity concentration in region 302 is greater than that in region 301, which is diagrammatically shown by the symbols “x” being arranged more densely in region 302 than in region 301.

[0172] After the mask 512 is removed, a P-type impurity is introduced into the semiconductor substrate 1 through the insulating film 410 (FIG. 46). More specifically, the P-type impurity is introduced through a mask (not shown) that has an opening in a region where the semiconductor layer 2 will be formed later.

[0173] As the P-type impurity, for example, boron (B) is introduced. Figure 46 shows an example in which ion implantation using boron ions (B+: the symbol "+" here does not indicate the magnitude of the impurity concentration but indicates that the ions are positive ions) is adopted for the introduction of the P-type impurity.

[0174] The symbol "●" in the semiconductor substrate 1 schematically indicates the location where P-type impurities are introduced. In FIG. 46, for both regions 301 and 302, a region 200 where P-type impurities are introduced is shown on the insulating film 410 side.

[0175] After P-type impurities are introduced into the semiconductor substrate 1, the semiconductor layers 2, 31, and 32 are obtained by drive-in. The P-type impurities are introduced into the region 200 regardless of the positions of the regions 301 and 302. The semiconductor layer 2 is caused by the P-type impurities introduced into the region 200. The semiconductor layer 2 is formed at a depth d2 on the insulating film 410 side with respect to both the semiconductor layers 31 and 32 (FIG. 47).

[0176] The concentration of the N-type impurities introduced in the region 301 is lower than the concentration of the N-type impurities introduced in the region 302. The N-type impurities introduced into the region 301 and the N-type impurities introduced into the region 302 are subjected to drive-in in parallel to form the semiconductor layers 31 and 32, respectively. Reflecting the high and low peak values of the above-mentioned impurity concentrations, the depth d31 of the semiconductor layer 31 is shallower than the depth d32 of the semiconductor layer 32 (d31 < d32: see also FIG. 24).

[0177] The process of forming the semiconductor layers 31 and 32 can be roughly classified into an introduction process and a diffusion process and described as follows: Prior to the formation of the semiconductor layers 31 and 32, N-type impurities are introduced into the semiconductor substrate 1 into the region 301 with a first introduction amount and into the region 302 with a second introduction amount, respectively. However, the second introduction amount is larger than the first introduction amount (introduction process); The diffusion of the N-type impurities introduced in the region 301 and the diffusion of the N-type impurities introduced in the region 302 are performed in parallel to form the semiconductor layers 31 and 32 (diffusion process).

[0178] Thereafter, the semiconductor layer 5 is formed by a known method, and the semiconductor layers 41 and 42 and the trench electrodes 81, 82, and 9 are formed in the same manner as in the first manufacturing method of the semiconductor device 100A, the second manufacturing method, and the manufacturing method of the semiconductor device 100B, and the semiconductor device 100D is obtained.

[0179] Prior to the introduction of the N-type impurity, the P-type impurity may be introduced.

[0180] When manufacturing the semiconductor devices 100A and 100B, the semiconductor layer 2, which is collectively shown as the semiconductor layer 25 together with the semiconductor layer 5, and the semiconductor layer 3 are formed by, for example, the steps illustrated in Figures 43 to 47. For example, in the semiconductor device 100A, when the peak values ​​of the impurity concentrations of the semiconductor layers 31 and 32 are made uniform, it is not necessary to introduce the N-type impurity in two stages (see Figures 44 and 45) using the masks 511 and 512. For example, similar to the introduction of the P-type impurity (see Figure 46), the N-type impurity is introduced in parallel into the regions 301 and 302 using a mask that opens in the region where the semiconductor layer 3 is to be formed.

[0181] In the semiconductor device 100C, the semiconductor layer 31 is considered to be a part of the semiconductor substrate 1. When manufacturing the semiconductor device 100C, no N-type impurity is required in the region 301. In this case, it is not necessary to introduce the N-type impurity using the mask 512. The manufacturing process of the semiconductor device 100C is simpler than that of the semiconductor devices 100A, 100B, and 100D.

[0182] <Second Manufacturing Method of Semiconductor Device 100D> FIG. 48 is a cross-sectional view illustrating a part of the second manufacturing method of the semiconductor device 100D, particularly a part of the manufacturing process of the semiconductor layers 31 and 32.

[0183] In the second manufacturing method of the semiconductor device 100D, an insulating film 410 is provided on the semiconductor substrate 1 in the same manner as in the first manufacturing method of the semiconductor device 100D (see FIG. 43).

[0184] The mask 510 selectively covers the insulating film 410. Like the mask 511 (see FIG. 44), the mask 510 avoids the region where the semiconductor layer 32 will be formed later, and covers the insulating film 410 in the region where the semiconductor layer 31 will be formed later. It can also be said that the insulating film 410 is covered by the mask 510 that has an opening in the region where the semiconductor layer 32 will be formed later.

[0185] However, the mask 510 has a lower ability to inhibit the introduction of N-type impurities than the mask 511. For example, the mask 510 has a stripe pattern or a dot pattern in the region where the semiconductor layer 31 is to be formed later.

[0186] For example, a patterned photoresist film is used as the mask 510. N-type impurities are introduced into the semiconductor substrate 1 through the insulating film 410 and the mask 510 with the openings as described above. For example, phosphorus (P) is introduced as the N-type impurity.

[0187] Through the stripe or dot pattern of mask 510, a smaller amount of N-type impurity is introduced into region 301 than into region 302. A larger amount of N-type impurity is introduced into region 302 not covered by mask 510 than into region 301. In FIG. 48 as in FIG. 45, the density of the symbols "x" diagrammatically indicates the amount of N-type impurity introduced.

[0188] Using a mask 510, N-type impurities are introduced into regions 301 and 302 in parallel, with different amounts introduced into each region. The effective amount of N-type impurities introduced into region 301 is lower than the effective amount of N-type impurities introduced into region 302.

[0189] After the introduction of N-type impurities into regions 301 and 302, P-type impurities are introduced as illustrated in Fig. 46. After the P-type impurities are introduced, a drive-in is performed to obtain the structure illustrated in Fig. 47. Subsequent processing is performed in the same manner as in the first manufacturing method of the semiconductor device 100D.

[0190] In accordance with the explanation of the “introduction process” already described, in this introduction process, the introduction of N-type impurities into region 301 and the introduction of N-type impurities into region 302 are carried out in parallel by ion implantation using a mask 510 having a stripe pattern or a dot pattern.

[0191] The second manufacturing method of the semiconductor device 100D has fewer steps for introducing N-type impurities than the first manufacturing method of the semiconductor device 100D, which contributes to simplifying the manufacturing process of the semiconductor device 100D. The simplification of the manufacturing process contributes to reducing the manufacturing cost of the semiconductor device 100D.

[0192] <Fifth Preferred Embodiment> In the above description of "the distance between the trench electrodes 81, 82, 9", the distance between the adjacent trench electrodes 82 and 9 along the direction in which the trench electrodes 82 and 9 are arranged, and the distance between the adjacent trench electrodes 9 via the trench electrode 81 are exemplified as the trench distance. The emitter region is not shared between the trench electrodes 81 and 82. Even if there are a plurality of trench electrodes 9 separating the semiconductor layer 31 facing the trench electrode 81 from the semiconductor layer 32 facing the trench electrode 82, an increase in forward conduction loss due to the extension of the depletion layer is suppressed, and thus the allowable range of the time difference dt for reducing loss is expanded.

[0193] Fig. 49 is a cross-sectional view illustrating a configuration example of a semiconductor device 100E according to embodiment 5. Fig. 50 is a cross-sectional view illustrating an example of the configuration of the semiconductor device 100E, and Fig. 51 is a cross-sectional view illustrating another example of the configuration of the semiconductor device 100E.

[0194] Both the cross section shown in Fig. 50 and the cross section shown in Fig. 51 appear when viewed from the direction of the arrow at position AA in Fig. 49. The cross section shown in Fig. 49 is also a cross section seen from the direction of the arrow at position BB in Fig. 50, and is also a cross section seen from the direction of the arrow at position CC in Fig. 51. The configuration shown in Fig. 50 contributes to suppressing the multi-layering of wiring using, for example, polysilicon, and ultimately to improving productivity.

[0195] Compared to the semiconductor device 100A (see FIGS. 1, 2, and 3), the semiconductor device 100E is understood to have a configuration in which the trench electrode 9 is divided into two in the direction in which the trench electrodes 81 and 82 are arranged. Between the divided trench electrode 9, the semiconductor layers 31, 2, and 5 are laminated in this order when viewed from the semiconductor substrate 1 side, and neither of the semiconductor layers 41 and 42 is present.

[0196] It is considered that the distance between adjacent trench electrodes 9 without passing through the trench electrode 81, as exemplified by the semiconductor device 100E, also corresponds to the trench pitch. In view of FIG. 25 and the description using the same, making the distance between adjacent trench electrodes 9 in the semiconductor device 100E narrower than 15 μm contributes to making the breakdown voltage of the semiconductor device 100E 90% or more of the target breakdown voltage.

[0197] The semiconductor device 100E can also be manufactured in the same manner as the semiconductor device 100A. Specifically, in the first manufacturing method of the semiconductor device 100A, a plurality of openings 503a (see FIG. 33) opened in the mask 503 are provided closer to the trench electrode 81 side than the opening 503b. Alternatively, in the second manufacturing method of the semiconductor device 100A, a plurality of openings 502b (see FIG. 38) opened in the mask 502 are provided between the openings 502a and 502c.

[0198] Also in the semiconductor device 100E, similar to the semiconductor device 100D, the peak value of the impurity concentration of the semiconductor layer 31 may be lower than the peak value of the impurity concentration of the semiconductor layer 32. Further, the semiconductor layer 31 may be thinner than the semiconductor layer 32, and the relationship d31 < d32 may hold. The semiconductor device 100E in this case can be manufactured, for example, in the same manner as the semiconductor device 100D. Specifically, for example, the first manufacturing method and the second manufacturing method of the semiconductor device 100D can be applied.

[0199] <Embodiment 6> Even if a pair of trench electrodes 9 sandwich a plurality of trench electrodes 82, the emitter regions are not shared between the trench electrodes 81 and 82. The increase in the forward conduction loss due to the extension of the depletion layer is suppressed, and thus the allowable range of the time difference dt for reducing the loss is expanded.

[0200] FIG. 52 is a cross-sectional view illustrating the configuration of a semiconductor device 100F according to Embodiment 6. FIG. 53 is a cross-sectional view showing an example of the configuration of the semiconductor device 100F, and FIG. 54 is a cross-sectional view showing another example of the configuration of the semiconductor device 100F.

[0201] Both the cross section shown in Fig. 53 and the cross section shown in Fig. 54 appear when viewed from the direction of the arrow at position DD in Fig. 52. The cross section shown in Fig. 52 is also a cross section seen from the direction of the arrow at position EE in Fig. 53, and is also a cross section seen from the direction of the arrow at position FF in Fig. 54. The configuration shown in Fig. 53 contributes to suppressing the multi-layering of wiring using, for example, polysilicon, and ultimately to improving productivity.

[0202] Compared to the semiconductor device 100A (see FIGS. 1, 2, and 3), the semiconductor device 100F is understood to have a configuration in which two trench electrodes 82 are provided in the direction in which the trench electrodes 81 and 9 are aligned. For each trench electrode 82, semiconductor layers 32, 2, and 5 are laminated in this order on both sides in the alignment direction when viewed from the semiconductor substrate 1 side. For each trench electrode 82, semiconductor layer 42 is present closer to the trench electrode 82 than semiconductor layer 5 on both sides in the alignment direction.

[0203] As exemplified in the semiconductor device 100F, the interval between adjacent trench electrodes 82 without any of the trench electrodes 81, 9 in between is also considered to correspond to the trench interval. In view of Fig. 25 and the explanation using it, making the interval between adjacent trench electrodes 82 in the semiconductor device 100F narrower than 15 µm contributes to making the withstand voltage of the semiconductor device 100F 90% or more of the target withstand voltage.

[0204] The semiconductor device 100F can be manufactured in the same manner as the semiconductor device 100A. Specifically, referring to Fig. 33, in a first manufacturing method for the semiconductor device 100A, a pair of semiconductor layers 42 are provided adjacent to each other, and an opening 503b is provided in the mask 503 in each of the semiconductor layers 42. Alternatively, referring to Fig. 38, in a second manufacturing method for the semiconductor device 100A, a pair of semiconductor layers 42 are provided adjacent to each other, and an opening 502c is provided in the mask 502 in each of the semiconductor layers 42.

[0205] Also in the semiconductor device 100F, similar to the semiconductor device 100D, the peak value of the impurity concentration of the semiconductor layer 31 may be lower than the peak value of the impurity concentration of the semiconductor layer 32. Further, the semiconductor layer 31 may be thinner than the semiconductor layer 32, and there may be a relationship of d31 < d32. The semiconductor device 100F in this case can be manufactured, for example, in the same manner as the semiconductor device 100D. Specifically, for example, the first manufacturing method and the second manufacturing method of the semiconductor device 100D can be applied.

[0206] Any of the technologies described above can be adopted for a reverse conducting IGBT (RC-IGBT).

[0207] Note that within the scope of the present invention, the embodiments can be freely combined with each other, or each embodiment can be appropriately modified or omitted.

[0208] Hereinafter, aspects of the present disclosure will be collectively described as appendices.

[0209] (Appendix 1) A semiconductor substrate of a first conductivity type, A first semiconductor layer of the first conductivity type located on the surface layer of the semiconductor substrate, A second semiconductor layer of the first conductivity type that is exclusively located in the surface layer of the semiconductor substrate with respect to the first semiconductor layer and has a peak value of impurity concentration higher than that of the semiconductor substrate, A third semiconductor layer of the second conductivity type located on the side opposite to the semiconductor substrate with respect to the first semiconductor layer and the second semiconductor layer, A fourth semiconductor layer of the second conductivity type that is selectively located on the side opposite to the semiconductor substrate with respect to the third semiconductor layer and has a peak value of impurity concentration higher than that of the third semiconductor layer, A fifth semiconductor layer of the first conductivity type that is exclusively located on the side opposite to the semiconductor substrate with respect to the third semiconductor layer with respect to the fourth semiconductor layer and has a peak value of impurity concentration higher than that of the second semiconductor layer, a sixth semiconductor layer of a second conductivity type located on the opposite side of the semiconductor substrate to any of the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, the fourth semiconductor layer, and the fifth semiconductor layer; a first electrode that penetrates the fifth semiconductor layer and the third semiconductor layer, extends to reach the first semiconductor layer farther from the sixth semiconductor layer than the boundary between the second semiconductor layer and the semiconductor substrate, and has an insulating surface; a second electrode that penetrates the second semiconductor layer, the fourth semiconductor layer, and the third semiconductor layer, or penetrates the second semiconductor layer, the fifth semiconductor layer, and the third semiconductor layer, extends to reach the semiconductor substrate, is closer to the sixth semiconductor layer than both the first semiconductor layer and the second semiconductor layer, and has an insulating surface; a third electrode that extends through the fourth semiconductor layer and the third semiconductor layer to reach the semiconductor substrate, is closer to the sixth semiconductor layer than either of the first semiconductor layer and the second semiconductor layer, separates the first semiconductor layer from the second semiconductor layer, sandwiches the second semiconductor layer together with the second electrode, and has an insulating surface; A semiconductor device comprising:

[0210] (Appendix 2) 2. The semiconductor device according to claim 1, wherein a peak value of the impurity concentration of the first semiconductor layer is higher than a peak value of the impurity concentration of the semiconductor substrate.

[0211] (Appendix 3) 3. The semiconductor device according to claim 2, wherein the second electrode penetrates the fifth semiconductor layer and the third semiconductor layer.

[0212] (Appendix 4) 4. The semiconductor device according to claim 3, wherein a peak value of the impurity concentration of the first semiconductor layer is lower than a peak value of the impurity concentration of the second semiconductor layer.

[0213] (Appendix 5) The semiconductor device of claim 4, wherein the first semiconductor layer is thinner than the second semiconductor layer.

[0214] (Appendix 6) 3. The semiconductor device according to claim 2, wherein the second electrode penetrates the fourth semiconductor layer and the third semiconductor layer.

[0215] (Appendix 7) The semiconductor device described in Appendix 1, wherein the first semiconductor layer is part of the semiconductor substrate.

[0216] (Appendix 8) 2. The semiconductor device described in claim 1, wherein the second electrode penetrates the fifth semiconductor layer and the third semiconductor layer.

[0217] (Appendix 9) 2. The semiconductor device described in claim 1, wherein the second electrode penetrates the fourth semiconductor layer and the third semiconductor layer.

[0218] (Appendix 10) 10. The semiconductor device according to claim 1, wherein a length by which the second electrode protrudes from the second semiconductor layer to the semiconductor substrate in a direction in which the second electrode extends is equal to a length by which the third electrode protrudes from the second semiconductor layer to the semiconductor substrate in a direction in which the third electrode extends.

[0219] (Appendix 11) 11. The semiconductor device according to claim 1, wherein a size of the first electrode in a direction perpendicular to a direction in which the first electrode extends is smaller than a size of the second electrode in a direction perpendicular to a direction in which the second electrode extends and a size of the third electrode in a direction perpendicular to a direction in which the third electrode extends.

[0220] (Appendix 12) 12. The semiconductor device according to claim 1, wherein a distance between adjacent second electrodes and third electrodes, a distance between adjacent second electrodes, or a distance between adjacent third electrodes is 15 μm or less along a direction in which the second electrodes and the third electrodes are arranged.

[0221] (Appendix 13) the third electrode is located on both sides of the first electrode in a direction in which the first electrode and the third electrode are arranged, 12. The semiconductor device according to claim 1, wherein a distance between the third electrode located on the one side of the first electrode and the third electrode located on the other side of the first electrode is 15 μm or less in the direction.

[0222] (Appendix 14) 14. A method for controlling a semiconductor device according to any one of claims 1 to 13, comprising: A first signal is applied to the first electrode; A second signal is applied to the second electrode; A method for controlling a semiconductor device, wherein when both the first signal and the second signal are caused to transition to turn off the semiconductor device, the first signal transitions with a delay relative to the second signal.

[0223] (Appendix 15) 15. The method of controlling a semiconductor device according to claim 14, wherein the first conductivity type is N-type, and the second signal transitions at a potential equal to or less than zero with respect to the third electrode.

[0224] (Appendix 16) A method for manufacturing the semiconductor device according to claim 5, comprising the steps of: an introduction step of introducing a first conductivity type impurity into a first region of the semiconductor substrate at a first introduction amount and into a second region of the semiconductor substrate at a second introduction amount greater than the first introduction amount, prior to the formation of the first semiconductor layer and the second semiconductor layer; a diffusion step of forming the first semiconductor layer and the second semiconductor layer by simultaneously diffusing the first conductive type impurity introduced in the first region and the first conductive type impurity introduced in the second region; A manufacturing method of a semiconductor device comprising:

[0225] (Appendix 17) 17. The method for manufacturing a semiconductor device according to claim 16, wherein in the introducing step, the introduction of the first conductivity type impurity into the first region and the introduction of the first conductivity type impurity into the second region are carried out in parallel by ion implantation using a mask having a stripe pattern or a dot pattern.

[0226] (Appendix 18) A method for manufacturing the semiconductor device according to claim 10, comprising the steps of: A method for manufacturing a semiconductor device, comprising the steps of: forming a trench into which the second electrode is to be embedded and a trench into which the third electrode is to be embedded in parallel by selective etching using a mask having an opening, prior to forming either the second electrode or the third electrode.

[0227] (Appendix 19) A method for manufacturing the semiconductor device according to claim 11, comprising the steps of: A method for manufacturing a semiconductor device, comprising the steps of: prior to forming any of the first electrode, the second electrode, and the third electrode, forming a first trench into which the first electrode is embedded, a second trench into which the second electrode is embedded, and a third trench into which the third electrode is embedded in in parallel by selective etching using a mask having openings; and an opening used in the etching to form the second trench and an opening used in the etching to form the third trench are wider than an opening used in the etching to form the first trench. [Explanation of symbols]

[0228] 1 semiconductor substrate, 2, 3, 5, 10, 11, 31, 32, 41, 42 semiconductor layer, 81, 82, 9 trench electrode, 100A to 100F semiconductor device, 301, 302 region, 502, 503 mask, 502a, 502b, 502c, 503a, 503b opening, 801, 802, 90 trench.

Claims

1. a semiconductor substrate of a first conductivity type; a first semiconductor layer of the first conductivity type located on a surface layer of the semiconductor substrate; a second semiconductor layer of the first conductivity type located exclusively with respect to the first semiconductor layer in the surface layer of the semiconductor substrate and having a peak value of an impurity concentration higher than that of the semiconductor substrate; a third semiconductor layer of a second conductivity type located on an opposite side of the semiconductor substrate with respect to the first semiconductor layer and the second semiconductor layer; a fourth semiconductor layer of the second conductivity type selectively located on the opposite side of the third semiconductor layer from the semiconductor substrate, the fourth semiconductor layer having a higher peak value of impurity concentration than the third semiconductor layer; a fifth semiconductor layer of the first conductivity type, the fifth semiconductor layer being located exclusively with the fourth semiconductor layer on the opposite side of the third semiconductor layer from the semiconductor substrate, and having a peak value of an impurity concentration higher than that of the second semiconductor layer; a sixth semiconductor layer of the second conductivity type located on the opposite side of the semiconductor substrate to any of the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, the fourth semiconductor layer, and the fifth semiconductor layer; a first electrode that penetrates the fifth semiconductor layer and the third semiconductor layer, extends to reach the first semiconductor layer farther from the sixth semiconductor layer than the boundary between the second semiconductor layer and the semiconductor substrate, and has an insulating surface; a second electrode that penetrates the second semiconductor layer, the fourth semiconductor layer, and the third semiconductor layer, or penetrates the second semiconductor layer, the fifth semiconductor layer, and the third semiconductor layer, extends to reach the semiconductor substrate, is closer to the sixth semiconductor layer than either the first semiconductor layer or the second semiconductor layer, and has an insulating surface; a third electrode that extends through the fourth semiconductor layer and the third semiconductor layer to reach the semiconductor substrate, is closer to the sixth semiconductor layer than either of the first semiconductor layer and the second semiconductor layer, separates the first semiconductor layer from the second semiconductor layer, sandwiches the second semiconductor layer together with the second electrode, and has an insulating surface; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, wherein a peak value of the impurity concentration of said first semiconductor layer is higher than a peak value of the impurity concentration of said semiconductor substrate.

3. The semiconductor device according to claim 2 , wherein the second electrode penetrates the fifth semiconductor layer and the third semiconductor layer.

4. 4. The semiconductor device according to claim 3, wherein a peak value of the impurity concentration of said first semiconductor layer is lower than a peak value of the impurity concentration of said second semiconductor layer.

5. The semiconductor device according to claim 4 , wherein the first semiconductor layer is thinner than the second semiconductor layer.

6. The semiconductor device according to claim 2 , wherein the second electrode penetrates the fourth semiconductor layer and the third semiconductor layer.

7. The semiconductor device according to claim 1 , wherein the first semiconductor layer is a part of the semiconductor substrate.

8. The semiconductor device according to claim 1 , wherein the second electrode penetrates the fifth semiconductor layer and the third semiconductor layer.

9. The semiconductor device according to claim 1 , wherein the second electrode penetrates the fourth semiconductor layer and the third semiconductor layer.

10. 10. The semiconductor device according to claim 1, wherein a length by which the second electrode protrudes from the second semiconductor layer to the semiconductor substrate in a direction in which the second electrode extends is equal to a length by which the third electrode protrudes from the second semiconductor layer to the semiconductor substrate in a direction in which the third electrode extends.

11. 10. The semiconductor device according to claim 1, wherein a size of the first electrode in a direction perpendicular to a direction in which the first electrode extends is smaller than a size of the second electrode in a direction perpendicular to a direction in which the second electrode extends and a size of the third electrode in a direction perpendicular to a direction in which the third electrode extends.

12. 10. The semiconductor device according to claim 1, wherein a distance between adjacent second electrodes and third electrodes, a distance between adjacent second electrodes, or a distance between adjacent third electrodes is 15 μm or less along a direction in which the second electrodes and the third electrodes are arranged.

13. the third electrode is located on both sides of the first electrode in a direction in which the first electrode and the third electrode are arranged, 10. The semiconductor device according to claim 1, wherein a distance between the third electrode located on the one side of the first electrode and the third electrode located on the other side of the first electrode is 15 μm or less in the direction.

14. A method for controlling a semiconductor device according to any one of claims 1 to 9, comprising the steps of: A first signal is applied to the first electrode; A second signal is applied to the second electrode; A method for controlling a semiconductor device, wherein when both the first signal and the second signal are caused to transition to turn off the semiconductor device, the first signal transitions with a delay relative to the second signal.

15. 15. The method of claim 14, wherein the first conductivity type is N-type, and the second signal transitions at a potential equal to or less than zero with respect to the third electrode.

16. A method for manufacturing the semiconductor device according to claim 5, comprising the steps of: an introduction step of introducing the first conductivity type impurity into the semiconductor substrate at a first introduction amount and into a second introduction amount, the second introduction amount being greater than the first introduction amount, into a first region and a second region, respectively, prior to the formation of the first semiconductor layer and the second semiconductor layer; a diffusion step of forming the first semiconductor layer and the second semiconductor layer by simultaneously diffusing the impurity of the first conductivity type introduced in the first region and the impurity of the first conductivity type introduced in the second region; A manufacturing method of a semiconductor device comprising:

17. 17. The method for manufacturing a semiconductor device according to claim 16, wherein in the introducing step, the introduction of the first conductivity type impurity into the first region and the introduction of the first conductivity type impurity into the second region are carried out in parallel by ion implantation using a mask having a stripe pattern or a dot pattern.

18. A method for manufacturing a semiconductor device according to claim 10, comprising the steps of: A method for manufacturing a semiconductor device, comprising the steps of: forming a trench into which the second electrode is to be embedded and a trench into which the third electrode is to be embedded in parallel by selective etching using a mask having an opening, prior to forming either the second electrode or the third electrode.

19. A method for manufacturing a semiconductor device according to claim 11, comprising the steps of: A method for manufacturing a semiconductor device, comprising the steps of: prior to the formation of any of the first electrode, the second electrode, and the third electrode, forming a first trench into which the first electrode is embedded, a second trench into which the second electrode is embedded, and a third trench into which the third electrode is embedded in in parallel by selective etching using a mask having openings; and an opening used in the etching to form the second trench and an opening used in the etching to form the third trench are wider than an opening used in the etching to form the first trench.

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