Display device

Abstract

To provide a light-emitting display device without adding a new step by simplifying the manufacturing process of a transistor and reducing the number of photomasks.SOLUTION: The use of an intrinsic or substantially intrinsic oxide semiconductor with high resistance for a semiconductor layer included in a transistor can omit the step of processing the semiconductor layer into an island shape for each transistor. The number of photolithography steps is reduced by simultaneously etching an unnecessary part of the semiconductor layer in a step of forming an opening in an insulation layer formed on the upper surface of the semiconductor layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a light-emitting display device having a transistor. [Background technology]

[0002] In recent years, a thin film of about several nm to several hundred nm thick has been formed on a substrate with an insulating surface such as a glass substrate. Thin film transistors, which are made up of thin semiconductor films of various thicknesses, have been attracting attention. is a company that deals with electronic devices including ICs (Integrated Circuits) and electro-optical devices. Thin film transistors are widely used in devices, especially EL (Electro Luminescence) It is used as a switching element in image display devices, such as Development is being rushed.

[0003] In an active matrix EL display device, one of the light emitting elements provided in a selected pixel A voltage is applied between one electrode and the other electrode that sandwiches the EL layer (including the light-emitting layer) together with the electrode. When a voltage is applied, a current flows through the EL layer, causing the light-emitting layer to emit light. This light emission is called a display pattern. Here, the active matrix type EL display device is a The pixels arranged in a grid are driven by switching elements to display This refers to an EL display device that employs a method for forming a display pattern.

[0004] The applications of such active matrix EL displays are expanding, and the screen size There is a growing demand for larger areas, higher definition, and higher aperture ratios. High reliability is required for the display device, and the manufacturing method requires high productivity and low production cost. One of the methods to increase productivity and reduce production costs is to simplify the process. Can be obtained.

[0005] In active matrix display devices, thin film transistors are mainly used as switching elements. It is used to reduce or eliminate the photolithography process in the manufacture of thin-film transistors. Simplifying the process is important for simplifying the entire process. For example, photolithography Adding one process step requires additional steps such as resist coating, pre-baking, exposure, development, and post-baking. The process before and after this includes the formation of a coating and the etching process, as well as the resist stripping and washing. Therefore, the photolithography process in the manufacturing process is The number of steps involved increases significantly with just one additional step. Many technologies have been developed to reduce or simplify the photolithography process. There are.

[0006] A thin-film transistor is a top-gate transistor in which the channel formation region is provided below the gate electrode. and bottom-gate type, in which the channel formation region is provided above the gate electrode. These thin-film transistors can be fabricated using at least five photomasks. It is common.

[0007] Conventional techniques for simplifying the photolithography process include backside exposure, resist reflection, and Many of them use complex techniques such as the lift-off method, which requires special equipment. The use of such complex technology often leads to various problems, In addition, the electrical characteristics of the thin film transistors must be sacrificed. Often times, this is not possible.

[0008] In addition, in order to simplify the photolithography process in the manufacturing process of thin film transistors, A typical method is a multi-tone mask (called a half-tone mask or gray-tone mask). The technology using multi-tone masks is widely known. Such a technique is disclosed in, for example, Patent Document 1. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] JP 2003-179069 A Summary of the Invention [Problem to be solved by the invention]

[0010] When using a multi-tone mask, the number of masks can be reduced, but it is necessary to create new resist masks. To achieve this shape, a new process such as ashing is required.

[0011] One embodiment of the present invention is to reduce the number of photomasks compared to the conventional method, and also to It is an object of the present invention to manufacture a light-emitting display device without increasing the number of [Means for solving the problem]

[0012] One embodiment of the present invention disclosed in this specification is a method for forming a semiconductor layer of a transistor by using a high-resistance oxidizing agent. By using solid semiconductors, the semiconductor layer can be processed into islands for each transistor. The present invention relates to a method for manufacturing a light-emitting display device that eliminates the steps of forming a conductive film and reduces the number of photolithography steps.

[0013] One embodiment of the present invention disclosed in this specification is a method for forming a first conductive film on a substrate, A first resist mask is formed on the first conductive film, and the first conductive film is selectively formed using the first resist mask. Then, the first gate electrode and the second gate electrode are formed by etching the first gate electrode and the second gate electrode. A first insulating film that will be a gate insulating layer is formed on the second gate electrode and the second gate electrode, and a semiconductor layer is formed on the gate insulating layer. A conductive film is formed, a second resist mask is formed on the semiconductor film, and the second resist mask is The semiconductor film and the first insulating film on the second gate electrode are selectively etched using the etching gas. A first opening is formed, and a second conductive film is formed so as to cover the semiconductor film and the first opening. A third resist mask is formed on the second conductive film, and the second conductive film is formed using the third resist mask. The conductive film is selectively etched to form a first solenoid that is electrically connected to the source / drain wiring. A first source electrode electrically connected to one of the source electrode and the drain electrode and the second gate electrode. the other of the source electrode and drain electrode, and a second source electrode and drain electrode connected to a power supply line The first electrode and the second source electrode and the drain electrode are formed on the first side of the first semiconductor layer. a first transistor having a gate electrode, a first source electrode, and a drain electrode; forming a second transistor having a second gate electrode, a second source electrode, and a drain electrode; The first source electrode and the drain electrode, the second source electrode and the drain electrode, and the semiconductor A second insulating film is formed on the main film to serve as a protective insulating film, and a fourth resist mask is formed on the second insulating film. A fourth resist mask is formed, and the second insulating film and the semiconductor film are selectively etched using the fourth resist mask. At the same time, the other of the second source electrode and the drain electrode is etched. A third opening is formed in the second insulating film so as to expose a portion of the second insulating film, and a second insulating film is formed so as to cover the third opening. A third conductive film is formed over the second insulating film, and a fifth resist mask is formed over the third conductive film. Then, the third conductive film is selectively etched using the fifth resist mask to form the first pixel electrode. a third insulating film is formed to cover the second opening, the third opening, and the periphery of the pixel electrode; A film is formed, a layer containing an organic compound is selectively formed on the pixel electrode, and a The method for manufacturing a light-emitting display device is characterized in that a second pixel electrode is formed on the first pixel electrode.

[0014] In this specification, ordinal numbers such as "first," "second," and "third" are used to refer to the mixture of elements. It should be noted that the numbers are added to avoid confusion and are not intended to be limiting.

[0015] Another embodiment of the present invention disclosed in this specification is a method for forming a first conductive film on a substrate, A first resist mask is formed on the conductive film, and the first conductive film is formed using the first resist mask. The film is selectively etched to form a first gate electrode and a second gate electrode. a first insulating film serving as a gate insulating layer is formed on the gate electrode and the second gate electrode; A semiconductor film is formed on the insulating layer, a second resist mask is formed on the semiconductor film, and the second resist A part of the semiconductor film and the first insulating film on the second gate electrode is selectively etched using a mask. A first opening is formed by etching, and a second conductive film is formed to cover the semiconductor film and the first opening. a third resist mask is formed on the second conductive film; The second conductive film is selectively etched using a SiO 2 film to form a layer electrically connected to the source / drain wiring. One of the first source electrode and the drain electrode is electrically connected to the second gate electrode. The other of the first source electrode and drain electrode and the second source electrode and and forming one of the first source electrode and the second drain electrode. A first transistor having a first gate electrode, a first source electrode and a drain electrode is formed. a second transistor having a second gate electrode, a second source electrode, and a drain electrode; A first source electrode and a drain electrode, a second source electrode and a drain electrode are formed on the first substrate. A second insulating film serving as a protective insulating film is formed on the semiconductor film, and a planarizing insulating film is formed on the second insulating film. A third insulating film is formed as an insulating film, a fourth resist mask is formed on the third insulating film, and a fourth resist mask is formed on the third insulating film. The third insulating film, the second insulating film and the semiconductor film are selectively etched using the resist mask of 4. The second opening is formed by etching the second source electrode and the other of the drain electrode. A third opening is formed in the second insulating film so that a part of the insulating film is exposed, and a second insulating film is formed so as to cover the third opening. A third conductive film is formed on the third insulating film, and a fifth resist mask is formed on the third conductive film. The third conductive film is selectively etched using a fifth resist mask to form a first pixel. A fourth insulating film is formed to cover the second opening, the third opening, and the periphery of the pixel electrode. An insulating film is formed, a layer containing an organic compound is selectively formed on the pixel electrode, and the layer containing the organic compound is The present invention relates to a method for manufacturing a light-emitting display device, and a method thereof for manufacturing the same.

[0016] It is preferable that an oxide semiconductor be used for the semiconductor film. The oxide semiconductor has extremely high resistance and can be considered as an insulator when constructing a circuit. Therefore, even if multiple transistors are configured on the same island-shaped semiconductor layer, they do not interfere with each other. Therefore, each transistor can be operated without any switching. Effect of the Invention

[0017] Since oxide semiconductors can be considered as insulators, island-shaped semiconductor layers can be formed for each transistor. A method for manufacturing a light-emitting display device that can omit a process for forming a light-emitting element and reduce a photolithography process The law can be provided. [Brief description of the drawings]

[0018] [Figure 1] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a light-emitting display device. [Diagram 2] FIG. 13 is a plan view of a light-emitting display device that does not have a capacitor element. [Diagram 3] FIG. 2 is an equivalent circuit diagram of a pixel portion of a light-emitting display device. [Figure 4] 1A to 1C are cross-sectional views illustrating one embodiment of a manufacturing method of a light-emitting display device. [Diagram 5] 1A to 1C are cross-sectional views illustrating one embodiment of a manufacturing method of a light-emitting display device. [Figure 6] 1A to 1C are cross-sectional views illustrating one embodiment of a manufacturing method of a light-emitting display device. [Figure 7] 1A to 1C are cross-sectional views illustrating one embodiment of a manufacturing method of a light-emitting display device. [Figure 8] 1A to 1C are cross-sectional views illustrating one embodiment of a manufacturing method of a light-emitting display device. [Figure 9] 1 is a cross-sectional view illustrating a structure of a light-emitting element. [Figure 10] FIG. [Figure 11] FIG. [Figure 12] FIG. [Figure 13] FIG. 1 is a diagram illustrating an example of a device for viewing 3D video or still images using special glasses that are synchronized with the video on a display device. [Figure 14] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a light-emitting display device. [Figure 15] 1 is a cross-sectional view illustrating a structure of a light-emitting element. [Figure 16] 1A to 1C are diagrams illustrating the structure of an oxide material. [Figure 17] 1A to 1C are diagrams illustrating the structure of an oxide material. [Figure 18]1A to 1C are diagrams illustrating the structure of an oxide material. [Figure 19] 1A to 1C are diagrams illustrating the structure of an oxide material. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and those skilled in the art will recognize that the present invention may be modified in various ways in form and detail. It will be easily understood. In addition, the present invention is not limited to the description of the embodiment shown below. In explaining the configuration of the invention using the drawings, the same symbols are used The numbers are used commonly across different drawings. Also, when referring to similar objects, the hatch pattern is used. Similarly, there are cases where no particular reference numeral is given.

[0020] (Embodiment 1) In this embodiment, a structure example of a pixel portion of a light-emitting display device according to one embodiment of the present invention will be described. vinegar.

[0021] 1A and 1B show an active matrix light-emitting display device to which one embodiment of the present invention is applied. FIG. 1(A) is a plan view of a pixel portion of a light-emitting display device, and FIG. 1(A) is a cross-sectional view taken along line A1-A2 in FIG. 1(A). FIG. 3(A) is a cross-sectional view taken along line A1-A2 in FIG. FIG. 3(A) is an equivalent circuit diagram of a pixel portion of an active matrix light-emitting display device. The EL layer 160 and the second pixel electrode layer (common electrode) 170 are shown in FIGS. Not shown.

[0022] In this specification, the EL layer refers to a layer provided between a pair of electrodes of a light-emitting element. Therefore, the layer containing an organic compound that is a light-emitting material sandwiched between the electrodes is one embodiment of the EL layer. It is.

[0023] This embodiment mode will explain a structure and a manufacturing method of a pixel portion of a light-emitting display device. Therefore, the transistor in this embodiment is the first transistor shown in FIGS. This refers to either or both of the first transistor 151 and the second transistor 152. In addition, the transistor is an n-channel transistor using an oxide semiconductor described later.

[0024] The pixel portion of the active matrix type light-emitting display device shown in FIG. A gate electrode layer 102a, a gate insulating layer 106, a semiconductor layer 108a, a first source electrode layer, and A first transistor 151 including drain electrode layers 112a and 112b and a second gate electrode The electrode layer 102b, the gate insulating layer 106, the semiconductor layer 108a, the second source electrode layer and the drain The second transistor 152 includes first electrode layers 112c and 112d.

[0025] Here, the first gate electrode layer 102a is connected to a gate wiring, and the first source electrode layer and The drain electrode layer 112a is connected to a source-drain wiring, and the first source electrode layer and the drain The first electrode layer 112b is connected to the second gate electrode layer 102b at the first opening 110a. The second source electrode layer and the drain electrode layer 112c are connected to a power supply wiring, and the second The source electrode layer and the drain electrode layer 112d are connected to the first pixel electrode 112a at the third opening 130b. In FIG. 1A, the gate wiring and the first gate electrode a source / drain wiring and one of a first source electrode layer and a first drain electrode layer; a power supply wiring and a second The source electrode layer and the drain electrode layer of each of the two electrodes are integral with each other and are denoted by the same reference numerals. be.

[0026] In addition, although the first transistor 151 is illustrated in FIG. 1 as having a single gate structure, A transistor with a multi-gate structure has a small off-state current. The display characteristics of a light-emitting display device including a transistor can be improved.

[0027] In addition, the second gate electrode layer 102b and the power supply wiring (the second source electrode layer and the drain electrode layer 112c) has an area overlapping the gate insulating layer 106 and the semiconductor layer 108a. In this way, the dielectric layer has a multi-layer structure, so that one Even if a pinhole occurs in the dielectric layer, the pinhole is covered by another dielectric layer, so the capacitance The element 153 can function normally. In addition, the relative dielectric constant of the oxide semiconductor is 14 to 15. 16, when an oxide semiconductor is used for the semiconductor layer 108a, the capacitance of the capacitor 153 The value can be increased.

[0028] A protective insulating layer 114 and a flat insulating layer 115 are provided on the first transistor 151 and the second transistor 152. A smoothed insulating layer 116 is formed, and a portion of the smoothed insulating layer 116 is opened to expose the gate insulating layer 106. A second opening 130a and a part of the second source electrode layer and drain electrode layer 112d are exposed. In addition, the planarization insulating layer 116 is omitted. It can also be done like this.

[0029] The third opening 130b is covered with a part of the first pixel electrode layer 118, and the second opening 130a is covered with a part of the first pixel electrode layer 118. The insulating material that becomes the partition wall 119 is filled in. Here, the partition wall 119 is not shown in FIG. However, the edge of the first pixel electrode layer 118 and the uneven area in the above configuration are not shown. The partition wall 119 is formed so as to cover the first pixel electrode layer 118 and the like. This can prevent the EL layer 160 and the second pixel electrode layer 170 that are formed from the light emitting diode 110 from being broken.

[0030] It is also possible to adopt a configuration in which the capacitance element as shown in FIG. The electrode layer 102c does not overlap the power supply wiring (the second source electrode layer and drain electrode layer 112c). The equivalent circuit of this structure is shown in FIG.

[0031] The material used for the semiconductor layer 108a is preferably an oxide semiconductor. Chemical formula InMO3(ZnO) m Formed by a thin film using a material represented by (m>0) Here, M is one selected from Sn, Zn, Ga, Al, Mn, and Co. or a plurality of metal elements. For example, M is Ga, Ga and Al, Ga and Mn Alternatively, Ga and Co can be used.

[0032] For example, In:Ga:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3) or In:G In-Ga-Zn-O with an atomic ratio of a:Zn=2:2:1 (=2 / 5:2 / 5:1 / 5) In:Sn:Zn oxides or oxides with similar compositions can be used. =1:1:1(=1 / 3:1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3 :1 / 6:1 / 2) or In:Sn:Zn=2:1:5(=1 / 4:1 / 8:5 / 8) ) or oxides with a composition close to that of the In-Sn-Zn-O system. .

[0033] However, the present invention is not limited to these, and can be applied to any semiconductor characteristics (mobility, threshold, variation, etc.) required. In order to obtain the required semiconductor characteristics, the appropriate composition should be used. Carrier concentration, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic bond length, density It is preferable to make the above appropriate.

[0034] For example, high mobility can be obtained relatively easily with In-Sn-Zn-O oxides. However, in the case of In-Ga-Zn-O oxides, the transfer function can be improved by reducing the defect density in the bulk. It can increase mobility.

[0035] For example, the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c(a+b+ c=1), the atomic ratio of the oxide is In:Ga:Zn=A:B:C (A+B+C=1). The oxides of are in the neighborhood of r if a, b, and c are (a-A) 2 +(b-B) 2 +(c― C) 2 ≦r 2 The condition is satisfied. For example, r can be set to 0.05. The same is true for compounds.

[0036] The oxide semiconductor may be single-crystalline or non-single-crystalline. In the latter case, it may be amorphous or polycrystalline. In addition, the structure may include a portion having crystallinity in the amorphous state, or a non-amorphous structure. That's fine too.

[0037] Since it is relatively easy to obtain a flat surface for an amorphous oxide semiconductor, This can reduce interface scattering when fabricating a transistor, and can be achieved relatively easily and with relatively high quality. Therefore, high mobility can be obtained.

[0038] In addition, in a crystalline oxide semiconductor, defects in the bulk can be further reduced, and the surface By improving the flatness of the oxide semiconductor, it is possible to obtain a mobility equal to or higher than that of an oxide semiconductor in an amorphous state. In order to improve the flatness of the surface, it is preferable to form an oxide semiconductor on a flat surface. Specifically, the average surface roughness (Ra) is 1 nm or less, preferably 0.3 nm or less, and more preferably It is preferable to form the surface on a thickness of 0.1 nm or less.

[0039] In addition, Ra is the center line average roughness defined in JIS B0601 that can be applied to the surface. This is a three-dimensional extension of the method, which is based on the principle of averaging the absolute value of the deviation from the reference surface to the specified surface. This can be expressed as the "value obtained by dividing the total number of bits by the number of bits" and is defined by the following formula:

[0040]

number

[0041] In the above, S0 is the measurement surface (coordinates (x1, y1) (x1, y2) (x2, y1 )(x2,y2) is the rectangular area bounded by the four points, and Z0 is It refers to the average height of the measurement surface. Ra is measured by an atomic force microscope (AFM). It can be evaluated using a microscope.

[0042] The transistor using an oxide semiconductor for the semiconductor layer 108a has an extremely small off-state current. The oxide semiconductor has the following characteristics: It is preferable that the oxygen supply is sufficient to make the oxygen highly purified. Specifically, for example, the hydrogen concentration in an oxide semiconductor is 5×10 19 atoms / cm 3 Below, wish Preferably 5 x 1018 atoms / cm 3 Less than or equal to 5×10 17 atoms / cm 3 Note that the hydrogen concentration in the oxide semiconductor is measured by secondary ion mass spectrometry. (SIMS: Secondary Ion Mass Spectrometry) In this way, the hydrogen concentration is sufficiently reduced and the hydrogen is highly purified, and sufficient oxygen is produced. Oxide in which defect levels in the energy gap caused by oxygen vacancies are reduced by supplying oxygen In semiconductors, the carrier density due to donors such as hydrogen is 1×10 12 / cm 3 Less than, desired Or 1×10 11 / cm 3 Less than 1.45×10 10 / cm 3 Less than For example, the off-state current at room temperature (25° C.) (here, unit channel width (1 μm ) is 100zA (1zA (zeptoampere) is 1×10 -21 A) Below is the desired Preferably, the current is 10zA or less. In this way, the i-type (intrinsic) or substantially i-type By using an oxide semiconductor, it is possible to obtain a transistor with excellent off-state current characteristics. can.

[0043] Therefore, when the charge retention characteristic of the pixel is extremely high and there is no capacitance element, or when Even if the area of ​​the storage capacitor is made smaller than that shown in 1(A) and (B), the general flash memory can be used. No problems at frame frequencies below 60Hz or 70Hz. The image can be retained.

[0044] In addition, oxide semiconductors are insensitive to impurities, and the film contains a significant amount of metal impurities. There is no problem with using sodalite, which is inexpensive and contains a large amount of alkali metals such as sodium. It has been pointed out that ash glass can also be used (Kamiya, Nomura, Hosono, "Amorphous Oxide Semiconductors" "Current status of physical properties and device development," Solid State Physics, September 2009, Vol. 44, p. 621 -633) However, this is not an appropriate indication. The alkali metals in oxide semiconductors are The minimum content by secondary ion mass spectrometry is 5×10 sodium (Na). 16 cm - 3 Less than or equal to 1×10 16 cm -3 Less than 1×10, more preferably 15 cm -3 The following is lithium (Li) at 5×10 15 cm -3 Less than or equal to 1×10 15 cm -3 The following potassium (K) is 5×10 15 cm -3 Less than or equal to 1×10 15 cm -3 Below Below.

[0045] Alkali metals and alkaline earth metals are harmful impurities for oxide semiconductors. In particular, among alkali metals, Na is a metal that is highly oxidized when the insulating film in contact with the oxide semiconductor is made of oxide. If so, Na will diffuse into it. + In addition, in the oxide semiconductor, It breaks the oxygen bonds or breaks into the bonds. As a result, the transistor characteristics are deteriorated ( For example, this can cause a normally-on state (a shift of the threshold voltage to the negative side), a decrease in mobility, etc. This problem is particularly serious when hydrogen is present in an oxide semiconductor. This is noticeable when the hydrogen concentration in the oxide semiconductor is sufficiently low. 5×10 19 cm -3 Below, especially 5×10 18 cm -3 If it is less than 1, the alkali metal It is strongly recommended that the concentrations of these elements be set to the values ​​listed above.

[0046] In addition, an i-type or substantially i-type oxide semiconductor has extremely high resistance and is difficult to form a circuit. Therefore, multiple transistors can be formed on the same island-shaped semiconductor layer. Even if multiple transistors are configured, they do not interfere with each other and each transistor can be operated. In this embodiment, two transistors are formed in the same island-shaped semiconductor layer. However, if the semiconductor layer is not left in the capacitance element section, the semiconductor The layers may also be separated.

[0047] In the configuration of FIG. 1B, the first pixel electrode layer 118 is disposed on the side surface of the semiconductor layer 108a. However, as described above, the region is i-type or substantially i-type. Since the oxide semiconductor can be regarded as a substantially insulating material, the first pixel electrode layer 118 and the semiconductor Even if the ends of the layers 108a come into contact with each other, problems such as leakage current do not occur.

[0048] In addition, when an oxide semiconductor is used for the semiconductor layer 108a, as shown in FIGS. As described above, the oxide semiconductor layer may be left on the entire surface of the pixel region. Because it has high resistance and is transparent to visible light, the light emitted from the light-emitting element is Light can be transmitted even on the transistor side.

[0049] The second transistor 152 in this embodiment has a second source electrode layer and a drain electrode The layer 112d is a U-shaped (C-shaped, U-shaped, or horseshoe-shaped) second source electrode layer and a drain electrode layer. The transistor is surrounded by the drain electrode layer 112c. Even if the area of ​​the transistor is small, it is possible to secure a sufficient channel width. It is possible to increase the amount of current that flows when conductive (also called on-current).

[0050] One embodiment of the present invention is to perform etching of the protective insulating layer 114 and the semiconductor film 108 in succession. This has the advantage that the photolithography process can be reduced. Next, referring to Figs. 4 to 7, An example of the manufacturing method will be described in detail.

[0051] Here, the method of manufacturing the transistor section 250 will be mainly described. In this manner, the capacitance element section 260, the wiring intersection section 270, and the FPC connection section 280 may also be formed as necessary. This will be explained in detail.

[0052] First, a first conductive film is formed on a substrate 100 having an insulating surface, and then a first photolithography is performed. The first gate electrode layer 102a and the second gate electrode layer 102b are formed by the roughening process and the etching process. A layer 102b is formed (see FIG. 4(A)).

[0053] The resist mask used in the photolithography process may be formed by an inkjet method. In the inkjet method, no photomask is used, which further reduces the manufacturing cost. The resist mask is peeled off after the etching process. A description of the photolithography process will be omitted.

[0054] Here, the substrate 100 has at least a heat resistance sufficient to withstand subsequent heat treatment. For example, barium borosilicate glass or aluminoborosilicate glass can be used. Glass substrates such as glass, ceramic substrates, quartz substrates, sapphire substrates, etc. can be used. In addition, single crystal semiconductor substrates such as silicon and silicon carbide, polycrystalline semiconductor substrates, Compound semiconductor substrates such as silicon germanium, SOI substrates, etc. can also be used.

[0055] Between the substrate 100 and the first gate electrode layer 102a and the second gate electrode layer 102b, An insulating film may be provided as a base film. The base film prevents diffusion of impurity elements from the substrate 100. It has the function of silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, oxide Forming the film from aluminum, gallium oxide, or aluminum gallium oxide Moreover, the undercoat film is not limited to a single layer, but may be a laminate of the above-mentioned multiple films.

[0056] The first gate electrode layer 102a and the second gate electrode layer 102b are made of molybdenum, titanium, or tantalum. Metallic materials such as tantalum, tungsten, aluminum, copper, neodymium, and scandium, The gate electrode can be formed by sputtering an alloy material mainly composed of these. The electrode layer is not limited to a single layer, but may be a laminate of the above materials. For example, aluminum and molybdenum laminations, aluminum and titanium laminations, copper and molybdenum laminations, or copper and There are also stacked layers of molybdenum on copper.

[0057] Next, a gate insulating layer 1 is formed on the first gate electrode layer 102a and the second gate electrode layer 102b. The gate insulating layer 106 is formed by using a CVD method, a sputtering method, or the like. , silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, Yttrium oxide, gallium oxide, lanthanum oxide, hafnium silicate (HfSi x O y (x>0, y>0)), nitrogen-doped hafnium silicate (HfSiO x N y ( x>0, y>0), nitrogen-doped hafnium aluminate (HfAlO x N y (x >0, y>0), etc., or a mixture of these materials. The gate insulating film can be formed by a plasma CVD method, a sputtering method, or the like. The edge layer 106 is not limited to a single layer, but may be a laminate of the above-mentioned materials. For example, when silicon oxide is used, the thickness is, but is not limited to, 1 nm or more and 100 nm or less. , and preferably 10 nm or more and 50 nm or less.

[0058] The gate insulating layer 106 is made of an insulating material containing the same components as the semiconductor film to be formed later. It is preferable to use such a material because it is possible to maintain a good state of the interface with the semiconductor film. Here, the term "component of the same kind as the semiconductor film" refers to one selected from the constituent elements of the semiconductor film. For example, a semiconductor film of the In-Ga-Zn-O system When the material is an oxide semiconductor, gallium oxide is an insulating material that contains the same components. Examples include Umu.

[0059] In addition, the gate insulating layer 106 can be formed by forming a high-quality insulating layer that is dense and has a high dielectric strength. The high-density plasma CVD using microwaves (for example, frequency 2.45 GHz) is used. It is preferable that the semiconductor layer and the high-quality gate insulating layer are in close contact with each other, thereby reducing the interface state. It is possible.

[0060] In addition, the quality of the gate insulating layer and the interface characteristics with the semiconductor layer are improved by heat treatment after film formation. In any case, the gate insulating layer must have good film quality. Of course, it is preferable to use a material that can reduce the interface state density with the semiconductor layer and form a good interface. .

[0061] In addition, hydrogen, In order to minimize the inclusion of hydroxyl groups and moisture, the gate insulating layer 106 was formed. The substrate 100 is heated in a vacuum in a preheating chamber of a film forming apparatus, and hydrogen, moisture, etc. adsorbed on the substrate 100 are removed. It is preferable to remove impurities from the preheating chamber and evacuate the gas. It is preferable to use a cryopump. This preheating process may be omitted. can.

[0062] Next, a film having a thickness of 2 nm to 200 nm, preferably 5 nm or more, is formed on the gate insulating layer 106. A semiconductor film 108 having a thickness of 30 nm or less is formed (see FIG. 4B).

[0063] It is preferable to use an oxide semiconductor for the semiconductor film 108. It is preferable that the alloy contains at least indium (In) or zinc (Zn). In and Zn are preferably contained in the oxide semiconductor. In addition, gallium (Ga) is added as a stabilizer to reduce the variation in characteristics. It is preferable to have tin (Sn) as a stabilizer. It is also preferable to have hafnium (Hf) as a stabilizer. It is preferable to have aluminum (Al) as a stabilizer.

[0064] Other stabilizers include the lanthanides lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Ho, Erbium, Thulium, Ytterbium, Ru The element may contain one or more of the elements tetraethynyl (Te) and tetraethynyl (Lu).

[0065] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and oxides of binary metals. In-Zn-O oxides, Sn-Zn-O oxides, Al-Zn-O oxides, Zn-Mg-O oxide, Sn-Mg-O oxide, In-Mg-O oxide, In-G aO-based oxides, In-Ga-Zn-O-based oxides (IGZO and (also written as In-Al-Zn-O oxide, In-Sn-Zn-O oxide, Sn- Ga-Zn-O oxide, Al-Ga-Zn-O oxide, Sn-Al-Zn-O oxide In-Hf-Zn-O oxides, In-La-Zn-O oxides, In-Ce-Zn -O oxides, In-Pr-Zn-O oxides, In-Nd-Zn-O oxides, In- Sm-Zn-O oxide, In-Eu-Zn-O oxide, In-Gd-Zn-O oxide In-Tb-Zn-O oxides, In-Dy-Zn-O oxides, In-Ho-Zn -O oxide, In-Er-Zn-O oxide, In-Tm-Zn-O oxide, In- Yb-Zn-O oxides, In-Lu-Zn-O oxides, and oxides of quaternary metals, I n-Sn-Ga-Zn-O oxide, In-Hf-Ga-Zn-O oxide, In-Al -Ga-Zn-O oxide, In-Sn-Al-Zn-O oxide, In-Sn-Hf- Zn-O based oxides and In-Hf-Al-Zn-O based oxides can be used.

[0066] In this case, for example, In-Ga-Zn-O oxide is an oxide having In, Ga, and Zn as main components. The ratio of In, Ga, and Zn does not matter. Metal elements other than Ga and Zn may be included.

[0067] In particular, oxide semiconductors containing indium, oxide semiconductors containing indium and gallium, etc. By using this, a transistor with favorable electrical characteristics can be formed. As the conductor film 108, a film made of an In-Ga-Zn-O oxide is formed by sputtering. do.

[0068] The target used in the sputtering method has a composition ratio of, for example, In2O3:Ga2O 3:ZnO=1:1:1 [molar ratio] oxide target is used. In2O3 An oxide target with a molar ratio of Ga2O3:ZnO=1:1:2 may also be used.

[0069] In addition, when an In-Zn-O oxide is used as the oxide semiconductor, the oxide target used is The composition ratio of the In alloy is In:Zn=50:1-1:2 in atomic ratio (converted to I n2O3:ZnO=25:1 to 1:4), preferably In:Zn=20:1 to 1:1 (m In terms of the ol ratio, In2O3:ZnO=10:1 to 1:2), and more preferably In :Zn=15:1~1.5:1 (converted to molar ratio In2O3:ZnO=15:2 For example, the oxide target used for forming an In-Zn-O-based oxide semiconductor is When the atomic ratio of In:Zn:O=X:Y:Z, Z>1.5X+Y.

[0070] In addition, In-Sn-Zn-O oxide can be called ITZO, and the target used is The composition ratio of In:Sn:Zn is 1:2:2, 2:1:3, 1:1:1, or An oxide target with a ratio of 20:45:35 or 20:45:35 is used.

[0071] The target filling rate is 90% or more and 100% or less, preferably 95% or more and 100% or less. By using a target with a high filling rate, the oxide semiconductor film formed is dense. It is possible to form a membrane.

[0072] The sputtering gas is a rare gas (typically argon), oxygen, or a rare gas and oxygen. The sputtering gas may contain hydrogen, water, hydroxyl or other elements. It is preferable to use a high-purity gas from which impurities such as hydrides have been removed.

[0073] The oxide semiconductor film is preferably formed while the substrate is heated. The substrate is held in the deposition chamber and the substrate temperature is set to 200° C. or more and 450° C. or less to perform deposition. By this, the concentration of impurities in the oxide semiconductor film can be reduced. The upper limit temperature varies depending on the material used for the electrode layer. When using laminated tungsten or copper and tungsten, the temperature should be above 450°C. However, when using a laminate containing aluminum with a low melting point, the upper limit can be set at 3 A temperature of 80°C is preferred.

[0074] In order to remove residual moisture in the deposition chamber, an adsorption type vacuum pump, for example, a cryostat It is preferable to use a pump, an ion pump, or a titanium sublimation pump. The exhaust means may be a turbo molecular pump with a cold trap added. The deposition chamber evacuated using a cryopump contains hydrogen atoms, water, and other chemicals that contain hydrogen atoms. Since the oxide semiconductor film formed in the film formation chamber is exhausted, the oxide semiconductor film formed in the film formation chamber is exhausted. The concentration of impurities contained in the film can be reduced.

[0075] As an example of the deposition conditions, the distance between the substrate and the target is 100 mm, and the pressure is 0.6 Pa. The conditions are: DC power supply 0.5kW, oxygen (oxygen flow rate 100%) atmosphere. In addition, when a pulsed DC power supply is used, the powdery substances (particles, etc.) generated during film formation are reduced. This can reduce the thickness loss (also called the "thinning") and make the film thickness distribution uniform.

[0076] Next, the semiconductor film 108 is dehydrated or dehydrogenated by a first heat treatment. In this case, dehydration or dehydrogenation refers only to the desorption of water or hydrogen molecules. This also includes the elimination of hydrogen atoms, hydroxyl groups, etc.

[0077] The heat treatment is carried out, for example, by placing the workpiece in an electric furnace using a resistance heating element, and heating the workpiece in a nitrogen atmosphere. The heat treatment can be performed at 450° C. for one hour. During this time, the semiconductor film 108 is not exposed to the air. Be sure to prevent water or hydrogen from getting into the fuel.

[0078] Excess hydrogen (including water and hydroxyl groups) is removed by this heat treatment, and the structure of the oxide semiconductor film is The temperature of the heat treatment is 25 The temperature range is from 0°C to 450°C. The heat treatment time is 1 hour if the temperature range is within the above range. However, it is also possible to carry out treatment at a low temperature for a long time or at a high temperature for a short time. The upper limit of the temperature depends on the material used for the gate electrode layer. Therefore, as mentioned above, when using a material containing copper, the upper limit can be set at 450°C. However, when using materials containing aluminum, the upper limit is 380°C.

[0079] The heat treatment device is not limited to an electric furnace, and may be heat conducted from a medium such as a heated gas or heat radiation. For example, a GRTA (Gas Rap id Thermal Anneal) equipment, LRTA (Lamp Rapid The RTA (Rapid Thermal Anneal) equipment ) equipment can be used. The LRTA equipment uses halogen lamps, metal halide lamps, etc. , xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure mercury lamp This is a device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a light bulb. The GRTA device is a device that performs heat treatment using high-temperature gas. The gas used is argon. Inert gases such as rare gases or nitrogen that do not react with the workpiece during heat treatment are used. Used.

[0080] For example, in the first heat treatment, the workpiece is placed in a heated inert gas atmosphere and left for several minutes. After the heating, the workpiece may be taken out of the inert gas atmosphere and subjected to GRTA treatment. GRTA processing allows high-temperature heat treatment in a short time. The present invention can be applied even under temperature conditions exceeding 100°C. During the treatment, inert gas is used instead of oxygen. By performing the first heat treatment in an atmosphere containing oxygen, This is because it is possible to reduce defect levels in the energy gap caused by oxygen vacancies. .

[0081] The inert gas atmosphere is nitrogen or a rare gas (helium, neon, argon, etc.). It is desirable to use an atmosphere containing 1,2-dichloroethane (CO), which is the main component, and does not contain water, hydrogen, etc. For example, nitrogen and rare gases such as helium, neon, and argon introduced into heat treatment equipment Purity should be 6N (99.9999%) or more, preferably 7N (99.99999%) or more ( That is, the impurity concentration is set to 1 ppm or less, preferably 0.1 ppm or less.

[0082] In either case, the first heat treatment reduces impurities and produces an i-type (intrinsic semiconductor) or i-type By forming an oxide semiconductor film that is close to the It can be realized.

[0083] The above-mentioned heat treatment is not limited to this timing, but may be performed after forming the source and drain electrodes or It may be performed after forming the protective insulating film. Moreover, it may be performed not only once but also multiple times.

[0084] Next, a second gate electrode is formed by a second photolithography step and an etching step. layer 102b, and the semiconductor film 108 and the gate insulating layer 102a on the first gate electrode layer 102a. First openings 110a and 110b are formed by opening a part of the substrate 6. 110a is a first source electrode layer and a drain electrode layer 1 of a first transistor 151. 12b and the second gate electrode 102b, and is formed in the FPC connection portion. The first opening 110b is an opening for exposing the first gate electrode layer 102a. (See Figure 4(C)).

[0085] Here, the etching of the semiconductor film 108 and the gate insulating layer 106 is performed by dry etching or Either dry etching or wet etching may be used. Alternatively, both may be used. For example, The etching solution for the semiconductor film 108, which is an oxide semiconductor, is a mixture of phosphoric acid, acetic acid, and nitric acid. A solution containing ITO-07N (manufactured by Kanto Chemical Co., Ltd.) can also be used. The gate insulating layer 106 may be formed using a hydrofluoric acid-based etching solution.

[0086] Next, the second gate electrode layer 102b, the first gate electrode layer 102a, and the semiconductor film 10 On the substrate 8, a source electrode layer and a drain electrode layer of a transistor (a wiring formed from the same layer) are formed. Then, a second conductive film 112 (including a line) is formed (see FIG. 5A).

[0087] The second conductive film 112 may be made of, for example, aluminum, chromium, copper, tantalum, titanium, A metal film containing an element selected from the group consisting of molybdenum and tungsten, or a metal film containing the above-mentioned elements. Metal nitride films (titanium nitride film, molybdenum nitride film, tungsten nitride film) are used as the component. Also, a metal film such as aluminum or copper may be provided on one or both sides of the film. High melting point metal films such as tungsten, molybdenum, and tungsten, or their nitride films (titanium nitride A laminated structure of a tungsten nitride film, a molybdenum nitride film, a tungsten nitride film, etc. may be used. For example, , tungsten and copper stack, tungsten, tungsten nitride, copper, tungsten stack , Molybdenum, Molybdenum nitride, Copper, Molybdenum laminate, Molybdenum, Aluminum, Mo In this embodiment, a laminate of copper on tungsten is used. There are.

[0088] Next, a resist mask is formed on the second conductive film 112 by a third photolithography process. The first source and drain electrode layers 112a are formed and selectively etched. , 112b, and second source and drain electrode layers 112c and 112d are formed. In the capacitance element portion, the second gate is connected via the gate insulating layer 106 and the semiconductor film 108. A power supply wiring (a second source electrode layer and a drain electrode layer 112c) is formed so as to overlap with the source electrode. The FPC connection portion is provided with a conductive layer electrically connected to the first gate electrode layer 102a. A layer 112e is formed (see FIG. 5(B)).

[0089] It is to be noted that the semiconductor film 108 is etched as little as possible when the second conductive film 112 is etched. However, it is preferable to etch only the second conductive film 112. It is difficult to obtain the above condition, and a part of the semiconductor film 108 may be damaged during etching of the second conductive film 112. It may also be etched to have a grooved (recessed) shape.

[0090] Through the above steps, the first transistor 151, the second transistor 152, and the capacitor 15 The transistor is formed by hydrogen, moisture, hydroxyl radicals, or hydrides (hydrogen compounds). In order to obtain a highly purified oxide semiconductor film, impurities such as SiO 2 and SiO 2 are intentionally removed from the semiconductor film 108. Therefore, the transistor has suppressed fluctuations in electrical characteristics. It is electrically stable.

[0091] Next, a protective insulating layer 114 is formed so as to cover the above-described structure formed on the substrate 100 (FIG. 5(C)). The protective insulating layer 114 has a thickness of at least 1 nm. The above-mentioned method is appropriately used to form the conductor 14 while minimizing the inclusion of impurities such as water and hydrogen. In this embodiment, the protective insulating layer 114 is formed by a sputtering method. If hydrogen is contained in the layer 114, the hydrogen may penetrate into the semiconductor film 108 or may be absorbed by the semiconductor film 108. A phenomenon may occur in which hydrogen extracts oxygen from the film 108. When such a phenomenon occurs, The back channel side of the semiconductor film 108 becomes low resistance (n-type), and a parasitic channel is formed. Therefore, the protective insulating layer 114 should be a film that contains as little hydrogen as possible. It is important to make it so.

[0092] The protective insulating layer 114 can be formed by using a PVD method, a CVD method, or the like. Silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, A single layer or a layer containing inorganic insulating materials such as gallium or aluminum gallium oxide is used. It can be formed by laminating layers.

[0093] The protective insulating layer 114 is formed of the same material as the semiconductor film 108, like the gate insulating layer 106. It is preferable to use an insulating material containing a fluorine atom. For example, when the semiconductor film 108 is an In-Ga-Zn-O oxide semiconductor, When made of conductive materials, insulating materials made of the same components are gallium oxide, etc. There is.

[0094] In addition, when the protective insulating layer 114 has a stacked structure, the protective insulating layer 114 may contain the same component as the semiconductor film 108. The product of an insulating film (hereinafter, film a) and a film (hereinafter, film b) containing a material different from the component material of film a It is more preferable to use a layered structure. The film a and the film b are stacked in this order from the semiconductor film 108 side. As a result, the charges are preferentially captured by the charge capture centers at the interface between the films a and b (semiconductor film 10 8 and the film a), charge trapping at the interface of the semiconductor film 108 is sufficiently suppressed. This is because it becomes possible to improve the reliability of the transistor.

[0095] For example, a gallium oxide film and a silicon oxide film are used as the protective insulating layer 114 from the semiconductor film 108 side. It is preferable to use a laminate of a gallium oxide film and a silicon nitride film, or a laminate of a gallium oxide film and a silicon nitride film. do.

[0096] In this embodiment, a silicon oxide film is used for the protective insulating layer 114. The film can be formed by sputtering using a mixture of rare gas, oxygen, or rare gas and oxygen. The substrate temperature during film formation may be from room temperature to 300° C. in this embodiment. The temperature is set to ℃. The target is a silicon oxide target or a silicon target. For example, a silicon target can be used with oxygen as the sputtering gas. Silicon oxide can be formed.

[0097] In addition, when the protective insulating layer 114 is formed, the same as in the case of forming the semiconductor film 108, To remove residual moisture, it is preferable to use an adsorption type vacuum pump (such as a cryopump). In a deposition chamber evacuated using a cryopump, hydrogen atoms, water, and other hydrogen atoms are generated. Since compounds containing atoms and compounds containing carbon atoms are exhausted, the protective insulating layer 1 The concentration of impurities contained in 14 can be reduced. In addition, the concentration of impurities in 14 can be reduced. The exhaust means may be a turbo molecular pump with a cold trap added.

[0098] The sputtering gas used in forming the protective insulating layer 114 may include hydrogen, water, a hydroxyl group, or hydrogen. It is preferable to use a high-purity gas from which impurities such as oxides have been removed.

[0099] A second heat treatment may be performed after the formation of the protective insulating layer 114. For this, the same method as in the first heat treatment described above can be used. The upper limit temperature of the heat treatment depends on the materials used for the gate electrode layer, the source electrode layer, and the drain electrode layer. The electrode layer is made of a metal with a high melting point, such as copper, molybdenum, or tungsten. If the electrode layer is made of aluminum or the like, the upper limit of the temperature can be set to 450°C. If the material contains a metal with a low melting point, the upper limit of the temperature may be 380°C. In addition, heat treatment can be performed in air at 100°C to 200°C for 1 hour to 30 hours. This heat treatment may be performed not only at a constant temperature but also at temperatures from room temperature to 100°C or higher for 20 minutes. The temperature may be raised to 0°C or lower and then lowered to room temperature several times. stomach.

[0100] When heat treatment is performed in a state where the semiconductor film 108 and the protective insulating layer 114 containing oxygen are in contact with each other, Oxygen can be further supplied to the semiconductor film 108 from the protective insulating layer 114 .

[0101] Next, a planarization insulating layer 116 is formed over the protective insulating layer 114 (see FIG. 6A). The insulating layer 116 is made of an organic resin such as acrylic, polyimide, or polyamide, or a siloxane. It is preferable to form the insulating film using a fluorine atom.

[0102] If a photosensitive resin is used as the resin, a photoresist is not required. Since the desired shape can be obtained, the process can be simplified. The cured photosensitive resin can be used as a resist mask.

[0103] In this embodiment, a photosensitive acrylic resin is used for the planarization insulating layer 116, and the planarization insulating layer 116 is formed by exposure (fourth photolithography). After obtaining a shape having an opening by a lithography process, the photosensitive acrylic resin is The protective insulating layer 114 and the semiconductor film 108 are etched as a mask to form a second opening 130a. , a third opening 130b is formed (see FIG. 6(B)).

[0104] The etching may be dry etching or wet etching, or both may be used. The etching gas used in dry etching is a gas containing chlorine (chlorine-based gas, e.g. For example, chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), and carbon tetrachloride. (CCl4, etc.) can be used. IE (Reactive Ion Etching) method and ICP (Inductive Using the inductively coupled plasma (ICP) etching method can be done.

[0105] The second opening 130a is formed by etching the protective insulating layer 114 and the semiconductor film 108. Here, unnecessary regions of the semiconductor film 108 are removed, and a semiconductor layer 108a is formed. Therefore, the process of processing the semiconductor film into islands can be omitted. The number of lithography steps can be reduced.

[0106] The third opening 130b exposes the second source electrode layer and the drain electrode layer below the protective insulating layer 114. Since the conductive layer 112d and the conductive layer 112e act as etching stoppers, the protective insulating layer Only 114 is etched.

[0107] According to the manufacturing process shown in this embodiment, a photoresist is directly applied on the semiconductor layer 108a. In the photoresist peeling and cleaning process, the semiconductor layer 108a Since the substrate is not contaminated, fluctuations in the electrical characteristics of the transistor can be suppressed.

[0108] Next, a third conductive film is formed to cover the third opening 130b. The first transistor 151 and the second transistor 152 have an oxide semiconductor layer 108a. The third conductive film, which is an n-channel type using a conductor and serves as the first pixel electrode layer 118, It is preferable to use a material that can be used as the cathode of the light-emitting element. Specifically, the cathode has a work function Materials with low resistance, such as Ca, Al, CaF, MgAg, and AlLi, can be used. In order to control the light emission direction, a light-transmitting conductive film may be used as the third conductive film. In this case, the material that becomes the cathode may be formed on the transparent conductive film. Examples of the film include indium oxide containing tungsten oxide, Indium zinc oxide, indium oxide with titanium oxide, indium Indium tin oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, Indium tin oxide doped with silicon dioxide. A material consisting of a sheet (one layer of graphite) may also be used.

[0109] Next, a resist mask is formed on the third conductive film by a fifth photolithography process. Then, selective etching is performed to form the first pixel electrode layer 118. The first pixel electrode layer 118 may be formed in the opening. By using an oxide conductive layer, the FPC connection part can be protected from the surface oxidation of the underlying metal conductive layer. It is possible to suppress an increase in contact resistance with the C terminal, thereby improving the reliability of the semiconductor device. can.

[0110] Next, the second opening 130a, the third opening 130b, and the first pixel electrode layer 118 are A partition wall 119 is formed so as to cover the periphery (see FIG. 6(C)).

[0111] Next, although not shown, an EL layer and a second pixel electrode layer are selected on the first pixel electrode layer 118. Selectively form.

[0112] A light-emitting display device can be completed by the manufacturing method including the above steps. Unlike the structure formed by the method described above, in the structure in which the capacitor element 153 is not formed, In the above, the second gate electrode layer 102b is not provided in the region where the capacitance element is to be formed. Good.

[0113] Alternatively, a structure in which the planarization insulating layer 116 is not provided can be used. This structure can be manufactured by the following method. The process up to FIG. 5(C) is the same as the above-mentioned process, and the fourth photolithography process A second opening 120a and a third opening 120b are formed (see FIG. 7(A)).

[0114] Next, a third conductive layer is formed on the protective insulating layer 114 so as to cover at least the third opening 120b. A resist mask is formed on the third conductive film by a fifth photolithography process. Then, the first pixel electrode layer 118 is formed by selectively etching the first The first pixel electrode layer 118 may be formed in a part of the second opening 120a.

[0115] Next, the second opening 120a, the third opening 120b, and the first pixel electrode layer 118 are A partition wall 119 is formed so as to cover the periphery (see FIG. 7(B)).

[0116] Through the above steps, the openings in the protective insulating layer 114 and the unnecessary regions of the semiconductor film 108 are removed. By simultaneously performing the deposition and removal of the photolithography process, a method for manufacturing a light-emitting display device is provided. It is possible.

[0117] Note that this embodiment mode can be freely combined with other embodiment modes.

[0118] (Embodiment 2) In this embodiment, an example of a process that is partially different from that in the first embodiment will be described with reference to FIG. 8, the same reference numerals are used for the same parts as those in FIG. 4, and detailed explanations of the same reference numerals are omitted here. Omitted.

[0119] First, as in the first embodiment, a conductive film is formed on a substrate 100 having an insulating surface. A gate electrode layer 142 is formed by a photolithography process and an etching process. .

[0120] An insulating film serving as a base film may be provided between the substrate 100 and the gate electrode layer. In this embodiment, an undercoat film 101 is provided. The undercoat film 101 is used to remove impurity elements (such as Na) from the substrate 100. ) and prevents the diffusion of silicon oxide, silicon oxynitride, silicon nitride, and halide oxide. A film selected from fluorine, aluminum oxide, gallium oxide, and gallium aluminum oxide In addition, the base film is not limited to a single layer, but may be a laminate of the above-mentioned multiple films. That's fine.

[0121] In this embodiment, the film formation temperature of the semiconductor film to be formed later is 200° C. or more and 450° C. or less. Since the temperature of the heat treatment after the deposition of the gate electrode layer is 200° C. or more and 450° C. or less, The material for 42 is a laminate with copper as the lower layer and molybdenum as the upper layer, or a laminate with copper as the lower layer and A stack of layers is used with tungsten as the top layer.

[0122] Next, in the same manner as in the first embodiment, the gate insulating layer 106 is formed on the gate electrode layer 142 by the CVD method. The film is formed by using a method such as sputtering. A cross-sectional view of the film after going through the steps up to this point is shown in FIG.

[0123] Next, a first oxide semiconductor film having a thickness of 1 nm to 10 nm is formed on the gate insulating layer 106. In this embodiment, a target for an oxide semiconductor (In-Ga-Zn-O-based oxide Semiconductor target (In2O3:Ga2O3:ZnO=1:1:2 [molar ratio]) The distance between the substrate and the target was 170 mm, the substrate temperature was 250°C, and the pressure was 0.4 P. a, DC power supply 0.5 kW, oxygen only, argon only, or argon and oxygen atmosphere A first oxide semiconductor film is formed to a thickness of 5 nm under atmospheric conditions.

[0124] Next, the atmosphere in which the substrate is placed is changed to nitrogen or dry air, and a first heat treatment is performed. The temperature of the first heat treatment is 200° C. or more and 450° C. or less. The time is from 1 hour to 24 hours. Then, a body layer 148a is formed (see FIG. 8(B)).

[0125] Next, a second oxide semiconductor layer having a thickness of more than 10 nm is formed on the first crystalline oxide semiconductor layer 148a. In this embodiment, an In-Ga-Zn-O oxide target (In2 The substrate and the target were The distance between the substrate and the substrate was 170 mm, the substrate temperature was 400°C, the pressure was 0.4 Pa, and the direct current (DC) power supply was 0. The second ion beam was 25 nm thick under 5 kW, oxygen only, argon only, or argon and oxygen atmosphere. An oxide semiconductor film is formed.

[0126] Next, the atmosphere in which the substrate is placed is changed to nitrogen or dry air, and a second heat treatment is performed. The temperature of the second heat treatment is 200° C. or more and 450° C. or less. The time is from 1 hour to 24 hours. Then, a body layer 148b is formed (see FIG. 8(C)).

[0127] The subsequent steps are the same as those in the first embodiment, and include forming the second conductive film 112 and the protective insulating layer 114. The protective insulating layer 114, the first crystalline oxide semiconductor layer 148a, and the second crystalline oxide semiconductor layer 148b are formed. The photoresist mask is used to etch the photoresist semiconductor layer 148b. Eliminate the lithography process.

[0128] Thus, the first transistor 151 and the second transistor 152 shown in FIG. However, when this embodiment is used, The semiconductor layer including the channel formation region of these transistors is made of a first crystalline oxide semiconductor. The first crystalline oxide semiconductor layer 148a and the second crystalline oxide semiconductor layer 148b are stacked. The first crystalline oxide semiconductor layer 148a and the second crystalline oxide semiconductor layer 148b are crystals having a C-axis orientation. It is a crystalline oxide semiconductor.

[0129] The crystalline oxide semiconductor has a c-axis orientation and a triangular shape when viewed from the ab-plane, surface, or interface direction. The metal atoms are arranged in layers or in a hexagonal shape along the c-axis. The oxygen atoms are arranged in layers, and the a-axis and b-axis directions are different on the ab plane (c CAAC: C Axis Aligned Crystal (also called.) is an oxide containing

[0130] Note that CAAC is a crystalline oxide semiconductor layer formed on the first crystalline oxide semiconductor layer 148a and the second crystalline oxide semiconductor layer 148b. The layer is not limited to a multilayer structure like the organic semiconductor layer 148b, and may be a single layer.

[0131] In order to form CAAC, the surface flatness of the base layer must be improved as much as possible by CMP or other methods. It is preferable that the average roughness is equal to or less than that of a thermally oxidized film of silicon. By forming the CAAC on a layer with a high flatness, the crystallinity and This can improve continuity.

[0132] In addition, during film formation, it is preferable to increase the oxygen ratio in the sputtering gas. For example, when using argon and oxygen as sputtering gas, the flow rate ratio of oxygen should be 30% or more. By doing so, the crystallinity of the crystals that compose the CAAC can be improved, and the oxygen vacancies in the film can be eliminated. In addition, by forming the film at a high temperature of 150℃ or higher, the CAA The crystallinity of the crystals constituting C can be further improved.

[0133] In addition, in the heat treatment after the film formation, the film is heated in a nitrogen atmosphere or under reduced pressure, and then the film is heated in an oxygen atmosphere or under reduced pressure. The oxygen in the CAAC is reduced by heating in a nitrogen atmosphere or a mixed atmosphere of nitrogen and oxygen. The temperature of the heat treatment is 450° C., and the oxygen vacancies can be effectively compensated for. It is preferable that the amount is about 100%.

[0134] In a broad sense, oxides containing CAAC are non-single crystals that are not crystalline when viewed from a direction perpendicular to the ab plane. The atomic arrangement is a triangle, a hexagon, an equilateral triangle, or an equilateral hexagon, and is perpendicular to the c-axis direction. From the viewpoint of the direction, it is an acid containing a phase in which metal atoms are arranged in layers, or metal atoms and oxygen atoms are arranged in layers. It refers to a monster.

[0135] CAAC is not a single crystal, but it is not composed of only amorphous matter. AC contains crystallized parts (crystalline parts), but the boundary between one crystalline part and another crystalline part is not clearly defined. Sometimes it is not possible to determine with certainty.

[0136] When oxygen is contained in CAAC, a part of the oxygen may be replaced with nitrogen. The c-axes of the individual crystals that make up the CAAC are aligned in a certain direction (e.g., the substrate surface supporting the CAAC, C The CAAC may be aligned in a direction perpendicular to the surface of the AAC. The normal to the ab plane of the crystal part of the CAAC is in a certain direction (for example, the substrate plane supporting the CAAC, The direction may be perpendicular to the surface of the substrate.

[0137] CAAC can be a conductor, a semiconductor, or an insulator depending on its composition. Also, depending on the composition, it may be transparent or opaque to visible light. To do.

[0138] An example of such a CAAC is a film-like CAAC that is perpendicular to the film surface or the supporting substrate surface. When observed from the direction, a triangular or hexagonal atomic arrangement is observed, and when the cross section of the film is observed, When the metal atoms are mixed, a layered arrangement of metal atoms or metal atoms and oxygen atoms (or nitrogen atoms) is observed. Crystals may also be mentioned.

[0139] An example of a crystal structure contained in CAAC will be described in detail with reference to FIGS. 16 to 18, the vertical direction is the c-axis direction, and the direction perpendicular to the c-axis direction is the The plane that is the boundary between the two is called the ab plane. The upper half and the lower half.

[0140] In Figure 16(A), one hexacoordinate In atom and six tetracoordinate oxygen atoms (hereafter referred to as 4) adjacent to the In atom are shown. The structure shown here has one metal atom and one nearby oxygen atom. The structure shown in Fig. 16(A) is an octahedral structure, but it is easy to For simplicity, the structure is shown in a plan view. There are three O atoms in each group that are 4-coordinated. The small group shown in Figure 16(A) has a zero charge.

[0141] In Figure 16(B), one pentagonal Ga atom and three trigonal oxygen atoms (hereafter referred to as 3 The structure shows a structure having a 4-coordinated O atom and two 4-coordinated O atoms adjacent to Ga. The 3-coordinated O atom is Both exist on the ab plane. There are four of them, one each in the upper and lower halves of Figure 16(B). In addition, since In also has a 5-coordinate structure, the structure shown in Figure 16(B) can be formed. The small group shown in FIG. 16(B) has a charge of 0.

[0142] FIG. 16(C) shows a structure having one tetracoordinate Zn and four tetracoordinate O atoms adjacent to the Zn. The upper half of Figure 16(C) has one tetracoordinate O atom, and the lower half has three tetracoordinate O atoms. Or, in the upper half of Fig. 16(C), there are three 4-coordinate Os, and in the lower half, there is one There may be four-coordinated O. The small group shown in Figure 16(C) has a zero charge.

[0143] FIG. 16(D) shows a structure having one hexacoordinate Sn atom and six tetracoordinate O atoms adjacent to the Sn atom. The upper half of Figure 16(D) has three tetracoordinate O atoms, and the lower half has three tetracoordinate O atoms. The small group shown in Figure 16(D) has a charge of +1.

[0144] Figure 16(E) shows a small group containing two Zn atoms. The upper half of Figure 16(E) shows one Zn atom. The small group shown in Figure 16(E) has four-coordinated O atoms, and one four-coordinated O atom in the lower half. has a charge of -1.

[0145] Here, a collection of multiple small groups is called a medium group, and a collection of multiple medium groups is called a These are called large groups (also called unit cells).

[0146] Here, we will explain the rules for combining these small groups. The upper three O's of the 6-coordinate In have three adjacent In's downward, and the lower three Each O has three In neighbors in the upward direction. One O in the upper half of the five-coordinate Ga is It has one adjacent Ga in the downward direction, and one O in the lower half has one adjacent Ga in the upward direction. One O in the upper half of the 4-coordinated Zn has one neighboring Zn below it, and the three O in the lower half There are three adjacent Zn atoms in the upward direction. Thus, the number of 4-coordinated O atoms in the upward direction of the metal atom and The number of adjacent metal atoms below the O in each group is equal, and similarly, the number of O atoms below the metal atom in each group is equal. The number of adjacent metal atoms above the O is equal to the number of adjacent metal atoms above the O. The sum of the number of adjacent metal atoms in the direction of the metal atom and the number of adjacent metal atoms in the direction above is 4. The sum of the number of 4-coordinated O atoms above the atom and the number of 4-coordinated O atoms below another metal atom When the number of metal atoms is four, two small groups containing metal atoms can be bonded together. For example, , 4 when a 6-coordinate metal atom (In or Sn) is bonded through a 4-coordinate O in the lower half Since there are three coordinated O atoms, it is possible to use a five-coordinated metal atom (Ga or In) or a four-coordinated metal atom. It will bond with one of the electrons (Zn).

[0147] Metal atoms with these coordination numbers are bonded in the c-axis direction via four-coordinate oxygen atoms. In addition, multiple small groups are bonded together so that the total charge of the layer structure is zero. Forms a medium group.

[0148] Figure 17(A) shows a model diagram of the middle group that constitutes the In-Sn-Zn-O system layer structure. Figure 17(B) shows a large group consisting of three medium groups. FIG. 17C shows the atomic arrangement when the layer structure of FIG. 17B is observed from the c-axis direction.

[0149] In FIG. 17(A), for simplicity, the tricoordinate O is omitted, and only the number of the tetracoordinate O is shown. For example, the upper and lower halves of Sn each contain three 4-coordinate O atoms, as shown in the circle. Similarly, in FIG. 17(A), the upper and lower halves of In are Each has one 4-coordinate O atom, which is indicated by the circle 1. Similarly, in Figure 17 In (A), there is one tetracoordinate O in the lower half and three tetracoordinate O in the upper half. Zn with one tetrahedral O atom in the upper half and three tetrahedral O atoms in the lower half. This shows that:

[0150] In FIG. 17(A), the middle group, which is composed of an In-Sn-Zn-O system layer structure, is Sn has three tetracoordinate O atoms in the upper half and three in the lower half, and one tetracoordinate O atom in the upper half. The In is bonded to the In in the upper and lower halves of the Z atom, which has three tetracoordinate O atoms in the upper half. n, and three tetracoordinate O atoms are bonded to the upper half of the Zn via one tetracoordinate O atom in the lower half of the Zn. and In in the lower half, which is bonded to Zn2 with one 4-coordinated O in the upper half. It bonds to a small group of 4-coordinate O atoms in the lower half of this small group. The structure has three O atoms bonded to Sn atoms in the upper and lower halves. Multiple loops are combined to form large groups.

[0151] Here, the charge per bond for the three-coordinated O and four-coordinated O is -0.6, respectively. 67, -0.5. For example, In (6 or 5 coordinates), Zn (4 The charges of Sn (5 or 6 coordinated) are +3, +2, and +4, respectively. Therefore, the small group containing Sn has a charge of +1. Therefore, a layer structure containing Sn is formed. To do this, a charge of -1 is required to cancel out the charge of +1. The structure shown in Figure 1 shows a structure that can take a charge of -1. As shown in Figure 6(E), a small group containing two Zn atoms is included. For example, Sn-containing If there is one small group with two Zn atoms per small group, the charges are cancelled out. Therefore, the total charge of the layer structure can be set to zero.

[0152] Specifically, the large group shown in FIG. 17(B) is repeated to form the In-Sn-Zn In-Sn-ZnO crystals (In2SnZn3O8) can be obtained. -The layered structure of the Zn-O system is In2SnZn2O7(ZnO) m (m is 0 or a natural number.) This can be expressed by the composition formula:

[0153] In addition, there are oxides of four-component metals, such as In-Sn-Ga-Zn-O oxides. In-Ga-Zn-O oxide (also written as IGZO), which is an oxide of a ternary metal. , In-Al-Zn-O oxides, Sn-Ga-Zn-O oxides, Al-Ga-Zn- O-based oxides, Sn-Al-Zn-O-based oxides, In-Hf-Zn-O-based oxides, In- La-Zn-O oxide, In-Ce-Zn-O oxide, In-Pr-Zn-O oxide In-Nd-Zn-O oxides, In-Sm-Zn-O oxides, In-Eu-Zn -O oxide, In-Gd-Zn-O oxide, In-Tb-Zn-O oxide, In- Dy-Zn-O oxide, In-Ho-Zn-O oxide, In-Er-Zn-O oxide In-Tm-Zn-O oxides, In-Yb-Zn-O oxides, In-Lu-Zn -O oxides, and binary metal oxides such as In-Zn-O oxides and Sn-Zn-O oxides. Oxides, Al-Zn-O oxides, Zn-Mg-O oxides, Sn-Mg-O oxides, The same applies to the case where In-Mg-O based oxides or In-Ga-O based oxides are used.

[0154] For example, Figure 18(A) shows a model of the middle group consisting of an In-Ga-Zn-O layer structure. A diagram of the rule is shown.

[0155] In FIG. 18(A), the middle group, which is made up of an In-Ga-Zn-O-based layer structure, is In the upper half and lower half, there are three tetracoordinate O atoms, and in the lower half, there is one tetracoordinate O atom. It bonds to Zn at the bottom of the Zn atom, and one tetracoordinate O atom is bonded to the Zn atom via the three tetracoordinate O atoms in the bottom half of the Zn atom. It bonds to Ga in the upper and lower halves, respectively, and is bonded to one tetracoordinate O in the lower half of the Ga. The structure is such that three 4-coordinate O atoms are bonded to In atoms in the upper and lower halves. These medium groups combine to form large groups.

[0156] Figure 18(B) shows a large group consisting of three medium groups. 18(B) shows the atomic arrangement when the layer structure of FIG. 18(B) is observed from the c-axis direction.

[0157] Here, the charges of In (6 or 5 coordinates), Zn (4 coordinates), and Ga (5 coordinates) are Since the valence numbers are +3, +2, and +3, respectively, the small group containing either In, Zn, or Ga is , the charge is 0. Therefore, if these small groups are combined, the combination of the medium groups The total charge will always be zero.

[0158] The middle group, which is made up of an In-Ga-Zn-O-based layer structure, is shown in FIG. Not limited to the middle group, large-scale combination of middle groups with different arrangements of In, Ga, and Zn Groups are also possible.

[0159] Specifically, the large group shown in FIG. 18(B) is repeated to form an In-Ga-Zn In-Ga-Zn-O crystals can be obtained. The resulting In-Ga-Zn-O layer structure is InGaO3(ZnO) n (n is a natural number.)

[0160] In the case of n=1 (InGaZnO4), for example, the crystal structure shown in FIG. 19(A) can be obtained. In the crystal structure shown in FIG. 19(A), as explained in FIG. 16(B), Ga and Since Ga and In have a 5-coordinate structure, a structure in which Ga is replaced by In is also possible.

[0161] In the case of n=2 (InGaZn2O5), for example, the crystal structure shown in FIG. 19(B) In the crystal structure shown in FIG. 19(B), as explained in FIG. Since Ga and In have five-coordinate groups, a structure in which Ga is replaced by In is also possible.

[0162] By using the above-mentioned CAAC in a transistor, the 2) The change in the threshold voltage of the transistor during a stress test can be reduced.

[0163] This embodiment mode can be freely combined with other embodiment modes.

[0164] (Embodiment 3) In this embodiment, an example of a light-emitting display device according to one embodiment of the present invention will be described. As the display element, a light-emitting element using electroluminescence is used here. Light-emitting elements that utilize electroluminescence are made of organic or inorganic light-emitting materials. Generally, the former is an organic EL element, and the latter is an inorganic EL element. It's called a child.

[0165] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into layers containing light-emitting organic compounds, causing a current to flow. The rears (electrons and holes) recombine to form an excited state in the light-emitting organic compound. When the excited state returns to the ground state, light is emitted. Such a light-emitting element is called a current-excitation type light-emitting element.

[0166] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements according to their element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor reaction that utilizes the donor and acceptor levels. Thin-film inorganic EL elements are made by sandwiching a light-emitting layer between dielectric layers. The structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0167] The light-emitting display device described in this embodiment has the structure of the pixel portion described in Embodiment 1. The semiconductor device includes a substrate 100, a first transistor 151, a second transistor 152, and a protection An insulating layer 114, a planarizing insulating layer 116, a partition wall 119, and a first pixel electrode used in a light-emitting element The first pixel electrode layer 118 has a first insulating layer 118 (see FIGS. 1A and 1B). The L layer has a second pixel electrode layer.

[0168] In this embodiment, the first transistor 151 and the second transistor 152 of the pixel are n-channel transistors. Since the LCD is a panel type LCD, it is preferable to use a cathode as the first pixel electrode layer 118. For the cathode, materials with small work functions, such as Ca, Al, CaF, MgAg, AlLi etc. can be used.

[0169] The partition wall 119 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. An opening is formed on the first pixel electrode layer 118 using a photosensitive material, and the side wall of the opening It is preferable that the inclined surface is formed so as to have a continuous curvature.

[0170] The EL layer may be composed of a single layer or a plurality of layers may be laminated. It doesn't matter whether they are there or not.

[0171] The second pixel electrode layer, which serves as an anode, is formed to cover the EL layer. Indium oxide containing tungsten oxide, Indium zinc oxide containing tungsten oxide Indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium Indium tin oxide (ITO), indium zinc oxide, and silicon oxide are added. A conductive material having light transmitting properties such as indium tin oxide can be used. A material consisting of up to 10 graphene sheets (one layer of graphite) may also be used. In addition to the above-mentioned transparent conductive film, a titanium nitride film or a titanium film may be used. The electrode layer 118, the EL layer, and the second pixel electrode layer are overlapped to form a light-emitting element. After this, the light emitting element is covered with a second electrode to prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light emitting element. A protective film may be formed on the electrode layer and the partition wall 119. The protective film may be a silicon nitride film, a nitriding oxide film, or the like. Silicon nitride films, DLC films, etc. can be formed.

[0172] In addition, a protective film (lamination) with high airtightness and low outgassing is used to prevent exposure to the outside air. It is possible to package (enclose) the product using a cover material (film, UV-curable resin film, etc.) preferable.

[0173] Next, the configuration of the light-emitting element will be described with reference to FIGS. 9(A), (B), and (C) show the cross-sectional structure of A2-A3 in FIG. 1(A) with the EL layer and the second The pixel electrode layer and the like are also shown in the figure.

[0174] The light emitting element only needs to have at least one of the anode and cathode transparent in order to extract light. Then, a transistor and a light emitting element are formed on the substrate, and light is emitted from the surface opposite the substrate. The top emission is from the top surface, the bottom emission is from the surface on the substrate side, and the bottom emission is from the surface on the substrate side and the opposite side to the substrate. There is a light-emitting element having a dual-side emission structure in which light is emitted from both sides. The present invention can be applied to any light emitting element with any emission structure.

[0175] A light emitting element having a top emission structure will be described with reference to FIG.

[0176] In FIG. 9A, the second transistor 152 is an n-channel transistor, and the light emitting element 7002 emits light. FIG. 9(A) shows a cross-sectional view of a pixel in the case where the light emitted from the pixel is emitted toward the anode 7005 side. The cathode 7003 of the element 7002 and the second transistor 152 are electrically connected to each other. A light-emitting layer 7004 and an anode 7005 are laminated in this order on the cathode 7003. Various materials can be used as long as the conductive film has a small reflectance function and reflects light. For example, Ca, Al, MgAg, AlLi, etc. are preferable. It can be composed of several layers or composed of several layers stacked together. When the layer is made up of a plurality of layers, an electron injection layer, an electron transport layer, a light emitting layer, and a The hole transport layer and the hole injection layer are laminated in this order. Note that it is not necessary to provide all of these layers. The anode 7005 is formed using a light-transmitting conductive material, for example, tungsten oxide. Indium oxide containing tungsten oxide, indium zinc oxide containing titanium oxide Indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter (denoted as ITO), indium zinc oxide, and indium tin oxide doped with silicon oxide. A light-transmitting conductive film such as a graphene sheet having one to ten sheets may be used. (one layer of graphite) may be used.

[0177] The region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 constitutes the light-emitting element 7002. In the case of the pixel shown in FIG. 9A, light emitted from the light emitting element 7002 is The light is emitted toward the anode 7005 as shown in FIG.

[0178] Next, a light emitting element having a bottom emission structure will be described with reference to FIG. The transistor 152 in FIG. 2 is an n-channel type, and the light emitted from the light emitting element 7012 is incident on the cathode 7 FIG. 9B is a cross-sectional view of a pixel in the case where light is emitted to the 013 side. A light-transmitting conductive film 7017 electrically connected to the light-emitting element 7012 is formed on the light-transmitting conductive film 7017. A cathode 7013 is formed, and a light-emitting layer 7014 and an anode 7015 are stacked in this order on the cathode 7013. In addition, when the anode 7015 is transparent, a light-reflecting layer is provided so as to cover the anode. A shielding film 7016 for reflecting or shielding light may be formed on the cathode 7013. As in the case of (A), various conductive materials with small work functions can be used. However, the thickness of the film should be such that it transmits light (preferably 5 nm to 30 nm). For example, an aluminum film having a thickness of 20 nm is used as the cathode 7013. The light-emitting layer 7014 is composed of a single layer, as in FIG. The anode 7015 may be a single layer or a laminate of multiple layers. Although it is not necessary for the material to transmit light, the material may be formed using a conductive material having light transmitting properties, as in FIG. 9(A). The shielding film 7016 can be made of, for example, a light-reflecting metal. However, the material is not limited to a metal film, and for example, a resin to which a black pigment is added may be used.

[0179] The region where the light-emitting layer 7014 is sandwiched between the cathode 7013 and the anode 7015 is the light-emitting element 7012. In the case of the pixel shown in FIG. 9B, the light emitted from the light emitting element 7012 is The light is emitted toward the cathode 7013 as indicated by the arrow.

[0180] Next, a light emitting element having a dual emission structure will be described with reference to FIG. , on a light-transmitting conductive film 7027 electrically connected to the second transistor 152, A cathode 7023 of the light-emitting element 7022 is formed, and a light-emitting layer 7024 is formed on the cathode 7023. The anode 7025 is laminated in order. The cathode 7023 is a workpiece, similar to the case of FIG. Various conductive materials with small functions can be used. However, the film thickness must be For example, an aluminum film having a thickness of 20 nm is used as the cathode 702. 3. The light-emitting layer 7024 can be a single layer, as in FIG. The film may be constructed by laminating a plurality of layers. The electrode 7025 may be formed using a light-transmitting conductive material, as in FIG. can.

[0181] The overlapping portion of the cathode 7023, the light-emitting layer 7024, and the anode 7025 constitutes the light-emitting element 70. In the case of the pixel shown in FIG. 9C, the light emitted from the light-emitting element 7022 is , and is emitted toward both the anode 7025 side and the cathode 7023 side as indicated by the arrows.

[0182] Although the organic EL element has been described as the light-emitting element here, inorganic EL elements can also be used as the light-emitting element. It is also possible to provide an L element.

[0183] In addition, the semiconductor layer 10 is formed on the entire surface of the pixel region shown in FIGS. 14(A) and 14(B) described in the first embodiment. Even in the case where 8a is left, the light emitting element can be configured in the same manner as in FIG. The structure of the light-emitting element is shown in Fig. 15(A), (B), and (C). Fig. 15(A) is the same as Fig. 9(A). The same top-injection structure, Fig. 15(B) is the same bottom-injection structure as Fig. 9(B), Fig. 15(C) is the same bottom-injection structure as Fig. 9 The double-sided injection structure is the same as that of (C), and the details of each are shown in Figs. 9(A), (B), and (C) above. The same as the explanation of (1) above. Note that the transmission of light toward the lower surface in the configurations of (B) and (C) of FIG. This is realized by using an oxide semiconductor layer having a property of transmitting visible light as the semiconductor layer 108a. It can be realized.

[0184] Note that the light-emitting display device described in this embodiment mode is not limited to the structure shown in FIG. However, various modifications based on the technical concept of the present invention are possible.

[0185] This embodiment mode can be freely combined with other embodiment modes.

[0186] (Embodiment 4) The light-emitting display device according to one embodiment of the present invention can be applied to various electronic devices (including game machines). The electronic device can be, for example, a television device (television or television (also called television receivers), computer monitors, digital cameras and digital video Cameras, digital photo frames, mobile phones (also called mobile phones or mobile phone devices) (hereinafter referred to as "computer games"), portable game machines, personal digital assistants, audio playback devices, large game machines such as pachinko machines etc.

[0187] FIG. 10A shows an example of a television device. The television device 9600 includes: A display unit 9603 is incorporated in a housing 9601. The display unit 9603 displays images. In this embodiment, the housing 9601 is supported by a stand 9605. The figure shows a configuration in which

[0188] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. This can be done by a remote controller 9610. The channel and volume can be controlled by the operation keys 9609. 3. The remote controller 9610 can also be used to control the image displayed on the A display unit 9607 for displaying information output from the remote controller is provided. This is also fine.

[0189] The television device 9600 includes a receiver and a modem. It can receive more general television broadcasts, and can also be connected to a modem via wired or wireless connection. By connecting to a network, communication can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0190] FIG. 10B shows an example of a digital photo frame. In the frame 9700, a display unit 9703 is incorporated in a housing 9701. 3 is capable of displaying various images, for example images taken with a digital camera. By displaying data, it can function just like a normal photo frame.

[0191] The Digital Photo Frame 9700 is equipped with an operation unit, external connection terminals (USB terminal, US A terminal that can be connected to various cables such as B cable, etc., and a recording medium insertion section, etc. These components may be installed on the same surface as the display unit, but they may be installed on the side or back. It is preferable to have a digital photo frame with a built-in memory card because it improves the design. A memory that stores image data taken with a digital camera is inserted into the body insertion section to store the image data. The captured image data can be displayed on the display portion 9703 .

[0192] The digital photo frame 9700 may also be configured to transmit and receive information wirelessly. It is also possible to wirelessly import and display desired image data.

[0193] FIG. 11(A) shows a portable gaming machine, which is composed of two housings, a housing 9881 and a housing 9891. The housing 9881 is connected to a connector 9893 so as to be openable and closable. A display unit 9883 is incorporated in the housing 9891. The portable gaming machine shown in FIG. 11(A) also includes a speaker unit 9884 and a recording medium insertion unit 988. 6, LED lamp 9890, input means (operation keys 9885, connection terminals 9887, sensors 9 888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, Chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration 9889) equipped with a microphone, etc. Of course, the configuration of the portable gaming machine is not limited to the above, and other accessories may be used as appropriate. The portable game machine shown in FIG. 11(A) is a game machine having a recording medium. The function of reading the recorded program or data and displaying it on the display unit, and other portable It has a function of sharing information with the gaming machine by wireless communication. The functions of the gaming machine are not limited to these, and the gaming machine may have a variety of functions.

[0194] FIG. 11B shows an example of a slot machine, which is a large-scale gaming machine. The slot machine 900 includes a display unit 9903 built into a housing 9901. 900 also includes other operating means such as a start lever and stop switch, a coin slot, Of course, the configuration of the slot machine 9900 is not limited to the above. The above is not limited to the above, and other auxiliary equipment may be provided as appropriate.

[0195] FIG. 12A shows an example of a mobile phone. The mobile phone 1000 has a housing 1001. In addition to the display unit 1002, the operation buttons 1003, the external connection port 1004, It is equipped with a speaker 1005, a microphone 1006, etc.

[0196] The mobile phone 1000 shown in FIG. 12A displays information by touching a display unit 1002 with a finger or the like. You can also make calls, send emails, and perform other operations. This can be done by touching the display portion 1002 with a finger or the like.

[0197] The screen of the display unit 1002 has three main modes. The first is a display mode that is mainly used for displaying images. The first mode is a display mode, the second is an input mode for inputting information such as characters, and the third mode is a display mode. This is a display + input mode that combines the display mode and the input mode.

[0198] For example, when making a call or composing an e-mail, the display unit 1002 is used for inputting characters. The main character input mode is to input characters displayed on the screen. It is preferable to display a keyboard or number buttons on most of the screen of the display unit 1002. I wish.

[0199] In addition, a sensor for detecting tilt, such as a gyro or an acceleration sensor, is installed inside the mobile phone 1000. By providing a detection device having the above configuration, the orientation of the mobile phone 1000 (portrait or landscape) can be determined and the display The screen display of the display unit 1002 can be automatically switched.

[0200] The screen mode can be changed by touching the display unit 1002 or by operating the housing 1001. This is done by operating the button 1003. Also, depending on the type of image displayed on the display unit 1002, For example, the image signal to be displayed on the display unit is a moving image. If it is data, the mode is switched to display mode, and if it is text data, the mode is switched to input mode.

[0201] In the input mode, the optical sensor of the display unit 1002 detects a signal and displays If there is no input by touch operation of the part 1002 for a certain period of time, the screen mode is changed to the input mode. Alternatively, the display mode may be switched from the normal mode to the display mode.

[0202] The display unit 1002 can also function as an image sensor. By touching the palm or fingers to the sensor 02, the palm print, fingerprint, etc. can be captured and identity authentication can be performed. In addition, the display unit may be equipped with a backlight that emits near-infrared light or a sensor that emits near-infrared light. By using a scanning light source, it is also possible to image finger veins, palm veins, etc.

[0203] FIG. 12B shows an example of an electronic book. For example, an electronic book 2700 has a housing 27 The device is made up of two housings, housing 2701 and housing 2703. 3 are connected by a shaft portion 2711, and opening and closing operations are performed around the shaft portion 2711. With this configuration, it becomes possible to operate like a paper book.

[0204] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a text is displayed on the right display unit (display unit 2705 in FIG. 12B) and An image can be displayed on the display portion (the display portion 2707 in FIG. 12B).

[0205] FIG. 12B shows an example in which an operating unit and the like are provided in the housing 2701. For example, In the housing 2701, a power switch 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. A keyboard, a pointing device, etc. may be provided on the same surface as the display. , the back or side of the housing has external connection terminals (earphone terminal, USB terminal, or AC adapter Terminals for connecting various cables such as printers and USB cables, a recording medium insertion port, etc. Furthermore, the electronic book 2700 may have a function as an electronic dictionary. It may be configured such that

[0206] The electronic book 2700 may be configured to transmit and receive information wirelessly. The desired book data can be purchased and downloaded from the electronic book server. is also possible.

[0207] This embodiment mode can be freely combined with other embodiment modes.

[0208] (Embodiment 5) In this embodiment, a light-emitting display device that switches between a left-eye image and a right-eye image at high speed is used. The user can view 3D images, which are either moving or still images, using special glasses that are synchronized with the image on the display device. An example of this is shown in FIG.

[0209] FIG. 13A shows a light-emitting display device 3711 and a dedicated eyeglass body 3701 connected by a cable 3703. The external view of the connected glasses is shown. The dedicated glasses body 3701 has a left eye panel 3702a and a right eye panel 3702b. The shutters on the eye panel 3702b alternately open and close to allow the user to The image on the light-emitting display device 3711 can be recognized as 3D.

[0210] In addition, the block diagram of the main configuration of the light-emitting display device 3711 and the dedicated eyeglass body 3701 is shown. The diagram is shown in FIG.

[0211] The light-emitting display device 3711 shown in FIG. 13B includes a display control circuit 3716, a display portion 3717, A timing generator 3713, a source line side driving circuit 3718, an external operation means 3722 and a gate The driver circuit 3719 is connected to the port line side. The output signal is varied according to the operation.

[0212] The timing generator 3713 generates a start pulse signal and generates the left eye image signal. A signal for synchronizing the image for the right eye with the shutter of the left-eye panel 3702a. The signal generator 3703 generates a signal for synchronizing with the shutter of the display panel 3702b.

[0213] A left-eye image synchronization signal 3731a is input to a display control circuit 3716 and displayed on a display unit 3717. At the same time, a synchronization signal 3730a that opens the shutter of the left eye panel 3702a is sent to the left A sync signal 3731b for the right eye image is input to the display control circuit 3702a. The image is input to a path 3716 and displayed on a display unit 3717, and at the same time, the signal on the right-eye panel 3702b is A synchronization signal 3730b that opens the shutter is input to the right eye panel 3702b.

[0214] In addition, in order to switch between the left eye image and the right eye image at high speed, the light emitting display device 3711 is, for example, For example, it is preferable to use a display panel that operates at a frame frequency of 120 Hz or 240 Hz. It is recommended to operate the display at high speeds of 120Hz or 240Hz. Light-emitting display panels using fast organic EL elements are suitable as display devices for viewing 3D images. In addition, in order to operate at high speeds at frame frequencies of 120Hz or 240Hz, the switches The switching element uses oxide semiconductors that have higher mobility than transistors using amorphous silicon. A transistor using a conductive material in the active layer is suitable.

[0215] This embodiment mode can be freely combined with other embodiment modes. [Explanation of symbols]

[0216] 100 Substrates 101 Base film 102a first gate electrode layer 102b second gate electrode layer 102c second gate electrode layer 106 Gate Insulation Layer 108 Semiconductor film 108a Semiconductor layer 110a First opening 110b First opening 112 Second conductive film 112a source electrode layer and drain electrode layer 112b source electrode layer and drain electrode layer 112c source electrode layer and drain electrode layer 112d source electrode layer and drain electrode layer 112e conductive layer 114 Protective Insulation Layer 116 Planarizing Insulating Layer 118 Pixel electrode layer 119 Bulkhead 120a Second opening 120b Third opening 130a Second opening 130b Third opening 142 Gate electrode layer 148a Crystalline oxide semiconductor layer 148b Crystalline oxide semiconductor layer 151 First Transistor 152 Second Transistor 153 Capacitive element 160 EL layer 170 Second pixel electrode layer (common electrode) 250 Transistor section 260 Capacitive element section 270 Wire intersection 280 FPC connection part 1000 Mobile Phones 1001 Case 1002 Display section 1003 Operation button 1004 External connection port 1005 Speaker 1006 Microphone 2700 e-books 2701 Case 2703 Case 2705 ​​Display section 2707 Display section 2711 Shaft 2721 Power Switch 2723 Operation key 2725 Speaker 3701 Glasses body 3703 Cable 3702a Left eye panel 3702b Right eye panel 3711 Light-emitting display devices 3713 Timing Generator 3716 Display control circuit 3717 Display section 3718 Source line side driver circuit 3719 Gate line side driving circuit 3722 External operation means 3730a Sync signal 3730b sync signal 3731a sync signal 3731b Sync signal 7002 Light emitting element 7003 Cathode 7004 Light-emitting layer 7005 Anode 7012 Light emitting element 7013 Cathode 7014 Light-emitting layer 7015 Anode 7016 Shielding membrane 7017 Conductive film 7022 Light emitting element 7023 Cathode 7024 Light-emitting layer 7025 Anode 7027 Conductive film 9600 Television Equipment 9601 Case 9603 Display section 9605 Stand 9607 Display section 9609 Operation key 9610 Remote Controller 9700 Digital Photo Frame 9701 Case 9703 Display section 9881 Case 9882 Display section 9883 Display section 9884 Speaker section 9885 Operation key 9886 Recording medium insertion section 9887 Connection terminal 9888 Sensor 9889 Microphone 9890 LED Lamp 9891 Case 9893 Connection section 9900 Slot Machine 9901 Case 9903 Display section

Claims

1. A pixel includes a first transistor, a second transistor, and a capacitor, one of a source electrode and a drain electrode of the first transistor is electrically connected to a gate electrode of the second transistor; a gate electrode of the second transistor is electrically connected to one electrode of the capacitance element, a semiconductor layer having a channel formation region of the first transistor and a channel formation region of the second transistor; a first conductive layer overlapping the semiconductor layer and having a function as a gate electrode of the second transistor and a function as one electrode of the capacitor; a second conductive layer having a region in contact with the semiconductor layer and functioning as one of a source electrode and a drain electrode of the first transistor; a first wiring having a function of inputting a signal to a gate electrode of the first transistor; a second wiring having a region intersecting the first wiring and having a function of inputting a signal to the other of the source electrode and the drain electrode of the first transistor; the second conductive layer has a region in contact with an upper surface of the first conductive layer; a channel length of the second transistor is greater than a channel length of the first transistor; the second wiring does not have a region overlapping with a channel formation region of the second transistor.

2. A pixel includes a first transistor, a second transistor, and a capacitor, one of a source electrode and a drain electrode of the first transistor is electrically connected to a gate electrode of the second transistor; a gate electrode of the second transistor is electrically connected to one electrode of the capacitance element, a semiconductor layer having a channel formation region of the first transistor and a channel formation region of the second transistor; a first conductive layer overlapping the semiconductor layer and having a function as a gate electrode of the second transistor and a function as one electrode of the capacitor; a second conductive layer having a region in contact with the semiconductor layer and functioning as one of a source electrode and a drain electrode of the first transistor; a first wiring having a function of inputting a signal to a gate electrode of the first transistor; a second wiring having a region intersecting the first wiring and having a function of inputting a signal to the other of the source electrode and the drain electrode of the first transistor; the second conductive layer has a region in contact with an upper surface of the first conductive layer; a channel length of the second transistor is greater than a channel length of the first transistor; the second wiring does not have a region overlapping with a channel formation region of the second transistor; a channel formation region of the first transistor has a channel length direction in one direction; The display device, wherein the channel formation region of the second transistor has channel formation regions in a plurality of directions.

3. A pixel includes a first transistor, a second transistor, and a capacitance element, one of a source electrode and a drain electrode of the first transistor is electrically connected to a gate electrode of the second transistor; a gate electrode of the second transistor is electrically connected to one electrode of the capacitance element, a semiconductor layer having a channel formation region of the first transistor and a channel formation region of the second transistor; a first conductive layer overlapping the semiconductor layer and having a function as a gate electrode of the second transistor and a function as one electrode of the capacitor; a second conductive layer having a region in contact with the semiconductor layer and functioning as one of a source electrode and a drain electrode of the first transistor; a first wiring having a function of inputting a signal to a gate electrode of the first transistor; a second wiring having a region intersecting the first wiring and having a function of inputting a signal to the other of the source electrode and the drain electrode of the first transistor; the second conductive layer has a region in contact with an upper surface of the first conductive layer; a channel length of the second transistor is greater than a channel length of the first transistor; the second wiring does not have a region overlapping with a channel formation region of the second transistor; a third wiring having a function as the other electrode of the capacitance element; the third wiring has a region extending in a direction intersecting a channel length direction of the first transistor.

4. A pixel includes a first transistor, a second transistor, and a capacitance element, one of a source electrode and a drain electrode of the first transistor is electrically connected to a gate electrode of the second transistor; a gate electrode of the second transistor is electrically connected to one electrode of the capacitance element, a semiconductor layer having a channel formation region of the first transistor and a channel formation region of the second transistor; a first conductive layer overlapping the semiconductor layer and having a function as a gate electrode of the second transistor and a function as one electrode of the capacitor; a second conductive layer having a region in contact with the semiconductor layer and functioning as one of a source electrode and a drain electrode of the first transistor; a first wiring having a function of inputting a signal to a gate electrode of the first transistor; a second wiring having a region intersecting the first wiring and having a function of inputting a signal to the other of the source electrode and the drain electrode of the first transistor; the second conductive layer has a region in contact with an upper surface of the first conductive layer; a channel length of the second transistor is greater than a channel length of the first transistor; the second wiring does not have a region overlapping with a channel formation region of the second transistor; a channel formation region of the first transistor has a channel length direction in one direction; the second transistor has a channel formation region in a plurality of directions; a third wiring having a function as the other electrode of the capacitance element; the third wiring has a region extending in a direction intersecting a channel length direction of the first transistor.

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