Solid-state imaging device, manufacturing method thereof, and electronic device

Abstract

To provide a solid-state imaging device, a manufacturing method thereof, and an electronic device that can obtain a large signal integration charge amount and stable optical sensitivity during signal integration without requiring cooling and without a decrease in gain, and can also realize a lower interface bandwidth.SOLUTION: A pixel 200 is formed by a photoelectric conversion film 210 that converts light into a photo-generated current, and a semiconductor pixel circuit 220. The photoelectric conversion film 210 and the semiconductor pixel circuit 220 are stacked and electrically coupled within the pixel 200, and the photoelectric conversion film 210 has sensitivity to infrared (NIR). The semiconductor pixel circuit 220 is configured to include a pixel analog circuit 230 that detects the photo-generated current, a sample and hold circuit 240, an ADC 250, an in-pixel logic 260, a digital memory 270, and the like.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a solid-state imaging device, a method for manufacturing a solid-state imaging device, and an electronic device. [Background technology]

[0002] 2. Description of the Related Art Complementary Metal Oxide Semiconductor (CMOS) image sensors are in practical use as solid-state imaging devices (image sensors) that use photoelectric conversion elements that detect light and generate electric charges. CMOS image sensors are widely used as part of various electronic devices, such as digital cameras, video cameras, surveillance cameras, medical endoscopes, personal computers (PCs), and portable terminal devices (mobile devices) such as mobile phones.

[0003] CMOS image sensors have a photodiode (photoelectric conversion element) and a floating diffusion (FD) amplifier with a floating diffusion layer for each pixel, and the mainstream readout method is the column-parallel output type, which selects a row in the pixel array and reads out the pixels simultaneously in the column direction.

[0004] Incidentally, the pixel configuration of a solid-state imaging device (CMOS image sensor) can be exemplified by a basic pixel having a four-transistor (4Tr) configuration in which, for one photodiode (photoelectric conversion element), there is a transfer transistor as a transfer element, a reset transistor as a reset element, a source follower transistor as a source follower element, and a selection transistor as a selection element.

[0005] The transfer transistor is held in a non-conductive state during the charge accumulation period of the photodiode, and during the transfer period in which the accumulated charge of the photodiode is transferred to the floating diffusion FD, a drive signal is applied to the gate to hold the transfer transistor in a conductive state, and the transfer transistor transfers the charge photoelectrically converted by the photodiode to the floating diffusion FD.

[0006] When a reset signal is applied to the gate of the reset transistor, the reset transistor resets the potential of the floating diffusion FD to the potential of the power supply line.

[0007] The floating diffusion FD is connected to the gate of a source follower transistor. The source follower transistor is connected to a vertical signal line via a selection transistor, and constitutes a constant current source and a source follower for a load circuit outside the pixel unit. Then, a control signal (address signal or select signal) is applied to the gate of the selection transistor, turning the selection transistor on. When the selection transistor is turned on, the source follower transistor amplifies the potential of the floating diffusion FD and outputs a voltage corresponding to the amplified potential to the vertical signal line. The voltage output from each pixel is output through the vertical signal line to the column-parallel processing unit serving as a pixel signal readout circuit. In the column-parallel processing, the image data is converted, for example, from an analog signal to a digital signal and transferred to a downstream signal processing unit, where it undergoes predetermined image signal processing to obtain a desired image.

[0008] As described above, in a CMOS image sensor, electrons generated by photoelectric conversion using a small amount of light are converted into a voltage using a very small capacitance, and then output using a source-follower transistor with a very small area. For this reason, it is necessary to remove minute noises such as noise that occurs when resetting the capacitance and minute noises due to variations in transistor elements, and the difference between the reset level and brightness level (signal level) for each pixel is output. In this way, CMOS image sensors can eliminate reset noise and threshold variations and detect signals of several electrons by outputting the difference between the reset level and brightness level for each pixel. The operation of detecting this difference is called Correlated Double Sampling (CDS) and is a widely used technology. CDS readout is performed sequentially for all pixels arranged in an array, and one frame's worth of normal image data is output.

[0009] For example, in a read scan period, after the floating diffusion FD is reset to, for example, the potential (reference potential) of the power supply line during the reset period, the charge of the floating diffusion FD is converted into a voltage signal with a conversion gain according to the FD capacitance and output to the vertical signal line as a reference level read reset signal (reference level signal) Vrst. Then, during a predetermined transfer period, the charge (electrons) photoelectrically converted and accumulated in the photodiode is transferred to the floating diffusion FD. The charge in the floating diffusion FD is converted into a voltage signal with a conversion gain according to the FD capacitance, and is output to the vertical signal line as a signal level readout signal (signal level signal) Vsig. The output signal of the pixel is subjected to CDS (correlated double sampling) processing as a differential signal (Vsig-Vrst) in the column readout circuit.

[0010] In this way, a normal pixel read signal (hereinafter, sometimes referred to as a pixel signal) PS is formed by a read reset signal Vrst of one reference level and a read signal Vsig of one signal level.

[0011] Meanwhile, in order to improve characteristics, various methods have been proposed for achieving a high-quality solid-state imaging device (CMOS image sensor) having a high dynamic range (HDR).

[0012] One approach to achieving a high dynamic range is a Lateral Overflow Integration Capacitor (LOFIC) configuration (see, for example, Patent Document 1). In a pixel with the LOFIC configuration, a storage capacitor and a storage transistor are added to the basic 4Tr configuration described above, and the oversaturated charge that overflows from the photodiode during the same exposure time is stored in the storage capacitor rather than being discarded.

[0013] This LOFIC pixel can have two types of conversion gain: one due to the floating diffusion capacitance Cfd1 (high gain side: proportional to 1 / Cfd1) and one due to the floating diffusion capacitance Cfd1 + the LOFIC capacitance Clofic of the storage capacitor C2 (low gain side: proportional to 1 / (Cfd1+Clofic)). That is, in the LOFIC pixel, a low conversion gain (LCG) signal and a high conversion gain (HCG) signal are used to achieve large saturation and small dark noise, respectively. [Prior art documents] [Patent documents]

[0014] [Patent Document 1] JP 2005-328493 A [Patent Document 2] Patent Publication No. 2020-115603 Summary of the Invention [Problem to be solved by the invention]

[0015] However, LOFIC has a major problem of SNR degradation at the junction of the high conversion gain (HCG) and low conversion gain (LCG) signals. That is, the LOFIC configuration alone cannot remove the kTC noise of the LCG signal, resulting in a decrease in SNR at the junction of the HCG and LCG signals.

[0016] For example, Patent Document 2 proposes a specific circuit configuration for a pixel signal processing unit in a readout circuit of a solid-state imaging device that is not subject to LOFIC but can eliminate noise gaps at the connection points between low conversion gain signals and high conversion gain signals, can suppress increases in power consumption and circuit area, and can achieve a high dynamic range.

[0017] Incidentally, in a CMOS image sensor having a LOFIC structure, the signal directions of the high conversion gain (HCG) signal and the low conversion gain (LCG) signal, that is, the level transition directions, are opposite to each other, so a dual readout circuit is required. However, since the pixel signal processing unit in the readout circuit described in Patent Document 2 is capable of reading both the HCG signal and the LCG signal generated from single-exposure HDR (SEHDR) pixels whose signal directions are the same, it is difficult to directly apply this to a CMOS image sensor having a LOFIC structure.

[0018] Furthermore, when attempting to realize a dual readout circuit applicable to a CMOS image sensor with a LOFIC structure, in order to reduce chip costs, a readout circuit that can process both the LCG signal and the HCG signal with minimal circuit overhead and can achieve low power consumption is required.

[0019] Incidentally, in the above-mentioned solid-state imaging device (image sensor), basically, owners of various electronic devices or users who are authorized to use the devices can easily play back captured image data and view the images.

[0020] In recent years, SWIR (short wavelength infrared, 1-1.7um-2.5um wavelength) imaging technology has come into practical use with many applications. Examples of this type of application include automobiles, atmospheric transillumination surveillance, eye-safe active IR imaging with strong secondary light above 940 nm, in-car monitors, night vision, texture 3D, factory automation through surveillance cameras on smartphones and displays, physical testing, image inspection, etc.

[0021] One of the technical challenges of SWIR image sensors is the cancellation of offset caused by large thermal dark current (offset signal) at room and high temperatures. To respond to lower energy photons compared to visible light photons (wavelengths 500–650 nm), SWIR photoelectric conversion materials (e.g., Ge, InGaAs, quantum dots) have lower energy bandgaps, and therefore such lower bandgap materials are more susceptible to larger thermal dark currents.

[0022] To achieve large offset cancellation, a large integration capacitance is required within the pixel to store both the offset signal and the effective signal, which in some cases can be much larger than the photo signal.

[0023] Previous techniques have involved increasing the charge capacity of the pixel, cooling the device, or reading out at high frame rates before saturation by the dark signal.

[0024] (Issues to be addressed) As practical issues, there are many challenges that need to be addressed and / or solved.

[0025] (System Cooling) Cooling the device is the most effective way to reduce the offset, but it is not preferred in consumer systems such as smartphones or in-car monitors because of the increased power consumption, size, mechanics, and time required for temperature stabilization.

[0026] (Increases pixel charge capacity) When charging a signal charge into a capacitor, the maximum voltage is limited by the power supply voltage of the pixel readout integrated circuit (ROIC), so the capacitance value needs to be increased. Increasing the capacitance is usually equivalent to decreasing the gain, which usually reduces the resolution of the circuit and degrades the input signal-equivalent noise.

[0027] Another challenge is that SWIR photoconductive materials typically have a voltage-dependent responsivity, which affects the accuracy of the offset subtraction.

[0028] (High frame rate readout before saturation by dark signal) A high frame rate readout that prevents offset saturation is also an effective measure. A practical issue with this method is the increase in the signal readout bandwidth and signal processing load in the external storage required to add multiple frame signals at a high frame rate. Overall, consumer SWIR image sensors require no cooling, a large signal integration charge without gain degradation, stable light sensitivity during signal integration, and lower interface bandwidth.

[0029] The present invention provides a solid-state imaging device that can obtain a large signal integration charge amount and stable photosensitivity during signal integration without requiring cooling and without a decrease in gain, and that can also realize a lower interface bandwidth, a method for manufacturing a solid-state imaging device, and electronic equipment. [Means for solving the problem]

[0030] To address the above challenges, digital pixel, charge transconductance integration amplifier (CTIA), and pixel-level oversampling techniques are introduced into SWIR image sensors.

[0031] A solid-state imaging device according to a first aspect of the present invention has a pixel section in which pixels are arranged, the pixels being formed by a photoelectric conversion film that converts light into a photo-generated current and a semiconductor pixel circuit, the photoelectric conversion film and the semiconductor pixel circuit being stacked and electrically coupled within the pixel, the photoelectric conversion film being sensitive to infrared rays, and the semiconductor pixel circuit including a pixel analog circuit that detects the photo-generated current, and a pixel analog-to-digital (AD) conversion circuit that converts an analog signal from the pixel analog circuit into a digital signal.

[0032] A second aspect of the present invention is a manufacturing method for a solid-state imaging device having a pixel portion in which pixels are arranged, the pixel being formed by a photoelectric conversion film that converts light into a photo-generated current and a semiconductor pixel circuit, the photoelectric conversion film and the semiconductor pixel circuit being stacked and electrically coupled within the pixel, the photoelectric conversion film being sensitive to infrared rays, and the semiconductor pixel circuit forming a pixel analog circuit that detects the photo-generated current, and a pixel analog-to-digital (AD) conversion circuit that converts an analog signal from the pixel analog circuit into a digital signal.

[0033] An electronic device according to a third aspect of the present invention comprises a solid-state imaging device and an optical system that forms an image of a subject on the solid-state imaging device, the solid-state imaging device having a pixel portion in which pixels are arranged, the pixels being formed by a photoelectric conversion film that converts light into a photo-generated current and a semiconductor pixel circuit, the photoelectric conversion film and the semiconductor pixel circuit being stacked and electrically coupled within the pixel, the photoelectric conversion film being sensitive to infrared rays, and the semiconductor pixel circuit including a pixel analog circuit that detects the photo-generated current, and a pixel analog-to-digital (AD) conversion circuit that converts an analog signal from the pixel analog circuit into a digital signal. Effect of the Invention

[0034] According to the present invention, it is possible to obtain a large signal integration charge without the need for cooling, without loss of gain, stable light sensitivity during signal integration, and to realize a lower interface bandwidth. [Brief description of the drawings]

[0035] [Figure 1] 1 is a block diagram showing an example of the configuration of a solid-state imaging device according to a first embodiment of the present invention. [Diagram 2] 1 is a diagram showing an example of an arrangement of a pixel section in a solid-state imaging device according to a first embodiment of the present invention. [Diagram 3] 1 is a circuit diagram showing an example of the configuration of a pixel in a solid-state imaging device according to a first embodiment of the present invention. [Figure 4] 1 is a simplified cross-sectional view for explaining a layered structure of a pixel in a solid-state imaging device according to a first embodiment of the present invention. [Diagram 5] 4 is a timing chart showing an example of a pixel readout sequence in the solid-state imaging device according to the first embodiment of the present invention. [Figure 6] FIG. 11 is a circuit diagram showing an example of the configuration of a pixel in a solid-state imaging device according to a second embodiment of the present invention. [Figure 7] FIG. 11 is a circuit diagram showing an example of the configuration of a pixel in a solid-state imaging device according to a third embodiment of the present invention. [Figure 8] FIG. 13 is a circuit diagram showing an example of the configuration of a pixel in a solid-state imaging device according to a fourth embodiment of the present invention. [Figure 9] 13 is a timing chart showing an example of a pixel readout sequence in a solid-state imaging device according to a fourth embodiment of the present invention. [Figure 10] FIG. 13 is a block diagram showing an example of the configuration of a pixel calibration system in a solid-state imaging device according to a fifth embodiment of the present invention. [Figure 11] 13 is a timing chart showing an example of a pixel readout sequence in a solid-state imaging device according to a fifth embodiment of the present invention. [Figure 12] 1 is a diagram showing an example of a configuration of an electronic device to which a solid-state imaging device according to an embodiment of the present invention is applied; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0036] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[0037] (First embodiment) FIG. 1 is a block diagram showing an example of the configuration of a solid-state imaging device according to the first embodiment of the present invention. FIG. 2 is a diagram showing an example of an arrangement of a pixel unit in the solid-state imaging device according to the first embodiment of the present invention. FIG. 3 is a circuit diagram showing an example of the configuration of a pixel in the solid-state imaging device according to the first embodiment of the present invention. FIG. 4 is a simplified cross-sectional view for explaining a layered structure of a pixel in the solid-state imaging device according to the first embodiment of the present invention. 5(A) to 5(D) are timing charts showing an example of a readout sequence of a readout pixel in the solid-state imaging device according to the first embodiment of the present invention.

[0038] In this embodiment, as shown in FIG. 2, the solid-state imaging device 10 includes a sensor, such as a SWIR sensor, which is configured of a pixel array formed in a pixel section 20 and a data readout circuit (pixel circuit).

[0039] As shown in FIG. 1, the solid-state imaging device 10 has as its main components a pixel section 20 as an imaging section, a vertical scanning circuit (row scanning circuit) 30, a readout circuit 40 including a pixel signal processing section, a horizontal scanning circuit (column scanning circuit) 50, and a timing control circuit 60. Of these components, for example, the vertical scanning circuit 30, the readout circuit 40, the horizontal scanning circuit 50, and the timing control circuit 60 constitute a pixel signal readout section 70.

[0040] In this first embodiment, the data saturation level is increased in the DPS by oversampling and accumulating pixel-level data, and the bias of the QD layer is kept constant by using a CTIA circuit instead of a source follower, stabilizing the dark current.

[0041] Digital frame oversampling using a DPS (Digital Pixel Sensor) with CTIA provides the following unique configurations and functions:

[0042] (Digital Frame Oversampling and Digital Accumulation) · By taking the DPS approach, data can be accumulated in the digital domain. Subframe oversampling using a high-speed ADC and digital adder enables improved dynamic range of offset cancellation.

[0043] (Fixing QD bias conditions by CTIA readout circuit) · The QD bias is almost fixed to the reference potential VREF by feedback. Since the error is VSIG / Av (Av is the amplifier gain, VSIG is the output signal voltage), the QD bias fluctuation is suppressed to 1 / Av, and the fluctuation can be almost ignored by increasing the amplifier gain.

[0044] (Basic architecture) In the first embodiment, the pixels 200 arranged in a matrix in the pixel section 20 basically have a configuration as shown in Fig. 2. A cross-sectional view of one pixel taken along the line AA' is shown in Fig. 4. That is, the pixel 200 is composed of a photoelectric conversion film (layer, material) 210 and a semiconductor pixel circuit 220. The photoelectric conversion material is sensitive to NIR (infrared) / SWIR (short wavelength infrared).

[0045] As shown in FIG. 3, the pixel 200 includes a pixel analog (amplifier) ​​circuit 230 that detects a photoelectric conversion current, a sample-and-hold circuit 240, an ADC 250, an in-pixel logic 260, and a digital memory 270. The analog circuit (amplifier) ​​230 also functions as a current integrator and voltage stabilizer for the photoelectric conversion layer 210 through a feedback operation.

[0046] More specifically, the pixel 200 is formed by a photoelectric conversion film 210 that converts light into a photo-generated current, and a semiconductor pixel circuit 220. A photoelectric conversion layer 210 and a semiconductor pixel circuit 220 are stacked and electrically coupled within the pixel 200, and the photoelectric conversion layer 210 is sensitive to infrared (NIR), for example.

[0047] The semiconductor pixel circuit 220 includes a pixel analog circuit 230 that detects a photo-generated current, and a pixel analog-to-digital (AD) conversion circuit (ADC) 250 that converts an analog signal from the pixel analog circuit 230 into a digital signal.

[0048] The pixel 200 includes a pixel digital memory 270 that records the digital signal from the pixel AD conversion circuit 250 , and a pixel digital readout circuit 280 that reads out the digital signal from the digital memory 270 .

[0049] The pixel analog circuit 230 includes an in-pixel feedback circuit 231 that keeps the voltage applied to the photoelectric conversion film constant, an in-pixel integration circuit 232 that integrates the photo-generated current and converts it into a voltage, and a pixel initialization circuit 233 that initializes the integration circuit 232.

[0050] A pixel sample-and-hold circuit 240 is provided between the pixel analog circuit 230 and the pixel AD conversion circuit 250 . Then, immediately after the integrated voltage signal is sampled and held in the pixel sample-and-hold circuit 240, the pixel integration circuit 232 is initialized, making it possible to integrate a subframe having a period indicated by the unit exposure time in FIG.

[0051] The image sensor has a readout unit 70 that controls the reading of pixel signals from the pixels 200, and under the control of the readout unit 70, digital conversion of the signal from the pixel sample-and-hold circuit 240 is started, and the in-pixel integration circuit 232 is initialized, so that the sample-and-hold, initialization, and AD conversion of the subframes can be repeated for each integration time that is constant or has a specific pattern.

[0052] The inclusion of a pixel digital addition circuit 290 that adds up the digital signals of the subframes obtained by repeated AD conversion and rewrites the signal in the memory enables addition on a pixel-by-pixel basis.

[0053] As will be described later, a configuration in which the pixel AD conversion circuit 250 is shared by a plurality of pixels is also possible.

[0054] It is also possible to have a digital addition circuit 290 that adjusts the ramp waveform input to the pixel AD conversion circuit 250 for each pixel that shares the same waveform to change the digital conversion gain.

[0055] (Pixel-level oversampling) The digital summing circuit 290 can be implemented in the in-pixel logic circuit 260 . During the total exposure time, the analog integrated signal (Vpix) is converted to digital at a faster cycle (Unit exposure time), and all the digital data is digitally integrated by a digital adder circuit (adder) 290. The equivalent LFW (Linear Full Well), which corresponds to the amount of integrated signal charge, increases depending on the number of subframe integrations / additions of the ADC 250 during the exposure time.

[0056] During the entire exposure time, the bias (Vin) of the photoelectric conversion layer is maintained at VREF by feedback from the amplifier 230, ensuring stability of the photoelectric conversion characteristics. Digital summation (the pixel-level oversampling mentioned above) allows data to be stored in the digital domain without reducing analog gain. Furthermore, compared to adding and integrating to an analog memory (capacitor) in the voltage domain, it is not affected by the leakage current of the analog memory, preventing time-dependent data degradation during the integration time.

[0057] Return to Figure 1.

[0058] The vertical scanning circuit 30 drives pixels in the shutter row and the readout row through row scanning control lines under the control of the timing control circuit 60 . Furthermore, the vertical scanning circuit 30 outputs a row selection signal of the row address of a read row for reading out a signal and a shutter row for resetting the charge accumulated in the photoelectric conversion film 210 in accordance with the address signal.

[0059] The horizontal scanning circuit 50 scans the signals processed by the multiple pixel signal processing units of the readout circuit 40, transfers them in the horizontal direction, and outputs them to a signal processing circuit (not shown).

[0060] The timing control circuit 60 generates timing signals necessary for signal processing in the pixel section 20, the vertical scanning circuit 30, the readout circuit 40, the horizontal scanning circuit 50, and the like.

[0061] As described above, in the first embodiment, the saturation level of data is increased in the DPS by oversampling and digitally integrating AD converted data at the pixel level, and the bias of the QD layer is kept constant and the dark current is stabilized by using a CTIA circuit instead of a source follower. In addition, the first embodiment includes at least the following configuration. That is, the pixel 200 is composed of a photoelectric conversion film (layer, material) 210 and a semiconductor pixel circuit 220. The photoelectric conversion material is sensitive to NIR (infrared) / SWIR (short wavelength infrared). The pixel 200 is composed of a pixel analog (amplifier) ​​circuit 230 that detects a photoelectric conversion current, a sample hold circuit 240, an ADC 250, an in-pixel logic 260, and a digital memory 270. The analog circuit (amplifier) ​​230 also functions as a current integrator and voltage stabilizer for the photoelectric conversion layer 210 through a feedback operation.

[0062] The semiconductor pixel circuit 220 includes a pixel analog circuit 230 that detects a photo-generated current, a sample and hold circuit 240, and a pixel analog-to-digital (AD) conversion circuit (ADC) 250 that converts an analog signal from the pixel analog circuit 230 into a digital signal. The pixel 200 includes a pixel digital memory 270 that records the digital signal from the pixel AD conversion circuit 250, and a pixel digital readout circuit 280 that reads out the digital signal from the digital memory 270. The pixel analog circuit 230 includes an in-pixel feedback circuit 231 that keeps the voltage applied to the photoelectric conversion film constant, an in-pixel integration circuit 232 that integrates the photo-generated current and converts it into a voltage, and a pixel initialization circuit 233 that initializes the integration circuit 232. A pixel sample-and-hold circuit 240 is provided between the pixel analog circuit 230 and the pixel AD conversion circuit 250 . Then, immediately after the integrated voltage signal is sampled and held in the pixel sample and hold circuit 240, the intra-pixel integration circuit 232 is initialized to enable integration for the next subframe.

[0063] Therefore, according to the first embodiment, it is possible to obtain a large signal integration charge amount and stable optical sensitivity during signal integration without the need for cooling and without a decrease in gain, and also to realize a lower interface bandwidth.

[0064] Second Embodiment FIG. 6 is a circuit diagram showing an example of the configuration of a pixel in a solid-state imaging device according to the second embodiment of the present invention.

[0065] A solid-state imaging device 10A according to the second embodiment differs from the solid-state imaging device 10 according to the first embodiment described above in the following points.

[0066] That is, in the pixel 200A of the solid-state imaging device 10A according to the second embodiment, the in-pixel logic circuit 260 is shared by a plurality of pixels (sub-pixels) 200A.

[0067] (In-pixel logic circuitry shared by multiple pixels) In a SWIR sensor system, the digital summer 290 and memory controller implemented in the in-pixel logic circuit 260 require a large number of transistors. Therefore, in the second embodiment, the in-pixel logic circuit 260 is shared by a plurality of sub-pixels. As a result, according to the second embodiment, it is possible to reduce the total number of logic transistors per subpixel.

[0068] According to the second embodiment, not only can the same effects as those of the first embodiment described above be obtained, but there is also the advantage that increases in power consumption and circuit area can be significantly suppressed.

[0069] (Third embodiment) FIG. 7 is a circuit diagram showing an example of the configuration of a pixel in a solid-state imaging device according to the third embodiment of the present invention.

[0070] The solid-state imaging device 10B according to the third embodiment differs from the solid-state imaging device 10A according to the second embodiment described above in the following respects.

[0071] That is, in the pixel 200B of the solid-state imaging device 10B according to the third embodiment, the ADC 250 and the in-pixel logic circuit 260 are shared by a plurality of pixels (sub-pixels) 200B.

[0072] (In-pixel logic circuit and ADC shared by multiple pixels) In a SWIR sensor system, a plurality of sub-pixels share the ADC 250 and the in-pixel logic circuit 260. In this embodiment, a latch circuit is used as the memory 270. The pixel signal is sampled and held within each sub-pixel, and then sequentially converted to digital by a shared ADC via a selection switch (Select). A voltage buffer VBF is disposed between the sample-and-hold (S / H) switch 240 and the select switch SSW to suppress the effect of the select switch SSW and the kickback effect of the ADC 250. As a result, in the third embodiment, it is possible to reduce not only the number of logic transistors but also the number of analog devices per subpixel.

[0073] According to the third embodiment, not only can the same effects as those of the first and second embodiments described above be obtained, but there is also an advantage that an increase in power consumption and an increase in circuit area can be significantly suppressed.

[0074] (Fourth embodiment) FIG. 8 is a circuit diagram showing an example of the configuration of a pixel in a solid-state imaging device according to the fourth embodiment of the present invention. FIG. 9 is a timing chart showing an example of a pixel readout sequence in the solid-state imaging device according to the fourth embodiment of the present invention. Figure 8 shows a circuit diagram of a latch circuit applied to memory using a single-slope (SS) ADC, and Figure 9 shows frame oversampling operation.

[0075] In the fourth embodiment, by employing an SS ADC, there is an advantage that the pixel configuration is simplified. In addition, VRAMP and the digital count code are common, and the AD conversion gain control and the conversion speed can be adaptively varied and applied.

[0076] Fifth embodiment FIG. 10 is a block diagram showing an example of the configuration of a pixel calibration system in a solid-state imaging device according to the fifth embodiment of the present invention. FIG. 11 is a timing chart showing an example of a pixel readout sequence in a solid-state imaging device according to the fifth embodiment of the present invention.

[0077] The fifth embodiment relates to dark signal subtraction using dark signal data in a solid-state imaging device 10D.

[0078] For n ADC / data summations during the exposure time, taking into account the stability of the dark current caused by the fixed bias condition at the photoconversion layer, the total dark current can be assumed to be n times the dark current (Dark) during the unit exposure time. The dark signal of each pixel for a unit exposure time is measured in advance and stored in the calibration system 2000. The offset calibration is performed by the following formula, where the signal data obtained by ADC / data addition n times is Sig(raw).

[0079] (Number 1) Sig = Sig(raw)-n×Dark (Unit exposure time)

[0080] In addition, when calculating the offset, temperature dependency can also be taken into account by multiplying Dark by a coefficient that depends on the temperature. Using this scheme, the offset calibration is flexible and can easily accommodate different exposure times. This calibration process can be performed in the pixel domain, on-chip domain, and externally.

[0081] The above-described solid-state imaging devices 10, 10A to 10D can be applied as imaging devices to electronic devices such as digital cameras, video cameras, mobile terminals, surveillance cameras, and medical endoscope cameras.

[0082] FIG. 12 is a diagram showing an example of the configuration of an electronic device equipped with a camera system to which a solid-state imaging device according to an embodiment of the present invention is applied.

[0083] As shown in FIG. 12, the electronic device 300 includes a SWIR image sensor 310 to which the solid-state imaging devices 10, 10A, 10B, 10C, and 10D according to the present embodiment can be applied. Furthermore, the electronic device 300 has an optical system (lens or the like) 320 that guides incident light to the pixel region of the SWIR image sensor 310 (forms an image of a subject). The electronic device 300 includes a signal processing circuit (PRC) 330 that processes an output signal from the CMOS image sensor 310 .

[0084] The signal processing circuit 330 performs predetermined signal processing on the output signal of the SWIR image sensor 310 . In the signal processing circuit 330 The processed image signal can be displayed as a moving image on a monitor such as a liquid crystal display, output to a printer, or directly recorded on a recording medium such as a memory card. Various other forms are possible.

[0085] As described above, by mounting the above-mentioned solid-state imaging devices 10, 10A, 10B, 10C, and 10D as the SWIR image sensor 310, it is possible to provide a high-performance, small-sized, low-cost camera system. This makes it possible to realize electronic devices such as surveillance cameras and medical endoscope cameras that are used in applications where the camera installation requirements include constraints such as mounting size, number of connectable cables, cable length, and installation height. [Explanation of symbols]

[0086] 10,10A-10D···solid-state imaging device, 20···pixel section, 200,200A-200D···pixel, 210···photoelectric conversion film (layer, material), 220···semiconductor pixel circuit, 230···pixel analog circuit, 240···sample and hold circuit, 250···ADC, 260···in-pixel logic, 270···digital memory, 290···digital addition circuit (adder), 30···vertical scanning circuit, 40···readout circuit, 50···horizontal scanning circuit, 60···timing control circuit, 70···readout section, 300···electronic device, 310···SWIR image sensor, 320···optical system, 330···signal processing circuit (PRC).

Claims

1. A pixel portion in which pixels are arranged, The pixel is The pixel is formed by a photoelectric conversion film that converts light into a photo-generated current and a semiconductor pixel circuit, The photoelectric conversion film and the semiconductor pixel circuit are laminated and electrically connected within the pixel, the photoelectric conversion film is sensitive to infrared light, the semiconductor pixel circuit includes a pixel analog circuit for detecting the photo-generated current; a pixel analog-to-digital (AD) conversion circuit for converting an analog signal from the pixel analog circuit into a digital signal. Solid-state imaging device.

2. The pixel is a pixel digital memory that records the digital signal generated by the pixel AD conversion circuit; a pixel digital readout circuit for reading out the digital signal from the digital memory.

2. The solid-state imaging device according to claim 1.

3. The pixel analog circuit includes: A pixel feedback circuit that keeps a voltage applied to the photoelectric conversion film constant; an in-pixel integration circuit that integrates the photo-generated current and converts it into a voltage; a pixel initialization circuit that initializes the pixel integration circuit; Includes 3. The solid-state imaging device according to claim 2.

4. The pixel is Between the pixel analog circuit and the pixel AD conversion circuit, A pixel sample and hold circuit is provided. The pixel integration circuit can be initialized immediately after the integrated voltage signal is sampled and held in the pixel sample-and-hold circuit.

4. The solid-state imaging device according to claim 3.

5. A readout unit that controls the reading out of pixel signals from the pixels, Under the control of the readout unit, It is possible to start digital conversion of the signal of the pixel sample-and-hold circuit, initialize the in-pixel integration circuit, and repeat sample-and-hold, initialization, and AD conversion for each integration time of a fixed or specific pattern.

5. The solid-state imaging device according to claim 4.

6. A pixel digital addition circuit is provided for adding the digital signals obtained by the repeated AD conversion and rewriting the signal in the memory.

6. The solid-state imaging device according to claim 5.

7. The pixel AD conversion circuit is shared by a plurality of pixels.

7. The solid-state imaging device according to claim 1.

8. The digital conversion gain is changed by adjusting each pixel that shares the ramp waveform input to the pixel AD converter.

8. The solid-state imaging device according to claim 7.

9. A method for manufacturing a solid-state imaging device having a pixel portion in which pixels are arranged, comprising the steps of: The pixel is The display device is formed by a photoelectric conversion film that converts light into a photo-generated current and a semiconductor pixel circuit. The photoelectric conversion film and the semiconductor pixel circuit are laminated and electrically coupled within the pixel; The photoelectric conversion film is made sensitive to infrared rays, The semiconductor pixel circuit includes: a pixel analog circuit for detecting the photo-generated current; A pixel analog-to-digital (AD) conversion circuit that converts an analog signal from the pixel analog circuit into a digital signal. A method for manufacturing a solid-state imaging device.

10. A solid-state imaging device; an optical system that forms a subject image on the solid-state imaging device; The solid-state imaging device includes: A pixel portion in which pixels are arranged, The pixel is The pixel is formed by a photoelectric conversion film that converts light into a photo-generated current and a semiconductor pixel circuit, The photoelectric conversion film and the semiconductor pixel circuit are laminated and electrically connected within the pixel, the photoelectric conversion film is sensitive to infrared light, the semiconductor pixel circuit includes a pixel analog circuit for detecting the photo-generated current; a pixel analog-to-digital (AD) conversion circuit for converting an analog signal from the pixel analog circuit into a digital signal. electronic equipment.

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