Photoelectric conversion device, electronic apparatus, and substrate

Abstract

To provide a technique advantageous for improving the usability of a photoelectric conversion device.SOLUTION: A photoelectric conversion device comprises: a photoelectric conversion unit that receives incident light; a difference circuit that receives input of a first signal and a second signal that are signals corresponding to signal charges generated by the photoelectric conversion unit on the basis of the incident light, and outputs a third signal indicating the difference between the first signal and the second signal; and an over-sampling type conversion circuit that performs analog-digital conversion of the third signal.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a photoelectric conversion device, an electronic device, and a substrate. [Background technology]

[0002] Patent Document 1 discloses a solid-state imaging device equipped with a ΔΣ analog-to-digital conversion circuit. It also discloses that the solid-state imaging device of Patent Document 1 performs differential processing between a data signal sampled in a data signal sample-and-hold circuit and a reset signal sampled in a reset signal sample-and-hold circuit. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2019 / 069614 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a technique that is advantageous for improving the usability of a photoelectric conversion device. [Means for solving the problem]

[0005] In view of the above problems, a photoelectric conversion device according to an embodiment of the present invention is characterized in that it includes a photoelectric conversion unit that receives incident light, a differential circuit that receives input of a first signal and a second signal, the first signal and the second signal being signals corresponding respectively to signal charges generated by the photoelectric conversion unit based on the incident light, and outputs a third signal indicating the difference between the first signal and the second signal, and an oversampling type conversion circuit that performs analog-to-digital conversion of the third signal. Effect of the Invention

[0006] According to the present invention, it is possible to provide a technique that is advantageous for improving the usability of a photoelectric conversion device. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a photoelectric conversion device according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a diagram showing an example of the configuration of a pixel in the photoelectric conversion device of FIG. 1; [Diagram 3] 2 is a diagram showing an example of the configuration of a sample-and-hold unit and a conversion circuit of the photoelectric conversion device of FIG. 1; [Figure 4] 2 is a timing chart showing an example of the operation of the photoelectric conversion device of FIG. 1. [Diagram 5] FIG. 2 is a diagram showing an example of the configuration of a pixel in the photoelectric conversion device of FIG. 1; [Figure 6] 2 is a timing chart showing an example of the operation of the photoelectric conversion device of FIG. 1. [Figure 7] FIG. 1 is a diagram showing an example of the configuration of a camera incorporating a photoelectric conversion device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, the embodiments will be described in detail with reference to the attached drawings. Note that the following embodiments do not limit the invention according to the claims. Although the embodiments describe a number of features, not all of these features are essential to the invention, and the features may be combined in any manner. Furthermore, in the attached drawings, the same reference numbers are used for the same or similar configurations, and duplicated descriptions are omitted.

[0009] A photoelectric conversion device according to an embodiment of the present disclosure will be described with reference to Figs. 1 to 6. Fig. 1 is a schematic diagram showing a configuration example of a photoelectric conversion device 1000 of the present disclosure. Fig. 2 is a diagram showing a configuration example of a pixel 10 arranged in the photoelectric conversion device 1000. Fig. 3 is a diagram showing a configuration example of a sample hold unit 50 and a conversion circuit 60 that performs analog-to-digital conversion arranged in the photoelectric conversion device 1000. Fig. 4 is a timing chart showing an operation example of the photoelectric conversion device 1000.

[0010] The photoelectric conversion device 1000 includes a pixel substrate 1, which is a substrate on which a plurality of pixels 10 (photoelectric conversion elements 400) are arranged, and a circuit substrate 2, which is a substrate on which circuits for operating the pixels 10 and the like are arranged. The photoelectric conversion device 1000 may have a laminated chip structure in which the pixel substrate 1 and the circuit substrate 2 are laminated on each other. The pixel substrate 1 includes a photoelectric conversion section 5 on which a plurality of pixels 10 (photoelectric conversion elements 400) are arranged. The circuit substrate 2 includes a current source 40, a sample hold section 50, a conversion circuit 60, a data processing circuit 90, and an output section 100.

[0011] In the photoelectric conversion unit 5 that receives incident light, a plurality of pixels 10 each including a photoelectric conversion element 400 are arranged in a matrix. Here, the row direction refers to the horizontal direction in Fig. 1, and the column direction refers to the vertical direction in Fig. 1. The pixels 10 generate charges according to the incident light.

[0012] In the photoelectric conversion unit 5, vertical signal lines 30 are arranged along the column direction corresponding to each pixel column in which the pixels 10 are arranged. The vertical signal lines 30 transfer signals based on charges generated by the photoelectric conversion elements 400 arranged in the pixels 10 from the pixels 10 to the sample hold unit 50.

[0013] The current sources 40 are arranged corresponding to the respective vertical signal lines 30. The current sources 40 supply bias currents for reading out signals via the vertical signal lines 30 to the pixels 10 selected to read out signals.

[0014] The sample and hold unit 50 samples and holds a signal generated by the photoelectric conversion element 400 arranged in each pixel 10 from the photoelectric conversion unit 5 via the vertical signal line 30. In this embodiment, in the sample and hold unit 50, two sample and hold circuits are connected to one vertical signal line 30, the details of which will be described later.

[0015] The conversion circuit 60 performs analog-to-digital conversion on the signal output from the sample-and-hold unit 50. The conversion circuits 60 are arranged corresponding to the respective vertical signal lines 30. As the conversion circuit 60 that performs the analog-to-digital conversion, an oversampling type analog-to-digital converter such as a delta-sigma (ΔΣ) type analog-to-digital conversion circuit may be used. However, the present invention is not limited to this, and as the conversion circuit 60, a slope type analog-to-digital conversion circuit, a successive approximation type analog-to-digital conversion circuit, or the like may be used.

[0016] The data processing circuit 90 is a digital signal processing circuit that processes the digital signal output from the conversion circuit 60. For example, the data processing circuit 90 may perform correction processing, complementation processing, etc. on the digital signal output from the conversion circuit 60. The output unit 100 outputs the signal processed by the data processing circuit 90 to the outside of the photoelectric conversion device 1000.

[0017] As shown in FIG. 2, the pixel 10 may include a photoelectric conversion element 400, a transfer transistor 410, a reset transistor 455, an amplification transistor 430, and a selection transistor 440. The photoelectric conversion element 400 may be, for example, a photodiode. One of two main electrodes of the photoelectric conversion element 400 is connected to a ground potential 450. The photoelectric conversion element 400 photoelectrically converts received light into a signal charge (for example, photoelectrons) having an amount of charge corresponding to the amount of light, and accumulates the signal charge. The other of the two main electrodes of the photoelectric conversion element 400 is connected to the gate electrode of the amplification transistor 430 via the transfer transistor 410. A node 420 electrically connected to the gate electrode of the amplification transistor 430 functions as a floating diffusion. The floating diffusion is a charge-voltage conversion unit that converts the signal charge generated by the photoelectric conversion element 400 into a signal voltage. Here, a plurality of pixels 10 are arranged in the photoelectric conversion unit 5. Therefore, it can be said that the photoelectric conversion section 5 has a plurality of photoelectric conversion elements 400 and a plurality of floating diffusions arranged to correspond to the plurality of photoelectric conversion elements 400, respectively.

[0018] A control signal TX is supplied to the gate electrode of the transfer transistor 410. When the transfer transistor 410 becomes conductive (ON state) in response to the control signal TX, photoelectric conversion is performed in the photoelectric conversion element 400, and the signal charge accumulated in the photoelectric conversion element 400 is transferred to a node 420 which is a floating diffusion.

[0019] The reset transistor 455 is connected between a power supply potential 460 and a node 420. Here, when it is expressed that "a transistor is connected between A and B," it means that one of the two main electrodes (source and drain) of the transistor is connected to A, and the other of the two main electrodes is connected to B. In this case, the gate electrode of the transistor is not connected to A or B.

[0020] A control signal RES is supplied to the gate electrode of the reset transistor 455. When the reset transistor 455 is turned on in response to the control signal RES, the potential of the node 420 functioning as a floating diffusion is reset to the power supply potential 460, and the charge held in the floating diffusion is swept away.

[0021] The amplification transistor 430 is connected between a power supply potential 460 and the selection transistor 440. The gate electrode of the amplification transistor 430 is connected to the node 420. The amplification transistor 430 constitutes an input section of a source follower that reads out a signal obtained by photoelectric conversion of the photoelectric conversion element 400. That is, one of two main electrodes of the amplification transistor 430 is connected to the vertical signal line 30 via the selection transistor 440. The amplification transistor 430 and the above-mentioned current source 40 connected to the vertical signal line 30 constitute a source follower that converts the voltage of the node 420 into the potential of the vertical signal line 30.

[0022] The selection transistor 440 is connected between the amplification transistor 430 and the vertical signal line 30. A control signal SEL is supplied to a gate electrode of the selection transistor 440. When the selection transistor 440 is turned on in response to the control signal SEL, the pixel 10 is placed in a selected state and a signal is output from the amplification transistor 430 to the vertical signal line 30.

[0023] The circuit configuration of the pixel 10 is not limited to the configuration shown in FIG. 2. For example, the selection transistor 440 may be connected between the power supply potential 460 and the amplification transistor 430. In addition, in the configuration shown in FIG. 2, a so-called 4-Transistor (4Tr.) type configuration is shown as the pixel 10, which includes the transfer transistor 410, the reset transistor 455, the amplification transistor 430, and the selection transistor 440. However, the configuration is not limited to this. For example, the selection transistor 440 may be omitted from the pixel 10, and the pixel 10 may have a 3Tr. type configuration in which the amplification transistor 430 also functions as a selection transistor. In addition, the pixel 10 may have a 5Tr. type or more configuration in which the number of transistors is increased. From the pixel 10, a reset signal when the potential of the node 420 is reset by the reset transistor 455 and the photoelectric conversion element 400 is reset, and a data signal that is a signal level when the photoelectric conversion element 400 performs photoelectric conversion in response to incident light can be output.

[0024] 3 shows an example of a circuit configuration focusing on the sample hold unit 50 and the conversion circuit 60 of the photoelectric conversion device 1000. In FIG. 3, the sample hold circuit and the analog-to-digital conversion circuit of the sample hold unit 50 and the conversion circuit 60 arranged corresponding to one vertical signal line 30 are shown. Two sample hold circuits 210 and 211 that sample and hold the reset signal and the data signal output from each pixel 10 for each pixel 10 are connected as the sample hold unit 50 corresponding to one vertical signal line 30. In addition, one conversion circuit 60 is connected corresponding to one vertical signal line 30.

[0025] The sample-and-hold circuit 210 includes the capacitive elements 120 and 123, and an inverting amplifier 220 which is an output amplifier shared by the capacitive elements 120 and 123. The switches 110 and 113 control the connection between the vertical signal line 30 and the capacitive elements 120 and 123 in accordance with control signals Smp_n1 and Smp_n2. The inverting amplifier 220 can be configured by a combination of a common source circuit and a source follower circuit. The inverting amplifier 220 includes transistors 130, 140, 150, 160, and 230, switches 170, 180, 190, and 193, and a current source 200. The switch 170 is connected between the input and output of the common source circuit configured by the transistors 130, 140, 150, and 160, and is controlled by a control signal Smpa_n. A signal sampled from the inverting amplifier 220 to the sample-and-hold circuit 210 is output in accordance with control signals Hld_n, Hld_n1, and Hld_n2.

[0026] The sample-and-hold circuit 211 may have a configuration similar to that of the sample-and-hold circuit 210. The sample-and-hold circuit 211 includes the capacitive elements 121 and 122, and an inverting amplifier 221 that is an output amplifier shared by the capacitive elements 121 and 122. The switches 111 and 112 control the connection between the vertical signal line 30 and the capacitive elements 121 and 122 in accordance with control signals Smp_s1 and Smp_s2. The inverting amplifier 221 may be configured by a combination of a common-source circuit and a source follower circuit. The inverting amplifier 221 includes transistors 131, 141, 151, 161, and 231, switches 171, 181, 191, and 192, and a current source 201. The switch 171 is connected between the input and output of the common-source circuit configured by the transistors 131, 141, 151, and 161, and is controlled by a control signal Smpa_s. The sampled signal is output from the inverting amplifier 221 to the sample-and-hold circuit 211 in accordance with the control signals Hld_s, Hld_s1, and Hld_s2.

[0027] 3, a resistive element 240 is disposed between the output terminal of the sample and hold circuit 210 and the output terminal of the sample and hold circuit 211. Here, the potential at the output terminal of the sample and hold circuit 210, that is, the potential corresponding to the signal sampled by the sample and hold circuit 210, is taken as V1. Similarly, the potential at the output terminal of the sample and hold circuit 211, that is, the potential corresponding to the signal sampled by the sample and hold circuit 211, is taken as V2. Also, the resistance value of the resistive element 240 is taken as R. By disposing the resistive element 240 between the output terminal of the sample and hold circuit 210 and the output terminal of the sample and hold circuit 211, the current I flowing through the resistive element 240 becomes I=(V1-V2) / R This current I is input to the conversion circuit 60.

[0028] In this case, the current I flowing through the resistance element 240 is proportional to the difference between the potential V1 at the output terminal of the sample and hold circuit 210 and the potential V2 at the output terminal of the sample and hold circuit 211. Therefore, it can be said that the resistance element 240 generates a current corresponding to the difference in signal voltage between the signal held in the sample and hold circuit 210 and the signal held in the sample and hold circuit 211 as a signal to be supplied to the conversion circuit 60. Therefore, the resistance element 240 functions as a differential circuit for outputting a signal indicating the difference between the signal held in the sample and hold circuit 210 of the sample and hold section 50 and the signal held in the sample and hold circuit 211. For example, the above-mentioned reset signal is sampled in the sample and hold circuit 210, and the data signal is sampled in the sample and hold circuit 211. As described above, the current I flowing through the resistance element 240 is proportional to the difference between the potential V1 at the output terminal of the sample and hold circuit 210 and the potential V2 at the output terminal of the sample and hold circuit 211, so that correlated double sampling (CDS) is performed at the stage when the current I is input to the conversion circuit 60. The conversion circuit 60 performs analog-to-digital conversion on a signal (current) indicating the difference between the signal held in the sample-and-hold circuit 210 and the signal held in the sample-and-hold circuit 211.

[0029] In this embodiment, the conversion circuit 60, which is a ΔΣ type analog-to-digital conversion circuit, includes a first integrator, a second integrator, a quantizer 370, and a decimation filter 380. In the conversion circuit 60, the first integrator is composed of an integral capacitance 320. The second integrator is composed of a Gm cell 330 that converts a voltage into a current, and an integral capacitance 360. A digital-to-analog converter 305 including a current source 300 and a switch 310 is connected to the input node of the first integrator. The digital-to-analog converter 305 controls the current to the first integrator in response to the digital signal via the second integrator and the quantizer 370. A digital-to-analog converter 345 including a current source 340 and a switch 350 is connected to the input node of the second integrator. The digital-to-analog converter 345 controls the current of the second integrator in response to the result quantized by the quantizer 370 as the output of the second integrator.

[0030] In the conversion circuit 60, the quantizer 370 performs an operation of feeding back the previous quantized value to the second integrator and the first integrator through the digital-to-analog converters 305 and 345. In this way, a second-order noise shaping characteristic can be obtained by passing the previous quantized value twice through the integrator while feeding it back to the digital-to-analog converters 305 and 345. Furthermore, by removing high-frequency noise with the decimation filter 380 arranged after the quantizer 370, it is possible to obtain an analog-to-digital conversion output with high accuracy.

[0031] 4 shows an example of the operation of each switch of the sample-and-hold circuits 210 and 211. FIG. 4 shows waveforms of the control signals RES and TX of the pixel 10, the potential of the vertical signal line 30, and the control signals Smp_n1, Smp_n2, Smpa_n, Hld_n, Hld_n1, Hld_n2, Smp_s1, Smp_s2, Smpa_s, Hld_s, Hld_s1, and Hld_s2 of the switches of the sample-and-hold circuits 210 and 211. In the waveforms shown in FIG. 4, the corresponding switch is in a conductive state while each control signal is at a high level, and the corresponding switch is in a non-conductive state (off state) while each control signal is at a low level. In addition, in FIG. 4, the operation of one pixel 10 (photoelectric conversion element 400) of interest is described, but the same operation can be performed in each pixel 10 (photoelectric conversion element 400) arranged in the photoelectric conversion unit 5. 4 may be performed simultaneously in the pixels 10 (photoelectric conversion elements 400) arranged in the same row as the pixel 10 (photoelectric conversion element 400) of interest. Also, in the pixels 10 (photoelectric conversion elements 400) arranged in the same column as the pixel 10 (photoelectric conversion element 400) of interest, a similar operation may be performed in order for each row.

[0032] 2 goes high and the reset transistor 455 goes on, resetting the node 420, which is a floating diffusion. In response to the node 420 being reset, the potential of the vertical signal line 30 goes to the level of the reset signal. At time t1, the control signals Smp_n1 and Smpa_n go high, and the switches 110 and 170 in the sample-and-hold circuit 210 go on. Next, at time t3 when the control signal Smpa_n goes from high to low, the potential Vn of the reset signal is sampled and stored in the capacitive element 120 of the sample-and-hold circuit 210. Next, at time t4, the control signal Smp_n1 goes from high to low, the switch 110 goes off, and the capacitive element 120 is disconnected from the vertical signal line 30. Although not shown in FIG. 4, the following description will be given on the assumption that the photoelectric conversion element 400 is reset before time t1 and accumulates electric charges according to the incident light.

[0033] At times t5 to t6, the control signal TX shown in FIG. 2 goes high and the transfer transistor 410 goes on, so that charges are transferred from the photoelectric conversion element 400 to the node 420, which is a floating diffusion. The potential of the node 420 drops according to the amount of charges transferred from the photoelectric conversion element 400. As a result, the potential of the vertical signal line 30 drops to the level of the first data signal. At time t5, the control signals Smp_s1 and Smpa_s go high, and in the sample-and-hold circuit 211, the switches 111 and 171 go on. Next, at time t7 when the control signal Smpa_s goes from high to low, the potential Vs1 of the first data signal is sampled and stored in the capacitive element 121. Next, at time t8, the control signal Smp_s1 goes from high to low, the switch 111 goes off, and the capacitive element 121 is disconnected from the vertical signal line 30.

[0034] Here, the voltage applied across the switch 171 when the switch 171 is transitioned to the off state at time t7 is always substantially the same regardless of the potential of the vertical signal line 30. Therefore, it is possible to suppress the occurrence of a gain component error in the potential Vs1 of the first data signal stored in the capacitance element 121 due to charge injection caused by the switch being turned off. Also, when the switch 111 is turned off at time t8, both ends of the capacitance element 121 are in a high impedance state, so that the effect of turning off the switch 111 is unlikely to occur. In this way, it is possible to suppress the gain error in the potential Vs1 of the first data signal.

[0035] In the above-described operation, at time t5, the control signals Smp_n2 and Smpa_n go to high level, and the switches 113 and 170 also go to the on state in the sample-and-hold circuit 210. Next, at time t7 when the control signal Smpa_n transitions from high level to low level, the potential Vs1 of the first data signal is sampled and stored in the capacitive element 123. Next, at time t8, the control signal Smp_n1 transitions from high level to low level, the switch 113 goes to the off state, and the capacitive element 123 is disconnected from the vertical signal line 30. Thus, in this embodiment, the potential Vs1 of the first data signal is sampled in the capacitive element 123 also in the sample-and-hold circuit 210.

[0036] At times t9 to t10, the control signal TX shown in FIG. 2 again goes high and the transfer transistor 410 goes on, so that the charge accumulated in the photoelectric conversion element 400 between times t6 and t10 is further transferred to the node 420, which is a floating diffusion. The potential of the node 420 further drops according to the amount of charge. As a result, the potential of the vertical signal line 30 further drops to the level of the second data signal. At time t9, the control signals Smp_s2 and Smpa_s go high, and the switches 112 and 171 in the sample-and-hold circuit 211 go on. Next, at time t11 when the control signal Smpa_s goes from high to low, the potential Vs2 of the second data signal is sampled and stored in the capacitive element 122. Next, at time t12, the control signal Smp_s2 goes from high to low, the switch 112 goes off, and the capacitive element 122 is disconnected from the vertical signal line 30.

[0037] Here, the voltage applied across the switch 171 when the switch 171 is transitioned to the off state at time t11 is always substantially the same regardless of the potential of the vertical signal line 30. Therefore, no gain component error occurs in the potential Vs2 of the second data signal stored in the capacitance element 122 due to charge injection caused by the switch being turned off. Also, when the switch 112 is turned off at time t12, both ends of the capacitance element 122 are in a high impedance state, so that the effect of turning off the switch 112 is unlikely to occur. In this way, it is possible to suppress the gain error in the potential Vs2 of the second data signal.

[0038] In this manner, the sample and hold unit 50 samples a first data signal based on the charge transferred to the floating diffusion in the capacitance element 123 of the sample and hold circuit 210 and the capacitance element 121 of the sample and hold circuit 211 after the first transfer operation in which the charge is transferred from the photoelectric conversion element 400 to the node 420, which is a floating diffusion, and before the second transfer operation in which the charge is transferred from the same photoelectric conversion element 400 to the node 420 without resetting the node 420 after the first transfer operation. Furthermore, the sample and hold unit 50 samples a second data signal based on the charge transferred to the floating diffusion in the capacitance element 122 of the sample and hold circuit 211 after the second transfer operation. Moreover, as described above, when the node 420 functioning as the floating diffusion is reset, the sample and hold unit 50 samples and holds a reset signal corresponding to the voltage of the reset node 420 in the capacitance element 120 of the sample and hold circuit 210.

[0039] Next, at time t13, the control signals Hld_n1 and Hld_n go to high level and the switches 180 and 190 go to the on state, causing the capacitive element 120 to output the potential Vn of the reset signal in the sample and hold circuit 210. Also, at the same time t13, the control signals Hld_s1 and Hld_s go to high level and the switches 181 and 191 go to the on state, causing the capacitive element 121 in the sample and hold circuit 211 to output the potential Vs1 of the first data signal.

[0040] As described above, a current corresponding to the difference between the potential Vn of the reset signal at the output terminal of the sample and hold circuit 210 and the potential Vs1 of the data signal at the output terminal of the sample and hold circuit 211 is input to the conversion circuit 60. The conversion circuit 60 performs analog-to-digital conversion on the current corresponding to the difference between the potentials Vn and Vs1.

[0041] At time t14, the control signal Hld_n1 goes to a low level, and the switch 190 is turned off. Then, at time t15, the control signal Hld_n2 goes to a high level, and the switch 193 is turned on. As a result, in the sample and hold circuit 210, the capacitive element 123 outputs the potential Vs1 of the first data signal. Also, at time t14, the control signal Hld_s1 goes to a low level, and the switch 191 is turned off. Then, at time t15, the control signal Hld_s2 goes to a high level, and the switch 192 is turned on. As a result, in the sample and hold circuit 211, the capacitive element 122 outputs the potential Vs2 of the second data signal.

[0042] As a result, a current corresponding to the difference between the potential Vs1 of the first data signal at the output terminal of the sample and hold circuit 210 and the potential Vs2 of the second data signal at the output terminal of the sample and hold circuit 211 is input to the conversion circuit 60. The conversion circuit 60 performs analog-to-digital conversion on the current corresponding to the difference between the potentials Vs1 and Vs2.

[0043] In this embodiment, a signal based on charges generated in response to the incidence of light in the photoelectric conversion element 400 during an accumulation time that starts before time t1 and ends at time t6 can be obtained from the result of analog-to-digital conversion of the difference between the potential Vn of the reset signal and the potential Vs1 of the first data signal. Also, a signal based on charges generated in response to the incidence of light in the photoelectric conversion element 400 during an accumulation time from time t6 to t10 can be obtained from the result of analog-to-digital conversion of the difference between the potential Vs2 of the second data signal and the potential Vs1 of the first data signal.

[0044] In this embodiment, not only the difference between the reset signal and the data signal, but also a signal corresponding to the difference between the first data signal and the second data signal, each of which is based on the charge generated in response to the incident light, is obtained. In this way, by obtaining the difference between the data signals and performing AD conversion based on the difference between the data signals, it is possible to read out two signals having different accumulation times, as described above. Signals having different accumulation times may be used, for example, for high dynamic range (HDR) imaging, and the photoelectric conversion device 1000 can be made more highly functional.

[0045] As described above, it is possible to suppress the gain error of the potentials Vs1 and Vs2 of the two data signals. Furthermore, the capacitive element 121 and the capacitive element 122 are arranged in one sample-and-hold circuit 211, and the inverting amplifier 221 is shared, so that it is possible to read out the potentials Vs1 and Vs2 of the two data signals without increasing the power during operation. Similarly, the capacitive element 120 and the capacitive element 123 are arranged in one sample-and-hold circuit 210, and the inverting amplifier 220 is shared, so that it is possible to read out the potential Vn of the reset signal and the potential Vs1 of the first data signal without increasing the power during operation. Furthermore, the sample-and-hold circuit 210 includes the capacitive elements 120 and 123, so that it is possible to perform CDS on both the potentials Vs1 and Vs2 of the two data signals sampled in the two capacitive elements 121 and 122.

[0046] Furthermore, noise can be reduced by performing analog-to-digital conversion on the differential signal between the potential Vs2 of the second data signal and the potential Vs1 of the first data signal. For example, when the potential Vs2 of the second data signal and the potential Vs1 of the first data signal are each analog-to-digital converted and then the difference is obtained, noise caused by the analog-to-digital conversion is increased by √2 times. In other words, in this embodiment, noise caused by the analog-to-digital conversion is reduced to 1 / √2 compared to the case where the difference is obtained after the analog-to-digital conversion.

[0047] Furthermore, by performing analog-to-digital conversion on the difference value between the potential Vs2 of the second data signal and the potential Vs1 of the first data signal, it is possible to reduce the power consumed by the photoelectric conversion device 1000. The signal amplitude of the potential Vs2 of the second data signal is larger than the signal amplitude of the potential Vs1 of the first data signal. Therefore, for example, when the difference between the potential Vs2 of the second data signal and the potential Vn of the reset signal is analog-to-digital converted, the voltage applied to both ends of the resistance element 240 becomes large, and the current input to the conversion circuit 60 becomes large. In that case, for example, the current value of the current source 300 needs to be increased, so that the power consumption increases. On the other hand, in this embodiment, the difference between the potential Vs2 of the second data signal and the potential Vs1 of the first data signal is smaller than the difference between the potential Vs2 of the second data signal and the potential Vn of the reset signal. Therefore, when reading out the difference value between the potential Vs2 of the second data signal and the potential Vs1 of the first data signal, the voltage applied to both ends of the resistance element 240 becomes small, and the current input to the conversion circuit 60 becomes small. Therefore, the current value of the current source 300 can be reduced, and the power consumption of the photoelectric conversion device 1000 can be reduced.

[0048] In addition, a gain is applied to the potentials Vs1 and Vs2 of the two data signals using a common resistor element 240. This makes it easier for the gain fluctuations due to temperature and process variations to be linked in the same direction to the potentials Vs1 and Vs2 of the two data signals. As a result, it is possible to suppress deterioration of the image quality of an HDR image caused by different variations being superimposed on signals corresponding to two different accumulation times.

[0049] Here, in the above description, it has been described that the difference value of two data signals obtained from one pixel 10 (photoelectric conversion element 400) among the plurality of pixels 10 (photoelectric conversion elements 400) arranged in the photoelectric conversion unit 5 is obtained, and then analog-to-digital conversion is performed. However, the above-mentioned operation is not limited to this. For example, the difference between data signals read from the photoelectric conversion elements 400 arranged in different pixels 10 may be obtained. The plurality of photoelectric conversion elements 400 may constitute a plurality of photoelectric conversion element groups each including two or more photoelectric conversion elements. The sample and hold unit 50 samples two or more data signals based on charges generated in response to light incident in each of the plurality of photoelectric conversion element groups for each of the plurality of photoelectric conversion element groups. The pixels 10 in which the photoelectric conversion elements 400 constituting one photoelectric conversion element group that obtains the difference between data signals are arranged may be, for example, pixels 10 adjacent to each other.

[0050] In the above, the configuration in which the two capacitive elements 120 and 123 are arranged in the sample-and-hold circuit 210, and the two capacitive elements 121 and 122 are arranged in the sample-and-hold circuit 211 has been described as an example. However, the present invention is not limited to this. For example, the capacitive elements 122 and 123 may not be arranged, and the capacitive elements 120 and 121 may hold data signals read from the photoelectric conversion elements 400 arranged in the pixels 10 adjacent to each other, and the differential signal between them may be analog-digital converted. In this case, for example, a signal for edge detection can be obtained. Even in such a case of reading, as described above, the noise caused by the analog-to-digital conversion can be reduced to 1 / √2, and reading can be performed with low power. However, in this case, it is difficult to cancel the reset noise generated in the floating diffusion of the pixel 10. Therefore, as for the reset noise, as described above, it is better to take the difference between the signals transferred to the same floating diffusion to suppress it.

[0051] Fig. 5 is a diagram showing a modified example of the pixel 10 shown in Fig. 2. Fig. 6 is a timing chart showing an example of the operation of a photoelectric conversion device 1000 including the pixel 10 shown in Fig. 5. Below, the following description will focus on points that are different from those described above using Figs. 1 to 4, and descriptions of configurations and operations that may be similar will be omitted as appropriate.

[0052] 5, the pixel 10 further includes a photoelectric conversion element 401 and a transfer transistor 411 in addition to the configuration shown in FIG. 2. In the configuration shown in FIG. 5, the pixel 10 is a so-called floating diffusion shared pixel in which the photoelectric conversion element 400 and the photoelectric conversion element 401 are connected to a node 420. The two photoelectric conversion elements 400 and 401 are configured to share the node 420 that functions as a floating diffusion. The pixel 10 shown in FIG. 5 can be said to be a pixel equivalent to two pixels each having one photoelectric conversion element in the vertical direction, for example.

[0053] Here, the photoelectric conversion element 400 and the photoelectric conversion element 401 arranged in the pixel 10 share one node 420 and constitute a photoelectric conversion element group that acquires the difference between data signals as described below. A plurality of pixels 10 are arranged in the photoelectric conversion unit 5. Therefore, it can be said that the photoelectric conversion unit 5 has a plurality of photoelectric conversion element groups each composed of the photoelectric conversion elements 400 and 401, and a plurality of floating diffusions arranged to correspond to each of the plurality of photoelectric conversion element groups.

[0054] The photoelectric conversion element 401 may be, for example, a photodiode similar to the photoelectric conversion element 400. The transfer transistor 411 may have a configuration similar to that of the transfer transistor 410. One of the two main electrodes of the photoelectric conversion element 401 is connected to a ground potential 450. The other of the two main electrodes of the photoelectric conversion element 401 is connected to a node 420 via the transfer transistor 411. A control signal TXA is supplied to the gate electrode of the transfer transistor 410 instead of the above-mentioned control signal TX in order to distinguish it from the control signal TXB supplied to the gate electrode of the transfer transistor 411. The control signals TXA and TXB are supplied to the gate electrodes of the transfer transistors 410 and 411, and the transfer transistors 410 and 411 are turned on in response to the control signals TXA and TXB, whereby the signal charges accumulated in the photoelectric conversion elements 400 and 401 are transferred to the node 420.

[0055] Next, an operation example of the photoelectric conversion device 1000 including the pixel 10 shown in FIG. 5 will be described with reference to a timing chart shown in FIG. 6, focusing on the difference from the operation example shown in FIG. 4. As in the description of FIG. 4, the operation of one photoelectric conversion element group of interest (pixel 10, photoelectric conversion elements 400, 401) will be described, but the same operation can be performed in each photoelectric conversion element group (pixel 10, photoelectric conversion elements 400, 401) arranged in the photoelectric conversion unit 5. In this case, the operation shown in FIG. 4 can be performed simultaneously in the photoelectric conversion element groups (pixel 10, photoelectric conversion elements 400, 401) arranged in the same row as the photoelectric conversion element group of interest (pixel 10, photoelectric conversion elements 400, 401). Furthermore, in photoelectric conversion element groups (pixels 10, photoelectric conversion elements 400, 401) arranged in the same column as the photoelectric conversion element group of interest (pixels 10, photoelectric conversion elements 400, 401), a similar operation can be performed in order for each row.

[0056] 5 goes high and the transfer transistor 410 turns on, transferring charge from the photoelectric conversion element 400 to the node 420 which is a floating diffusion. In the period from time t5 to t8, similarly to the above, a first data signal based on the charge of the photoelectric conversion element 400 is sampled and held in the capacitance element 121 of the sample and hold circuit 211 and the capacitance element 123 of the sample and hold circuit 210 shown in FIG.

[0057] 5 goes high and the transfer transistor 411 turns on, transferring charge from the photoelectric conversion element 401 to the node 420 which is a floating diffusion. During the period from time t9 to t12, a second data signal based on the charges of the photoelectric conversion elements 400 and 401 is sampled and held in the capacitance element 122 of the sample and hold circuit 211 shown in FIG.

[0058] In this way, the sample and hold unit 50 samples a first data signal based on the charge transferred from the photoelectric conversion element 400 to the floating diffusion in the capacitance element 123 of the sample and hold circuit 210 and the capacitance element 121 of the sample and hold circuit 211 after the first transfer operation of transferring charge from the photoelectric conversion element 400 to the node 420 which is a floating diffusion and before the second transfer operation of transferring charge from the same photoelectric conversion element 401 to the node 420 without resetting the node 420 after the first transfer operation. Furthermore, the sample and hold unit 50 samples a second data signal based on the charge transferred from the photoelectric conversion element 400 and the photoelectric conversion element 401 to the floating diffusion in the capacitance element 122 of the sample and hold circuit 211 after the second transfer operation. In addition, similar to the above, when a node 420 functioning as a floating diffusion is reset, the sample and hold unit 50 samples and holds a reset signal corresponding to the voltage of the reset node 420 in the capacitive element 120 of the sample and hold circuit 210.

[0059] After time t13, the difference between the potential Vs1 of the first data signal and the potential Vn of the reset signal is converted from analog to digital by the conversion circuit 60 in the same manner as described above. Also, the difference between the potential Vs2 of the second data signal and the potential Vs1 of the first data signal is converted from analog to digital by the conversion circuit 60. This makes it possible to obtain digital signals based on charges generated in response to light incident on each of the photoelectric conversion elements 400 and 401. By the above-mentioned operation, it becomes possible to read signals from the photoelectric conversion elements 400 and 401 for two rows during a unit read period in which signals are read from one pixel 10, and it becomes possible to speed up signal readout. Also, similar to the operation shown in FIG. 4, by performing analog to digital conversion of the difference signal (difference value) after differential processing between the data signals, it becomes possible to read signals with low noise and low power.

[0060] In the configuration shown in FIG. 5 and the operation shown in FIG. 6, a microlens corresponding to the photoelectric conversion element 400 and a microlens corresponding to the photoelectric conversion element 401 may be arranged separately. This allows the data signal (which may also be called an image signal) to be read out at high speed, as described above. However, this is not limited to this, and the photoelectric conversion element 400 and the photoelectric conversion element 401 may share a microlens. The photoelectric conversion elements 400 and 401 may be, for example, a pair of photodiodes formed under the same microlens, and the pixel 10 may constitute a pixel for detecting a phase difference. In this case, the above-mentioned read operation allows the signal for autofocus (AF) to be read out at high speed, with low noise and low power.

[0061] Also, for example, the photoelectric conversion element 400 and the photoelectric conversion element 401 may have different sensitivities to incident light. For example, the photoelectric conversion elements 400 and 401 may be photodiodes having different areas on which light is incident in order to make the sensitivities different from each other. This enables the above-mentioned HDR imaging.

[0062] The form of the photoelectric conversion device 1000 is not limited to the above-mentioned form. For example, in the photoelectric conversion unit 5 that receives incident light, a plurality of vertical signal lines 30 may be arranged for one pixel column. In this case, a plurality of selection transistors 440 may be arranged in the pixel 10 to select a vertical signal line 30 that outputs a signal from among the plurality of vertical signal lines 30 arranged corresponding to one pixel column. Also, for example, some of the pixels 10 arranged in one pixel column may be connected to one vertical signal line 30, and other parts of the pixels 10 arranged in one pixel column may be connected to another vertical signal line 30. Also, the photoelectric conversion device 1000 may be configured not to include the sample and hold circuits 210 and 211. In this case, a signal corresponding to the difference between the signals output to each of the plurality of vertical signal lines 30 may be input to the conversion circuit 60. The plurality of vertical signal lines 30 from which this difference is obtained may be a plurality of vertical signal lines 30 arranged corresponding to one column of pixels 10. In this case, a signal corresponding to the signal difference between the pixels 10 in a plurality of rows can be obtained. The plurality of vertical signal lines 30 from which the difference is obtained may be a vertical signal line 30 arranged corresponding to the pixels 10 in the first column and a vertical signal line 30 arranged corresponding to the pixels 10 in another second column. In this case, a signal corresponding to the signal difference between the pixels 10 in a plurality of columns can be obtained. That is, two signals each corresponding to a signal charge generated by the photoelectric conversion unit 5 based on incident light may be input to a resistance element 240 functioning as a differential circuit arranged between different vertical signal lines 30.

[0063] As described above, in the photoelectric conversion device 1000, the pixel substrate 1 and the circuit substrate 2 may be laminated. In addition, in the configuration shown in FIG. 1, the current source 40, the sample hold section 50, the conversion circuit 60, the data processing circuit 90, and the output section 100 are described as being arranged on one circuit board 2. However, this is not limited to this, and each element constituting the circuit board 2 may be arranged separately on multiple boards. For example, the circuit board 2 may be a laminate of a board including the current source 40 and the sample hold section 50 and a board including the conversion circuit 60, the data processing circuit 90, and the output section 100. The circuit board 2 may be a laminated board of three or more layers in which each configuration is appropriately distributed and arranged. On the other hand, for example, the pixel substrate 1 and the circuit board 2 may be arranged on one substrate. They may be appropriately arranged according to the specifications required for the photoelectric conversion device 1000. In addition, the configuration of the photoelectric conversion device 1000 may be arranged separately on three or more laminated substrates.

[0064] An application example of the photoelectric conversion device 1000 according to the above embodiment will be described below. Fig. 7 is a schematic diagram of an electronic device EQP equipped with the photoelectric conversion device 1000. Fig. 7 shows a camera as an example of the electronic device EQP. Here, the concept of a camera includes not only a device whose main purpose is to take pictures, but also a device that has a supplementary photography function (for example, a personal computer or a mobile terminal such as a smartphone).

[0065] The photoelectric conversion device 1000 may be a semiconductor chip with a stacked structure in which a photoelectric conversion unit 5 is provided. As shown in FIG. 7, the photoelectric conversion device 1000 is accommodated in a semiconductor package PKG. The package PKG may include a base on which the photoelectric conversion device 1000 is fixed, a cover such as glass facing the photoelectric conversion device 1000, and a conductive connection member such as a bonding wire or bump that connects a terminal provided on the base to a terminal provided on the photoelectric conversion device 1000. The equipment EQP may further include at least one of an optical system OPT, a control device CTRL, a processing device PRCS, a display device DSPL, and a memory device MMRY.

[0066] The optical system OPT forms an image on the photoelectric conversion device 1000, and may be, for example, a lens, a shutter, or a mirror. The control device CTRL controls the operation of the photoelectric conversion device 1000, and may be, for example, a semiconductor device such as an ASIC. The processing device PRCS processes a signal output from the photoelectric conversion device 1000, and may be, for example, a semiconductor device such as a CPU or an ASIC. The display device DSPL may be an EL display device or a liquid crystal display device that displays image data obtained by the photoelectric conversion device 1000. The memory device MMRY is a magnetic device or a semiconductor device that stores image data obtained by the photoelectric conversion device 1000. The memory device MMRY may be a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive. The mechanical device MCHN has a moving part or a propulsion part such as a motor or an engine. The mechanical device MCHN in the camera can drive parts of the optical system OPT for zooming, focusing, and shutter operation. In the device EQP, the image data output from the photoelectric conversion device 1000 is displayed on the display device DSPL, or transmitted to the outside by a communication device (not shown) included in the device EQP. For this reason, the device EQP may include a memory device MMRY and a processing device PRCS.

[0067] A camera incorporating the photoelectric conversion device 1000 can be used as a surveillance camera, or an on-board camera mounted on transportation equipment such as automobiles, railroad cars, ships, aircraft, or industrial robots. In addition, a camera incorporating the photoelectric conversion device 1000 can be used not only in transportation equipment but also in a wide range of equipment that uses object recognition, such as an intelligent transport system (ITS).

[0068] The disclosure of this specification includes the following photoelectric conversion device, electronic device, and substrate.

[0069] (Item 1) A photoelectric conversion unit that receives incident light; a differential circuit to which a first signal and a second signal, each of which corresponds to a signal charge generated by the photoelectric conversion unit based on the incident light, are input, and which outputs a third signal indicating a difference between the first signal and the second signal; an oversampling type conversion circuit that performs analog-to-digital conversion of the third signal; A photoelectric conversion device comprising:

[0070] (Item 2) A plurality of photoelectric conversion elements are arranged in the photoelectric conversion unit, the first signal is a signal based on charges generated in response to light incident on a portion of the plurality of photoelectric conversion elements, 2. The photoelectric conversion device according to item 1, wherein the second signal is a signal based on charges generated in response to light incident on another part of the plurality of photoelectric conversion elements.

[0071] (Item 3) a sample-and-hold unit to which the first signal and the second signal are input and which holds the first signal and the second signal, an output node of the sample-and-hold unit is electrically connected to the differential circuit; The photoelectric conversion unit further includes a plurality of floating diffusions arranged to correspond to the plurality of photoelectric conversion elements, The sample and hold unit includes: after a first transfer operation of transferring charges from a first photoelectric conversion element of interest among the plurality of photoelectric conversion elements to a first floating diffusion of the plurality of floating diffusions corresponding to the first photoelectric conversion element, and before a second transfer operation of transferring charges from the first photoelectric conversion element to the first floating diffusion without resetting the first floating diffusion after the first transfer operation, sampling the first signal based on the charges transferred to the first floating diffusion; 3. The photoelectric conversion device according to claim 2, wherein after the second transfer operation, the second signal based on the charges transferred to the first floating diffusion is sampled.

[0072] (Item 4) A plurality of photoelectric conversion elements are arranged in the photoelectric conversion unit, the plurality of photoelectric conversion elements constitute a plurality of photoelectric conversion element groups each including two or more photoelectric conversion elements; the first signal is a signal based on charges generated in response to light incident on a part of the plurality of photoelectric conversion element groups, The photoelectric conversion device according to item 1, characterized in that the second signal is a signal based on charges generated in response to incident light in another part of the photoelectric conversion element groups among the plurality of photoelectric conversion element groups.

[0073] (Item 5) Each of the plurality of photoelectric conversion element groups includes a first photoelectric conversion element and a second photoelectric conversion element, the first signal is a signal based on an electric charge generated in response to light incident on the first photoelectric conversion element, The photoelectric conversion device described in item 4, characterized in that the second signal is a signal based on charges generated in response to light incident on the first photoelectric conversion element and charges generated in response to light incident on the second photoelectric conversion element.

[0074] (Item 6) a sample-and-hold unit to which the first signal and the second signal are input and which holds the first signal and the second signal, an output node of the sample-and-hold unit is electrically connected to the differential circuit; a plurality of floating diffusions are further arranged in the photoelectric conversion unit so as to correspond to the plurality of photoelectric conversion element groups, The sample and hold unit includes: sampling the first signal based on the charge transferred to the first floating diffusion after a first transfer operation of transferring charge from the first photoelectric conversion element of a photoelectric conversion element group of interest among the plurality of photoelectric conversion element groups to a first floating diffusion of the plurality of floating diffusions corresponding to the photoelectric conversion element group of interest and before a second transfer operation of transferring charge from the second photoelectric conversion element to the first floating diffusion without resetting the first floating diffusion after the first transfer operation; 6. The photoelectric conversion device according to item 5, wherein after the second transfer operation, the second signal based on the charge transferred to the first floating diffusion is sampled.

[0075] (Item 7) 7. The photoelectric conversion device according to item 6, wherein the first photoelectric conversion element and the second photoelectric conversion element share a microlens.

[0076] (Item 8) 7. The photoelectric conversion device according to item 6, wherein the first photoelectric conversion element and the second photoelectric conversion element have different sensitivities to incident light.

[0077] (Item 9) the sample and hold unit samples a fourth signal when the first floating diffusion is reset; The photoelectric conversion device described in any one of items 3 and 6 to 8, characterized in that the conversion circuit further performs analog-to-digital conversion on a fifth signal indicating the difference between the first signal and the fourth signal output by the difference circuit.

[0078] (Item 10) the sample and hold unit comprises: a first sample and hold circuit including a first capacitive element, a second capacitive element, and an output amplifier shared by the first capacitive element and the second capacitive element; and a second sample and hold circuit including a third capacitive element, a fourth capacitive element, and an output amplifier shared by the third capacitive element and the fourth capacitive element; the first signal is held in the first capacitive element and the third capacitive element; the second signal is held in the fourth capacitive element; the fourth signal is held in the second capacitive element; 10. The photoelectric conversion device according to item 9, wherein the differential circuit generates the third signal from the first signal held in the first capacitive element and the second signal held in the fourth capacitive element.

[0079] (Item 11) 11. The photoelectric conversion device according to item 10, wherein the differential circuit generates the fifth signal from the first signal held in the third capacitive element and the fourth signal held in the second capacitive element.

[0080] (Item 12) 12. The photoelectric conversion device according to any one of items 1 to 11, wherein the differential circuit generates, as the third signal, a current corresponding to a difference in signal voltage between the first signal and the second signal.

[0081] (Item 13) 13. The photoelectric conversion device according to any one of items 1 to 12, wherein the conversion circuit includes a ΔΣ analog-to-digital conversion circuit.

[0082] (Item 14) A photoelectric conversion device according to any one of items 1 to 13, A control device for controlling an operation of the photoelectric conversion device; An electronic device comprising:

[0083] (Item 15) A substrate laminated on a substrate provided with a photoelectric conversion unit that receives incident light, a differential circuit to which a first signal and a second signal, each of which corresponds to a signal charge generated by the photoelectric conversion unit based on the incident light, are input, and which outputs a third signal indicating a difference between the first signal and the second signal; an oversampling type conversion circuit that performs analog-to-digital conversion of the third signal; A substrate comprising:

[0084] The invention is not limited to the above-described embodiments, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, the following claims are appended to apprise the public of the scope of the invention. [Explanation of symbols]

[0085] 5: photoelectric conversion section, 50: sample hold section, 60: conversion circuit, 400: photoelectric conversion element, 1000: photoelectric conversion device

Claims

1. A photoelectric conversion unit that receives incident light; a differential circuit that receives a first signal and a second signal, the first signal and the second signal being signals corresponding to signal charges generated by the photoelectric conversion unit based on the incident light, and outputs a third signal indicating a difference between the first signal and the second signal; an oversampling type conversion circuit that performs analog-to-digital conversion of the third signal; A photoelectric conversion device comprising:

2. The photoelectric conversion unit includes a plurality of photoelectric conversion elements, the first signal is a signal based on charges generated in response to light incident on a portion of the plurality of photoelectric conversion elements, 2 . The photoelectric conversion device according to claim 1 , wherein the second signal is a signal based on charges generated in response to light incident on another part of the plurality of photoelectric conversion elements.

3. a sample-and-hold unit to which the first signal and the second signal are input and which holds the first signal and the second signal, an output node of the sample-and-hold unit is electrically connected to the differential circuit; The photoelectric conversion unit further includes a plurality of floating diffusions arranged to correspond to the plurality of photoelectric conversion elements, The sample and hold unit includes: after a first transfer operation of transferring charges from a first photoelectric conversion element of interest among the plurality of photoelectric conversion elements to a first floating diffusion of the plurality of floating diffusions corresponding to the first photoelectric conversion element, and before a second transfer operation of transferring charges from the first photoelectric conversion element to the first floating diffusion without resetting the first floating diffusion after the first transfer operation, sampling the first signal based on the charges transferred to the first floating diffusion; 3. The photoelectric conversion device according to claim 2, wherein after the second transfer operation, the second signal based on the charges transferred to the first floating diffusion is sampled.

4. The photoelectric conversion unit includes a plurality of photoelectric conversion elements, the plurality of photoelectric conversion elements constitute a plurality of photoelectric conversion element groups each including two or more photoelectric conversion elements; the first signal is a signal based on charges generated in response to light incident on a part of the plurality of photoelectric conversion element groups, 2. The photoelectric conversion device according to claim 1, wherein the second signal is a signal based on charges generated in response to incident light in another part of the plurality of photoelectric conversion element groups.

5. Each of the plurality of photoelectric conversion element groups includes a first photoelectric conversion element and a second photoelectric conversion element, the first signal is a signal based on charges generated in response to light incident on the first photoelectric conversion element, The photoelectric conversion device according to claim 4, characterized in that the second signal is a signal based on charges generated in response to light incident on the first photoelectric conversion element and charges generated in response to light incident on the second photoelectric conversion element.

6. a sample-and-hold unit to which the first signal and the second signal are input and which holds the first signal and the second signal, an output node of the sample-and-hold unit is electrically connected to the differential circuit; a plurality of floating diffusions are further arranged in the photoelectric conversion unit so as to correspond to the plurality of photoelectric conversion element groups, The sample and hold unit includes: sampling the first signal based on the charge transferred to the first floating diffusion after a first transfer operation of transferring charge from the first photoelectric conversion element of a photoelectric conversion element group of interest among the plurality of photoelectric conversion element groups to a first floating diffusion of the plurality of floating diffusions corresponding to the photoelectric conversion element group of interest and before a second transfer operation of transferring charge from the second photoelectric conversion element to the first floating diffusion without resetting the first floating diffusion after the first transfer operation; 6. The photoelectric conversion device according to claim 5, wherein the second signal based on the charges transferred to the first floating diffusion is sampled after the second transfer operation.

7. 7. The photoelectric conversion device according to claim 6, wherein the first photoelectric conversion element and the second photoelectric conversion element share a microlens.

8. 7. The photoelectric conversion device according to claim 6, wherein the first photoelectric conversion element and the second photoelectric conversion element have different sensitivities to incident light.

9. The sample and hold unit samples a fourth signal when the first floating diffusion is reset, 4. The photoelectric conversion device according to claim 3, wherein the conversion circuit further performs analog-to-digital conversion on a fifth signal indicating a difference between the first signal and the fourth signal output by the difference circuit.

10. the sample and hold unit comprises: a first sample and hold circuit including a first capacitive element, a second capacitive element, and an output amplifier shared by the first capacitive element and the second capacitive element; and a second sample and hold circuit including a third capacitive element, a fourth capacitive element, and an output amplifier shared by the third capacitive element and the fourth capacitive element; the first signal is held in the first capacitance element and the third capacitance element; the second signal is held in the fourth capacitive element, the fourth signal is held in the second capacitive element; 10. The photoelectric conversion device according to claim 9, wherein the differential circuit generates the third signal from the first signal held in the first capacitive element and the second signal held in the fourth capacitive element.

11. 11. The photoelectric conversion device according to claim 10, wherein the differential circuit generates the fifth signal from the first signal held in the third capacitive element and the fourth signal held in the second capacitive element.

12. 2. The photoelectric conversion device according to claim 1, wherein the difference circuit generates, as the third signal, a current corresponding to a difference in signal voltage between the first signal and the second signal.

13. 2. The photoelectric conversion device according to claim 1, wherein the conversion circuit includes a ΔΣ analog-to-digital conversion circuit.

14. The photoelectric conversion device according to claim 1 , A control device for controlling an operation of the photoelectric conversion device; An electronic device comprising:

15. A substrate laminated on a substrate provided with a photoelectric conversion unit that receives incident light, a differential circuit to which a first signal and a second signal, each of which corresponds to a signal charge generated by the photoelectric conversion unit based on the incident light, are input, and which outputs a third signal indicating a difference between the first signal and the second signal; an oversampling type conversion circuit that performs analog-to-digital conversion of the third signal; A substrate comprising:

Images