Signal amplifier circuit and sensor signal processing unit including the same

Abstract

To make a further investigation with regard to correcting of an input offset voltage of an auto-zero amplifier.SOLUTION: A signal amplifier circuit (X) is an auto-zero signal amplifier circuit includes a first amplifier (1) and a correction circuit (2x). The first amplifier (1) is configured to amplify an input signal (Vin). The correction circuit (2x) is configured to correct a first input offset voltage (Vofs1) of the first amplifier (1). The signal amplifier circuit (X) includes a correction control circuit (5) configured to detect a saturation state of an output signal (Vout) of the first amplifier (1) and to control the correction circuit (2x) to stop a correction operation of the first input offset voltage (Vofs1) of the first amplifier (1).SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present disclosure relates to a signal amplification circuit and a sensor signal processing device including the same. [Background technology]

[0002] 2. Description of the Related Art Conventionally, there are signal amplifier circuits that employ an auto-zero method, and these signal amplifier circuits include a main amplifier, a correction amplifier, and a plurality of capacitors.

[0003] The auto-zero type signal amplifier circuit is configured to switch between the correction amplifier and the signal path of each capacitor to charge and discharge each capacitor, and to correct the input offset voltage of each amplifier using the charging voltage of each capacitor. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2023-006637 A Summary of the Invention [Problem to be solved by the invention]

[0005] Such an auto-zero amplifier leaves room for further consideration in terms of input offset voltage compensation. [Means for solving the problem]

[0006] The signal amplifier circuit disclosed in this specification is an auto-zero type signal amplifier circuit including a first amplifier and a correction circuit. The first amplifier is configured to amplify an input signal. The correction circuit is configured to correct a first input offset voltage of the first amplifier. The signal amplifier circuit includes a correction control circuit configured to detect a saturation state of the output signal of the first amplifier and control the correction circuit to stop the correction operation of the first input offset voltage of the first amplifier.

[0007] The sensor signal processing device disclosed in this specification includes a sensor that generates an input signal, and a signal amplifier circuit having the above-described configuration. Effect of the Invention

[0008] The signal amplifier circuit disclosed in this specification is more suitable for compensating for the input offset voltage.

[0009] Furthermore, according to the sensor signal processing device disclosed in this specification, it is possible to provide a sensor signal processing device that is more suitable for correcting the input offset voltage. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a block diagram showing a signal amplifier circuit of a comparative example in a first state. [Diagram 2] FIG. 2 is a block diagram showing a signal amplifier circuit of a comparative example in the second state. [Diagram 3] FIG. 3 is a graph showing how the output signal changes in response to the differential input signal through feedback control. [Figure 4] FIG. 4 is a timing chart showing the differential input signal, the output signal, the voltage developed across each switch, and the charging voltage of the second capacitor. [Diagram 5] FIG. 5 is a block diagram illustrating a signal amplifier circuit of the present disclosure. [Figure 6] FIG. 6 is a block diagram showing the internal configuration of the first amplifier. [Figure 7] FIG. 7 is a timing chart showing the voltage levels of the differential input signal, the output signal, and the high-side signal, the voltage developed across each switch, and the charging voltage of the second capacitor. [Figure 8] FIG. 8 is a block diagram showing a correction control circuit of the signal amplifier circuit according to the second embodiment. [Figure 9] FIG. 9 is a block diagram showing the sensor module. [Figure 10]FIG. 10 is a block diagram showing a configuration of a current detection amplifier. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] <Comparative Example Signal Amplification Circuit Y> First, a signal amplifier circuit Y will be described as a comparative example (= a configuration to be compared with an embodiment of the present disclosure described later) of the signal amplifier circuit X of the present disclosure with reference to Fig. 1 to Fig. 3. Fig. 1 is a block diagram showing a signal amplifier circuit Y of a comparative example in a first state. Fig. 2 is a block diagram showing a signal amplifier circuit Y of a comparative example in a second state.

[0012] The signal amplifier circuit Y is an integrated circuit (IC [Integrated Circuit]) that integrates multiple elements. As shown in Figures 1 and 2, the signal amplifier circuit Y has multiple external terminals (for example, input terminals INP, INM, and an output terminal OUT in this figure) as means for establishing an electrical connection with the outside.

[0013] The signal amplifier circuit Y inverts and amplifies a differential input signal Vin (=a differential voltage between input signals Vinp and Vinm) supplied to input terminals INP and INM, and outputs an output signal Vout from an output terminal OUT.

[0014] Resistors 20 to 23 are externally attached to the signal amplifier circuit Y. An input signal Vinp is input to an input terminal INP via a resistor 20. An input signal Vinm is input to an input terminal INM via a resistor 21. An output terminal OUT and an input terminal INM are short-circuited via a resistor 22 to form a feedback path according to an output signal Vout. A reference voltage Vref is input to the input terminal INP as a bias voltage via a resistor 23. The signal amplifier circuit Y is described in detail below.

[0015] The signal amplifier circuit Y includes a first amplifier 1 and a correction circuit 2y.

[0016] The first amplifier 1 is an operational amplifier configured to amplify a differential input signal Vin to generate an output signal Vout. The input terminal INP is connected to the non-inverting input terminal (+) of the first amplifier 1, and the input terminal INM is connected to the inverting input terminal (-) of the first amplifier 1. The output of the first amplifier 1 is input to the output terminal OUT.

[0017] An input offset voltage occurs in the first amplifier 1. The input offset voltage of the first amplifier 1 is designated as a first input offset voltage Vofs1.

[0018] The first amplifier 1 has an offset adjustment terminal PT1. The first amplifier 1 has a function of correcting a first input offset voltage Vofs1 based on a voltage input to the offset adjustment terminal PT1.

[0019] The correction circuit 2y is configured to correct the first input offset voltage Vofs1. More specifically, the correction circuit 2y is configured to generate a voltage required for the first amplifier 1 to correct the first input offset voltage Vofs1 and input the voltage to the offset adjustment terminal PT1. More specifically, the correction circuit 2y is configured as follows.

[0020] The correction circuit 2y includes a second amplifier 3, a first capacitor C1, a second capacitor C2, a switch circuit 4y, and a switch controller 15y.

[0021] The second amplifier 3 is an operational amplifier configured to receive a differential input signal and charge and discharge the first capacitor C1 and the second capacitor C2. The second amplifier 3 has an offset adjustment terminal PT2. The second amplifier 3 has a function of correcting its own input offset voltage according to the voltage input to the offset adjustment terminal PT2. Here, the input offset voltage of the second amplifier 3 is referred to as a second input offset voltage Vofs2, and is also shown in FIG. 1 as a schematic representation of the second input offset voltage Vofs2.

[0022] The switch circuit 4y includes switches 40 to 43. The switch circuit 4y is configured to be switchable between a first state and a second state, which will be described later. The switches 40 and 42 are controlled to be turned on / off by a switch control signal SW1, which will be described later. The switches 41 and 43 are controlled to be turned on / off by a switch control signal SW2, which will be described later.

[0023] The non-inverting input terminal (+) of the second amplifier 3 is connected to the input terminal INP via a switch 41. The inverting input terminal (-) of the second amplifier 3 is connected to the input terminal INM. The switch 40 is connected between the non-inverting input terminal (+) of the second amplifier 3 and the inverting input terminal (-) of the second amplifier 3. The output terminal of the second amplifier 3 is connected in parallel to the first capacitor C1 via a switch 42 and to the second capacitor C2 via a switch 43.

[0024] A first terminal of the first capacitor C1 is connected to the offset adjustment terminal PT2. A second terminal of the first capacitor C1 is connected to the ground terminal. A first terminal of the second capacitor C2 is connected to the offset adjustment terminal PT1. A second terminal of the second capacitor C2 is connected to the ground terminal.

[0025] Here, the above-mentioned first state refers to a state (state in FIG. 1) in which the switches 40 and 42 are on and the switches 41 and 43 are off. That is, this is a state in which the non-inverting input terminal (+) and the inverting input terminal (-) of the second amplifier 3 are short-circuited, and the output of the second amplifier 3 is input to the first capacitor C1.

[0026] The second state described above is a state in which the switches 40 and 42 are off and the switches 41 and 43 are on (the state in FIG. 2). In the second state, the input signal Vinp is input to the non-inverting input terminal (+) of the second amplifier 3, and the input signal Vinm is input to the inverting input terminal (-). In other words, the differential input signal of the second amplifier 3 in the second state is the difference voltage between the input signals Vinp and Vinp, that is, the first input offset voltage Vofs1. In addition, the output of the second amplifier 3 is input to the second capacitor C2 and the offset adjustment terminal PT1.

[0027] The switch controller 15y receives a clock signal (not shown) and switches the switch circuit 4y between a first state and a second state. Specifically, the switch controller 15y generates switch control signals SW1 and SW2 and inputs them to the switch circuit 4y. The switch control signal SW1 is a signal that turns on / off both the switches 40 and 42. The switch control signal SW2 is a signal that turns on / off both the switches 41 and 43. When the clock signal is at a high level, the switch controller 15y controls the on / off of the switches 40 to 43 so that the switch circuit 4y is in the first state. Conversely, when the clock signal is at a low level, the switch controller 15y controls the on / off of the switches 40 to 43 so that the switch circuit 4y is in the second state.

[0028] As described above, in the first state, the non-inverting input terminal (+) and the inverting input terminal (-) of the second amplifier 3 are short-circuited. Therefore, the differential input signal of the second amplifier 3 becomes the second input offset voltage Vofs2. As a result, the second amplifier 3 charges and discharges the first capacitor C1 by outputting according to the second input offset voltage Vofs2. The charging voltage of the first capacitor C1 at this time is input to the offset adjustment terminal PT2, so that the second amplifier 3 corrects the second input offset voltage Vofs2 so as to approach zero. After passing through the second state, even in the first state, the first amplifier 1 corrects the first input offset voltage Vofs1 so as to approach zero according to the charging voltage of the second capacitor C2.

[0029] Even in the second state, the charging voltage of the first capacitor C1 is input to the offset adjustment terminal PT2. As a result, the second amplifier 3 maintains a state in which the second input offset voltage Vofs2 is corrected to approximately zero. Therefore, the second amplifier 3 charges and discharges the second capacitor C2 by outputting according to the first input offset voltage Vofs1. At this time, the charging voltage of the second capacitor C2 is input to the offset adjustment terminal PT1, and the first amplifier 1 corrects the first input offset voltage Vofs1 to approach zero.

[0030] In this way, the first input offset voltage Vofs1 can be corrected to approximately zero by alternately switching the switch circuit 4y between the first state and the second state to charge and discharge the first capacitor C1 and the second capacitor C2 while switching the current paths of the first amplifier 1 and the second amplifier 3. This operation of correcting the first input offset voltage Vofs1 to approximately zero by switching the switch circuit 4y between the first state and the second state is also referred to hereinafter as "auto-zero operation (correction operation)."

[0031] <Considerations regarding output saturation> Fig. 3 is a graph showing how the output signal Vout changes according to the differential input signal Vin through feedback control. As shown in Fig. 3, when the voltage level of the differential input signal Vin is within a predetermined range r1, the output signal Vout changes linearly to follow the differential input signal Vin. When the differential input signal Vin is zero, the output signal Vout matches the reference voltage Vref.

[0032] When the voltage value of the differential input signal Vin is within a predetermined range r1, feedback control from the output signal Vout to the input signal Vinm is performed appropriately. When the voltage value of the differential input signal Vin is within the range r1, the above-mentioned correction operations of the first input offset voltage Vofs1 and the second input offset voltage Vofs2 are also performed normally.

[0033] On the other hand, when an excessively large voltage value of the differential input signal Vin is input to the signal amplifier circuit Y (when the voltage level of the differential input signal Vin is in a range r2 outside the range r1 shown in FIG. 3), the output signal Vout becomes saturated. The saturated state is a state in which the output signal Vout does not change and remains at a constant value even if the differential input signal Vin changes. When the output signal Vout becomes saturated, the feedback control is not properly established. In other words, the output signal Vout deviates from the bias point (=reference voltage Vref), and the first input offset voltage Vofs1 is not properly corrected. For this reason, it takes time for the signal amplifier circuit Y to restore the output signal Vout to a normal state.

[0034] 4 is a timing chart showing the differential input signal Vin, the output signal Vout, the switch control signals SW1 and SW2, and the charging voltage of the second capacitor C2. As shown in FIG. 4, the voltage level of the differential input signal Vin can alternately switch between, for example, a first voltage level V1 and a second voltage level V2. The first voltage level V1 belongs to the range r1 shown in FIG. 3 above. On the other hand, the second voltage level V2 belongs to the range r2 (where Vinp>Vinm) shown in FIG. 4. In FIG. 4, the differential input signal Vin is excessively large in the positive direction during the period when the voltage level of the differential input signal Vin is the second voltage level V2 (the period from time t0 to t1 and the period from time t4 to t5).

[0035] As described above, when the differential input signal Vin is excessive, the output signal Vout is saturated and the feedback control is not properly established. Therefore, after the differential input signal Vin falls to the first voltage level V1 at time t1, the output signal Vout does not change and remains constant (= stuck at high level) until time t2. Furthermore, when time t2 arrives, the output signal Vout starts to decrease, but it has undershooted to a voltage value lower than the original bias point. Therefore, it takes a certain time (the time from time t1 to time t3) until the output signal Vout becomes relatively stable at the bias point at time t3. That is, it takes a relatively long time for the output signal Vout to return from the saturated state to the normal state. Note that this figure illustrates an example in which the differential input signal Vin is excessive in the positive direction, but the same problem occurs when the differential input signal Vin is excessive in the negative direction.

[0036] <Signal Amplification Circuit of the Present Disclosure> In response to such problems, the signal amplifier circuit X according to the present disclosure can suppress the time required for the offset correction operation to return to a normal state from being prolonged even when an excessively large differential input signal Vin is input, and can also suppress the occurrence of an error in the output signal Vout. The signal amplifier circuit X according to the present disclosure will be described in detail below. Note that the same reference numerals are used to designate components common to the signal amplifier circuit Y described above, and description thereof will be omitted.

[0037] First, a first embodiment of the signal amplifier circuit X will be described. Fig. 5 is a block diagram showing the signal amplifier circuit X of the present disclosure. The signal amplifier circuit X is an integrated circuit (IC) in which multiple elements are integrated. As shown in Fig. 5, the signal amplifier circuit X has multiple external terminals (for example, input terminals INP, INM, and an output terminal OUT in accordance with this figure) as means for establishing an electrical connection with the outside.

[0038] The signal amplifier circuit X inverts and amplifies a differential input signal Vin (= the difference voltage between the input signals Vinp and Vinm) supplied to the input terminals INP and INM, and outputs an output signal Vout from the output terminal OUT. The output terminal OUT and the input terminal INM are short-circuited to form a feedback path according to the output signal Vout.

[0039] The signal amplifier circuit X includes a first amplifier 1, a correction circuit 2x, and a correction control circuit 5.

[0040] 6 is a block diagram showing the internal configuration of the first amplifier 1. As shown in FIG. 6, the first amplifier 1 includes an input stage 6, a gain stage 7, and an output stage 8.

[0041] The input stage 6 includes a PMOSFET (P-Channel Metal Oxide Semiconductor Field Effect Transistor) whose gate terminal is connected to the non-inverting input terminal (+) and a PMOSFET whose gate terminal is connected to the inverting input terminal (-). The input stage 6 receives the differential input signal Vin, generates an internal signal (=first internal signal), and inputs it to the gain stage 7.

[0042] The gain stage 7 receives the internal signal from the input stage 6 and generates a high-side signal G1 (=second internal signal) and a low-side signal G2 (=second internal signal). More specifically, it is as follows. The gain stage 7 has a high-side driver and a low-side driver. The high-side driver inputs the high-side signal G1 to the gate terminal of a PMOSFET 9, which will be described later. The low-side driver inputs the low-side signal G2 to the gate terminal of an NMOSFET 10, which will be described later.

[0043] The output stage 8 includes a PMOSFET 9 and an NMOSFET 10. The drains of the PMOSFET 9 and the NMOSFET 10 are connected to the output terminal OUT. The output stage 8 generates an output signal Vout according to the high-side signal G1 and the low-side signal G2.

[0044] Returning to FIG. 5, the correction circuit 2x includes a second amplifier 3, a first capacitor C1, a second capacitor C2, and a switch circuit 4x.

[0045] The switch circuit 4x includes switches 40 to 44 and a switch controller 15x. The switch circuit 4x is configured to be switchable between a first state (as described above, the switches 40 and 42 are on and the switches 41 and 43 are off) and a second state (as described above, the switches 40 and 42 are off and the switches 41 and 43 are on).

[0046] The switch 44 is connected between both ends of the second capacitor C2. When the switch 44 is turned on, both ends of the second capacitor C2 are short-circuited. The on / off state of the switch 44 is controlled by a switch control signal SW3, which will be described later.

[0047] The switch controller 15x receives a clock signal (not shown) and switches the switch circuit 4x between a first state and a second state. Specifically, the switch controller 15x generates switch control signals SW1 to SW3 and inputs them to the switch circuit 4x. The switch control signal SW3 is a signal that turns on / off the switch 44. More specifically, it is as follows.

[0048] First, a case will be described where the output level of the correction control circuit 5 described later is low (a state where the correction control circuit 5 has not detected a saturated state of the output signal Vout). In this case, when the clock signal is at a high level, the switch controller 15x controls the on / off of the switches 40 to 44 so that the switch circuit 4x is in the first state. Conversely, when the clock signal is at a low level, the switch controller 15x controls the on / off of the switches 40 to 44 so that the switch circuit 4x is in the second state. When the correction control circuit 5 is outputting a low-level signal, the switch controller 15x keeps the switch 44 off regardless of the voltage level of the clock signal.

[0049] Next, a case where the output level of the correction control circuit 5 described later is at a high level (a state where the correction control circuit 5 detects a saturated state of the output signal Vout) will be described. In this case, the switch controller 15x is in the first state and controls the on / off of the switches 40 to 44 so as to turn on the switch 44.

[0050] The correction control circuit 5 controls the correction circuit 2x so as to detect a saturated state of the output signal Vout of the first amplifier 1 and stop the auto-zero operation. More specifically, the correction control circuit 5 controls the correction circuit 2x as follows.

[0051] The correction control circuit 5 is capable of detecting the saturation state of the output signal Vout by monitoring the high-side signal G1 and the low-side signal G2. When the correction control circuit 5 detects the saturation state of the output signal Vout, it inputs a high-level signal to the switch controller 15x. When the correction control circuit 5 does not detect the saturation state of the output signal Vout, it inputs a low-level signal to the switch controller 15x. More specifically, this is as follows.

[0052] As shown in Fig. 6, the correction control circuit 5 includes comparators COMP1 and COMP2 and an OR gate 11. The correction control circuit 5 is configured such that when an excessively large differential input signal Vin is input (when the output signal Vout is saturated), at least one of the comparators COMP1 and COMP2 generates a high-level output, and when the excessive state of the differential input signal Vin is eliminated, both the comparators COMP1 and COMP2 generate a low-level output. The OR gate 11 receives the outputs of the comparators COMP1 and COMP2, generates a high-level / low-level output, and inputs it to the switch controller 15x. More specifically, it is as follows.

[0053] A first threshold voltage Vth1 (e.g., Vcc-Vth) based on the power supply is input to the non-inverting input terminal (+) of the comparator COMP1. A high-side signal G1 is input to the inverting input terminal (-) of the comparator COMP1. The comparator COMP1 generates a high-level / low-level output according to the result of comparing the high-side signal G1 with the first threshold voltage Vth1.

[0054] The low-side signal G2 is input to the non-inverting input terminal (+) of the comparator COMP2. The ground-referenced second threshold voltage Vth2 is input to the inverting input terminal (-) of the comparator COMP2. The comparator COMP2 generates a high-level / low-level output according to the result of comparing the low-side signal G2 with the second threshold voltage Vth2.

[0055] For example, when the differential input signal Vin is excessively large in the positive direction, the PMOSFET 9 is fully on, the NMOSFET 10 is fully off, and the output signal Vout is saturated. At this time, the high-side signal G1 falls below the first threshold voltage Vth1. As a result, the comparator COMP1 generates a high-level output.

[0056] On the other hand, when the differential input signal Vin is excessively large in the negative direction, the PMOSFET 9 is fully off, the NMOSFET 10 is fully on, and the output signal Vout is saturated. At this time, the low-side signal G2 exceeds the second threshold voltage Vth2. As a result, the comparator COMP2 generates a high-level output.

[0057] 7 is a timing chart showing the differential input signal Vin, the output signal Vout, the voltage levels of the high-side signal G1, the switch control signals SW1-SW3, and the charging voltage of the second capacitor C2. In FIG. 7, the differential input signal Vin is in an excessively large state in the positive direction while the voltage level of the differential input signal Vin is the second voltage level V2 (from time t0 to t1 and from time t4 to t6).

[0058] At time t0, the differential input signal Vin is at the second voltage level V2. That is, the differential input signal Vin is in an excessively large state in the positive direction. At this time, the auto-zero operation described above is stopped, and the switch 44 is in an on state. When time t1 arrives, the differential input signal Vin falls to the first voltage level V1. However, at time t1, the output signal Vout remains at a high level and is in a saturated state.

[0059] At time t2, the high-side signal G1 rises to a high level. Then, the correction control circuit 5 detects the rising edge of the high-side signal G1 (G1>Vth1). Then, the correction control circuit 5 resumes the auto-zero operation at time t3, which is a predetermined time lag (several μs) from time t2. Between time t2 and time t3, the output signal Vout drops to the bias point (=Vref).

[0060] During the period from time t3 to time t4, the switch circuit 4x alternates between the first state and the second state, and the switch 44 is turned off. Therefore, the voltage across each of the switches 40 to 43 alternates between high level and low level.

[0061] When time t4 arrives and the differential input signal Vin rises again to the second voltage level V2 and becomes in an over-large state in the positive direction, the high-side signal G1 falls to the low level. When the correction control circuit 5 detects the fall (G1 < Vth1) of this high-side signal G1, it stops the auto-zero operation at time t5 with a predetermined time lag (several μs) from time t4. That is, the switch circuit 4x becomes in the first state, and the switch 44 is turned on.

[0062] During the short period from time t4 to time t5 when the auto-zero operation stops, although the charging voltage of the first capacitor C1 rises, the charging voltage of the switch 44 drops to the ground level because the switch 44 is turned off. Then, the auto-zero operation is kept stopped until time t6 (the timing when the correction control circuit 5 next detects the fall of the high-side signal G1 and a predetermined time lag is interposed).

[0063] As described above, the auto-zero operation is stopped during the period (time t0 to t1) from when the correction control circuit 5 detects the rise of the high-side signal G1 to when it detects the fall. Therefore, the time (the period from time t1 to time t3) from when the over-large state of the differential input signal Vin is eliminated at time t1 until the output signal Vout follows the differential input signal Vin and falls to the bias point can be made relatively short. Also, the output signal Vout is less likely to generate an undershoot when falling to the bias point. For this reason, the time until the output signal Vout returns to the normal state becomes relatively short, and the offset correction can be quickly restored to normal.

[0064] According to the signal amplifier circuit X of the above embodiment, it is possible to detect that the differential input signal Vin is in an excessively large state by detecting the saturation state of the output signal Vout. Then, the auto-zero operation is stopped when the saturation state of the output signal Vout is detected. That is, when an excessively large differential input signal Vin is input, the auto-zero operation is stopped. This makes it possible to prevent a correction voltage (= the charging voltage of the second capacitor C2) that is not suitable for correcting the first input offset voltage Vofs1 from being input to the offset adjustment terminal PT1. Therefore, it is possible to shorten the time until the output signal Vout becomes normal (a state in which feedback control to the input signal Vinm is operating normally) after the excessive state of the differential input signal Vin is eliminated.

[0065] Furthermore, when the excessive state of the differential input signal Vin is eliminated, the auto-zero operation is resumed. This makes it possible to secure a period for correcting the first input offset voltage Vofs1 to zero. Furthermore, by shortening the time until the output signal Vout becomes normal, the first input offset voltage Vofs1 can be quickly corrected to zero.

[0066] As described above, when the output signal Vout becomes saturated, the switch 44 is turned on and the second capacitor C2 is discharged. Therefore, even if the second capacitor C2 is charged or discharged by the second amplifier 3 for a short period of time when the differential input signal Vin becomes excessive, the charge of the second capacitor C2 is discharged and the charging voltage of the second capacitor C2 can be reduced. This makes it possible to reduce the recovery time of the auto-zero operation after the excessive state of the differential input signal Vin is resolved, while suppressing the input of an inappropriate voltage (more specifically, a voltage that is not suitable for the first amplifier 1 to correct the first input offset voltage Vofs1) to the offset adjustment terminal PT1.

[0067] As described above, when the output signal Vout is saturated, the correction circuit 2x is in the first state. Therefore, even if the differential input signal Vin is in an excessively large state, the second input offset voltage Vofs2 can be corrected. Therefore, after the excessive state of the differential input signal Vin is eliminated, the time required for charging and discharging the second capacitor C2 can be shortened. Note that, although this figure illustrates an example in which the differential input signal Vin is in an excessively large state in the positive direction, the time until the output signal Vout becomes normal can be shortened even when the differential input signal Vin is in an excessively large state in the negative direction.

[0068] Next, a second embodiment of the signal amplifier circuit X will be described. In the following, differences from the first embodiment will be described, and the same configurations as those in the first embodiment will be denoted by the same reference numerals and will not be described. FIG. 8 is a block diagram showing a correction control circuit 5 of the signal amplifier circuit X according to the second embodiment. As shown in FIG. 8, the correction control circuit 5 according to this embodiment includes a level shifter 16 and a saturation state detection circuit 12.

[0069] The level shifter 16 is configured to receive the high-side signal G1 based on the power supply and generate an internal signal G3 (third internal signal) based on the ground.

[0070] The level shifter 16 includes a voltage-current conversion circuit 13 and a resistor 14. The voltage-current conversion circuit 13 is configured to receive a high-side signal G1 and generate a predetermined current signal. The resistor 14 is connected between the output terminal of the voltage-current conversion circuit 13 and the ground terminal. The internal signal G3 is a signal corresponding to the voltage generated across the resistor 14 by the current signal generated by the voltage-current conversion circuit 13.

[0071] The saturation state detection circuit 12 is configured to monitor the internal signal G3 and detect the saturation state of the output signal Vout. Specifically, this is as follows.

[0072] The saturation state detection circuit 12 includes comparators COMP3 and COMP4, and an OR gate 11. Both comparators COMP3 and COMP4 operate with respect to the ground.

[0073] The internal signal G3 is input to the non-inverting input terminal (+) of the comparator COMP3. The ground-referenced second threshold voltage Vth2 is input to the inverting input terminal (-) of the comparator COMP3. The output of the comparator COMP3 is input to the OR gate 11.

[0074] The low-side signal G2 is input to the non-inverting input terminal (+) of the comparator COMP4. The ground-referenced second threshold voltage Vth2 is input to the inverting input terminal (-) of the comparator COMP4. The output of the comparator COMP4 is input to the OR gate 11.

[0075] In the signal amplifier circuit X according to the second embodiment, the current signal generated by the voltage-current conversion circuit 13 is sufficiently reduced, so that the internal signal G3 also has a relatively low voltage. The comparator COMP3 operates based on the ground. This allows the comparator COMP3 to be made of low-voltage elements. This prevents the circuit area of ​​the correction control circuit 5 from becoming large.

[0076] <Sensor signal processing device> Here, the signal amplifier circuit X according to each of the above embodiments can be used as a current detection amplifier in the sensor signal processing device 100. Hereinafter, a sensor module 200 including the sensor signal processing device 100 will be described.

[0077] Fig. 9 is a block diagram showing a sensor module 200. As shown in Fig. 9, the sensor module 200 includes a sensor 101 and a sensor signal processing device 100. The sensor 101 includes a current sense resistor. The sensor signal processing device 100 is a circuit that receives a weak detection signal detected by the sensor 101, amplifies and converts the signal into a signal that can be processed by an MPU [Micro Processor Unit].

[0078] The sensor signal processing device 100 includes a current detection amplifier 103 , an A / D (analog-to-digital) converter 62 , a temperature sensor 63 , a digital block 64 , a D / A (digital-to-analog) section 60 , and a D / A section 65 .

[0079] Fig. 10 is a block diagram showing the configuration of the current detection amplifier 103. As shown in Fig. 10, the current detection amplifier 103 is connected to the sensor 101 and receives the output signal of the sensor 101. The output signal of the sensor 101 is a signal that may fall outside the input dynamic range of the current detection amplifier 103 (more specifically, the signal amplification circuit X). The current detection amplifier 103 generates a current detection signal corresponding to the output current of the sensor 101 (the current to be monitored). The current detection signal corresponds to the above-mentioned differential input signal Vin. Specifically, the current detection amplifier 103 is as follows.

[0080] The current detection amplifier 103 includes a pre-amplifier 104 and a signal amplifier circuit X. The pre-amplifier 104 amplifies the output of the sensor 101 with a predetermined gain to generate input signals Vinp, Vinm, which are input to the signal amplifier circuit X (more specifically, input terminals INP, INM). As described above, the signal amplifier circuit X inverts and amplifies the differential input signal Vin (=the difference voltage between the input signals Vinp, Vinm) supplied to the input terminals INP, INM, and outputs the output signal Vout from the output terminal OUT.

[0081] 9, the A / D converter 62 A / D converts the analog signal (=output signal Vout) input from the signal amplifier circuit X, and outputs the digital signal to the digital block 64. The digital block 64 outputs the output signal Vout, which is a digital signal output from the A / D converter 62, to the MPU 31 as a serial signal.

[0082] The D / A unit 65 performs D / A conversion on the digital signal (a signal based on the output signal Vout) output from the digital block 64 to generate an analog signal, amplifies the analog signal, and outputs a DC voltage. The output DC voltage is input to the MPU.

[0083] The D / A section 60 performs D / A conversion on the digital signal output from the digital block 64 to generate an analog signal, amplifies this analog signal, and inputs it to the sensor 101 as a DC voltage.

[0084] The present invention is not limited to the above-described embodiments, and various modifications are possible without departing from the spirit of the present invention. For example, in the above-described embodiments, the switch controller 15x controls the on / off of the switches 40 to 43 so that the switch circuit 4x is in the first state when a clock signal (not shown) is at a high level, and the switch circuit 4x is in the second state when the clock signal is at a low level. However, the on / off of the switches 40 to 43 may be controlled so that the switch circuit 4x is in the first state when a clock signal (not shown) is at a low level, and the switch circuit 4x is in the second state when the clock signal is at a high level.

[0085] In addition, in the above, an example is given in which the sensor 101 includes a current sensing resistor, but the sensor 101 may be replaced with a pressure sensor, a magnetic sensor, an infrared sensor, or the like.

[0086] <Additional Notes> The signal amplifier circuit (X) disclosed in the specification is an auto-zero type signal amplifier circuit (X) including a first amplifier (1) configured to amplify an input signal (Vin) and a correction circuit (2x) configured to correct a first input offset voltage (Vofs1) of the first amplifier (1), and includes a correction control circuit (5) configured to detect a saturation state of the output signal (Vout) of the first amplifier (1) and control the correction circuit (2x) to stop the correction operation of the first input offset voltage (Vofs1) of the first amplifier (1) (first configuration).

[0087] In addition, the signal amplification circuit (X) having the first configuration may be configured such that the first amplifier (1) includes an input stage (6) that receives an input signal (Vin) and generates a first internal signal, a gain stage (7) configured to receive the first internal signal and generate a second internal signal (G1, G2), and an output stage (8) configured to receive the second internal signal (G1, G2) and generate an output signal (Vout), and the correction control circuit (5) is configured to detect a saturation state of the output signal (Vout) based on the second internal signal (G1, G2) (second configuration).

[0088] In addition, the signal amplifier circuit (X) having the second configuration may be configured so that the correction control circuit (5) includes a level shifter (16) configured to receive a second internal signal (G1, G2) referenced to the power supply and generate a third internal signal referenced to ground, and a saturation state detection circuit (12) configured to detect a saturation state of the output signal (Vout) based on the third internal signal (third configuration).

[0089] In addition, in the signal amplifier circuit (X) having a third configuration, the level shifter (16) includes a voltage-current conversion circuit (13) configured to receive the second internal signal (G1, G2), which is a voltage signal, and generate a predetermined current signal, and a resistor (14) connected between the output terminal of the voltage-current conversion circuit (13) and the ground terminal, and the third internal signal is preferably configured to be a signal corresponding to the voltage generated across the resistor (14) by the current signal (fourth configuration).

[0090] In addition, in the signal amplifier circuit (X) according to any one of the first to fourth configurations, the correction circuit (2x) includes a first capacitor (C1) and a second capacitor (C2), a second amplifier (3) configured to receive a differential input signal and charge and discharge the first capacitor (C1) and the second capacitor (C2), and a switch circuit (4x) configured to switch the charge and discharge states of the first capacitor (C1) and the second capacitor (C2), and the switch circuit (4x) switches the output of the second amplifier (3) while the differential input terminals of the second amplifier (3) are short-circuited. and a second state in which the second capacitor (C2) is charged / discharged by the output of the second amplifier (3) in a state in which an input signal (Vin) is input to the second amplifier (3). The first amplifier (1) may have a function of correcting a first input offset voltage (Vofs1) in accordance with the charging voltage of the second capacitor (C2), and the second amplifier (3) may have a function of correcting a second input offset voltage (Vofs2) of the second amplifier (3) in accordance with the charging voltage of the first capacitor (C1) (fifth configuration).

[0091] In addition, in the signal amplifier circuit (X) having the fifth configuration, the correction control circuit (5) may be configured to control the switch circuit (4x) to discharge the second capacitor (C2) when it detects a saturated state of the output signal (Vout) (sixth configuration).

[0092] In addition, in the signal amplifier circuit (X) having the sixth configuration, when the correction control circuit (5) detects a saturated state of the output signal (Vout), it is preferable to control the switch circuit (4x) to charge and discharge the first capacitor (C1) using the output of the second amplifier (3) while shorting the differential input terminals, and to discharge the second capacitor (C2) (seventh configuration).

[0093] In addition, in the signal amplifier circuit (X) relating to any of the fifth to seventh configurations, the switch circuit (4x) may be configured to repeatedly switch the state of the correction circuit (2x) alternately between the first state and the second state when the correction control circuit (5) has not detected a saturated state of the output signal (Vout) (eighth configuration).

[0094] In addition, the signal amplifier circuit (X) according to any one of the first to eighth configurations may be configured so that the input signal (Vin) is a current detection signal corresponding to the monitored current (ninth configuration).

[0095] In addition, the sensor signal processing device disclosed in the specification may be configured to include a sensor that generates an input signal (Vin) and a signal amplifier circuit (X) having any of the first to ninth configurations (tenth configuration).

[0096] In the signal amplifier circuit (X) according to the first configuration, when the output signal (Vout) is saturated, the correction operation of the first input offset voltage (Vofs1) is stopped. Therefore, even if the input signal (Vin) is excessively large, it is possible to prevent the correction of the first input offset voltage (Vofs1) from becoming inappropriate.

[0097] Moreover, the signal amplifier circuit (X) according to the second configuration can more appropriately detect whether the input signal (Vin) is in an excessively large state.

[0098] Furthermore, in the signal amplifier circuit (X) according to the third configuration, even if the power supply voltage or the output voltage is relatively high, the elements constituting the correction control circuit (5) can be made to have a relatively low withstand voltage, thereby preventing the circuit area of ​​the correction control circuit (5) from becoming large.

[0099] Moreover, the signal amplifier circuit (X) according to the fourth configuration can suitably prevent the circuit area of ​​the correction control circuit (5) from increasing in size.

[0100] Furthermore, the signal amplifier circuit (X) according to the fifth configuration can more suitably prevent the correction of the first input offset voltage (Vofs1) from becoming inappropriate.

[0101] Furthermore, in the signal amplifier circuit (X) according to the sixth configuration, when the output voltage becomes saturated, the second capacitor (C2) is discharged. This causes the charging voltage of the second capacitor (C2) to decrease. This makes it possible to more appropriately stop the correction operation of the first input offset voltage (Vofs1).

[0102] Furthermore, in the signal amplifier circuit (X) according to the seventh configuration, the first capacitor (C1) is charged and discharged by the output of the second amplifier (3) in a state where the differential input is short-circuited. Furthermore, the second capacitor (C2) is discharged, and the correction operation of the first input offset voltage (Vofs1) is stopped. Therefore, the correction operation of the first input offset voltage (Vofs1) can be stopped while the second input offset voltage (Vofs2) remains in a corrected state. This makes it possible to shorten the recovery time of the correction operation when the correction operation of the first input offset voltage (Vofs1) is resumed.

[0103] Moreover, in the signal amplifier circuit (X) according to the eighth configuration, the first input offset voltage (Vofs1) can be suitably corrected by the auto-zero operation.

[0104] Furthermore, with the signal amplifier circuit (X) according to the ninth configuration, even if the current detection signal becomes a relatively high voltage, the recovery time of the correction operation of the first input offset voltage (Vofs1) can be shortened.

[0105] In addition, according to the sensor signal processing device of the tenth configuration, a sensor signal processing device can be provided that is capable of shortening the recovery time of the correction operation of the first input offset voltage (Vofs1) even if the voltage of the input signal (Vin) generated by the sensor becomes excessively high. [Explanation of symbols]

[0106] 1 First Amplifier 2x compensation circuit 2y correction circuit 3. Second Amplifier 4x Switch Circuit 4y Switch circuit 5. Correction control circuit 6 Input Stage 7 Gain Stage 8 Output Stage 11. OR Gate 12 Saturation detection circuit 13 Voltage-current conversion circuit 14 Resistance 15x Switch Controllers 15y Switch Controller 16 Level Shifter 40~44 Switch 60 D / A section 60 D / A Converter 62 A / D Converter 64 Digital Blocks 65 D / A section 100 Sensor signal processing device 101 Sensors 103 Current Sense Amplifier 104 Front-stage amplifier 200 Sensor Module C1 First capacitor C2 Second capacitor COMP1 Comparator COMP2 Comparator COMP3 Comparator COMP4 Comparator G1 High side signal G2 Low Side Signal G3 internal signal INP, INM input terminal OUT Output terminal PT1 Offset adjustment terminal PT2 Offset adjustment terminal SW1 Switch control signal SW2 Switch control signal Vin Differential input signal Vinp Input signal Vofs1 First input offset voltage Vofs2 Second input offset voltage Vout Output signal Vref Reference voltage Vth1 First threshold voltage Vth2 Second threshold voltage X signal amplifier circuit Y signal amplifier circuit r1 Range r2 Range

Claims

1. a first amplifier configured to amplify an input signal; a correction circuit configured to correct a first input offset voltage of the first amplifier; An auto-zero type signal amplifier circuit comprising: a correction control circuit configured to detect a saturation state of the output signal of the first amplifier and control the correction circuit to stop a correction operation of the first input offset voltage of the first amplifier; A signal amplifier circuit comprising:

2. The first amplifier is an input stage receiving the input signal and generating a first internal signal; a gain stage configured to receive the first internal signal and generate a second internal signal; an output stage configured to receive the second internal signal and generate the output signal; Including, 2. The signal amplifier circuit according to claim 1, wherein the correction control circuit detects a saturation state of the output signal based on the second internal signal.

3. The correction control circuit includes: a level shifter configured to receive the second internal signal referenced to a power supply and generate a third internal signal referenced to ground; a saturation detection circuit configured to detect a saturation state of the output signal based on the third internal signal; 3. The signal amplifier circuit of claim 2, comprising:

4. The level shifter includes: a voltage-current conversion circuit configured to receive the second internal signal, which is a voltage signal, and generate a predetermined current signal; A resistor connected between an output terminal and a ground terminal of the voltage-current conversion circuit; Including, 4. The signal amplifier circuit according to claim 3, wherein the third internal signal is a signal corresponding to a voltage generated across the resistor by the current signal.

5. The correction circuit includes: a first capacitor and a second capacitor; a second amplifier configured to receive a differential input signal and charge and discharge the first capacitor and the second capacitor; a switch circuit configured to switch between a charge and discharge state of the first capacitor and the second capacitor; Including, The switch circuit includes: a first state in which the first capacitor is charged / discharged by an output of the second amplifier in a state in which the differential input terminals of the second amplifier are short-circuited; a second state in which the second capacitor is charged / discharged by an output of the second amplifier while the input signal is being input to the second amplifier; Including, the first amplifier has a function of correcting the first input offset voltage in accordance with a charging voltage of the second capacitor; 2. The signal amplifier circuit according to claim 1, wherein the second amplifier has a function of correcting a second input offset voltage of the second amplifier in accordance with a charging voltage of the first capacitor.

6. 6. The signal amplifier circuit according to claim 5, wherein the correction control circuit controls the switch circuit to discharge the second capacitor when the correction control circuit detects a saturated state of the output signal.

7. 7. The signal amplification circuit according to claim 6, wherein when the correction control circuit detects a saturated state of the output signal, the correction control circuit controls the switch circuit to discharge the second capacitor while charging and discharging the first capacitor with the output of the second amplifier with the differential input terminals shorted.

8. 8. The signal amplification circuit according to claim 5, wherein the switch circuit repeatedly switches the state of the correction circuit alternately between the first state and the second state when the correction control circuit does not detect a saturation state of the output signal.

9. 8. The signal amplifier circuit according to claim 1, wherein the input signal is a current detection signal corresponding to a current to be monitored.

10. a sensor generating the input signal; A signal amplifier circuit according to any one of claims 1 to 7; A sensor signal processing device comprising:

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