Compiler, compilation method, and compilation apparatus

Abstract

To improve performance by optimizing software pipelining.SOLUTION: A compilation apparatus 101 acquires performance counter information 130 when executing a loop process 111 in a program 110 by applying software pipelining for reordering instructions in the loop process 111 based on latency information 120. The latency information 120 is the latency of the instruction corresponding to a CPU of the compilation apparatus 101, and indicates an ideal value when there is no problem in executing the instruction at the time of execution. The compilation apparatus 101 specifies the type of instruction in which a waiting time has occurred based on the acquired performance counter information 130. The compilation apparatus 101 increases the value of the latency information 120 of any instruction of the specified type among the instructions in the loop process 111, and applies the software pipelining to create an executable program 150.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a compiler, a compiling method, and a compiling device. [Background technology]

[0002] In conventional HPC (High Performance Computing) applications, most of the execution time is often consumed by a single innermost loop. In such applications, it is expected that the execution time can be reduced by applying a compiler optimization technique to the single innermost loop. Software pipelining, for example, is one of the optimization techniques.

[0003] Prior art techniques include a technique in which a program is executed by a computer to collect profile information, an operation wait time is calculated based on the profile information, and if the operation wait time is longer than a first threshold value and if the SIMD instruction rate in a loop of the program is lower than a second threshold value, a SIMD conversion control line is inserted into the loop of the program to convert the instructions in an IF statement in the loop to SIMD. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2016-40691 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, the conventional technology has a problem in that the effect of optimization achieved by software pipelining may be impaired.

[0006] In one aspect, the present invention aims to improve performance by optimizing software pipelining. [Means for solving the problem]

[0007] In one embodiment, a compiler is provided that acquires performance counter information of a CPU when a loop process in a program is executed by applying software pipelining, which rearranges instructions in the loop process based on latency information of instructions corresponding to the CPU, identifies a type of instruction that has caused a wait time based on the acquired performance counter information, and creates an executable program by applying the software pipelining by increasing a value of latency information for any of the instructions in the loop process that has been identified as being of that type. Effect of the Invention

[0008] Advantageous Effects of Invention According to one aspect of the present invention, there is an effect that performance can be improved by optimizing software pipelining. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram illustrating an example of a compiling method according to the first embodiment. [Diagram 2] FIG. 2 is a block diagram showing an example of a hardware configuration of an information processing device 200 according to the second embodiment. [Diagram 3] FIG. 3 is an explanatory diagram showing a specific example of an input program. [Figure 4] FIG. 4 is an explanatory diagram showing a specific example of the intermediate language representation. [Diagram 5] FIG. 5 is an explanatory diagram showing a specific example of a data dependency graph. [Figure 6] FIG. 6 is an explanatory diagram of an example of the contents of the tuning database information. [Figure 7] FIG. 7 is a block diagram illustrating an example of a functional configuration of an information processing device 200 according to the second embodiment. As shown in FIG. [Figure 8] FIG. 8 is an explanatory diagram showing an example of the operation of the information processing device 200. As shown in FIG. [Figure 9]FIG. 9 is an explanatory diagram (part 1) showing a specific example of performance counter information. [Figure 10] FIG. 10 is a diagram (part 1) illustrating an example of the contents of the tuning work information. [Figure 11] FIG. 11 is a diagram (part 2) of an example of the contents of the tuning work information. [Figure 12] FIG. 12 is an explanatory diagram (part 2) showing a specific example of the performance counter information. [Figure 13] FIG. 13 is a diagram of an example of the contents of the tuning work information (part 3). [Figure 14] FIG. 14 is a diagram of an example of the contents of the tuning work information (part 4). [Figure 15] FIG. 15 is a diagram of an example of the contents of the tuning work information (part 5). [Figure 16] FIG. 16 is an explanatory diagram showing an example of updating the tuning database information. [Figure 17] FIG. 17 is a flowchart (part 1) illustrating an example of a compilation procedure of the information processing device 200 according to the second embodiment. [Figure 18] FIG. 18 is a second flowchart illustrating an example of the compilation procedure of the information processing device 200 according to the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, with reference to the drawings, embodiments of a compiler, a compiling method, and a compiling device according to the present invention will be described in detail.

[0011] (Embodiment 1) Fig. 1 is an explanatory diagram showing an example of a compiling method according to the first embodiment. In Fig. 1, a compiling device 101 is a computer having a function of applying software pipelining to loop processing in a program when compiling the program.

[0012] The program includes a loop process. The loop process is a process (a group of instructions) that is executed repeatedly. The program is, for example, an HPC application that consumes most of the execution time in a single innermost loop. The program is executed repeatedly multiple times, for example, while changing the data or conditions given.

[0013] Software pipelining is one of the optimization techniques used by compilers, and is a technology that aims to improve performance by, for example, rearranging instructions in a loop so that an arithmetic unit of a CPU (Central Processing Unit) can efficiently process the instructions.

[0014] CPUs often have many performance counters implemented inside them. By using performance counters, it is possible to obtain information about various internal CPU states when a certain range of a program is executed. Examples of information that can be obtained by using performance counters include the following:

[0015] - The time when the integer data load command waited for data Time when waiting for floating-point data load instruction occurred - Time when waiting for the result of an integer arithmetic instruction occurs -Time spent waiting for the result of a floating-point operation

[0016] When applying software pipelining to a certain CPU, various information in the CPU data sheet provided by the CPU vendor may be used as a reference. For example, software pipelining uses instruction latency information, which indicates how many cycles it takes for each CPU instruction to produce a result.

[0017] Instruction latency information is often an ideal value when there are no obstacles to the execution of instructions at run time. However, during actual program execution, various factors can cause instruction latency to be longer than expected. This difference in latency can disrupt the steady state assumed by the compiler when applying optimizations, and can degrade the performance of the software pipelining optimization results.

[0018] In addition, modern CPUs have very complex configurations, so it is not possible to describe all the detailed behavior of the hardware in the CPU data sheet provided by the CPU vendor. Furthermore, when compiling a program, it is difficult to anticipate all the situations that may occur during program execution that may increase the latency of instructions.

[0019] As a result, there is a possibility that an increase in instruction latency may occur during program execution, the cause of which is difficult for CPU users to verify. For this reason, in the conventional technology, when software pipelining is applied to an application, the instruction latency assumed at compile time increases at execution time, which reduces the effectiveness of optimization.

[0020] In this embodiment, a compiling method is described that uses information from a CPU's performance counter to prevent a performance drop due to an increase in instruction latency during program execution, thereby improving performance through optimization of software pipelining. Here, an example of processing by the compiling device 101 is described.

[0021] (1) The compiling device 101 acquires performance counter information 130 for a loop process 111 in a program 110 when the loop process 111 is executed by applying software pipelining that rearranges instructions in the loop process 111 based on latency information 120. Here, the program 110 is a program to be compiled.

[0022] The latency information 120 indicates the latency of an instruction corresponding to the CPU of the compiling device 101. The latency is the time it takes to execute an instruction. The latency information 120 indicates an ideal value when there is no failure in the execution of the instruction during execution. The latency information 120 corresponds to, for example, information in a data sheet for the CPU provided by a CPU vendor.

[0023] The performance counter information 130 is information (profile information) of the performance counter of the CPU. The performance counter information is information acquired by using a hardware register present in the CPU, and is information relating to the entire program or a certain range within the program.

[0024] The performance counter information 130 is information about the internal state of the CPU when the loop process 111 in the program 110 is executed. The performance counter information 130 includes, for example, the time when data wait occurred for an integer data load instruction. Note that the time when the wait occurred is, for example, the accumulated time when the wait occurred during execution.

[0025] The performance counter information 130 also includes the time when a data wait for a floating-point data load instruction occurred. The performance counter information 130 also includes the time when a wait for the result of an integer arithmetic instruction occurred. The arithmetic operation is, for example, addition, subtraction, multiplication, division, etc. The performance counter information 130 also includes the time when a wait for the result of a floating-point arithmetic instruction occurred.

[0026] However, although the performance counter information 130 can identify the type of instruction that caused the data wait or result wait, it cannot uniquely identify which instruction it was.

[0027] Specifically, for example, the compiling device 101 applies software pipelining to a loop process 111 in a program 110 based on latency information 120 to create an executable program 140. The executable program 140 is a file (executable format) that includes instructions that can be interpreted by a computer to execute processing. The compiling device 101 then executes the created executable program 140 to obtain performance counter information 130.

[0028] (2) The compiling device 101 identifies the type of instruction for which a wait time has occurred, based on the acquired performance counter information 130. The types of instructions include, for example, an integer data load instruction, a floating-point data load instruction, an integer arithmetic instruction, and a floating-point arithmetic instruction.

[0029] Specifically, for example, the compiling device 101 may identify an instruction type whose latency indicated by the performance counter information 130 is greater than 0. In addition, the compiling device 101 may identify an instruction type whose latency indicated by the performance counter information 130 is equal to or greater than a preset threshold value.

[0030] (3) The compiling device 101 applies software pipelining by increasing the value of the latency information 120 of any of the identified types of instructions among the instructions in the loop process 111 to create an executable program 150. Here, an instruction that has a waiting time can be said to be an instruction whose latency has increased during execution compared to the value assumed in the latency information 120.

[0031] For this reason, it can be said that the specified type of instruction is more likely to improve the performance of the entire program by increasing the latency compared to other instructions. Therefore, the compiling device 101 tunes the optimization result of the software pipelining by increasing the value of the latency information 120 of any of the specified types of instructions by a predetermined increment (e.g., one cycle) to bring it closer to the value at run time.

[0032] For example, assume that an "integer data load instruction" is identified as the type of instruction in which a latency has occurred. It can be said that the type of instruction "integer data load instruction" includes an instruction that is not operating as expected. In this case, the compiling device 101 adjusts the latency information 120 by increasing the value of the latency information 120 of any of the integer data load instructions among the instructions in the loop process 111. Then, the compiling device 101 creates the executable program 150 by applying software pipelining again based on the latency information 120 after the adjustment.

[0033] In this way, the compiling device 101 according to the first embodiment can prevent performance degradation due to an increase in the latency of instructions during execution for the program 110 including the loop process 111, and can improve performance by optimizing software pipelining. For example, the compiling device 101 can narrow down instructions that may not be operating as expected using the performance counter information 130, and increase the latency of the instructions to try to improve performance. Specifically, for example, the compiling device 101 can increase the value of the latency information 120 of any of the integer data load instructions among the instructions in the loop process 111, and apply software pipelining again to try to improve performance.

[0034] (Embodiment 2) Next, the compiling device 101 according to the second embodiment will be described. In the following description, the compiling device 101 is applied to an information processing device 200 as an example. The information processing device 200 is, for example, a server. The information processing device 200 may also be a PC (Personal Computer), a tablet terminal, or the like.

[0035] First, a hardware configuration example of an information processing device 200 according to the second embodiment will be described.

[0036] Fig. 2 is a block diagram showing an example of a hardware configuration of an information processing device 200 according to the second embodiment. In Fig. 2, the information processing device 200 includes a CPU 201, a memory 202, a disk drive 203, a disk 204, a communication I / F (Interface) 205, a portable recording medium I / F 206, and a portable recording medium 207. Each component is connected to each other via a bus 208.

[0037] Here, the CPU 201 is responsible for the overall control of the information processing device 200. The CPU 201 may have multiple cores. The memory 202 has, for example, a read only memory (ROM), a random access memory (RAM), and a flash ROM. Specifically, for example, the flash ROM stores an OS program, the ROM stores an application program, and the RAM is used as a work area for the CPU 201. The programs stored in the memory 202 are loaded into the CPU 201 to cause the CPU 201 to execute the coded processes.

[0038] The disk drive 203 controls reading / writing data from / to the disk 204 under the control of the CPU 201. The disk 204 stores data written under the control of the disk drive 203. The disk 204 is, for example, a magnetic disk, an optical disk, or the like.

[0039] The communication I / F 205 is connected to a network 210 through a communication line, and is connected to an external computer via the network 210. The communication I / F 205 manages the interface between the network 210 and the inside of the device, and controls input and output of data from the external computer. The communication I / F 205 is, for example, a modem or a LAN adapter. The network 210 is, for example, the Internet, a LAN (Local Area Network), or a WAN (Wide Area Network).

[0040] The portable recording medium I / F 206 controls reading / writing of data from / to the portable recording medium 207 under the control of the CPU 201. The portable recording medium 207 stores data written under the control of the portable recording medium I / F 206. The portable recording medium 207 is, for example, a CD (Compact Disc)-ROM, a DVD (Digital Versatile Disk), or a USB (Universal Serial Bus) memory.

[0041] In addition to the above-mentioned components, the information processing device 200 may have, for example, an input device, a display, etc. Also, the information processing device 200 may not have, for example, the portable recording medium I / F 206 and the portable recording medium 207 among the above-mentioned components.

[0042] (Example of input program) Next, a specific example of an input program used by the information processing device 200 will be described.

[0043] Fig. 3 is an explanatory diagram showing a specific example of an input program. In Fig. 3, the input program 300 is a program to be compiled and includes a loop process. For example, the input program 300 is an excerpt of a part of an HPC application. The program 110 shown in Fig. 1 corresponds to the input program 300, for example.

[0044] (Examples of intermediate language representation) Next, a specific example of an intermediate language representation obtained by converting an input program will be described.

[0045] Fig. 4 is an explanatory diagram showing a specific example of an intermediate language representation. In Fig. 4, an intermediate language representation 400 is an intermediate language representation obtained by converting the input program 300 shown in Fig. 3. The conversion from the input program 300 to the intermediate language representation 400 is performed by one function of a compiler.

[0046] In the intermediate language representation 400, i1 to i6 indicate instructions in a loop included in the input program 300. i1 indicates an integer addition instruction. i2 indicates a floating-point data load instruction. i3 indicates a floating-point multiplication instruction. i4 indicates a floating-point subtraction instruction. i5 indicates a floating-point addition instruction. i6 indicates a floating-point data store instruction.

[0047] (Example of data dependency graph) Next, a specific example of a data dependency graph created from the intermediate language representation will be described.

[0048] Fig. 5 is an explanatory diagram showing a specific example of a data dependence graph. In Fig. 5, a data dependence graph 500 is a data dependence graph created from the intermediate language representation 400 shown in Fig. 4. The data dependence graph 500 is a directed graph in which instructions i1 to i6 are represented as nodes 501 to 506, and data dependence relationships and control dependence relationships of the instructions i1 to i6 are represented as edges 511 to 516.

[0049] (Tuning database information storage contents) Next, a description will be given of the stored contents of tuning database information used by the information processing device 200. The tuning database information is information corresponding to a CPU (for example, the CPU 201 shown in FIG. 2).

[0050] Fig. 6 is an explanatory diagram showing an example of the stored contents of tuning database information. In Fig. 6, tuning database information 600 has fields for command, number of trials, and number of improvements, and by setting information in each field, tuning information 600-1 to 600-8 is stored as records.

[0051] Here, the instruction indicates an instruction executed by the CPU 201. iadd is an integer addition instruction. isub is an integer subtraction instruction. imult is an integer multiplication instruction. iload is an integer load instruction. fadd is a floating-point addition instruction. fsub is a floating-point subtraction instruction. fmult is a floating-point multiplication instruction. fload is a floating-point load instruction.

[0052] The number of attempts indicates the number of attempts to improve performance by increasing instruction latency and applying software pipelining. The number of improvements indicates the number of times performance was improved by increasing instruction latency and applying software pipelining.

[0053] For example, the tuning information 600-1 indicates the number of attempts "2000" and the improvement amount "40" when trying to improve performance by increasing the latency of the instruction "iadd" and applying software pipelining. In this case, the improvement rate is 0.02 (=40 / 2000).

[0054] (Example of functional configuration of information processing device 200) Next, an example of a functional configuration of the information processing device 200 according to the second embodiment will be described.

[0055] FIG. 7 is a block diagram showing an example of a functional configuration of the information processing device 200 according to the second embodiment. In FIG. 7, the information processing device 200 includes a receiving unit 701, an optimizing unit 702, an executing unit 703, an adjusting unit 704, an output unit 705, and a storage unit 710. The receiving unit 701 to the output unit 705 are functions that become the control unit 700, and specifically, the functions are realized by making the CPU 201 execute a program (a compiler that tunes software pipelining) stored in a storage device such as the memory 202, the disk 204, or the portable recording medium 207 shown in FIG. 2, or by the communication I / F 205. The processing results of each functional unit are stored in a storage device such as the memory 202 or the disk 204. The storage unit 710 is realized by a storage device such as the memory 202 or the disk 204. Specifically, for example, the storage unit 710 stores the tuning database information 600 as shown in FIG. 6.

[0056] The receiving unit 701 receives an input program. Here, the input program is a program (source program) including a loop process. The input program is, for example, the input program 300 shown in FIG.

[0057] Specifically, for example, the reception unit 701 receives an input program from another computer, thereby receiving the received input program. The other computer is, for example, a PC or a tablet terminal used by a user. The reception unit 701 may also receive the input program by a user's operation input using an input device (not shown).

[0058] The optimization unit 702 creates an executable program by applying software pipelining to the loop processing in the received input program, which rearranges instructions in the loop processing based on latency information of instructions corresponding to the CPU 201.

[0059] Here, the latency information indicates the latency of an instruction corresponding to the CPU 201. The latency is the time it takes to execute an instruction, and is expressed, for example, by the number of cycles. The latency information is, for example, input in advance and stored in a storage device such as the memory 202 or the disk 204. An executable program is a file that includes instructions that can be interpreted by a computer to execute a process.

[0060] Specifically, for example, the optimization unit 702 converts the received input program 300 into an intermediate language representation 400 as shown in Fig. 4 for applying optimization. Next, the optimization unit 702 creates a data dependency graph 500 as shown in Fig. 5 from the converted intermediate language representation 400.

[0061] Then, the optimization unit 702 applies software pipelining to the intermediate language representation 400 based on the intermediate language representation 400 and the data dependency graph 500 to create an executable program. In software pipelining, instructions in a loop are rearranged based on latency information of instructions corresponding to the CPU 201 so that they can be efficiently processed by the arithmetic unit of the CPU 201.

[0062] Note that the specific processing content of software pipelining is omitted here because it is an existing technology. For software pipelining, for example, refer to the non-patent document "Ikuo Nakata, Compiler Structure and Optimization (2nd Edition), Asakura Publishing, 2009, pp. 383-386."

[0063] The execution unit 703 executes the created executable program. At this time, the execution unit 703 measures, for example, the execution time of the executable program. The execution time is the time from when the execution of the executable program starts to when it ends. The execution time of the executable program differs depending on, for example, how instructions are arranged in software pipelining.

[0064] The adjustment unit 704 acquires performance counter information as a result of execution of the executable program. Then, the adjustment unit 704 adjusts the value of latency information of the instruction corresponding to the CPU 201 based on the acquired performance counter information. Here, the performance counter information is information of the performance counter of the CPU 201.

[0065] The performance counter information includes information that can identify the type of instruction that has caused a wait time during execution. The performance counter information includes, for example, the time when a data wait occurred for an integer data load instruction. The performance counter information also includes the time when a data wait occurred for a floating-point data load instruction.

[0066] The performance counter information also includes the time when the result of an integer arithmetic instruction is waited for. The performance counter information also includes the time when the result of a floating-point arithmetic instruction is waited for. Specific examples of the performance counter information will be described later with reference to FIGS. 9 and 14.

[0067] Specifically, for example, the adjustment unit 704 identifies the type of instruction that has generated the latency based on the acquired performance counter information. Then, the adjustment unit 704 increases the value of latency information of any of the identified types of instructions in the loop process included in the input program.

[0068] The types of instructions include, for example, an integer data load instruction, a floating-point data load instruction, an integer arithmetic instruction, and a floating-point arithmetic instruction. An instruction that has a waiting time may have an incorrect latency estimate. However, the instruction that has a waiting time cannot be uniquely identified from the performance counter information.

[0069] Therefore, the adjustment unit 704 narrows down the commands for which the latency (value indicated by the latency information) is to be adjusted by identifying the type of command for which a latency has occurred.

[0070] To explain in more detail, for example, the adjustment unit 704 may identify the type of instruction whose waiting time indicated by the performance counter information is greater than 0 seconds. Also, the adjustment unit 704 may identify the type of instruction whose waiting time indicated by the performance counter information is equal to or greater than a threshold value. The threshold value can be set arbitrarily, and may be set to, for example, 1 second. Also, there may be a case where there are multiple types of instructions that generate waiting times. In this case, the adjustment unit 704 may identify, for example, the type of instruction whose waiting time is the longest.

[0071] Next, the adjustment unit 704 selects one of the identified types of instructions. The selection of the instruction may be performed randomly, for example. Alternatively, in order to adjust the latency and tune the optimization result of the software pipelining to improve the probability of improving the performance, the adjustment unit 704 may select the instruction as follows:

[0072] For example, the adjustment unit 704 may select an instruction of a specified type and with a high improvement rate from among the instructions in the loop processing by referring to the storage unit 710. The storage unit 710 stores information representing an improvement rate when an attempt is made to improve performance by increasing the latency of the instruction and applying software pipelining, in association with the instruction executed by the CPU 201.

[0073] More specifically, for example, the adjustment unit 704 refers to the tuning database information 600 and calculates the improvement rate of each of the identified types of instructions among the instructions in the loop processing. The improvement rate can be calculated, for example, by dividing the number of improvements by the number of trials. Then, the adjustment unit 704 selects the instruction with the highest calculated improvement rate.

[0074] The adjustment unit 704 may also detect an instruction sequence that is a critical path based on the input program. Here, a critical path is an instruction sequence that has a large effect on performance. For example, the adjustment unit 704 may refer to a data dependency graph created based on the input program and detect an instruction sequence with the largest number of hops as an instruction sequence that is a critical path. Then, the adjustment unit 704 may select any of the identified types of instructions from the detected instruction sequences.

[0075] Furthermore, the adjustment unit 704 may refer to the storage unit 710 and select an instruction of the specified type from the detected instruction sequence that has a high improvement rate. To explain in more detail, for example, the adjustment unit 704 refers to the tuning database information 600 and calculates the improvement rate of each instruction of the specified type from the detected instruction sequence. Then, the adjustment unit 704 selects the instruction with the highest calculated improvement rate.

[0076] Then, the adjustment unit 704 increases the value of the latency information of the selected instruction. More specifically, for example, the adjustment unit 704 increases the value of the latency information of the selected instruction by a predetermined increment. The predetermined increment can be set arbitrarily, and is set to a time such as one cycle.

[0077] In addition, as a result of adjusting the value of the latency information of the identified type of instruction, the optimization unit 702 creates an executable program by applying software pipelining again to the loop processing in the input program based on the latency information of the instruction corresponding to the adjusted CPU 201.

[0078] Furthermore, the execution unit 703 executes the created executable program. Then, the adjustment unit 704 judges whether or not the performance has improved as a result of executing the executable program. The performance is the execution performance of the input program. The performance is judged, for example, by the execution time of the executable program.

[0079] Specifically, for example, the adjustment unit 704 determines that the performance has improved when the execution time of the currently created executable program is shorter than the execution time of the previously created executable program. Furthermore, when the adjustment unit 704 determines that the performance has improved, it may set the currently created executable program as the latest executable program.

[0080] On the other hand, if the execution time of the currently created executable program is equal to or longer than the execution time of the previously created executable program, the adjustment unit 704 determines that the performance has not improved. Also, if the adjustment unit 704 determines that the performance has not improved, it may delete the currently created executable program and make the previously created executable program the latest executable program.

[0081] Furthermore, the adjustment unit 704 may update the information representing the improvement rate corresponding to the instruction whose latency information value has been adjusted, stored in the storage unit 710, based on the result of the determination. For example, assume that the performance has improved as a result of adjusting the latency information value of a certain instruction. In this case, the adjustment unit 704 increments the number of trials and the number of improvements in the tuning database information 600 corresponding to that instruction.

[0082] On the other hand, if the latency information value of a certain instruction is adjusted and the performance does not improve, the adjustment unit 704 increments only the trial count in the tuning database information 600 corresponding to that instruction. As a result, the adjustment unit 704 updates the information indicating the improvement rate for the instruction whose latency information value has been adjusted.

[0083] Here, it is assumed that the performance is improved as a result of executing the created executable program. In this case, the information processing device 200 may repeatedly execute a series of processes for increasing the latency of instructions and applying software pipelining while maintaining the state in which the value of the latency information of the instructions is increased.

[0084] Also, suppose that the created executable program is executed and the performance is not improved, in which case the information processing device 200 may return to a state in which the value of the latency information of the instruction is not increased, and may repeatedly execute a series of processes in which the latency of the instruction is increased and software pipelining is applied.

[0085] Specifically, for example, when the performance is improved as a result of executing the created executable program, the adjustment unit 704 maintains the state in which the value of the latency information of the instruction is increased. Next, the adjustment unit 704 acquires performance counter information, and identifies the type of instruction that has generated the latency time based on the acquired performance counter information.

[0086] Then, the adjustment unit 704 increases the value of the latency information of any of the instructions of the specified type among the instructions in the loop processing. As a result of adjusting the value of the latency information of the instruction of the specified type, the optimization unit 702 creates an executable program by applying software pipelining again to the loop processing in the input program based on the latency information of the instruction corresponding to the adjusted CPU 201.

[0087] Next, the execution unit 703 executes the created executable program. Then, the adjustment unit 704 judges whether or not the performance has improved as a result of the execution of the executable program. As a result, the information processing device 200 repeatedly executes a series of processes that increase the latency of the instruction and apply software pipelining. The series of processes is repeatedly executed, for example, until the type of the instruction that has caused the wait time can no longer be identified.

[0088] The output unit 705 outputs the created executable program. The output format of the output unit 705 may be, for example, storage in a storage device such as the memory 202 or the disk 204, or transmission to another computer via the communication I / F 205. Specifically, for example, the output unit may output only the latest executable program with improved performance as a result of repeated performance improvements being made to the input program.

[0089] More specifically, for example, the information processing device 200 attempts to improve the performance of the input program until the type of instruction causing the wait time is no longer identified. Then, when the type of instruction causing the wait time is no longer identified, the output unit 705 may output the latest executable program with improved performance.

[0090] (Operation example of information processing device 200) Next, an example of the operation of the information processing device 200 according to the second embodiment will be described. Here, a case where the speed of the input program 300 shown in FIG. 3 is increased by tuning the optimization result of the software pipelining will be described as an example.

[0091] Fig. 8 is an explanatory diagram showing an example of the operation of the information processing device 200. In Fig. 8, the information processing device 200 converts the input program 300 into an intermediate language representation 400 (see Fig. 4), and creates a data dependency graph 500 (see Fig. 5) from the converted intermediate language representation 400.

[0092] The information processing device 200 detects an instruction sequence that is a critical path from the data dependence graph 500. The critical path corresponds to, for example, the longest path in the data dependence graph 500. Here, the instruction sequence "i1→i2→i3→i5→i6" that is the critical path is detected.

[0093] Next, the information processing device 200 refers to the intermediate language representation 400 and the data dependency graph 500, and creates an executable program OP(OUTPUT) by applying software pipelining to the intermediate language representation 400 based on latency information of instructions corresponding to the CPU 201. The latency information is included in, for example, a data sheet for the CPU 201 provided by a CPU vendor or the like.

[0094] Then, the information processing device 200 executes the created executable program OP and measures the execution time of the executable program OP. The information processing device 200 sets the measured execution time as "execution time TBEST". Furthermore, the information processing device 200 acquires performance counter information P at the time of execution of the executable program OP. Here, a specific example of the performance counter information P at the time of the first execution will be described with reference to FIG. 9.

[0095] Fig. 9 is an explanatory diagram (part 1) showing a specific example of performance counter information. In Fig. 9, performance counter information P is information of the performance counter of CPU 201, and is information capable of identifying the type of event (instruction) in which a wait time occurred during execution of executable program OP.

[0096] In the performance counter information P, an integer operation wait indicates the time during which a wait for the result of an integer arithmetic instruction occurs, and a floating-point operation wait indicates the time during which a wait for the result of a floating-point arithmetic instruction occurs.

[0097] In addition, the integer load memory access wait indicates the time when data wait for an integer data load instruction occurs, and the floating-point load memory access wait indicates the time when data wait for a floating-point data load instruction occurs.

[0098] Returning to the explanation of Fig. 8, the information processing device 200 creates initial state tuning work information W from the instruction sequence "i1 → i2 → i3 → i5 → i6" that forms the detected critical path. Here, the stored contents of the tuning work information W will be explained with reference to Fig. 10.

[0099] Fig. 10 is an explanatory diagram (part 1) showing an example of the stored contents of tuning work information. In Fig. 10, the tuning work information W has a latency increment and an implementation state for each instruction i1, i2, i3, and i5 on the critical path. The latency increment indicates a value by which the latency of an instruction is increased.

[0100] Although instruction i6 is on the critical path, it is a data store instruction, and the occurrence of a wait time cannot be identified in the performance counter information P of the example shown in Fig. 9. For this reason, the information processing device 200 does not register instruction i6 in the tuning work information W.

[0101] Here, the implementation state indicates the implementation state of a process that attempts to improve performance by increasing the latency of instructions and applying software pipelining. For example, the implementation state is set to one of N (neutral), C (completed), and a numerical value (current latency increment).

[0102] In the initial state, the latency increment of each of the instructions i1, i2, i3, and i5 is "0." Also, in the initial state, the implementation state of each of the instructions i1, i2, i3, and i5 is "N."

[0103] Returning to the explanation of Fig. 8, the information processing device 200 creates a set I of instructions to be tuned by referring to the performance counter information P and the tuning work information W. Here, the set I of instructions to be tuned is set to instructions that are on the critical path (tuning work information W) and that are related to the type of event causing the longest waiting time in the performance counter information P.

[0104] 9, the type of event that has the most waiting time is floating-point operation wait (waiting for the result of a floating-point operation instruction). Therefore, the set I of instructions to be tuned is as follows:

[0105] I={i3,i5}

[0106] Next, the information processing device 200 refers to the tuning database information 600 (see FIG. 6) and selects an instruction J to be tuned from the set I of instructions to be tuned. Here, it is assumed that an instruction with the highest improvement rate (an instruction with the highest probability of contributing to performance improvement) is selected from the set I of instructions to be tuned.

[0107] Here, the instruction i3 is fmult (floating-point multiplication instruction). Therefore, the improvement rate of the instruction i3 is "0.1 (=100 / 1000)" according to the tuning information 600-7. Moreover, the instruction i5 is fadd (floating-point addition instruction). Therefore, the improvement rate of the instruction i5 is "0.03 (≈100 / 3000)" according to the tuning information 600-5.

[0108] As a result, the instruction with the highest improvement rate among the set I of instructions to be tuned is instruction i3. Also, in the tuning work information W shown in Fig. 10, the implementation state of instruction i3 is not C (completed). Therefore, instruction i3 is selected as instruction J to be tuned.

[0109] It should be noted that, when set I of instructions to be tuned contains only one instruction, for example, that instruction is selected without considering the improvement rate.

[0110] Next, in order to verify whether performance improves when the latency of instruction i3 is increased by 1, the information processing device 200 creates tuning work information WT as shown in FIG. 11 from the tuning work information W shown in FIG. 10.

[0111] Fig. 11 is an explanatory diagram (part 2) showing an example of the stored contents of tuning work information. In Fig. 11, in the tuning work information WT, "1", which indicates an increment in latency, is set in the implementation state of instruction i3. The number set in the implementation state is a tentative value, not a fixed value as the latency increment.

[0112] Next, the information processing device 200 refers to the intermediate language representation 400, the data dependence graph 500, and the tuning work information WT, and applies software pipelining to the intermediate language representation 400 to generate an executable program WOP (WOUTPUT).

[0113] In this case, when applying software pipelining, the information processing device 200 applies optimization by adding the values ​​in the latency increment column and the implementation status column of each instruction i1, i2, i3, i5 in the tuning work information WT to the latency of each instruction i1, i2, i3, i5. The latency (original value) of each instruction i1, i2, i3, i5 is a value indicated by latency information provided by a CPU vendor or the like.

[0114] Then, the information processing device 200 executes the created executable program WOP and measures the execution time T. Furthermore, the information processing device 200 acquires performance counter information PT during execution of the executable program WOP.

[0115] Next, the information processing device 200 compares the execution time TBEST with the execution time T. Here, it is assumed that the execution time T is smaller than the execution time TBEST. This means that the executable program WOP has better performance than the executable program OP, and the performance has been improved by increasing the latency of the instruction i3 and applying software pipelining.

[0116] In this case, the information processing device 200 sets the executable program WOP as the executable program OP, the execution time T as the execution time TBEST, and further sets the performance counter information PT as the performance counter information P. Here, a specific example of the performance counter information P at the time of the second execution will be described with reference to Fig. 12.

[0117] 12 is an explanatory diagram (part 2) showing a specific example of performance counter information. In the example of Fig. 12, the waiting times for Integer operation wait, Floating-point operation wait, and Integer load memory access wait are set to 0.

[0118] Furthermore, the information processing device 200 creates new tuning work information W as shown in FIG. 13 from the tuning work information WT shown in FIG.

[0119] Fig. 13 is an explanatory diagram (part 3) showing an example of the stored contents of tuning work information. In Fig. 13, in tuning work information W, for instruction i3, the implementation state value "1" of instruction i3 in tuning work information WT shown in Fig. 11 is added to the latency increment, and the implementation state is changed to "N".

[0120] Then, the information processing device 200 implements further performance improvement. First, the information processing device 200 refers to the performance counter information P and the tuning work information W to create a set I of instructions to be tuned.

[0121] In the performance counter information P shown in Figure 12, the only type of event that is causing a wait is floating-point load memory access wait (waiting for data for a floating-point data load instruction). Therefore, the set I of instructions to be tuned is as follows:

[0122] I={i2}

[0123] 13, the implementation state of instruction i2 is not C (completed). Therefore, the information processing device 200 selects instruction i2 as instruction J to be tuned.

[0124] Next, in order to verify whether performance improves when the latency of instruction i2 is increased by 1, the information processing device 200 creates tuning work information WT as shown in FIG. 14 from the tuning work information W shown in FIG. 13.

[0125] 14 is a diagram (part 4) showing an example of the stored contents of tuning work information. In Fig. 14, in the tuning work information WT, "1" indicating an increment in latency is set in the execution state of instruction i2.

[0126] Next, the information processing device 200 refers to the intermediate language representation 400, the data dependence graph 500, and the tuning work information WT, and applies software pipelining to the intermediate language representation 400 to generate an executable program WOP (WOUTPUT).

[0127] In this case, when applying software pipelining, the information processing device 200 applies optimization by adding the values ​​of the latency increment column and the implementation status column of each instruction i1, i2, i3, and i5 in the tuning work information WT to the latency of each instruction i1, i2, i3, and i5.

[0128] Then, the information processing device 200 executes the created executable program WOP and measures the execution time T. Furthermore, the information processing device 200 acquires performance counter information PT during execution of the executable program WOP.

[0129] Next, the information processing device 200 compares the execution time TBEST with the execution time T. Here, it is assumed that the execution time T is greater than the execution time TBEST. This means that the executable program OP has better performance than the executable program WOP, and the performance was not improved even if software pipelining was applied by increasing the latency of the instruction i2.

[0130] In this case, the information processing device 200 creates new tuning work information W as shown in FIG. 15 from the tuning work information WT shown in FIG.

[0131] Fig. 15 is an explanatory diagram (part 5) showing an example of the stored contents of tuning work information. In Fig. 15, in tuning work information W, the implementation state for instruction i2 has been changed to "C." Here, because performance improvement has failed, the implementation state value "1" for instruction i2 in tuning work information WT shown in Fig. 14 is not added to the latency increase.

[0132] Then, the information processing device 200 implements further performance improvement. First, the information processing device 200 creates a set I of instructions to be tuned by referring to the performance counter information P and the tuning work information W. Here, since the performance counter information P remains as shown in FIG. 12, the set I of instructions to be tuned is the same as the previous time, as follows:

[0133] I={i2}

[0134] 15, the implementation state of instruction i2 is C (completed). Therefore, the information processing device 200 does not select instruction i2 as an instruction J to be tuned. Also, there are no instructions for which a waiting time has occurred other than instruction i2, whose performance has already been improved.

[0135] Therefore, the information processing device 200 does not implement any further performance improvements. In this case, the information processing device 200 updates the tuning database information 600 by referring to the tuning work information W shown in FIG.

[0136] 15, the value for increasing the latency to 1 is "1", so it can be seen that for instruction i3, the number of attempts is 1 and the number of improvements is 1. Therefore, the information processing device 200 increments (+1) each of the values ​​of the number of attempts and the number of improvements for the instruction "fmult" in the tuning database information 600.

[0137] 15, it can be seen that for instruction i2, the latency increment is "0", so the number of attempts is 1 and the number of improvements is 0. Therefore, the information processing device 200 increments (+1) the value of the number of attempts for the instruction "fload" in the tuning database information 600.

[0138] Fig. 16 is an explanatory diagram showing an example of updating the tuning database information. In Fig. 16, the number of trials and the number of improvements for tuning information 600-7 in tuning database information 600 have each increased by 1 compared to the cases shown in Fig. 6. Also, the number of trials for tuning information 600-8 in tuning database information 600 has increased by 1 compared to the cases shown in Fig. 6.

[0139] Finally, the information processing device 200 outputs the executable program OP with the best performance as the optimization result of the software pipelining, and ends the series of processes. In this way, the information processing device 200 can improve the performance of the input program 300 by tuning the optimization result of the software pipelining.

[0140] For example, when a user repeatedly executes the input program 300 while changing the data or conditions to be provided, the user can use the output executable program OP to significantly reduce the execution time of the input program 300.

[0141] In this embodiment, the executable program OP is output as the final output, but the present invention is not limited to this. For example, the information processing device 200 may output tuning work information W as shown in Fig. 15 in association with the input program 300 (source program) as the final output. This allows the information processing device 200 to specify which instruction's latency should be increased to apply software pipelining when executing the input program 300 in the information processing device 200 itself or in another computer having the same CPU configuration as the information processing device 200 itself.

[0142] (Compilation process procedure of information processing device 200) Next, the compilation procedure of the information processing device 200 will be described.

[0143] 17 and 18 are flowcharts showing an example of a compilation procedure of the information processing device 200 according to the second embodiment. In the flowchart of Fig. 17, the information processing device 200 first determines whether an input program to be compiled has been received (step S1701). Here, the information processing device 200 waits for the input program to be received (step S1701: No).

[0144] If the information processing device 200 accepts an input program (step S1701: Yes), the information processing device 200 converts the input program into an intermediate language representation (step S1702). Next, the information processing device 200 creates a data dependency graph from the converted intermediate language representation (step S1703).

[0145] The information processing device 200 then detects an instruction sequence that is a critical path from the created data dependence graph (step S1704). The detected instruction sequence is an instruction in a loop process included in the input program. Next, the information processing device 200 refers to the intermediate language representation and the data dependence graph, and creates an executable program OP(OUTPUT) by applying software pipelining to the intermediate language representation based on latency information of instructions corresponding to the CPU 201 (step S1705).

[0146] Then, the information processing device 200 executes the created executable program OP (step S1706). Next, the information processing device 200 acquires the execution time of the executed executable program OP (hereinafter, referred to as "execution time TBEST") and performance counter information P at the time of execution (step S1707).

[0147] Then, information processing device 200 creates initial state tuning work information W from the instruction sequence that is the detected critical path (step S1708), and proceeds to step S1801 shown in FIG.

[0148] 18, first, the information processing device 200 creates a set I of instructions to be tuned by referring to the performance counter information P and the tuning work information W (step S1801). Specifically, for example, the information processing device 200 creates, as the set I of instructions to be tuned, a set of instructions that are on the critical path (tuning work information W) and that are related to the type of event causing the longest waiting time in the performance counter information P.

[0149] Next, the information processing device 200 refers to the created set of instructions I and the tuning work information W to determine whether or not there is an instruction that should be tuned (step S1802). Specifically, for example, the information processing device 200 determines that there is an instruction that should be tuned when there is an instruction that is included in the set of instructions I and has an implementation state of N in the tuning work information W.

[0150] Here, if there is an instruction to be tuned (step S1802: Yes), the information processing device 200 selects an instruction J to be tuned from the set of instructions I (step S1803). Specifically, for example, the information processing device 200 refers to the tuning database information 600 and selects an instruction with the highest improvement rate from the set of instructions I.

[0151] Next, in order to verify whether performance improves when the latency of the selected instruction J is increased (step S1804), the information processing device 200 creates tuning work information WT from the tuning work information W. In the tuning work information WT, for example, "1" indicating the latency increment is set to the implementation state of instruction J.

[0152] Then, the information processing device 200 refers to the intermediate language representation, the data dependency graph, and the tuning work information WT, and applies software pipelining to the intermediate language representation to create an executable program WOP (WOUTPUT) (step S1805). At this time, when applying software pipelining, the information processing device 200 applies optimization by adding the values ​​in the latency increment column and the implementation status column of each instruction in the tuning work information WT to the latency of each instruction.

[0153] Next, the information processing device 200 executes the created executable program WOP (step S1806). Then, the information processing device 200 acquires the execution time T of the executed executable program WOP and performance counter information PT at the time of execution (step S1807).

[0154] Next, information processing device 200 determines whether execution time TBEST is greater than execution time T (step S1808). If execution time TBEST is greater than execution time T (step S1808: Yes), information processing device 200 sets executable program WOP to executable program OP, execution time T to execution time TBEST, and performance counter information PT to performance counter information P (step S1809).

[0155] Then, information processing device 200 adds the implementation state value of instruction J in tuning work information WT to the latency increment, changes the implementation state of instruction J to "N", creates new tuning work information W (step S1810), and returns to step S1801.

[0156] Also, in step S1808, if the execution time TBEST is less than or equal to the execution time T (step S1808: No), the information processing device 200 changes the implementation status of instruction J in the tuning work information WT to "C", creates new tuning work information W (step S1811), and returns to step S1801.

[0157] Furthermore, in step S1802, if there are no instructions to be tuned (step S1802: No), information processing device 200 refers to tuning work information W and updates tuning database information 600 (step S1812). Then, information processing device 200 outputs the executable program OP (step S1813) and ends the series of processes according to this flowchart.

[0158] As a result, the information processing device 200 attempts to improve performance by increasing the instruction latency of the input program, thereby improving performance through optimization of software pipelining.

[0159] As described above, the information processing device 200 according to the second embodiment can acquire performance counter information of the CPU 201 when the loop processing in the input program is executed by applying software pipelining. Software pipelining is to rearrange instructions in the loop processing based on latency information of the instructions corresponding to the CPU 201. Furthermore, the information processing device 200 can identify the type of instruction that has generated a wait time based on the acquired performance counter information. The type of instruction is, for example, any of an integer data load instruction, a floating-point data load instruction, an integer arithmetic instruction, and a floating-point arithmetic instruction. Then, the information processing device 200 can create an executable program by applying software pipelining by increasing the value of latency information of any of the identified types of instructions in the loop processing.

[0160] This allows the information processing device 200 to improve performance by optimizing software pipelining for an input program including a loop process. For example, the information processing device 200 can use information on the performance counter of the CPU 201 to narrow down instructions that may not be operating as expected, and increase the latency of those instructions to try to improve performance.

[0161] Moreover, the information processing device 200 can select, from among the instructions in the loop processing, an instruction of a specified type that has a high improvement rate, by referring to the storage unit 710. The storage unit 710 stores information representing an improvement rate when an attempt is made to improve performance by increasing the latency of the instruction and applying software pipelining, in association with the instruction executed by the CPU 201. Then, the information processing device 200 can create an executable program by increasing the value of the latency information of the selected instruction and applying software pipelining.

[0162] This allows the information processing device 200 to select an instruction that has been successful in past attempts to improve performance, and to increase the latency of that instruction in an attempt to improve performance. Therefore, the information processing device 200 can efficiently improve performance by utilizing the fact that the cause of latency deviation tends to depend on the CPU 201 (internal configuration).

[0163] Furthermore, the information processing device 200 can detect an instruction sequence that is a critical path based on an input program, and select any of the specified types of instructions from the detected instruction sequence. The information processing device 200 can then increase the value of the latency information of the selected instruction and apply software pipelining to create an executable program.

[0164] This allows the information processing device 200 to select an instruction that has a large effect on the execution performance of a program and attempt to improve performance by increasing the latency of that instruction, thereby enabling efficient performance improvement.

[0165] Moreover, the information processing device 200 can refer to the storage unit 710 and select, from the detected sequence of instructions, an instruction that is of a specified type and has a high improvement rate.

[0166] This enables the information processing device 200 to select instructions that have a large impact on the execution performance of a program and have had a high rate of success in past attempts to improve performance, and to attempt to improve performance by increasing the latency of those instructions, thereby enabling more efficient performance improvement.

[0167] Furthermore, according to the information processing device 200, as a result of executing the created executable program, it is possible to determine whether or not the performance (effective performance) of the input program has improved based on the execution time of the executable program. Then, according to the information processing device 200, it is possible to update information indicating an improvement rate corresponding to the command (the command that has increased the value of the latency information) stored in the storage unit 710 based on the result of the determination.

[0168] As a result, the information processing device 200 can accumulate results (improvement success / improvement failure) of attempts to improve performance by increasing instruction latency for the CPU 201, and use the results for future performance improvements. The cause of latency deviations tends to depend on the CPU 201 (internal configuration). For this reason, the results (improvement success / improvement failure) of attempts to improve performance by increasing instruction latency can be said to be useful information for performing software pipelining in the CPU 201.

[0169] Moreover, according to the information processing device 200, if the performance of the input program is improved, the state in which the latency information value of the instruction is increased can be maintained, and further performance improvement can be implemented. Moreover, according to the information processing device 200, if the performance of the input program is not improved, the value of the latency information of the instruction can be returned to a state in which it is not increased, and further performance improvement can be implemented.

[0170] This allows the information processing device 200 to adjust the latency of instructions depending on the success or failure of performance improvement, and increase the latency of instructions that may not be operating as expected in an attempt to further improve performance.

[0171] Moreover, the information processing device 200 can output the created executable program. Specifically, for example, the information processing device 200 may repeatedly perform performance improvement on an input program, and output only the latest executable program (for example, executable program OP) whose performance has been improved.

[0172] As a result, the information processing device 200 can provide an executable program (for example, an executable program OP) with improved performance by enhancing the effect of optimization through software pipelining.

[0173] From these facts, the information processing device 200 according to the second embodiment can prevent performance degradation due to factors not described in the data sheet of the CPU 201 and performance degradation due to complex conditions during program execution as a result of applying optimization of software pipelining. As a result, the information processing device 200 can reduce the execution time of a program such as an HPC application that consumes most of its execution time in a single innermost loop.

[0174] The compiling method described in the present embodiment can be realized by executing a prepared program on a computer such as a personal computer or a workstation. The compiler is recorded on a computer-readable recording medium such as a hard disk, a flexible disk, a CD-ROM, a DVD, or a USB memory, and is executed by being read from the recording medium by a computer. The compiler may also be distributed via a network such as the Internet.

[0175] The following supplementary notes are further disclosed regarding the above-described embodiment.

[0176] (Note 1) For loop processing in a program, information on a performance counter of the CPU is obtained when the loop processing is executed by applying software pipelining that rearranges instructions in the loop processing based on latency information of instructions corresponding to the CPU; Identifying the type of instruction that has caused the wait time based on the acquired performance counter information; creating an executable program by increasing a value of latency information of any of the identified types of instructions among the instructions in the loop processing and applying the software pipelining; A compiler that causes a computer to execute a process.

[0177] (Note 2) A storage unit stores information indicating an improvement rate when an attempt is made to improve performance by increasing the latency of an instruction executed by the CPU and applying software pipelining, and selects, from among the instructions in the loop process, an instruction of the specified type that has a high improvement rate. causing the computer to execute a process; The creating process includes: 2. The compiler according to claim 1, further comprising: a compiler for generating an executable program by applying software pipelining that reorders instructions in the loop processing by increasing a value of latency information of the selected instructions.

[0178] (Appendix 3) Based on the program, an instruction sequence that is a critical path is detected; selecting one of the identified types of instructions from the detected sequence of instructions; causing the computer to execute a process; The creating process includes: 3. The compiler according to claim 1 or 2, characterized in that it creates an executable program by applying software pipelining that increases a value of latency information of the selected instruction and rearranges the instructions in the loop processing.

[0179] (Appendix 4) Based on the program, an instruction sequence that is a critical path is detected. causing the computer to execute a process; The process of selecting includes: The compiler according to claim 2, further comprising: referring to the memory unit and selecting, from the detected sequence of instructions, an instruction of the specified type that has a high improvement rate.

[0180] (Supplementary Note 5) The compiler according to any one of Supplementary Notes 1 to 4, characterized in that it causes the computer to execute a process of outputting the created executable program.

[0181] (Appendix 6) executing the created executable program and determining whether performance of the program has improved based on the execution time of the executable program; updating information representing an improvement rate corresponding to any one of the instructions stored in the storage unit based on a result of the determination; A compiler as described in Appendix 2, characterized in that it causes the computer to execute processing.

[0182] (Supplementary Note 7) Executing the created executable program and determining whether the performance of the program has improved based on the execution time of the executable program; if the performance has improved, maintaining the increased value of the latency information of any one of the instructions, identifying a type of instruction that has generated a wait time based on information from the performance counter when the executable program is executed, and creating an executable program by increasing the value of the latency information of any one of the instructions of the identified type among the instructions in the loop processing and applying the software pipelining; 7. The compiler according to any one of claims 1 to 6, further comprising a processor for causing the computer to execute a process.

[0183] (Note 8) If the performance is not improved, returning to a state in which the value of the latency information of any of the instructions is not increased, identifying a type of instruction that has generated a wait time based on information from the performance counter when the executable program is executed, and increasing the value of the latency information of any of the instructions of the identified type among the instructions in the loop processing, thereby creating an executable program by applying the software pipelining. 8. The compiler according to claim 7, further causing the computer to execute a process.

[0184] (Supplementary Note 9) The compiler according to any one of Supplementary Notes 1 to 8, wherein the type of instruction is any one of an integer data load instruction, a floating-point data load instruction, an integer arithmetic instruction, and a floating-point arithmetic instruction.

[0185] (Appendix 10) For a loop process in a program, information on a performance counter of the CPU is obtained when the loop process is executed by applying software pipelining that rearranges instructions in the loop process based on latency information of instructions corresponding to the CPU; Identifying the type of instruction that has caused the wait time based on the acquired performance counter information; creating an executable program by increasing a value of latency information of any of the identified types of instructions among the instructions in the loop processing and applying the software pipelining; A compiling method, the processing of which is executed by a computer.

[0186] (Appendix 11) For loop processing in a program, information on a performance counter of the CPU when the loop processing is executed by applying software pipelining that rearranges instructions in the loop processing based on latency information of instructions corresponding to the CPU is obtained; Identifying the type of instruction that has caused the wait time based on the acquired performance counter information; creating an executable program by increasing a value of latency information of any of the identified types of instructions among the instructions in the loop processing and applying the software pipelining; A compiling device comprising a control unit. [Explanation of symbols]

[0187] 101 Compilation device 110 Programs 111 Loop Processing 120 Latency Information 130 Performance Counter Information 140,150 executable programs 200 Information processing device 201 CPU 202 Memory 203 Disk Drive 204 Disk 205 Communication I / F 206 Portable recording medium I / F 207 Portable recording media 208 Bus 210 Network 300 Input Program 400 Intermediate Language Representation 500 Data Dependency Graphs 501,502,503,504,505,506 nodes 511,512,513,514,515,516 Edge 600 Tuning Database Information 700 Control section 701 Reception 702 Optimization Department 703 Executive Department 704 Adjustment section 705 Output section 710 Storage section

Claims

1. Acquire information on a performance counter of a CPU when a loop process in a program is executed by applying software pipelining that rearranges instructions in the loop process based on latency information of instructions corresponding to the CPU; Identifying the type of instruction that has caused the wait time based on the acquired performance counter information; creating an executable program by increasing a value of latency information of any of the identified types of instructions among the instructions in the loop processing and applying the software pipelining; A compiler that causes a computer to execute a process.

2. selecting, from among the instructions in the loop processing, an instruction of the specified type that has a high improvement rate, by referring to a storage unit that stores information representing an improvement rate when performance is improved by increasing the latency of the instruction and applying software pipelining in association with the instruction executed by the CPU; causing the computer to execute a process; The creating process includes:

2. The compiler according to claim 1, further comprising: a compiler for generating an executable program by applying software pipelining that rearranges instructions in the loop processing by increasing a value of latency information of the selected instruction.

3. Detecting an instruction sequence that is a critical path based on the program; selecting one of the identified types of instructions from the detected sequence of instructions; causing the computer to execute a process; The creating process includes:

2. The compiler according to claim 1, further comprising: a compiler for generating an executable program by applying software pipelining that rearranges instructions in the loop processing by increasing a value of latency information of the selected instruction.

4. 2. The compiler according to claim 1, wherein the compiler causes the computer to execute a process of outputting the created executable program.

5. executing the created executable program and determining whether performance of the program has improved based on the execution time of the executable program; updating information representing an improvement rate corresponding to any one of the instructions stored in the storage unit based on a result of the determination; 3. The compiler according to claim 2, which causes the computer to execute a process.

6. executing the created executable program and determining whether performance of the program has improved based on the execution time of the executable program; if the performance has improved, maintaining the increased value of the latency information of any one of the instructions, identifying a type of instruction that has generated a wait time based on information from the performance counter when the executable program is executed, and creating an executable program by increasing the value of the latency information of any one of the instructions of the identified type among the instructions in the loop processing and applying the software pipelining; 2. The compiler according to claim 1, further comprising a step of causing the computer to execute a process.

7. if the performance has not improved, returning to a state in which the value of the latency information of any of the instructions is not increased, identifying a type of instruction that has generated a wait time based on information from the performance counter when the executable program is executed, and increasing the value of the latency information of any of the instructions of the identified type among the instructions in the loop processing, thereby creating an executable program by applying the software pipelining.

7. The compiler according to claim 6, further comprising a step of causing the computer to execute a process.

8. Acquire information on a performance counter of a CPU when a loop process in a program is executed by applying software pipelining that rearranges instructions in the loop process based on latency information of instructions corresponding to the CPU; Identifying the type of instruction that has caused the wait time based on the acquired performance counter information; creating an executable program by increasing a value of latency information of any of the identified types of instructions among the instructions in the loop processing and applying the software pipelining; A compiling method, the processing of which is executed by a computer.

9. Acquire information on a performance counter of a CPU when a loop process in a program is executed by applying software pipelining that rearranges instructions in the loop process based on latency information of instructions corresponding to the CPU; Identifying the type of instruction that has caused the wait time based on the acquired performance counter information; creating an executable program by increasing a value of latency information of any of the identified types of instructions among the instructions in the loop processing and applying the software pipelining; A compiling device comprising a control unit.

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