Image sensor

Abstract

To provide a pixel of which a trap characteristic is improved.SOLUTION: An image sensor contains: a substrate containing a photoelectric conversion region; a semiconductor pattern that is provided onto the substrate; a gate electrode that is provided onto the semiconductor pattern; and a gate insulator that is provided to between the semiconductor pattern and the gate electrode. The semiconductor pattern contains: a first sub pattern containing a first source / drain region; a second sub pattern containing a second source / drain region; and a third sub pattern provided to the first and second sub patterns. The gate electrode is provided onto the third sub pattern, and the first, second, and third sub patterns are extended along a different direction each other.SELECTED DRAWING: Figure 4A

Description

[Technical field]

[0001] The present invention relates to an image sensor. [Background technology]

[0002] Image sensors are devices that convert optical image signals into electrical signals, and include CCD (charge coupled device) image sensors and CMOS (complementary metal oxide semiconductor) image sensors. Image sensors include a number of pixels. Each pixel includes a light receiving area that receives incident light and converts it into an electrical signal, and a pixel circuit that outputs a pixel signal using charges generated in the light receiving area.

[0003] Recently, as the integration density of image sensors increases, the size of each pixel is becoming smaller, but in order to realize this, there is a problem that image transmission delays occur depending on the layout and shape of components within the pixel, which reduces the quality of the image sensor. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US Patent No. 7,582,516 B2 Summary of the Invention [Problem to be solved by the invention]

[0005] The problem to be solved is to provide a pixel having improved trapping characteristics.

[0006] The problem to be solved is to provide an image sensor having improved noise characteristics.

[0007] However, the problem to be solved is not limited to that disclosed above. [Means for solving the problem]

[0008] In one aspect, an image sensor may be provided, comprising: a substrate including a photoelectric conversion region; a semiconductor pattern provided on the substrate; a gate electrode provided on the semiconductor pattern; and a gate insulating film provided between the semiconductor pattern and the gate electrode, the semiconductor pattern including a first sub-pattern including a first source / drain region, a second sub-pattern including a second source / drain region, and a third sub-pattern provided between the first sub-pattern and the second sub-pattern, the gate electrode being provided on the third sub-pattern, and the first sub-pattern, the second sub-pattern, and the third sub-pattern extending in different directions from each other.

[0009] The gate electrode may extend onto a first side of the third sub-pattern.

[0010] The first side can be a {310} plane or a {210} plane.

[0011] The semiconductor pattern may further include a fourth sub-pattern provided between the second sub-pattern and the third sub-pattern, the gate electrode may be provided on the fourth sub-pattern, and the fourth sub-pattern may extend along a different direction than the first sub-pattern, the second sub-pattern, and the third sub-pattern.

[0012] The gate electrode may extend onto a third side of the fourth sub-pattern and a fourth side of the fourth sub-pattern opposite the third side.

[0013] The third side and the fourth side can be {310} planes or {210} planes.

[0014] The semiconductor pattern may further include a fifth sub-pattern provided between the first sub-pattern and the second sub-pattern, the fifth sub-pattern being arranged alongside the third sub-pattern, and the gate electrode being provided on the fifth sub-pattern.

[0015] The third sub-pattern has a first side and a second side arranged opposite each other, the fifth sub-pattern has a fifth side and a sixth side arranged opposite each other, and the gate electrode may extend on the first side, the second side, the fifth side, and the sixth side.

[0016] The first side, the second side, the fifth side, and the sixth side may be {310} planes or {210} planes.

[0017] In one aspect, an image sensor may be provided that includes a first pixel and a second pixel, each of the first and second pixels including a substrate including a photoelectric conversion region and a floating diffusion region, a semiconductor pattern provided on the substrate, a gate electrode provided on the semiconductor pattern, and a gate insulating film provided between the semiconductor pattern and the gate electrode, and in each of the first and second pixels, the semiconductor pattern includes a first sub-pattern including a first source / drain region, a second sub-pattern including a second source / drain region, and a third sub-pattern provided between the first sub-pattern and the second sub-pattern, the first sub-pattern, the second sub-pattern, and the third sub-pattern extending along different directions from each other, the gate electrode being provided on a side of the third sub-pattern, and the floating diffusion regions of the first and second pixels being electrically connected to the gate electrode of the first pixel or the gate electrode of the second pixel. Effect of the Invention

[0018] The present invention can provide a pixel with improved trapping characteristics.

[0019] The present invention provides an image sensor having improved noise characteristics.

[0020] However, the effects of the invention are not limited to the above disclosure. [Brief description of the drawings]

[0021] [Figure 1] FIG. 1 is a block diagram of an image sensor in accordance with an example embodiment. [Diagram 2] FIG. 2 is a plan view of the pixel array of FIG. [Diagram 3] FIG. 2 is an equivalent circuit diagram of the pixel group of FIG. [Figure 4A] FIG. 2 is a plan view illustrating a pixel of an image sensor according to an exemplary embodiment. [Figure 4B] FIG. 4B is a cross-sectional view taken along line A1-A1' in FIG. 4A. [Figure 4C] FIG. 4B is a cross-sectional view taken along line A2-A2' in FIG. 4A. [Figure 4D] FIG. 4B is a plan view showing the semiconductor pattern of FIG. 4A. [Figure 5A] FIG. 2 is a plan view illustrating a pixel of an image sensor according to an exemplary embodiment. [Figure 5B] FIG. 5B is a cross-sectional view taken along line B1-B1' in FIG. 5A. [Figure 6A] FIG. 2 is a plan view illustrating a pixel of an image sensor according to an exemplary embodiment. [Figure 6B] FIG. 6B is a cross-sectional view taken along line C1-C1' in FIG. 6A. [Figure 6C] FIG. 6B is a cross-sectional view taken along line C2-C2' in FIG. 6A. [Figure 7A] FIG. 2 is a plan view illustrating a pixel of an image sensor according to an exemplary embodiment. [Figure 7B] FIG. 7B is a plan view showing the semiconductor pattern of FIG. 7A. [Figure 8] FIG. 2 is a plan view illustrating a pixel of an image sensor according to an exemplary embodiment. [Figure 9A] FIG. 2 is a plan view illustrating a pixel of an image sensor according to an exemplary embodiment. [Figure 9B]FIG. 9B is a plan view showing the semiconductor pattern of FIG. 9A. [Figure 10A] FIG. 2 is a plan view illustrating a pixel group of an image sensor according to an exemplary embodiment. [Figure 10B] 10B is a cross-sectional view taken along line G1-G1' in FIG. 10A. [Figure 10C] 10B is a cross-sectional view taken along line G2-G2' in FIG. 10A. [Figure 10D] FIG. 10B is a plan view showing the semiconductor pattern of FIG. 10A. [Figure 11] FIG. 2 is a plan view illustrating a pixel group of an image sensor according to an exemplary embodiment. [Figure 12] FIG. 2 is a plan view illustrating a pixel group of an image sensor according to an exemplary embodiment. [Figure 13] FIG. 2 is a plan view illustrating a pixel group of an image sensor according to an exemplary embodiment. [Figure 14] FIG. 2 is a plan view illustrating a pixel group of an image sensor according to an exemplary embodiment. [Figure 15] FIG. 2 is a plan view illustrating a pixel group of an image sensor according to an exemplary embodiment. [Figure 16A] FIG. 2 is a plan view illustrating a pixel group of an image sensor according to an exemplary embodiment. [Figure 16B] FIG. 16B is a cross-sectional view taken along line H1-H1' in FIG. 16A. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following, the embodiments of the present invention will be described clearly and in detail to the extent that those skilled in the art can easily practice the present invention.

[0023] Figure 1 is a block diagram of an image sensor according to an exemplary embodiment. Figure 2 is a plan view of a pixel array of Figure 1. Figure 3 is an equivalent circuit diagram of a group of pixels of Figure 1.

[0024] Referring to FIG 1, an image sensor 1000 may be provided. The image sensor 1000 may be mounted in an electronic device having an image or light sensing function. For example, the image sensor 1000 may be mounted in electronic devices such as a camera, a smartphone, a wearable device, an Internet of Things (IoT), a tablet PC (Personal Computer), a PDA (Personal Digital Assistant), a PMP (Portable Multimedia Player), a navigation device, etc. The image sensor 1000 may be mounted in electronic devices provided as components in vehicles, furniture, manufacturing equipment, doors, various measuring devices, etc.

[0025] The image sensor 1000 may include a pixel array 1110 , a controller 1130 , a row driver 1120 , and a control unit including a pixel signal processor 1140 .

[0026] As shown in FIG. 2, the pixel array 1110 may include a plurality of pixels arranged two-dimensionally along a first direction DR1 and a second direction DR2. The plurality of pixels may be arranged in a certain pattern to generate a high quality image. For example, the plurality of pixels may be arranged in a Bayer pattern or a chess mosaic pattern. When the plurality of pixels have a Bayer pattern, the pixels in the pixel array 1110 may each receive red light, green light, and blue light. In one example, the plurality of pixels may receive cyan light, magenta light, yellow light, and white light. Each of the pixels may include a photoelectric conversion element. The photoelectric conversion element may absorb light and generate charge carriers (electrons or holes). For example, the photoelectric conversion element may include photodiodes, phototransistors, photogates, pinned photodiodes, or a combination thereof. The output voltages of the multiple pixels can be determined based on the generated charge carriers.

[0027] The pixel array 1110 may include a pixel group PXG. A pixel group PXG may be a collection of pixels PX that share a reset transistor RX, a selection transistor SX, and a source follower transistor DX. Although the pixel group PXG is illustrated as being composed of four pixels PX, this is merely an example. In other examples, the pixel group PXG may include fewer or more than four pixels PX.

[0028] The pixel array 1110 may be driven by receiving a number of drive signals, such as a row selection signal, a reset signal, and a charge transfer signal, from the row driver 1120. The row driver 1120 may provide a number of drive signals to the pixel array 1110 for driving a number of pixels. In one example, the drive signals may be provided in units of rows of the pixel array 1110. Pixels belonging to one row of the pixel array 1110 selected by the drive signal of the row driver 1120 may be simultaneously activated by a signal output by the row driver 1120. The pixels belonging to the selected row may provide an output voltage to an output line of a corresponding column in response to absorbed light. In one example, the pixels may provide an output voltage one at a time in units of rows. The output voltage may be provided to a correlated double sampler 1142.

[0029] The pixel signal processing unit 1140 may include a correlated double sampler (CDS) 1142, an analog-to-digital converter (ADC) 1144, and a buffer 1146. The correlated double sampler 1142 may sample and hold an output voltage provided by the pixel array 1110. The correlated double sampler 1142 may reduce noise and improve a signal-to-noise ratio (SNR). The correlated double sampler 1142 may be configured to remove a noise voltage from an output voltage of a pixel. For example, the correlated double sampler 1142 may double sample a specific noise level and a signal level according to an output signal, and output a difference level corresponding to a difference between the noise level and the signal level. The correlated double sampler 1142 may receive a ramp signal generated by the ramp signal generator 1148, compare the ramp signals with each other, and output a comparison result.

[0030] The analog-to-digital converter 1144 may convert an analog signal corresponding to the difference level received from the correlated double sampler 1142 into a digital signal. The buffer 1146 may latch the digital signal, and the latched signals may be sequentially output to the outside of the image sensor 1000 and transmitted to an image processor (not shown).

[0031] The controller 1130 may control the row driver 1120 to cause the pixel array 1110 to absorb light and accumulate charge, or to temporarily store the accumulated charge, and to output an electrical signal corresponding to the stored charge to the outside of the pixel array 1110. The controller 1130 may also control the pixel signal processor 1140 to measure an output voltage provided by the pixel array 1110.

[0032] 3, each of the pixels PX may include a photoelectric conversion element PD, a transfer transistor TX, and a floating diffusion region FD. The photoelectric conversion element PD may generate and accumulate photocharges in proportion to the amount of light incident from the outside, and may include a photodiode, a phototransistor, a photogate, a pinned photodiode, or a combination thereof.

[0033] The transfer transistor TX may include a transfer gate TG. The transfer gate TG may transfer charge carriers generated in the photoelectric conversion element to the floating diffusion region FD. A transfer control voltage provided by a row driver 1120 may be applied to the transfer gate TG. For example, a channel may be formed between the photoelectric conversion element FD and the floating diffusion region 104 by the transfer control voltage applied to the transfer gate. Charge carriers generated in the photoelectric conversion element may move to the floating diffusion region 104 along the channel between the photoelectric conversion element FD and the floating diffusion region 104. A drain terminal of the transfer transistor TX may be electrically connected to the floating diffusion region 104, and a source terminal of the transfer transistor TX may be electrically connected to the photoelectric conversion element FD.

[0034] The floating diffusion region FD may accumulate and store the charges generated in the photoelectric conversion element PD. The source follower transistor DX may be controlled according to the amount of charges accumulated in the floating diffusion region FD. The gate terminal of the source follower transistor DX may be electrically connected to the floating diffusion region 104, a second power supply voltage VDD2 may be applied to the drain terminal, and the source terminal may be electrically connected to the drain terminal of the selection transistor SX. The source follower transistor DX may be a source follower buffer amplifier that outputs a current in proportion to the amount of charges in the floating diffusion region FD.

[0035] The reset transistor RX can periodically reset the charge stored in the floating diffusion region FD. The gate terminal of the reset transistor RX can be electrically connected to a reset signal line RG. The drain terminal of the reset transistor RX can be connected to the floating diffusion region FD, and the source terminal can be connected to a first power supply voltage VDD1. In one embodiment, the first power supply voltage VDD1 can be substantially the same as the second power supply voltage VDD2. When the reset transistor RX is turned on, the first power supply voltage VDD1 connected to the source terminal of the reset transistor RX is transferred to the floating diffusion region FD. When the reset transistor RX is turned on, the charge stored in the floating diffusion region FD can be discharged, and the floating diffusion region FD can be reset. When the charge carriers are electrons, the voltage of the floating diffusion region 104 can be lowered by electrons being accumulated in the floating diffusion region 104. When the reset transistor RX is turned on, electrons in the floating diffusion region 104 are discharged to the outside, and the voltage of the floating diffusion region 104 may rise to the first power supply voltage VDD1. As the first power supply voltage VDD1 is applied to the floating diffusion region 104, the first power supply voltage VDD1 is applied to the gate terminal of the source follower transistor DX, and the output of the source follower transistor DX may be reset.

[0036] The selection transistor SX can select a plurality of pixels PX in units of a row. The selection transistor SX can transmit a current generated in the source follower transistor DX included in each of the selected pixels to an output line (not shown). The drain terminal, source terminal, and gate terminal of the selection transistor SX can be electrically connected to the source terminal of the source follower transistor DX, the output line, and a row selection line SG, respectively. A selection control signal applied from the row selection line SG is applied to the gate terminal of the selection transistor SX, so that a signal generated by the source follower transistor DX can be output to the output line.

[0037] FIG 4A is a plan view showing a pixel of an image sensor according to an exemplary embodiment, FIG 4B is a cross-sectional view taken along line A1-A1' in FIG 4A, FIG 4C is a cross-sectional view taken along line A2-A2' in FIG 4A, and FIG 4D is a plan view showing a semiconductor pattern in FIG 4A.

[0038] 4A to 4C, a substrate 100 may be provided. The substrate 100 may be a semiconductor substrate. In this specification, the substrate 100 is described as a silicon (Si) substrate. However, the technical idea of ​​the present invention may be applied to other semiconductor substrates. The substrate 100 may include a first surface 100a and a second surface 100b facing in opposite directions. The first surface 100a and the second surface 100b may extend along a first direction DR1 and a second direction DR2. The first direction DR1 and the second direction DR2 may be a first axis direction and a second axis direction of a cubic structure, respectively. The first surface 100a and the second surface 100b may be spaced apart from each other along a third direction DR3. The third direction DR3 may be perpendicular to the first direction DR1 and the second direction DR2. The third direction DR3 may be a third axis direction of the cubic structure. When the crystal axes of the cubic structure are represented by the x-axis, y-axis, and z-axis, the first direction DR1, the second direction DR2, and the third direction DR3 may be the x-axis, y-axis, and z-axis directions, respectively. When the crystal axes of the cubic structure are represented by the a1-axis, a2-axis, and a3-axis, the first direction DR1, the second direction DR2, and the third direction DR3 may be the a1-axis, a2-axis, and a3-axis directions, respectively. The substrate 100 may be a

[0100] substrate. The equivalent plane index of the first surface 100a may be {100}. Hereinafter, the equivalent plane index may indicate the Miller index of a crystallographically equivalent surface. For example, the first surface 100a may be a (100) surface.

[0039] The substrate 100 may have a first conductivity type. For example, the first conductivity type may be p-type or n-type. When the conductivity type of the substrate 100 is p-type, the substrate 100 may be a silicon (Si) substrate containing a group 3 element (e.g., boron (B), aluminum (Al), gallium (Ga), indium (In), etc.) or a group 2 element as an impurity. When the conductivity type of the substrate 102 is n-type, the substrate 100 may be a silicon (Si) substrate containing a group 5 element (e.g., phosphorus (P), arsenic (As), antimony (Sb), etc.), a group 6 element, or a group 7 element as an impurity. Hereinafter, the region having an n-type conductivity may contain a group 5, 6, or 7 element as an impurity. Hereinafter, the impurities that cause the substrate 100 to have the first conductivity type and the second conductivity type may be referred to as a first impurity and a second impurity, respectively. When the first conductivity type is p-type or n-type, the second conductivity type may be n-type or p-type, respectively. The substrate 100 may be an epi layer formed by an epitaxial growth process. For ease of explanation, the first conductivity type is hereinafter described as p-type and the second conductivity type is hereinafter described as n-type.

[0040] An isolation layer 110 may be provided on the substrate 100. The isolation layer 110 may define an active region. The active region may be a region in which a transfer gate structure 106, a floating diffusion region 104, and a ground region 105, which will be described later, are provided. The first surface 100a may refer to an upper surface of the active region. In a plan view, the isolation layer 110 may surround the active region. The isolation layer 110 may have a thickness along a third direction DR3. The thickness of the isolation layer 110 may be smaller than the thickness of a pixel isolation layer 108, which will be described later. For example, the isolation layer 110 may be a shallow trench isolation (STI) layer. In one example, the upper surface of the isolation layer 110 may be located at substantially the same level as the first surface 100a. The isolation layer 110 may include silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof.

[0041] A pixel isolation layer 108 may be provided on a side of the substrate 100. In a plan view, the pixel isolation layer 108 may surround the substrate 100. The pixel isolation layer 108 may extend along a third direction DR3. In one example, a top surface and a bottom surface of the pixel isolation layer 108 may be located at substantially the same level as the first surface 100a and the second surface 100b, respectively. The pixel isolation layer 108 may prevent or reduce an electric crosstalk phenomenon that reduces a signal-to-noise ratio due to charge carrier exchange between adjacent pixels. For example, the pixel separation layer 108 may include a conductive material (e.g., at least one of doped polysilicon, a metal, a metal silicide, a metal nitride, or a metal-containing material), an insulating material (e.g., a silicon-based insulating material (e.g., silicon nitride, silicon oxide, and / or silicon oxynitride), or a metal oxide including at least one metal selected from the group consisting of a high dielectric material (e.g., hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium (Y), and lanthanide (La)). In one example, a sidewall of the pixel separation layer 108 is doped with a material having a high reflectivity to prevent optical crosstalk detected by a pixel adjacent to the pixel where light is incident. The crosstalk phenomenon can be prevented or reduced. For example, the material with high reflectivity can be boron. When the pixel separation layer 108 includes a conductive material, for example, a negative fixed charge layer can be provided between the pixel separation layer 108 and the substrate 100. The negative fixed charge layer can include a metal oxide including at least one metal selected from the group consisting of hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium (Y), and lanthanoid (La). However, the structure of the pixel separation layer 108 can be determined as necessary. In one embodiment, the pixel separation layer 108 can be an insulating film having a single structure.In one embodiment, the pixel isolation layer 108 may include an upper insulating layer adjacent to the first surface 100a and a lower insulating layer adjacent to the second surface 100b.

[0042] The photoelectric conversion region 102 may be provided in the substrate 100. In one embodiment, the photoelectric conversion region 102 may include at least one photodiode. For example, the photoelectric conversion region 102 may include a pn photodiode. For example, the p-type region of the photoelectric conversion region 102 may be the substrate 100, and the n-type region may be formed by implanting a second impurity into the substrate 100. In one example, the p-type region may be a region formed by implanting a first impurity into the substrate 100. In this case, the doping concentration of the p-type region may be higher than the doping concentration of the substrate 100. In one example, the first impurity may be further implanted into the substrate 100 to form a plurality of pn junctions located at different depths. However, it is exemplary that the photoelectric conversion region 102 includes a photodiode. In one embodiment, the photoelectric conversion region 102 may include phototransistors, photogates, or pinned photodiodes. When light is incident on the photoelectric conversion region 102, electron-hole pairs (EHPs) may be generated in the photoelectric conversion region 102. For example, the electron-hole pairs may be generated in a depletion region formed in a region adjacent to the pn junction. Since light penetrates the substrate 100 at different depths depending on its wavelength, light having different wavelengths may be efficiently detected when multiple pn junctions located at different depths are used. The stronger the intensity of light incident on the photoelectric conversion region 102, the more electron-hole pairs may be generated. When a reverse bias is applied to the photoelectric conversion region 102, charge carriers (electrons or holes) may be accumulated in the photoelectric conversion region 102. The charge carriers accumulated in the photoelectric conversion region 102 may move to the floating diffusion region 104 by a voltage applied to the transfer gate electrode 106g. The photoelectric conversion region 102 may be separated from the floating diffusion region 104.

[0043] A floating diffusion region 104 may be provided on the substrate 100. The floating diffusion region 104 may have a second conductivity type. In one embodiment, the floating diffusion region 104 may be formed by implanting a second impurity into the substrate 100. The floating diffusion region 104 may be separated from the photoelectric conversion region 102. A region between the floating diffusion region 104 and the photoelectric conversion region 102 (i.e., a region of the substrate 100) may have a first conductivity type. The floating diffusion region 104 may receive and accumulate charge carriers provided from the photoelectric conversion region 102.

[0044] A transfer gate structure 106 may be provided adjacent to the floating diffusion region 104 and the photoelectric conversion region 102. The transfer gate structure 106 may be inserted into the substrate 100. In one example, a portion of the transfer gate structure 106 may protrude above the first surface 100a, and another portion may be inserted into the substrate 100. The transfer gate structure 106 may extend along a third direction DR3. The transfer gate structure 106 may be referred to as a vertical transfer gate (VTG). The transfer gate structure 106 may include a transfer gate electrode 106g and a transfer gate insulating film 106i.

[0045] The transmission gate electrode 106g may be spaced apart from the substrate 100. The transmission gate electrode 106g may extend along a third direction DR3. The transmission gate electrode 106g may include an electrically conductive material. For example, the transmission gate electrode 106g may include doped polysilicon or a metal (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), platinum (Pt), titanium (Ti), tantalum (Ta), tungsten (W), or a combination thereof).

[0046] The transfer gate insulating layer 106i may be provided between the transfer gate electrode 106g and the substrate 100. The transfer gate insulating layer 106i may extend along a surface of the transfer gate electrode 106g. The transfer gate insulating layer 106i may be configured to electrically isolate the transfer gate electrode 106g from the substrate 100. For example, the transfer gate insulating layer 106i may include a silicon-based insulating material (e.g., silicon nitride, silicon oxide, and / or silicon oxynitride) or a high dielectric material (e.g., a metal oxide including at least one metal selected from the group consisting of hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium (Y), and lanthanides (La)).

[0047] The transfer gate structure 106, the photoelectric conversion region 102, and the floating diffusion region 104 may form a transfer transistor. The transfer gate structure 106, the photoelectric conversion region 102, and the floating diffusion region 104 may form a gate, a source, and a drain of the transfer transistor, respectively. When a voltage is applied to the transfer gate electrode 106g, a channel of a second conductivity type may be formed in a region of the substrate 100 adjacent to the transfer gate structure 106. The channel may be configured to move charge carriers generated in the photoelectric conversion region 102 to the floating diffusion region 104. When no voltage is applied to the transfer gate electrode 106g, the charge carriers generated in the photoelectric conversion region 102 may be accumulated in the photoelectric conversion region 102.

[0048] A ground region 105 may be provided on the substrate 100. The ground region 105 may have a second conductivity type. The ground region 105 may be formed by implanting a second impurity into the substrate 100. The ground region 105 may be spaced apart from the photoelectric conversion region 102. The ground region 105 may be configured to apply a ground voltage to the substrate 100.

[0049] A pixel transistor 200 may be provided on a first surface 100a of the substrate 100. The pixel transistor 200 may be any one of transistors used in a circuit required for driving an image sensor. For example, the pixel transistor 200 may be any one of a source follower transistor, a reset transistor, and a selection transistor. The pixel transistor 200 may include a semiconductor pattern 210, a gate electrode 220, and a gate insulating layer 230.

[0050] The semiconductor pattern 210 may be provided on the substrate 100. The semiconductor pattern 210 may include substantially the same material as the substrate 100. For example, the semiconductor pattern 210 may be a silicon (Si) pattern. The semiconductor pattern 210 may be connected to the substrate 100 without an interface. In one example, the semiconductor pattern 210 may be formed by an epitaxial growth process using the substrate 100 as a seed layer. In another example, the semiconductor pattern 210 may be formed by a process of etching an upper portion of the substrate 100. The semiconductor pattern 210 may include a first sub-pattern 211, a second sub-pattern 212, and a third sub-pattern 213 extending in different directions. The first sub-pattern 211 may extend along a first direction DR1. The second sub-pattern 212 may be spaced apart from the first sub-pattern 211. The second sub-pattern 212 may extend along a second direction DR2. The third sub-pattern 213 may be provided between the first sub-pattern 211 and the second sub-pattern 212. The third sub-pattern 213 may extend along a fourth direction DR4 intersecting the first direction DR1 and the second direction DR2. In a plan view, the semiconductor pattern 210 may have a shape bent twice.

[0051] The semiconductor pattern 210 may include a first source / drain region SD1 and a second source / drain region SD2. The first source / drain region SD1 may be provided in the second sub-pattern 212. The first source / drain region SD1 may have the second conductive type. Although the first source / drain region SD1 is illustrated as being provided in a portion of the second sub-pattern 212, this is merely an example. In another example, the first source / drain region SD1 may be provided in the entire second sub-pattern 212. When one region of the second sub-pattern 212 is the first source / drain region SD1, the remaining region of the second sub-pattern 212 may have the first conductive type.

[0052] The second source / drain region SD2 may be provided in the first sub-pattern 211. The second source / drain region SD2 may have the second conductivity type. Although the second source / drain region SD2 is illustrated to be provided in a portion of the first sub-pattern 211, this is merely an example. In another example, the second source / drain region SD2 may be provided in the entire first sub-pattern 211. When one region of the first sub-pattern 211 is the second source / drain region SD2, the remaining region of the first sub-pattern 211 may have the first conductivity type.

[0053] The third sub-pattern 213 may have a first conductivity type. A channel connecting the first source / drain region SD1 and the second source / drain region SD2 may be formed in the third sub-pattern 213 by a voltage applied to the gate electrode 220. The channel may be provided adjacent to a surface of the third sub-pattern 213. The third sub-pattern 213 may have an A1 surface 213a, an A2 surface 213b, and an A3 surface 213c. The A1 surface 213A and the A2 surface 213b may be both side surfaces of the third sub-pattern 213 located opposite to each other. The A1 surface 213a, the A2 surface 213b, and the A3 surface 213c may extend along a fourth direction DR4. The A3 surface 213c may be an upper surface of the third sub-pattern 213. The A3 surface 213c may have substantially the same plane index as the first surface 100a. For example, the A3 surface 213c may be a (100) surface. The plane index of the A1 plane 213a can be determined to have a low density of interface traps.

[0054] In one example, the A1 surface 213a may be a {310} surface. Hereinafter, the {310} surface may refer not only to a {310} surface but also to a substantially {310} surface. The substantially {310} surface may be a surface that is slightly offset from the {310} surface and has substantially the same characteristics as the {310} surface. For example, the A1 surface 213a may be a (310) surface. When the A1 surface 213a is a (310) surface, the ratio of the size of the first direction DR1 component of the fourth direction DR4 to the size of the second direction DR2 component may be 1:3. For example, the A1 surface 213a may be a (130) surface. When the A1 surface 213a is a (130) surface, the ratio of the size of the first direction DR1 component of the fourth direction DR4 to the size of the second direction DR2 component may be 3:1. In one example, the A1 surface 213a may be a {210} surface. Hereinafter, the {210} plane may refer not only to the {210} plane but also to a substantial {210} plane. The substantial {210} plane may be, for example, a plane that is slightly offset from the {210} plane and has substantially the same characteristics as the {210} plane. For example, the A1 plane 213a may be a {210} plane. When the A1 plane 213a is a {210} plane, the ratio of the size of the first direction DR1 component of the fourth direction DR4 to the size of the second direction DR2 component may be 1:2. For example, the A1 plane 213a may be a (120) plane. When the A1 plane 213a is a {120} plane, the ratio of the size of the first direction DR1 component of the fourth direction DR4 to the size of the second direction DR2 component may be 2:1.

[0055] The gate electrode 220 may be provided on the third sub-pattern 213. The gate electrode 220 may be provided on the A3 surface 213c and the A1 surface 213a. In a plan view, the gate electrode 220 may completely overlap the A3 surface 213c and the A1 surface 213a. The gate electrode 220 may include an electrically conductive material. For example, the gate electrode 220 may include doped polysilicon or a metal (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), platinum (Pt), titanium (Ti), tantalum (Ta), tungsten (W), or a combination thereof). When the pixel transistor 200 is a source follower transistor, the gate electrode 220 may be electrically connected to the floating diffusion region 104. A voltage according to the amount of charge stored in the floating diffusion region may be a gate voltage. When the pixel transistor 200 includes a reset transistor, a reset signal voltage may be applied to the gate electrode 220 to apply an initial voltage to the floating diffusion region 104. Applying an initial voltage to the floating diffusion region 104 may be referred to as a reset operation. If the pixel transistor 200 includes a select transistor, a select signal voltage may be applied to the gate electrode 220 to output a signal.

[0056] The gate insulating layer 230 may be provided between the gate electrode 220 and the third sub-pattern 213. The gate insulating layer 230 may include an electrically insulating material. For example, the gate insulating layer 230 may include a silicon oxide, a silicon nitride, or a silicon oxynitride. In one embodiment, the gate insulating layer 230 may extend beyond the region between the gate electrode 220 and the semiconductor pattern 210 onto the device isolation layer 110, the transfer gate structure 106, the floating diffusion region 104, and the ground region 105.

[0057] The gate electrode 220 is provided on the A3 surface 213c and the A1 surface 213a, so that the channel of the pixel transistor 200 can be formed on the A3 surface 213c and the A1 surface 213a. The formation of a channel on a certain surface means that the channel is formed on that surface and an area adjacent to that surface. A charge trap phenomenon can occur at the interface between the semiconductor pattern 211 and the gate insulating film 230 due to the material properties of the semiconductor pattern 211 and the gate insulating film 230. The trap phenomenon is a factor that generates noise in the image sensor, such as random noises and random telegraph signals. The interface trap densities of the silicon (Si) film and the silicon dioxide (SiO2) film are about 4.0, 4.1, 2.4, and 2.0 for the {100}, {110}, {310}, and {210} surfaces of the silicon film, respectively. When a channel is formed on a (310) plane that is a {310} plane or a (210) plane that is a {210} plane, the charge trapping phenomenon can be improved more than when a channel is formed on a {100} plane or a {110} plane.

[0058] The present invention can provide a pixel 10 having improved trap characteristics by using a plane with a low interface trap density (e.g., {310} plane, {210} plane) as a channel, and therefore can provide an image sensor with improved noise characteristics.

[0059] FIG 5A is a plan view showing a pixel of an image sensor according to an exemplary embodiment. FIG 5B is a cross-sectional view taken along line B1-B1' in FIG 5A. The cross-sectional view taken along line B2-B2' in FIG 5A may be substantially the same as FIG 4C. For ease of explanation, differences from the embodiment described with reference to FIG 4A will be described.

[0060] 4C, 5A, and 5B, unlike the above description of FIG. 4A, the gate electrode 220 and the gate insulating film 230 may be further extended onto the A2 surface 213b of the third sub-pattern 213. The equivalent plane index of the A2 surface 213b may be determined to have a low interface trap density. In one example, the A2 surface 213b may be a {310} surface. For example, the A2 surface 213b may be a {310} surface.

[0061]

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[0063]

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[0064]

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[0065] The gate electrode 220 is provided on the A1 surface 213a, the A2 surface 213b, and the A3 surface 213c, so that the channel of the pixel transistor 200 can be formed on the A1 surface 213a, the A2 surface 213b, and the A3 surface 213c.

[0066]

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[0067]

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[0068] The present invention can provide a pixel 11 with an improved trapping phenomenon by using a plane with a low interface trap density (e.g., {310} plane, {210} plane) as a channel, and therefore can provide an image sensor with improved noise characteristics.

[0069] FIG 6A is a plan view showing a pixel of an image sensor according to an exemplary embodiment. FIG 6B is a cross-sectional view taken along line C1-C1' in FIG 6A. FIG 6C is a cross-sectional view taken along line C2-C2' in FIG 6A. The cross-sectional view taken along line C3-C3' in FIG 6A may be substantially the same as FIG 4C. For ease of explanation, differences from the embodiment described with reference to FIG 4A will be described.

[0070] 4C and 6A to 6C, unlike the description made with reference to FIG. 4A, the semiconductor pattern 210 may include a fourth sub-pattern 214 and a fifth sub-pattern 215 instead of the third sub-pattern 213. The fourth sub-pattern 214 and the fifth sub-pattern 215 may extend along a fourth direction DR4 between the first sub-pattern 211 and the second sub-pattern 212. The fourth sub-pattern 214 and the fifth sub-pattern 215 may be spaced apart from each other.

[0071] The fourth sub-pattern 214 and the fifth sub-pattern 215 may have a first conductivity type. A channel connecting the first source / drain region SD1 and the second source / drain region SD2 may be formed in the fourth sub-pattern 214 and the fifth sub-pattern 215 by a voltage applied to the gate electrode 220. The channel may be provided adjacent to the surfaces of the fourth sub-pattern 214 and the fifth sub-pattern 215. The fourth sub-pattern 214 may have a B1 surface 214a, a B2 surface 214b, and a B3 surface 214c. The B1 surface 214a, the B2 surface 214b, and the B3 surface 214c may extend along a fourth direction DR4. The B1 surface 214a and the B2 surface 214b may be both side surfaces of the fourth sub-pattern 214 located opposite to each other. The B3 surface 214c may be an upper surface of the fourth sub-pattern 214. The fifth sub-pattern 215 may have a C1 surface 215a, a C2 surface 215b, and a C3 surface 215c. The C1 surface 215a, the C2 surface 215b, and the C3 surface 215c may extend along a fourth direction DR4. The C1 surface 215a and the C2 surface 215b may be both side surfaces of the fifth sub-pattern 215 located opposite to each other. The C3 surface 215c may be a top surface of the fifth sub-pattern 215. The B1 surface 214a and the C2 surface 215b may face each other.

[0072] The B3 plane 214c and the C3 plane 215c may have substantially the same plane index as the first plane 100a. For example, the B3 plane 214c and the C3 plane 215c may be (100) planes. The plane indexes of the B1 plane 214a, the B2 plane 214b, the C1 plane 215a, and the C2 plane 215b may be determined to have a low interface trap density. In one embodiment, each of the B1 plane 214a, the B2 plane 214b, the C1 plane 215a, and the C2 plane 215b may be at least one of a {310} plane and a {210} plane. For example, the B1 plane 214a and the C1 plane 215a are (310) planes, and the C2 plane 215b and the B2 plane 214b are (310) planes.

[0073]

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[0074]

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[0075] The gate electrode 220 may be provided on the fourth semiconductor pattern 214 and the fifth semiconductor pattern 215. The gate electrode 220 may be configured to face the B1 surface 214a, the B2 surface 214b, the B3 surface 214c, the C1 surface 215a, the C2 surface 215b, and the C3 surface 215c. A portion of the gate electrode 220 may extend to a region between the fourth sub-pattern 214 and the fifth sub-pattern 215.

[0076] The gate insulating film 230 may be provided between the gate electrode 220 and the semiconductor pattern 210. For example, the gate insulating film 230 may cover the B1 surface 214a, the B2 surface 214b, the B3 surface 214c, the C1 surface 215a, the C2 surface 215b, and the C3 surface 215c. The gate insulating film 230 may electrically separate the semiconductor pattern 210 and the gate electrode 220. In one embodiment, the gate insulating film 230 and the gate electrode 220 may fill the region between the fourth sub-pattern 214 and the fifth sub-pattern 215.

[0077] The present invention provides a pixel 12 with improved charge trapping by increasing the area of ​​a surface with low interface trap density (e.g., {310} surface, {210} surface) used when forming a channel using the fourth sub-pattern 214 and the fifth sub-pattern 215. Therefore, an image sensor with improved noise characteristics can be provided.

[0078] FIG 7A is a plan view showing a pixel of an image sensor according to an exemplary embodiment. FIG 7B is a plan view showing a semiconductor pattern of FIG 7A. A cross-sectional view taken along line D1-D1' of FIG 7A may be substantially the same as FIG 4B. A cross-sectional view taken along line D2-D2' of FIG 7A may be substantially the same as FIG 4C. For ease of explanation, differences from the embodiment described with reference to FIG 4A will be described.

[0079] 4B, 4C, 7A, and 7B, unlike the embodiment described with reference to FIG. 4A, the semiconductor pattern 210 may include a sixth sub-pattern 241 and a seventh sub-pattern 242 instead of the third sub-pattern 213. The sixth sub-pattern 241 may be provided between the seventh sub-pattern 242 and the first sub-pattern 211. One end of the sixth sub-pattern 241 may be connected to the first sub-pattern 211, and the other end may be connected to the seventh sub-pattern 242. The sixth sub-pattern 241 may extend along a fifth direction DR5 intersecting the first direction DR1 and the second direction DR2. The fifth direction DR5 may have a first direction DR1 component and a second direction DR2 component. In one example, the ratio of the size of the first direction DR1 component and the size of the second direction DR2 component of the fifth direction DR5 may be 3:1, 2:1, or 1:2.

[0080] The sixth sub-pattern 241 may have a first conductivity type. A channel connecting the first source / drain region SD1 and the second source / drain region SD2 may be formed in the sixth sub-pattern 241 by a voltage applied to the gate electrode 220. The channel may be provided adjacent to a surface of the sixth sub-pattern 241. The sixth sub-pattern 241 may have a D1 surface 241a, a D2 surface, and a D3 surface 241c. The D1 surface 241a, the D2 surface, and the D3 surface 241c may extend along a fifth direction DR5. The D1 surface 241a and the D2 surface 241b may be both side surfaces of the sixth sub-pattern 241 located opposite to each other. The D3 surface 241c may be an upper surface of the sixth sub-pattern 241. The D3 surface 241c may have substantially the same plane index as the first surface 100a. For example, the D3 surface 241c may be a (100) surface. The equivalent plane index of the D1 surface 241a can be determined to have a low interface trap density. For example, the D1 surface 241a can be a {310} surface or a {210} surface. For example, the D1 surface 241a can be a (130), (120), or (210) surface.

[0081] The seventh sub-pattern 242 may be provided between the sixth sub-pattern 241 and the second sub-pattern 212. One end of the seventh sub-pattern 242 may be connected to the sixth sub-pattern 241, and the other end may be connected to the second sub-pattern 212. The seventh sub-pattern 242 may extend along a sixth direction DR6 intersecting the first direction DR1, the second direction DR2, and the fifth direction DR5. The sixth direction DR6 may have a first direction DR1 component and a second direction DR2 component. When the sizes of the first direction DR1 components of the sixth direction DR6 and the fifth direction DR5 are the same, the size of the second direction DR2 component of the sixth direction DR6 may be larger than the size of the second direction DR2 component of the fifth direction DR5. When the ratio of the size of the first direction DR1 component to the size of the second direction DR2 component of the fifth direction DR5 is 3:1, the ratio of the size of the first direction DR1 component to the size of the second direction DR2 component of the sixth direction DR6 may be 2:1, 1:2, or 1:3. When the ratio of the size of the first direction DR1 component to the size of the second direction DR2 component of the fifth direction DR5 is 2:1, the ratio of the size of the first direction DR1 component to the size of the second direction DR2 component of the sixth direction DR6 may be 1:2 or 1:3. When the ratio of the size of the first direction DR1 component to the size of the second direction DR2 component of the fifth direction DR5 is 1:2, the ratio of the size of the first direction DR1 component to the size of the second direction DR2 component of the sixth direction DR6 may be 1:3.

[0082] The seventh sub-pattern 242 may have a first conductivity type. A channel connecting the first source / drain region SD1 and the second source / drain region SD2 may be formed in the seventh sub-pattern 242 by a voltage applied to the gate electrode 220. The channel may be provided adjacent to a surface of the seventh sub-pattern 242. The seventh sub-pattern 242 may have an E1 plane 242a, an E2 plane, and an E3 plane 242c. The E1 plane 242a, the E2 plane, and the E3 plane 242c may extend along a sixth direction DR6. The E1 plane 242a and the E2 plane 242b may be both side surfaces of the seventh sub-pattern 242 located opposite to each other. The E3 plane 242c may be an upper surface of the seventh sub-pattern 242. The E3 plane 242c may have substantially the same plane index as the first plane 100a. For example, the E3 plane 242c may be a (100) plane. The equivalent plane index of the E1 plane 242a can be determined to have a low interface trap density. For example, the E1 plane 242a can be a {210} plane or a {310} plane. For example, the E1 plane 241a can be a (120), (210), or (310) plane.

[0083] The gate electrode 220 may be provided on the sixth sub-pattern 241 and the seventh sub-pattern 242. The gate electrode 220 may be provided on the D1 plane 241a, the D3 plane 241c, the E1 plane 242a, and the E3 plane 242c. In a plan view, the gate electrode 220 may completely overlap the D1 plane 241a, the D3 plane 241c, the E1 plane 242a, and the E3 plane 242c. The gate insulating film 230 may be provided between the gate electrode 220 and the sixth sub-pattern 241 and between the gate electrode 220 and the seventh sub-pattern 242. The gate insulating film 230 may include an electrically insulating material. For example, the gate insulating film 230 may include silicon oxide, silicon nitride, or silicon oxynitride. The gate electrode 220 is provided on the D1 plane 241a, the D3 plane 241c, the E1 plane 242a, and the E3 plane 242c, so that the channel of the pixel transistor 200 can be formed on the D1 plane 241a, the D3 plane 241c, the E1 plane 242a, and the E3 plane 242c.

[0084] The present invention can provide a pixel 13 with improved charge trapping phenomenon by using a surface with low interface trap density (e.g., {310} surface, {210} surface) as a channel using the sixth sub-pattern 241 and the seventh sub-pattern 242. Therefore, an image sensor with improved noise characteristics can be provided.

[0085] 8 is a plan view showing a pixel of an image sensor according to an exemplary embodiment. A cross-sectional view taken along line E1-E1' in FIG. 8 may be substantially the same as FIG. 5B. A cross-sectional view taken along line E2-E2' in FIG. 8 may be substantially the same as FIG. 4C. For ease of explanation, differences from the embodiment described with reference to FIG. 7A will be described.

[0086] 4C, 5B, and 8, unlike that described with reference to FIG. 7A, the gate electrode 220 and the gate insulating film 230 may be further extended onto the D2 surface 241b of the sixth sub-pattern 241 and the E2 surface 242b of the seventh sub-pattern 242. The equivalent plane indexes of the D2 surface 241b and the E2 surface 242b may be determined to have a low interface trap density. The D2 surface 241b may be a {210} surface or a {310} surface. When the D1 surface 241a is a (210) surface, the D2 surface 241b may be a {210} surface or a {310} surface.

[0087]

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[0090]

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[0092]

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[0093] The gate electrode 220 is provided on the D1 plane 241a, the D2 plane 241b, the D3 plane 241c, the E1 plane 242a, the E2 plane 242b, and the E3 plane 242c, so that a channel of the pixel transistor 200 can be formed in the region adjacent to the D1 plane 241a, the D2 plane 241b, the D3 plane 241c, the E1 plane 242a, the E2 plane 242b, and the E3 plane 242c.

[0094] The present invention can provide a pixel 14 with improved charge trapping by using a plane with low interface trap density (e.g., {310} plane and {210} plane) as a channel, thereby providing an image sensor with improved noise characteristics.

[0095] FIG 9A is a plan view showing a pixel of an image sensor according to an exemplary embodiment. FIG 9B is a plan view showing a semiconductor pattern of FIG 9A. A cross-sectional view taken along line F1-F1' of FIG 9A may be substantially the same as FIG 4B. A cross-sectional view taken along line F2-F2' of FIG 9A may be substantially the same as FIG 6B. A cross-sectional view taken along line F3-F3' of FIG 9A may be substantially the same as FIG 4C. For ease of explanation, differences from the embodiment described with reference to FIG 7A will be described.

[0096] 7C and 9A to 9C, unlike the description with reference to FIG. 7A, the semiconductor pattern 210 may include an eighth sub-pattern 243 and a ninth sub-pattern 244 instead of the sixth sub-pattern 241, and may include a tenth sub-pattern 245 and an eleventh sub-pattern 246 instead of the seventh sub-pattern 242. The eighth sub-pattern 243 may be provided between the tenth sub-pattern 245 and the first sub-pattern 211. One end of the eighth sub-pattern 243 may be connected to the first sub-pattern 211, and the other end may be connected to the tenth sub-pattern 245. The ninth sub-pattern 244 may be provided between the eleventh sub-pattern 246 and the first sub-pattern 211. One end of the ninth sub-pattern 244 may be connected to the first sub-pattern 211, and the other end may be connected to the eleventh sub-pattern 246. The eighth sub-pattern 243 and the ninth sub-pattern 244 may extend along a fifth direction DR5.

[0097] The tenth subpattern 245 may be provided between the second subpattern 212 and the eighth subpattern 243. One end of the tenth subpattern 245 may be connected to the eighth subpattern 243 and the other end may be connected to the second subpattern 212. The eleventh subpattern 246 may be provided between the second subpattern 212 and the ninth subpattern 244. One end of the eleventh subpattern 246 may be connected to the ninth subpattern 244 and the other end may be connected to the second subpattern 212. The tenth subpattern 245 and the eleventh subpattern 246 may extend along a sixth direction DR5.

[0098] The eighth to eleventh sub-patterns 243, 244, 245, and 246 may have a first conductivity type. A channel connecting the first source / drain region SD1 and the second source / drain region SD2 may be formed in the eighth to eleventh sub-patterns 243, 244, 245, and 246 by a voltage applied to the gate electrode 220. The channel may be provided adjacent to the surfaces of the eighth to first patterns 243, 244, 245, and 246. The eighth sub-pattern 243 may have an F1 surface 243a, an F2 surface 243b, and an F3 surface 243c. The F1 surface 243a and the F2 surface 243b may be both side surfaces of the eighth sub-pattern 243 located opposite to each other. The F3 surface 243c may be an upper surface of the eighth sub-pattern 243. The ninth sub-pattern 244 may have a G1 surface 244a, a G2 surface 244b, and a G3 surface 244c. The G1 surface 244a and the G2 surface 244b may be opposite side surfaces of the ninth sub-pattern 244. The G3 surface 244c may be the top surface of the ninth sub-pattern 244. The F1 surface 243a and the G2 surface 244b may face each other.

[0099] The tenth sub-pattern 245 may have an H1 surface 245a, an H2 surface 245b, and an H3 surface 245C. The H1 surface 245a and the H2 surface 245b may be both side surfaces of the tenth sub-pattern 245 located opposite to each other. The H3 surface 245C may be the top surface of the tenth sub-pattern 245. The eleventh sub-pattern 246 may have an I1 surface 246A, an I2 surface 246B, and an I3 surface 246C. The I1 surface 246A and the I2 surface 246B may be both side surfaces of the eleventh sub-pattern 246 located opposite to each other. The I3 surface 246C may be the top surface of the eleventh sub-pattern 246. The H1 surface 245a and the I2 surface 246B may face each other.

[0100] The F3 plane 243c, the G3 plane 244c, the H3 plane 245C, and the I3 plane 246C may have substantially the same plane index as the first plane 100a. For example, the F3 plane 243c, the G3 plane 244c, the H3 plane 245C, and the I3 plane 246C may be (100) planes. The equivalent plane indexes of the F1 plane 243a, the F2 plane 243b, the G1 plane 244a, the G2 plane 244b, the H1 plane 245a, the H2 plane 245b, the I1 plane 246A, and the I2 plane 246B may be determined to have a low interface trap density. In one example, the F1 plane 243a, the F2 plane 243b, the G1 plane 244a, and the G2 plane 244b may be {310} planes. In one example, the F1 surface 243a and the G1 surface 244a are (130) surfaces, and the F2 surface 243b and the G2 surface 244b are (130) surfaces.

[0101]

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[0110] The gate electrode 220 may be provided on the eighth to eleventh sub-patterns 243, 244, 245, and 246. The gate electrode 220 may be configured to face the F1 surface 243a, the F2 surface 243b, the F3 surface 243c, the G1 surface 244a, the G2 surface 244b, the G3 surface 244c, the H1 surface 245a, the H2 surface 245b, the H2 surface 245b, the I1 surface 246A, the I2 surface 246B, and the I3 surface 246C. A portion of the gate electrode 220 may extend to a region between the eighth sub-pattern 243 and the ninth sub-pattern 244 and a region between the tenth sub-pattern 245 and the eleventh sub-pattern 246.

[0111] The gate insulating film 230 may be provided between the gate electrode 220 and the semiconductor pattern 210. For example, the gate insulating film 230 may cover the F1 surface 243a, the F2 surface 243b, the F3 surface 243c, the G1 surface 244a, the G2 surface 244b, the G3 surface 244c, the H1 surface 245a, the H2 surface 245b, the H2 surface 245b, the I1 surface 246A, the I2 surface 246B, and the I3 surface 246C. The gate insulating film 230 may electrically separate the semiconductor pattern 210 and the gate electrode 220. In one embodiment, the gate insulating film 230 and the gate electrode 220 may fill a region between the eighth sub-pattern 243 and the ninth sub-pattern 244 and a region between the tenth sub-pattern 245 and the eleventh sub-pattern 246.

[0112] The present invention provides a pixel 15 in which the charge trapping phenomenon is improved by increasing the area of ​​a surface (e.g., {310} surface, {210} surface) having a low interface trap density used as a channel by using the eighth to eleventh sub-patterns 243, 244, 245, and 246. Therefore, an image sensor with improved noise characteristics can be provided.

[0113] FIG 10A is a plan view showing a pixel group of an image sensor according to an exemplary embodiment. FIG 10B is a cross-sectional view taken along line G1-G1' in FIG 10A. FIG 10C is a cross-sectional view taken along line G2-G2' in FIG 10A. FIG 10D is a plan view showing a semiconductor pattern in FIG 10A. For ease of explanation, contents that are substantially the same as those described with reference to FIG 4A to FIG 4D will not be described.

[0114] 10A to 10D, a first pixel group 20 including a first pixel PX1, a second pixel PX2, a third pixel PX3, and a fourth pixel PX4 may be provided. The first pixel group 20 may be a collection of pixels that share pixel transistors. For example, the first to fourth pixels PX1, PX2, PX3, and PX4 may share at least one of a source follower transistor, a reset transistor, and a selection transistor.

[0115] The first pixel PX1 may be substantially the same as the pixel 10 described with reference to FIGS. 4A to 4D rotated by 180° in a plan view. The second pixel PX2 may be substantially the same as the first pixel PX1 inverted along the arrangement direction of the first pixel PX1 and the second pixel PX2 in a plan view. The third pixel PX3 may be substantially the same as the first pixel PX1 rotated by 180° in a plan view. The third pixel PX3 may be substantially the same as the pixel 10 described with reference to FIGS. 4A to 4D. The fourth pixel PX4 may be substantially the same as the first pixel PX1 inverted along the arrangement direction of the first pixel PX1 and the fourth pixel PX4 in a plan view. As described above and below, one pixel being substantially the same as another pixel means, for example, that the layout of one pixel is the same as the layout of another pixel.

[0116] In one embodiment, the equivalent plane indexes of the A1 plane 213a and the A2 plane 213b of the first to fourth pixels PX1, PX2, PX3, and PX4 may be {310}. When the A1 plane 213a of the third pixel PX3 is a (310) plane, the A1 planes 213a of the first pixel PX1, the second pixel PX2, and the fourth pixel PX4 are each

[0117]

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[0129] In one embodiment, the equivalent plane indexes of the A1 plane 213a and the A2 plane 213b of the first to fourth pixels PX1, PX2, PX3, and PX4 may be {210}. When the A1 plane 213a of the third pixel PX3 is a (210) plane, the A1 planes 213a of the first pixel PX1, the second pixel PX2, and the fourth pixel PX4 are each

[0130]

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[0142] The first pixel PX1 and the second pixel PX2 may be spaced apart from each other along a first direction DR1. The first pixel PX1 and the fourth pixel PX4 may be spaced apart from each other along a second direction DR2. The third pixel PX3 may be spaced apart from the second pixel PX2 along the second direction DR2. The fourth pixel PX4 may be spaced apart from the third pixel PX3 along the first direction DR1. A pixel isolation layer 108 may be provided between the first to fourth pixels PX1, PX2, PX3, and PX4. The pixel isolation layer 108 may surround each of the first to fourth pixels PX1, PX2, PX3, and PX4.

[0143] An interlayer insulating layer 310 may be provided on the substrate 100. The interlayer insulating layer 310 may cover the pixel transistors 200a, 200b, 200c, and 200d. The interlayer insulating layer 310 may include, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0144] A first contact CT1, a second contact CT2, a third contact CT3, a fourth contact CT4, a fifth contact CT5, and a sixth contact CT6 may be provided through the interlayer insulating film 310. The first contact CT1, the second contact CT2, the third contact CT3, the fourth contact CT4, the fifth contact CT5, and the sixth contact CT6 may extend along a third direction DR3. The first contact CT1 may be electrically connected to the transmission gate electrode 106g. The second contact CT2 may be electrically connected to the floating diffusion regions 104a, 104b, 104c, and 104d. The third contact CT3 may be electrically connected to the first source / drain region SD1. The fourth contact CT4 may be electrically connected to the gate electrode 220. The fifth contact CT5 may be electrically connected to the second source / drain region SD2. The sixth contact CT6 may be electrically connected to the ground region 105. The first to sixth contacts CT6 may be electrically connected to the horizontal conductive line HL, respectively. Although one contact and one horizontal conductive line are illustrated as being connected, this is merely an example. The number of contacts and horizontal conductive lines may be determined as necessary. For example, a plurality of contacts and a plurality of horizontal conductive lines may be alternately connected.

[0145] A capping insulating layer 320 may be provided on the interlayer insulating layer 310. The capping insulating layer 320 may be configured to cover the horizontal conductive line HL to protect the horizontal conductive line HL. The capping insulating layer 320 may include, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0146] A backside insulating layer 410 may be provided on the second side 100b. The backside insulating layer 410 may include, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0147] The color filter 420 may be provided on the rear insulating film 410. The color filter 420 may be provided to correspond to the photoelectric conversion region PD. The color filter 420 may be included in a color filter 420 array arranged in a matrix shape. In one embodiment, the color filter 420 array may have a Bayer pattern including a red filter, a green filter, and a blue filter. In another embodiment, the color filter 420 array may include a yellow filter, a magenta filter, and a cyan filter. Also, the color filter 420 array may further include a white filter. Meanwhile, according to an embodiment, an anti-reflection layer, at least one insulating film, etc. may be further formed between the second surface 110R of the semiconductor substrate 110 and the color filter 420.

[0148] The microlens 430 may be provided on the color filter 420. The microlens 430 may be configured to focus incident light on the microlens 430 to the photoelectric conversion region PD. The microlenses 430 may be included in a microlens array arranged in a matrix shape. Although the microlenses 430 are illustrated as being arranged one per pixel, this is merely an example. In one example, the microlenses 430 may be arranged one per multiple pixels.

[0149] The present invention can provide a pixel group 20 with improved charge trapping phenomenon by using a plane with low interface trap density (e.g., {310} plane, {210} plane) as a channel, and therefore can provide an image sensor with improved noise characteristics.

[0150] 11 to 15 are plan views of pixel groups of an image sensor according to an exemplary embodiment. For ease of explanation, differences from those described with reference to FIGS. 10A to 10D will be mainly described.

[0151] 11 to 15, a second pixel group 21, a third pixel group 22, a fourth pixel group 23, a fifth pixel group 24, and a sixth pixel group 25 including a first pixel PX1, a second pixel PX2, a third pixel PX3, and a fourth pixel PX4 may be provided.

[0152] In the second pixel group 21 of FIG. 11, the first pixel PX1 may be substantially the same as the pixel 11 described with reference to FIGS. 5A and 5B rotated by 180° in a plan view. The second pixel PX2 may be substantially the same as the first pixel PX1 inverted along the arrangement direction of the first pixel PX1 and the second pixel PX2 in a plan view. The third pixel PX3 may be substantially the same as the first pixel PX1 rotated by 180° in a plan view. The third pixel PX3 may be substantially the same as the pixel 11 described with reference to FIGS. 5A and 5B. The fourth pixel PX4 may be substantially the same as the first pixel PX1 inverted along the arrangement direction of the first pixel PX1 and the fourth pixel PX4 in a plan view.

[0153] In the third pixel group 22 of FIG. 12, the first pixel PX1 may be substantially the same as the pixel 12 described with reference to FIGS. 6A to 6D rotated by 180° in a plan view. The second pixel PX2 may be substantially the same as the first pixel PX1 inverted along the arrangement direction of the first pixel PX1 and the second pixel PX2 in a plan view. The third pixel PX3 may be substantially the same as the first pixel PX1 rotated by 180° in a plan view. The third pixel PX3 may be substantially the same as the pixel 12 described with reference to FIGS. 6A to 6D. The fourth pixel PX4 may be substantially the same as the first pixel PX1 inverted along the arrangement direction of the first pixel PX1 and the fourth pixel PX4 in a plan view.

[0154] In the fourth pixel group 23 of FIG. 13, the first pixel PX1 may be substantially the same as the pixel 13 described with reference to FIGS. 7A and 7B rotated by 180° in a plan view. The second pixel PX2 may be substantially the same as the first pixel PX1 inverted along the arrangement direction of the first pixel PX1 and the second pixel PX2 in a plan view. The third pixel PX3 may be substantially the same as the first pixel PX1 rotated by 180° in a plan view. The third pixel PX3 may be substantially the same as the pixel 13 described with reference to FIGS. 7A and 7B. The fourth pixel PX4 may be substantially the same as the first pixel PX1 inverted along the arrangement direction of the first pixel PX1 and the fourth pixel PX4 in a plan view.

[0155] In the fifth pixel group 24 of FIG. 14, the first pixel PX1 may be substantially the same as the pixel 14 described with reference to FIG. 8 rotated by 180° in a plan view. The second pixel PX2 may be substantially the same as the first pixel PX1 inverted along the arrangement direction of the first pixel PX1 and the second pixel PX2 in a plan view. The third pixel PX3 may be substantially the same as the first pixel PX1 rotated by 180° in a plan view. The third pixel PX3 may be substantially the same as the pixel 14 described with reference to FIG. 8. The fourth pixel PX4 may be substantially the same as the first pixel PX1 inverted along the arrangement direction of the first pixel PX1 and the fourth pixel PX4 in a plan view.

[0156] In the sixth pixel group 25 of FIG. 15, the first pixel PX1 may be substantially the same as the pixel 15 described with reference to FIGS. 9A and 9B rotated by 180° in a plan view. The second pixel PX2 may be substantially the same as the first pixel PX1 inverted along the arrangement direction of the first pixel PX1 and the second pixel PX2 in a plan view. The third pixel PX3 may be substantially the same as the first pixel PX1 rotated by 180° in a plan view. The third pixel PX3 may be substantially the same as the pixel 15 described with reference to FIGS. 9A and 9B. The fourth pixel PX4 may be substantially the same as the first pixel PX1 inverted along the arrangement direction of the first pixel PX1 and the fourth pixel PX4 in a plan view.

[0157] The present invention can provide pixel groups 21, 22, 23, 24, and 25 in which the charge trapping phenomenon is improved by using a plane with a low interface trap density (e.g., {310} plane, {210} plane) as a channel, thereby providing an image sensor with improved noise characteristics.

[0158] Figure 16A is a plan view showing a pixel group of an image sensor according to an exemplary embodiment. Figure 16B is a cross-sectional view taken along line H1-H1' in Figure 16A. The cross-sectional view taken along line H2-H2' in Figure 16A may be substantially the same as Figure 10C. For ease of explanation, contents substantially the same as those described with reference to Figures 10A to 10D will not be described.

[0159] 16A and 16B, a seventh pixel group 26 including a first pixel PX1, a second pixel PX2, a third pixel PX3, and a fourth pixel PX4 may be provided. Unlike what has been described with reference to FIGS. 10A to 10D, the first to fourth pixels PX1, PX2, PX3, and PX4 may share a floating diffusion region 104. The floating diffusion region 104 may be provided between the first to fourth pixels PX1, PX2, PX3, and PX4. For example, the floating diffusion region 104 may be located at the center of the first to fourth pixels PX1, PX2, PX3, and PX4. However, the illustrated position and shape of the floating diffusion region 104 are merely exemplary, and the position and shape may be determined as necessary.

[0160] In a plan view, the substrate 100 may surround the floating diffusion region 104. The substrate 100 of the first pixel PX1 and the substrate 100 of the second pixel PX2, the substrate 100 of the first pixel PX1 and the substrate 100 of the fourth pixel PX4, the substrate 100 of the second pixel PX2 and the substrate 100 of the third pixel PX3, and the substrate 100 of the third pixel PX3 and the substrate 100 of the fourth pixel PX4 may be connected to each other.

[0161] The pixel isolation layer 108 may fill the regions between the first to fourth pixels PX1, PX2, PX3, and PX4. Unlike what has been described with reference to Figures 10A to 10D, the pixel isolation layer 108 may partially surround each of the first to fourth pixels PX1, PX2, PX3, and PX4.

[0162] The present invention can provide a pixel group 26 with improved charge trapping by using a plane with low interface trap density (e.g., {310} plane, {210} plane) as a channel, thereby providing an image sensor with improved noise characteristics.

[0163] The above is a specific embodiment for carrying out the present invention. In addition to the above-described embodiment, the present invention also includes embodiments that can be simply modified or easily modified. The present invention also includes techniques that can be easily modified using the embodiment. Therefore, the scope of the present invention is not limited to the above-described embodiment, but should be determined not only by the claims below, but also by equivalents to the claims of the present invention. [Explanation of symbols]

[0164] 10 pixels 100 Substrates 102 Photoelectric conversion area 104 Floating Diffusion Region 105 Grounding area 106 Transmission Gate Structure 106g Transmission gate electrode 106i Transmission gate insulating film 108 Pixel separation membrane 110 Element isolation film SD1, SD2 source / drain regions VTG Vertical Transmission Gate 200 pixel transistor 210 Semiconductor Pattern 211,212,213 Subpatterns 220 Gate electrode 230 Gate insulating film

Claims

1. A substrate including a photoelectric conversion region; a semiconductor pattern provided on the substrate; a gate electrode provided on the semiconductor pattern; a gate insulating film provided between the semiconductor pattern and the gate electrode, the semiconductor pattern includes a first sub-pattern including a first source / drain region, a second sub-pattern including a second source / drain region, and a third sub-pattern provided between the first sub-pattern and the second sub-pattern; the gate electrode is provided on the third sub-pattern; The first sub-pattern, the second sub-pattern, and the third sub-pattern extend along different directions from each other.

2. The image sensor of claim 1 , wherein the gate electrode extends onto a first side of the third sub-pattern.

3. The image sensor of claim 2 , wherein the first side surface is a {310} surface or a {210} surface.

4. The semiconductor pattern further includes a fourth sub-pattern provided between the second sub-pattern and the third sub-pattern, the gate electrode is provided on the fourth sub-pattern; The image sensor of claim 1 , wherein the fourth sub-pattern extends along a different direction than the first sub-pattern, the second sub-pattern, and the third sub-pattern.

5. The image sensor of claim 4 , wherein the gate electrode extends onto a third side of the fourth sub-pattern and a fourth side of the fourth sub-pattern opposite the third side.

6. The image sensor of claim 5 , wherein the third side surface and the fourth side surface are {310} surfaces or {210} surfaces.

7. The semiconductor pattern further includes a fifth sub-pattern provided between the first sub-pattern and the second sub-pattern, The fifth sub-pattern is arranged alongside the third sub-pattern, The image sensor of claim 1 , wherein the gate electrode is provided on the fifth sub-pattern.

8. the third sub-pattern has a first side and a second side disposed opposite each other; the fifth sub-pattern has a fifth side and a sixth side disposed opposite each other; The image sensor of claim 7 , wherein the gate electrode extends onto the first side, the second side, the fifth side, and the sixth side.

9. The image sensor of claim 8 , wherein the first side, the second side, the fifth side, and the sixth side are {310} or {210} surfaces.

10. A first pixel; a second pixel, Each of the first and second pixels includes a substrate including a photoelectric conversion region and a floating diffusion region, a semiconductor pattern provided on the substrate, a gate electrode provided on the semiconductor pattern, and a gate insulating layer provided between the semiconductor pattern and the gate electrode, In each of the first and second pixels, the semiconductor pattern includes a first sub-pattern including a first source / drain region, a second sub-pattern including a second source / drain region, and a third sub-pattern provided between the first sub-pattern and the second sub-pattern, the first sub-pattern, the second sub-pattern, and the third sub-pattern extending along different directions from each other, and the gate electrode is provided on a side of the third sub-pattern; The floating diffusion regions of the first and second pixels are electrically connected to the gate electrode of the first pixel or the gate electrode of the second pixel.

Images