Semiconductor device, manufacturing method of the semiconductor device, and electronic device

Abstract

To realize a semiconductor device with high performance, having a source field plate.SOLUTION: A semiconductor device 1A contains: a substrate 10; a gate electrode 20 provided to a surface 13 side of the substrate 10; a source electrode 30 that is provided to each of both sides of the gate electrode 20 on the surface 13 side of the substrate 10; and a drain electrode 40. The semiconductor device 1A further contains a source field plate 50 that is provided at a neighbor of the gate electrode 20 that is near from the drain electrode 40 so as to be between the gate electrode 20 and the drain electrode 40 on the surface 13 side of the substrate 10. In the semiconductor device 1A, the source electrode 30 and the source field plate 50 are connected with air bridge wiring 80. Thus, a damage due to a magnetic filed of a drain voltage at an electric connection part of the source electrode 30 and the source field plate 50 is suppressed.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, a method for manufacturing a semiconductor device, and an electronic device. [Background technology]

[0002] Known semiconductor device technologies include a technique of arranging a source field plate shorted to a source electrode near a gate electrode, and a technique of arranging a shield plate electrode shorted to a source electrode near a drain electrode (Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2013-183062 A Summary of the Invention [Problem to be solved by the invention]

[0004] In a semiconductor device equipped with a source field plate, depending on the form of the electrical connection between the source electrode and the source field plate, the electric field of the drain voltage may cause breakdown in the electrical connection, resulting in a decrease in performance of the semiconductor device.

[0005] In one aspect, the present invention aims to provide a high-performance semiconductor device including a source field plate. [Means for solving the problem]

[0006] In one aspect, a semiconductor device is provided, comprising: a substrate; a gate electrode provided on a first surface side of the substrate; a source electrode and a drain electrode provided on either side of the gate electrode on the first surface side of the substrate; a source field plate provided between the gate electrode and the drain electrode on the first surface side of the substrate and closer to the gate electrode than the drain electrode; and an air bridge wiring connecting the source electrode and the source field plate.

[0007] In another aspect, there is provided a method for manufacturing the semiconductor device as described above, and an electronic device including the semiconductor device as described above. Effect of the Invention

[0008] According to one aspect, it becomes possible to realize a high-performance semiconductor device having a source field plate. [Brief description of the drawings]

[0009] [Figure 1] 1A and 1B are diagrams illustrating a configuration example of a semiconductor device. [Diagram 2] 1A and 1B are diagrams illustrating an example of a semiconductor device. [Diagram 3] FIG. 1 is a diagram (part 1) for explaining an example of a semiconductor device according to a first embodiment. [Figure 4] FIG. 2 is a diagram (part 2) for explaining an example of the semiconductor device according to the first embodiment. [Diagram 5] 1A to 1C are diagrams illustrating an example of a method for manufacturing a semiconductor device according to a first embodiment; [Figure 6] FIG. 2 is a second view for explaining an example of the method for manufacturing the semiconductor device according to the first embodiment; [Figure 7] FIG. 11 is a view (part 3) illustrating an example of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] 10A to 10C are diagrams illustrating an example of a semiconductor device according to a second embodiment. [Figure 9]13A to 13C are diagrams illustrating an example of a semiconductor device according to a third embodiment. [Figure 10] 13A to 13C are views (part 1) illustrating an example of a method for manufacturing a semiconductor device according to a third embodiment. [Figure 11] FIG. 13 is a second view for explaining an example of a method for manufacturing a semiconductor device according to a third embodiment. [Figure 12] 13A to 13C are diagrams illustrating an example of a semiconductor device according to a fourth embodiment. [Figure 13] 13A to 13C are diagrams illustrating an example of a semiconductor package according to a fifth embodiment. [Figure 14] FIG. 13 is a diagram illustrating an example of a power factor correction circuit according to a sixth embodiment. [Figure 15] FIG. 13 is a diagram illustrating an example of a power supply device according to a seventh embodiment. [Figure 16] FIG. 13 is a diagram illustrating an example of an amplifier according to an eighth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] First, an example of a semiconductor device will be described. As an example of a semiconductor device, one using a nitride semiconductor is known. Semiconductor devices using nitride semiconductors are being developed as high-voltage, high-power devices by utilizing characteristics such as high saturation electron velocity and wide band gap. For example, gallium nitride (GaN) has a band gap of 3.4 eV, which is larger than the band gap of silicon (Si) of 1.1 eV and the band gap of gallium arsenide (GaAs) of 1.4 eV, and has a high dielectric breakdown field. Therefore, nitride semiconductors such as GaN are promising materials for semiconductor devices that operate at high voltages and have high power, such as semiconductor devices applied to amplifiers, power supplies, communication devices, radar devices, etc. As a semiconductor device using a nitride semiconductor, a field effect transistor (FET), for example, a high electron mobility transistor (HEMT), is known.

[0011] Fig. 1 is a diagram for explaining a configuration example of a semiconductor device, which diagrammatically shows a cross-sectional view of a main part of an example of a semiconductor device. The semiconductor device 1 shown in Fig. 1 is an example of a HEMT. The semiconductor device 1 includes a substrate 10 including an underlying substrate 11 and a semiconductor layer 12 provided thereon. The semiconductor device 1 further includes a gate electrode 20, a source electrode 30, and a drain electrode 40 provided on the substrate 10.

[0012] The base substrate 11 may be made of various materials such as silicon carbide (SiC), Si, GaN, aluminum nitride (AlN), sapphire, diamond, etc. The base substrate 11 may have a single layer structure of one material, or a laminate structure of one or more materials.

[0013] A nitride semiconductor such as GaN or aluminum gallium nitride (AlGaN) is used for the semiconductor layer 12. The semiconductor layer 12 includes, for example, a channel layer 12a, a barrier layer 12b, and a cap layer 12c as shown in FIG.

[0014] The channel layer 12a is provided on the base substrate 11. The channel layer 12a is made of, for example, GaN. The channel layer 12a may be made of a nitride semiconductor such as AlGaN, indium gallium nitride (InGaN), or indium aluminum gallium nitride (InAlGaN). The channel layer 12a may be a single-layer structure of one type of nitride semiconductor, or a multilayer structure of one or more types of nitride semiconductors. The channel layer 12a is formed on the base substrate 11 by using a metal organic chemical vapor deposition (MOCVD) or metal organic vapor phase epitaxy (MOVPE) method, a molecular beam epitaxy (MBE) method, or the like. The channel layer 12a is also called an electron transport layer, a carrier transport layer, or the like.

[0015] The barrier layer 12b is provided on the channel layer 12a. For example, AlGaN is used for the barrier layer 12b. Alternatively, a nitride semiconductor such as indium aluminum nitride (InAlN), InAlGaN, or AlN may be used for the barrier layer 12b. The barrier layer 12b may have a single-layer structure of one type of nitride semiconductor, or a laminate structure of one or more types of nitride semiconductors. The barrier layer 12b is formed on the channel layer 12a by using a MOVPE method or the like. The barrier layer 12b is also called an electron supply layer, a carrier supply layer, or the like.

[0016] Here, the channel layer 12a and the barrier layer 12b are made of nitride semiconductors with different bandgaps. A two-dimensional electron gas (2DEG) region 101 is generated in the channel layer 12a by spontaneous polarization of the nitride semiconductor of the barrier layer 12b and piezoelectric polarization generated in the barrier layer 12b due to strain caused by a lattice constant difference between the barrier layer 12b and the nitride semiconductor of the channel layer 12a. The channel layer 12a and the barrier layer 12b are made of nitride semiconductors in such a combination that the 2DEG region 101 is generated in the channel layer 12a.

[0017] The cap layer 12c is provided on the barrier layer 12b. The cap layer 12c is made of a doped (p-type or n-type) or non-doped nitride semiconductor such as GaN. The cap layer 12c may have a single-layer structure of one type of nitride semiconductor, or a laminate structure of one or more types of nitride semiconductors. The cap layer 12c has a function of protecting the barrier layer 12b and the like. In addition, the cap layer 12c may have a function of modulating the electron concentration of the 2DEG region 101 of the channel layer 12a.

[0018] Although not shown here, a layer of AlN or the like may be provided between the base substrate 11 and the channel layer 12a as an initial layer, a layer of AlGaN or the like may be provided as a buffer layer, or a layer of GaN or the like doped with iron (Fe) may be provided. In addition, a layer of AlN, AlGaN or the like may be provided between the base substrate 11 and the channel layer 12a as a barrier layer (back barrier layer) for realizing a quantum well (quantum confinement) structure. A layer of AlGaN, InGaN or the like may be provided between the channel layer 12a and the barrier layer 12b as a spacer layer. The semiconductor layer 12 may include one or more of such initial layers, buffer layers, spacer layers, back barrier layers, etc., in addition to the channel layer 12a, the barrier layer 12b, and the cap layer 12c.

[0019] The gate electrode 20 is provided on the semiconductor layer 12. A metal material is used for the gate electrode 20. For example, a laminate having nickel (Ni) and gold (Au) provided thereon is provided as the gate electrode 20. The gate electrode 20 is formed by using a deposition method or the like. The gate electrode 20 is provided so as to function as, for example, a Schottky electrode. Alternatively, the gate electrode 20 may be provided on the semiconductor layer 12 via a gate insulating film (not shown) to form a MIS (Metal Insulator Semiconductor) type gate structure.

[0020] The source electrode 30 and the drain electrode 40 are provided on the semiconductor layer 12 on both sides of the gate electrode 20, on the cap layer 12c in this example, at a distance from the gate electrode 20. A metal material is used for the source electrode 30 and the drain electrode 40. For example, a laminate having tantalum (Ta) and aluminum (Al) provided thereon is provided as the source electrode 30 and the drain electrode 40. The source electrode 30 and the drain electrode 40 are formed by using a deposition method or the like. The source electrode 30 and the drain electrode 40 are provided so as to function as ohmic electrodes. As long as the source electrode 30 and the drain electrode 40 function as ohmic electrodes, they may be connected to the barrier layer 12b without being limited to the cap layer 12c, or may be connected to the channel layer 12a through the barrier layer 12b. A contact layer (regrowth layer) using a nitride semiconductor such as n-type GaN or n-type AlGaN may be provided at the portion of the semiconductor layer 12 where the source electrode 30 and the drain electrode 40 are connected.

[0021] When the semiconductor device 1 is in operation, a predetermined voltage is applied between the source electrode 30 and the drain electrode 40, and a predetermined voltage is applied to the gate electrode 20. The amount of charge passing through the 2DEG region 101 immediately below the gate electrode 20 between the source electrode 30 and the drain electrode 40 is controlled by the electric field effect caused by the voltage applied to the gate electrode 20, thereby controlling the output drain current. In this manner, the transistor function of the semiconductor device 1 is realized.

[0022] Incidentally, as a semiconductor device equipped with a HEMT, for example, one as shown in FIG. 2 is known. Fig. 2 is a diagram for explaining an example of a semiconductor device. Fig. 2(A) shows a schematic plan view of a main part of an example of a semiconductor device. Fig. 2(B) shows a schematic cross-sectional view of a main part of an example of a semiconductor device. Fig. 2(B) is a schematic cross-sectional view taken along II-II in Fig. 2(A). For convenience, hatching is also applied to the plan view in Fig. 2(A).

[0023] 2A and 2B includes a substrate 110, a gate electrode 120, a source electrode 130, and a drain electrode 140. The semiconductor device 100 further includes a source field plate 150.

[0024] As shown in Fig. 2(B), the substrate 110 includes a base substrate 111 and a semiconductor layer 112 provided thereon. The base substrate 11 described above with reference to Fig. 1 is used for the base substrate 111. The semiconductor layer 112 includes the semiconductor layer 12 described above with reference to Fig. 1, and includes the channel layer 12a, barrier layer 12b, cap layer 12c, and the like described above.

[0025] The gate electrodes 120, the source electrodes 130, and the drain electrodes 140 are provided on one surface 113 of the substrate 110. A plurality of gate electrodes 120, a plurality of source electrodes 130, and a plurality of drain electrodes 140 are provided on the surface 113 of the substrate 110. The gate electrodes 120 are connected to gate bus lines 121 (FIG. 2(A)). The gate electrodes 120 are provided side by side. The source electrodes 130 are provided side by side with each other and with the gate electrodes 120. The drain electrodes 140 are provided side by side with each other and with the gate electrodes 120.

[0026] A source electrode 130 and a drain electrode 140 are provided on both sides of the gate electrode 120, respectively, at a distance from the gate electrode 120. For example, the gate electrode 120 is provided closer to the source electrode 130 than the drain electrode 140. The portions between the source electrode 130 and the drain electrode 140 sandwiching the gate electrode 120 function as transistor elements (or transistor cells). At least a portion of each of the gate electrode 120, the source electrode 130, and the drain electrode 140 is provided on an active region 110a defined by an element isolation region 110b formed in the substrate 110 (FIG. 2(A)).

[0027] On the element isolation region 110b of the substrate 110, a gate bus line 121 connected to the gate electrode 120 is provided, and a gate pad portion (not shown) connected to the gate bus line 121 may also be provided. Furthermore, on the element isolation region 110b of the substrate 110, a source pad portion (not shown) connected to the source electrode 130, a drain pad portion (not shown) connected to the drain electrode 140, etc. may also be provided.

[0028] It should be noted that the numbers of gate electrodes 120, source electrodes 130 and drain electrodes 140 of the semiconductor device 100, that is, the number of transistor elements, are not limited to those shown in FIGS. 2(A) and 2(B).

[0029] The semiconductor device 100 further includes a passivation film 160 and an interlayer insulating film 170 provided on the surface 113 side of the substrate 110 . The passivation film 160 is provided between the source electrode 130 and the drain electrode 140, as shown in Figures 2(A) and 2(B). The passivation film 160 is provided so as to partially cover a part of the surface 113 of the substrate 110, as well as a lower part of the source electrode 130 and a lower part of the drain electrode 140, as shown in Figure 2(B). The passivation film 160 is made of an insulating material such as silicon nitride (SiN). The gate electrode 120 is provided in an opening 161 provided in the passivation film 160, as shown in Figure 2(B).

[0030] 2(A) and 2(B), the interlayer insulating film 170 is provided so as to cover the passivation film 160, the gate electrode 120, and the gate bus line 121. An insulating material such as silicon oxide (SiO) is used for the interlayer insulating film 170. As shown in FIG. 2(B), an upper layer portion of the source electrode 130 and an upper layer portion of the drain electrode 140 are provided so as to penetrate the interlayer insulating film 170 and the passivation film 160.

[0031] In the semiconductor device 100, a source field plate 150 is provided in the interlayer insulating film 170 in the vicinity of the gate electrode 120 and alongside the gate electrode 120. The source field plate 150 is provided on the drain electrode 140 side of the gate electrode 120 in a plan view. The source field plate 150 is made of a metal material such as Au, copper (Cu), Al, Ni, Ta, or titanium (Ti).

[0032] 2A, the source field plate 150 is connected to the source electrode 130 through a wiring 180 in the interlayer insulating film 170. The wiring 180 is made of a metal material such as Au, Cu, Al, Ni, Ta, or Ti. The source field plate 150 is set to the same potential as the source electrode 130 through the wiring 180. The source field plate 150 is provided to disperse the electric field of the voltage (drain voltage) applied to the drain electrode 140 during operation of the semiconductor device 100, and to prevent breakdown of the semiconductor device 100 and a decrease in the withstand voltage.

[0033] However, in the semiconductor device 100, the portion of the wiring 180 that is routed within the interlayer insulating film 170 and connects the source field plate 150 and the source electrode 130, i.e., the portion P1 in Fig. 2(A), may be destroyed by the electric field of the drain voltage. This is thought to be because the wiring 180 has a shape with corners, and the electric field of the drain voltage is likely to be applied to such corners, making the portion of the wiring 180 (portion P1) more likely to be destroyed. Destruction of the portion of the wiring 180 leads to a decrease in the withstand voltage of the semiconductor device 100.

[0034] In the semiconductor device 100, an interlayer insulating film 170 is filled between the gate electrode 120 and the source electrode 130, and between the gate electrode 120 and the drain electrode 140. In this case, capacitance components such as a gate-source capacitance Cgs and a gate-drain capacitance Cgd may be added to the semiconductor device 100. The addition of such capacitance components may affect the high-frequency characteristics of the semiconductor device 100, for example, the cutoff frequency (f T = gm / (2π × Cgs), gm: mutual conductance).

[0035] In view of the above, a configuration as shown in the following embodiment is adopted to realize a high-performance semiconductor device. [First embodiment] Figures 3 and 4 are diagrams for explaining an example of a semiconductor device according to the first embodiment. Figure 3 is a schematic plan view of a main part of the example of the semiconductor device according to the first embodiment. Figure 4 is a schematic cross-sectional view of a main part of the example of the semiconductor device according to the first embodiment. Figure 4 is a schematic cross-sectional view taken along line IV-IV in Figure 3. For convenience, hatching is also applied to the plan view of Figure 3.

[0036] 3 and 4 includes a substrate 10, a gate electrode 20, a source electrode 30, and a drain electrode 40. The semiconductor device 1A further includes a source field plate 50 and an air bridge wiring 80.

[0037] As shown in Fig. 4, the substrate 10 includes a base substrate 11 and a semiconductor layer 12 provided thereon. The base substrate 11 is the same as that described with reference to Fig. 1. The semiconductor layer 12 is the same as that described with reference to Fig. 1, and includes the channel layer 12a, barrier layer 12b, cap layer 12c, and the like.

[0038] The gate electrodes 20, the source electrodes 30, and the drain electrodes 40 are provided on one surface 13 of the substrate 10. The surface 13 of the substrate 10 is also referred to as the "first surface." A plurality of gate electrodes 20, source electrodes 30, and drain electrodes 40 are provided on the surface 13 of the substrate 10. The gate electrodes 20 are connected to gate bus lines 21 as shown in FIG. 3. The gate electrodes 20 are provided side by side. The source electrodes 30 are provided side by side and also with the gate electrodes 20. The drain electrodes 40 are provided side by side and also with the gate electrodes 20.

[0039] A source electrode 30 and a drain electrode 40 are provided on both sides of the gate electrode 20, respectively, at a distance from the gate electrode 20. For example, the gate electrode 20 is provided closer to the source electrode 30 than the drain electrode 40. The portions between the source electrode 30 and the drain electrode 40 sandwiching the gate electrode 20 function as transistor elements (or transistor cells). At least a portion of each of the gate electrode 20, the source electrode 30, and the drain electrode 40 is provided on an active region 10a defined by an element isolation region 10b formed in the substrate 10, as shown in FIG.

[0040] On the element isolation region 10b of the substrate 10, a gate bus line 21 connected to the gate electrode 20 is provided, and a gate pad portion (not shown) connected to the gate bus line 21 may also be provided. Furthermore, on the element isolation region 10b of the substrate 10, a source pad portion (not shown) connected to the source electrode 30, a drain pad portion (not shown) connected to the drain electrode 40, etc. may also be provided.

[0041] It should be noted that the numbers of gate electrodes 20, source electrodes 30 and drain electrodes 40 of the semiconductor device 1A, that is, the number of transistor elements, are not limited to those shown in FIGS. The semiconductor device 1A further includes a passivation film 60 and an interlayer insulating film 70 provided on the surface 13 side of the substrate 10.

[0042] The passivation film 60 is provided between the source electrode 30 and the drain electrode 40, as shown in Figures 3 and 4. The passivation film 60 is provided so as to partially cover a part of the surface 13 of the substrate 10, as well as a lower part of the source electrode 30 (also referred to as a "source electrode lower part") and a lower part of the drain electrode 40 (also referred to as a "drain electrode lower part"), as shown in Figure 4. An insulating material such as SiN is used for the passivation film 60. The gate electrode 20 is provided in an opening 61 provided in the passivation film 60, as shown in Figure 4.

[0043] As shown in FIG. 3 and FIG. 4, the interlayer insulating film 70 is provided so as to cover a part of the passivation film 60, the gate electrode 20, and the gate bus line 21. A cavity 90 is provided between the interlayer insulating film 70 and the source electrode 30, and between the interlayer insulating film 70 and the drain electrode 40. That is, the interlayer insulating film 70 is provided around the gate electrode 20, among the gate electrode 20, the source electrode 30, and the drain electrode 40, but is not provided around the source electrode 30 and the drain electrode 40. An insulating material such as SiO is used for the interlayer insulating film 70. As shown in FIG. 4, an upper layer part of the source electrode 30 (also referred to as the "upper layer part of the source electrode") and an upper layer part of the drain electrode 40 (also referred to as the "upper layer part of the drain electrode") are provided so as to penetrate the passivation film 60.

[0044] 3 and 4, the source field plate 50 is provided on an interlayer insulating film 70 that covers a part of the passivation film 60 and the gate electrode 20. It can also be said that the source field plate 50 is provided on the side of the interlayer insulating film 70 opposite to the substrate 10 side. The source field plate 50 is provided on the interlayer insulating film 70 in the vicinity of the gate electrode 20 and alongside the gate electrode 20. For example, the source field plate 50 is provided on the drain electrode 40 side of the gate electrode 20 or so as to partially overlap with the end of the gate electrode 20 on the drain electrode 40 side in a plan view. The source field plate 50 is made of a metal material such as Au, Cu, Al, Ni, Ta, or Ti.

[0045] 3 and 4, the air bridge wiring 80 is provided so as to connect the source electrode 30 and the source field plate 50. The air bridge wiring 80 connects the source electrode 30 and the source field plate 50 across a cavity 90 between the source electrode 30 and the interlayer insulating film 70 in which the source field plate 50 is provided. The air bridge wiring 80 is made of a metal material such as Au, Cu, Al, Ni, Ta, or Ti.

[0046] In the semiconductor device 1A, a source field plate 50 is provided on an interlayer insulating film 70 that covers the gate electrode 20. In the semiconductor device 1A, the source electrode 30 and the source field plate 50 are connected by an air bridge wiring 80 that is provided so as to straddle a cavity 90 between the source electrode 30 and the interlayer insulating film 70. The source field plate 50 is electrically connected to the source electrode 30 through the air bridge wiring 80 and is at the same potential as the source electrode 30. The source field plate 50 has the function of dispersing the electric field of the drain voltage applied to the drain electrode 40 during operation of the semiconductor device 1A, and suppressing breakdown and a decrease in the breakdown voltage of the semiconductor device 1A.

[0047] In the semiconductor device 1A, the source electrode 30 and the source field plate 50 are connected by an air bridge wiring 80, rather than by a routed wiring having a corner shape to which the electric field of the drain voltage is likely to be applied. That is, in the semiconductor device 1A, the source electrode 30 and the source field plate 50 are connected by an air bridge wiring 80 as shown in Figures 3 and 4, rather than by the wiring 180 of the form shown in Figures 2(A) and 2(B) above.

[0048] According to the air bridge wiring 80, it is possible to prevent the formation of corners to which the electric field of the drain voltage is likely to be applied. Therefore, from the viewpoint of the shape of the air bridge wiring 80, the electric field of the drain voltage is unlikely to be applied to the air bridge wiring 80, and the occurrence of destruction of the air bridge wiring 80 is prevented. Furthermore, according to the air bridge wiring 80, the source electrode 30 and the source field plate 50 are connected in the space above them. Therefore, from the viewpoint of the layout of the air bridge wiring 80, the electric field of the drain voltage is unlikely to be applied to the air bridge wiring 80, and the occurrence of destruction of the air bridge wiring 80 is prevented.

[0049] In the semiconductor device 1A, the application of an electric field of the drain voltage and the occurrence of breakdown due to the electric field of the drain voltage are suppressed by employing the air bridge wiring 80. This effectively suppresses a decrease in the breakdown voltage of the semiconductor device 1A caused by breakdown of the electrical connection between the source electrode 30 and the source field plate 50.

[0050] In the semiconductor device 1A, the gate electrode 20 is covered and protected by the interlayer insulating film 70. In the semiconductor device 1A, a cavity 90 in which the interlayer insulating film 70 is not present is provided between the gate electrode 20 (the interlayer insulating film 70 covering it) and the source electrode 30 and between the gate electrode 20 and the drain electrode 40. In the semiconductor device 1A, the provision of the cavity 90 prevents the addition of capacitive components such as the gate-source capacitance Cgs and the gate-drain capacitance Cgd. This effectively prevents the deterioration of the high-frequency characteristics of the semiconductor device 1A, such as the cutoff frequency, caused by the addition of capacitive components.

[0051] According to the above-described configuration, a high-performance semiconductor device 1A is realized that includes the source field plate 50 and effectively prevents degradation of the breakdown voltage and high-frequency characteristics. Next, a method for manufacturing the semiconductor device 1A will be described.

[0052] 5 to 7 are diagrams for explaining an example of a manufacturing method of a semiconductor device according to the first embodiment. FIG. 5(A) shows a schematic cross-sectional view of a main part of an example of a source electrode lower layer part, a drain electrode lower layer part, and a passivation film forming process. FIG. 5(B) shows a schematic cross-sectional view of a main part of an example of a gate electrode forming process. FIG. 5(C) shows a schematic cross-sectional view of a main part of an example of an interlayer insulating film forming process. FIG. 6(A) shows a schematic cross-sectional view of a main part of an example of an opening forming process. FIG. 6(B) shows a schematic cross-sectional view of a main part of an example of a source electrode upper layer part, a drain electrode upper layer part, and a source field plate forming process. FIG. 6(C) shows a schematic cross-sectional view of a main part of an example of an interlayer insulating film partial removal process. FIG. 7(A) shows a schematic cross-sectional view of a main part of an example of an air bridge resist and air bridge wiring forming process. FIG. 7(B) shows a schematic cross-sectional view of a main part of an example of an air bridge resist removing process.

[0053] Here, the description will be centered on the manufacture of the active region 10a of the semiconductor device 1A. First, a substrate 10 as shown in Fig. 5(A) is prepared. That is, a channel layer 12a, a barrier layer 12b, a cap layer 12c, and the like as shown in Fig. 1 are formed as a semiconductor layer 12 on an underlying substrate 11 by using a method such as MOVPE, to prepare the substrate 10. An element isolation region 10b as shown in Fig. 3 is formed in the substrate 10 by ion implantation of argon (Ar), for example. An active region 10a as shown in Fig. 3 is formed in the region defined by the element isolation region 10b.

[0054] After the substrate 10 is prepared, as shown in Fig. 5(A), a metal material having a laminated structure of Ta and Al or the like is formed on the surface 13 of the substrate 10 on the semiconductor layer 12 side by using lithography, deposition, and lift-off techniques. This forms a source electrode lower layer 31 which is a lower layer of the source electrode 30, and a drain electrode lower layer 41 which is a lower layer of the drain electrode 40. In addition to the source electrode lower layer 31 and the drain electrode lower layer 41, a source pad portion and a drain pad portion (for example, their lower layers) may be formed on the element isolation region 10b of the substrate 10.

[0055] Before the formation of the source electrode lower-layer portion 31 and the drain electrode lower-layer portion 41, a contact layer (regrowth layer) may be formed in the recesses provided in the semiconductor layer 12. After the formation of the source electrode lower-layer portion 31 and the drain electrode lower-layer portion 41, a heat treatment may be performed to establish an ohmic connection.

[0056] After the source electrode lower layer 31 and the drain electrode lower layer 41 are formed, as shown in Fig. 5(A), a passivation film 60 is formed on the substrate 10 on which they are formed. For example, the passivation film 60 made of SiN or the like is formed by using a chemical vapor deposition (CVD) method or the like.

[0057] 5(B), an opening 61 is formed in a predetermined position of the passivation film 60 between the source electrode lower layer 31 and the drain electrode lower layer 41. Then, a metal material having a laminated structure of Ni and Au or the like is formed in the position of the opening 61 using lithography, deposition and lift-off techniques. This forms the gate electrode 20. Note that, together with the gate electrode 20, a gate bus line 21 and a gate pad portion connected to the gate electrode 20 may be formed on the element isolation region 10b of the substrate 10.

[0058] 5C, an interlayer insulating film 70 is formed to cover the passivation film 60 and the gate electrode 20. For example, the interlayer insulating film 70 made of SiO or the like is formed by using a CVD method or the like.

[0059] 6(A), openings 91 are formed which penetrate the interlayer insulating film 70 and the passivation film 60 and reach the source electrode lower-layer portion 31 and the drain electrode lower-layer portion 41. For example, the openings 91 are formed by using an etching method.

[0060] Next, as shown in FIG. 6(B), a source electrode upper layer portion 32 which is an upper layer portion of the source electrode 30, and a drain electrode upper layer portion 42 which is an upper layer portion of the drain electrode 40 are formed at the position of the opening 91. For example, the source electrode upper layer portion 32 and the drain electrode upper layer portion 42 are formed using lithography technology and plating technology. The source electrode upper layer portion 32 is formed on the source electrode lower layer portion 31 and is connected to the source electrode lower layer portion 31. The drain electrode upper layer portion 42 is formed on the drain electrode lower layer portion 41 and is connected to the drain electrode lower layer portion 41. The source electrode upper layer portion 32 and the drain electrode upper layer portion 42 are made of a metal material such as Au, Cu, or Al. The source electrode upper layer portion 32 and the drain electrode upper layer portion 42 may be made of a metal material different from that of the source electrode lower layer portion 31 and the drain electrode lower layer portion 41. In addition, together with the source electrode upper layer portion 32 and the drain electrode upper layer portion 42, a source pad portion and a drain pad portion (for example, their upper layer portions) may be formed on the element isolation region 10b of the substrate 10.

[0061] The source electrode 30 of the semiconductor device 1A is formed by the source electrode lower-layer portion 31 and the source electrode upper-layer portion 32. The drain electrode 40 of the semiconductor device 1A is formed by the drain electrode lower-layer portion 41 and the drain electrode upper-layer portion .

[0062] The source field plate 50 is formed on the interlayer insulating film 70 together with the source electrode upper layer 32 and the drain electrode upper layer 42. For example, as shown in FIG. 6(B), the source field plate 50 is formed on the interlayer insulating film 70 at a position corresponding to the end of the gate electrode 20 on the drain electrode 40 side. For example, the source field plate 50 is formed using lithography and plating techniques. A metal material such as Au, Cu, or Al is used for the source field plate 50. A metal material different from that of the source electrode upper layer 32 and the drain electrode upper layer 42 may be used for the source field plate 50.

[0063] 6(C), the interlayer insulating film 70 is partially removed. Here, the interlayer insulating film 70 is partially removed so that the interlayer insulating film 70 remains around the gate electrode 20 (and the gate bus line 21), including the region in which the source field plate 50 is formed. By partially removing the interlayer insulating film 70 in this manner, a cavity 90 is formed between the remaining interlayer insulating film 70 and the source electrode 30 and the drain electrode 40, without the interlayer insulating film 70 being interposed therebetween.

[0064] Next, as shown in FIG. 7A, an air bridge resist 81 serving as a sacrificial layer is formed so as to fill the cavity 90 between the interlayer insulating film 70 and the source electrode 30. Then, as shown in FIG. 7A, an air bridge wiring 80 is formed on the air bridge resist 81 to connect the source field plate 50 on the interlayer insulating film 70 and the source electrode 30 (the source electrode upper layer portion 32). For example, the air bridge wiring 80 is formed using lithography technology and plating technology. A metal material such as Au, Cu, or Al is used for the air bridge wiring 80. A metal material different from that of the source field plate 50 and the source electrode 30 may be used for the air bridge wiring 80.

[0065] 8(B), the air bridge resist 81 of the sacrificial layer is removed. As a result, the source electrode 30 is provided between the interlayer insulating film 70 covering the gate electrode 20 and the cavity 90, and a structure is formed in which the source field plate 50 on the interlayer insulating film 70 and the source electrode 30 are connected by the air bridge wiring 80.

[0066] By the processes shown in Figures 5(A) to 5(C), Figures 6(A) to 6(C), Figures 7(A) and 7(B) described above, a semiconductor device 1A having the configuration shown in Figures 3 and 4 is manufactured.

[0067] In the semiconductor device 1A, the source field plate 50 and the source electrode 30 are connected by the air bridge wiring 80, thereby suppressing breakdown due to the electric field of the drain voltage and suppressing a decrease in the breakdown voltage. Furthermore, in the semiconductor device 1A, a cavity 90 is provided between the gate electrode 20 and the source electrode 30 and between the semiconductor device 1A and the drain electrode 40, thereby suppressing a decrease in high-frequency characteristics due to the addition of a capacitive component. A high-performance semiconductor device 1A is realized that includes the source field plate 50 and suppresses a decrease in the breakdown voltage and a decrease in the high-frequency characteristics.

[0068] In the description of the first embodiment, a HEMT using a nitride semiconductor is taken as an example, but the above-mentioned configuration can also be applied to various FETs using semiconductors other than nitride semiconductors or compound semiconductors. That is, the configuration in which the source field plate on the interlayer insulating film covering the gate electrode is connected to the source electrode by air bridge wiring is not limited to HEMTs and can be applied to various FETs. The same applies to the second to fourth embodiments described below.

[0069] [Second embodiment] Fig. 8 is a diagram for explaining an example of a semiconductor device according to the second embodiment. Fig. 8 is a schematic cross-sectional view of a main part of the example of the semiconductor device according to the second embodiment. For convenience, hatching is also applied to the plan view of Fig. 8.

[0070] 8 has a configuration in which a plurality of air bridge wirings 80 connect the source field plate 50 on the interlayer insulating film 70 to the source electrode 30. The semiconductor device 1B differs from the semiconductor device 1A described in the first embodiment in that it has such a configuration.

[0071] The semiconductor device 1B also provides the same effects as those described for the semiconductor device 1A. That is, in the semiconductor device 1B, the source field plate 50 and the source electrode 30 are connected by a plurality of air bridge wirings 80, thereby suppressing breakdown due to the electric field of the drain voltage and suppressing a decrease in the breakdown voltage. Furthermore, in the semiconductor device 1B, a cavity 90 is provided between the gate electrode 20 and the source electrode 30 and between the semiconductor device 1B and the drain electrode 40, thereby suppressing a decrease in high-frequency characteristics due to the addition of a capacitive component. A high-performance semiconductor device 1B is realized that includes the source field plate 50 and suppresses a decrease in the breakdown voltage and high-frequency characteristics.

[0072] Moreover, in the semiconductor device 1B, the air bridge wirings 80 are multiple. Therefore, each air bridge wiring 80 can be formed with high accuracy to connect the source field plate 50 and the source electrode 30. When connecting the source field plate 50 and the source electrode 30 that are long in one direction with one air bridge wiring 80, the air bridge wiring 80 may be interrupted or the film thickness may vary when forming the long air bridge wiring 80. As a result, the potential of the source field plate 50 may become unstable, the electric field of the drain voltage may be locally applied, or other such situations may occur. In contrast, when the air bridge wirings 80 are multiple, it is possible to form each air bridge wiring 80 with high accuracy while suppressing interruption and film thickness variation, compared to the case of forming one long air bridge wiring 80. As a result, it is possible to suppress the above-mentioned situation.

[0073] 7(A), after forming an air bridge resist 81, a plurality of air bridge wirings 80 that connect the source field plate 50 and the source electrode 30 are formed using lithography and plating techniques. The other steps can be the same as those described for the manufacture of the semiconductor device 1A.

[0074] [Third embodiment] Fig. 9 is a diagram for explaining an example of a semiconductor device according to the third embodiment. Fig. 9 is a schematic cross-sectional view of a main part of the example of the semiconductor device according to the third embodiment.

[0075] The semiconductor device 1C shown in FIG. 9 has a configuration in which the source field plate 50 is provided at a lower position with respect to the substrate 10 (surface 13) than the source electrode 30. That is, the semiconductor device 1C has a configuration in which a surface 50a of the source field plate 50 opposite the substrate 10 side is located closer to the substrate 10 than a surface 30a of the source electrode 30 opposite the substrate 10 side. The surface 50a of the source field plate 50 is also referred to as the "second surface," and the surface 30a of the source electrode 30 is also referred to as the "third surface." The semiconductor device 1C differs from the semiconductor device 1A described in the first embodiment in that it has such a configuration.

[0076] The semiconductor device 1C also provides the same effects as those described for the semiconductor device 1A. That is, in the semiconductor device 1C, the source field plate 50 and the source electrode 30 are connected by the air bridge wiring 80, thereby suppressing breakdown due to the electric field of the drain voltage and suppressing a decrease in the breakdown voltage. Furthermore, in the semiconductor device 1C, a cavity 90 is provided between the gate electrode 20 and the source electrode 30 and between the semiconductor device 1C and the drain electrode 40, thereby suppressing a decrease in high-frequency characteristics due to the addition of a capacitive component. A high-performance semiconductor device 1C is realized that includes the source field plate 50 and suppresses a decrease in the breakdown voltage and high-frequency characteristics.

[0077] In semiconductor device 1C, source field plate 50 is provided at a position lower than source electrode 30 with respect to substrate 10. In semiconductor device 1C, the thickness of interlayer insulating film 70 covering gate electrode 20 is adjusted to be thinner than the height of source electrode 30. Source field plate 50 is formed on interlayer insulating film 70 whose thickness has been adjusted to be thinner than source electrode 30, and source field plate 50 and source electrode 30 are connected by air bridge wiring 80.

[0078] Unlike the semiconductor device 1C, the surface 50a of the source field plate 50 does not necessarily have to be located at the same height as the surface 30a of the source electrode 30. In the semiconductor device 1C, the thickness of the interlayer insulating film 70 and the height of the source field plate 50 can be adjusted with respect to the height of the source electrode 30. For example, when the height of the source electrode 30 of the semiconductor device 1C is set to the same height as the source electrode 30 of the semiconductor device 1A, the thickness of the interlayer insulating film 70 of the semiconductor device 1C is relatively thinner than the thickness of the interlayer insulating film 70 of the semiconductor device 1A. As a result, the height of the source field plate 50 relative to the substrate 10 of the semiconductor device 1C is relatively lower than the height of the source field plate 50 relative to the substrate 10 of the semiconductor device 1A.

[0079] In the semiconductor device 1C, the distance between the source field plate 50 and the gate electrode 20 can be adjusted independently of the height of the source electrode 30. In the semiconductor device 1C, the distance between the source field plate 50 and the gate electrode 20 can also be adjusted based on the electric field of the drain voltage. According to the semiconductor device 1C, it is possible to adjust the distance between the source field plate 50 and the gate electrode 20, effectively disperse the electric field of the drain voltage by the source field plate 50, and effectively prevent the electric field of the drain voltage from concentrating on the gate electrode 20.

[0080] Next, a method for manufacturing the semiconductor device 1C will be described. 10 and 11 are diagrams for explaining an example of a method for manufacturing a semiconductor device according to the third embodiment. FIG. 10(A) shows a schematic cross-sectional view of an important part of an example of an electrode formation resist forming step. FIG. 10(B) shows a schematic cross-sectional view of an important part of an example of an opening formation step. FIG. 10(C) shows a schematic cross-sectional view of an important part of an example of a source electrode top layer part and a drain electrode top layer part forming step. FIG. 11(A) shows a schematic cross-sectional view of an important part of an example of an electrode formation resist removing step. FIG. 11(B) shows a schematic cross-sectional view of an important part of an example of an air bridge resist and air bridge wiring forming step. FIG. 11(C) shows a schematic cross-sectional view of an example of an air bridge resist removing step.

[0081] In manufacturing the semiconductor device 1C, the steps shown in Figures 5(A) to 5(C) and Figures 6(A) to 6(C) described in the manufacturing method of the semiconductor device 1A of the first embodiment above can be similar to those shown in Figures 5(A) to 5(C) and Figures 6(A) to 6(C).

[0082] In manufacturing the semiconductor device 1C, after the process of FIG. 6(C) above, an electrode formation resist 93 is formed so as to cover the source electrode upper layer 32 and the drain electrode upper layer 42, etc., formed on the substrate 10, as shown in FIG. 10(A).

[0083] Next, as shown in FIG. 10B, openings 94 that communicate with the source electrode upper layer portion 32 and the drain electrode upper layer portion 42 are formed in the electrode formation resist 93. 10(C), the source electrode uppermost layer portion 33 and the drain electrode uppermost layer portion 43 are formed in the opening 94. For example, the source electrode uppermost layer portion 33 and the drain electrode uppermost layer portion 43 are formed by using a plating technique. The source electrode uppermost layer portion 33 is formed on the source electrode uppermost layer portion 32 and is connected to the source electrode uppermost layer portion 32. The drain electrode uppermost layer portion 43 is formed on the drain electrode uppermost layer portion 42 and is connected to the drain electrode uppermost layer portion 42. The source electrode uppermost layer portion 33 and the drain electrode uppermost layer portion 43 are made of a metal material such as Au, Cu, or Al. The source electrode uppermost layer portion 33 and the drain electrode uppermost layer portion 43 may be made of a metal material different from that of the source electrode uppermost layer portion 32 and the drain electrode uppermost layer portion 42. In addition, together with the source electrode uppermost layer portion 33 and the drain electrode uppermost layer portion 43, a source pad portion and a drain pad portion (for example, their uppermost layers) may be formed on the element isolation region 10b of the substrate 10.

[0084] The source electrode 30 of the semiconductor device 1C is formed by the source electrode lower-layer portion 31, the source electrode upper-layer portion 32, and the source electrode uppermost-layer portion 33. The drain electrode 40 of the semiconductor device 1C is formed by the drain electrode lower-layer portion 41, the drain electrode upper-layer portion 42, and the drain electrode uppermost-layer portion 43.

[0085] Next, as shown in FIG. 11(A), the electrode formation resist 93 is removed. In this way, a configuration is obtained in which the source field plate 50 is located at a lower position relative to the substrate 10 (its surface 13) than the source electrode 30, i.e., the surface 50a of the source field plate 50 is located closer to the substrate 10 than the surface 30a of the source electrode 30.

[0086] Next, as shown in FIG. 11(B), an air bridge resist 81 serving as a sacrificial layer is formed so as to fill the cavity 90 between the interlayer insulating film 70 and the source electrode 30. Then, as shown in FIG. 7(A), an air bridge wiring 80 is formed on the air bridge resist 81, connecting the source field plate 50 on the interlayer insulating film 70 and the source electrode 30 (the source electrode uppermost layer portion 33). For example, the air bridge wiring 80 is formed using lithography technology and plating technology. A metal material such as Au, Cu, or Al is used for the air bridge wiring 80. A metal material different from that of the source field plate 50 and the source electrode 30 may be used for the air bridge wiring 80.

[0087] 11(C), the air bridge resist 81 is removed. As a result, the source electrode 30 is provided with the cavity 90 between it and the interlayer insulating film 70 covering the gate electrode 20, and a structure is formed in which the source field plate 50 on the interlayer insulating film 70 and the source electrode 30 are connected by the air bridge wiring 80.

[0088] After the process of Figure 6(C) above, a semiconductor device 1C having the configuration as shown in Figure 9 above is manufactured by the processes as shown in Figures 10(A) to 10(C) and Figures 11(A) to 11(C).

[0089] [Fourth embodiment] Fig. 12 is a diagram for explaining an example of a semiconductor device according to the fourth embodiment. Fig. 12 is a schematic cross-sectional view of a main part of the example of the semiconductor device according to the fourth embodiment.

[0090] 12 has a configuration in which an interlayer insulating film 70 is filled between the source electrode 30 and the drain electrode 40. That is, the semiconductor device 1D has a configuration in which the above-mentioned cavity 90 is not provided. The semiconductor device 1D differs from the semiconductor device 1A described in the first embodiment in that it has such a configuration.

[0091] As described above for semiconductor device 1A, semiconductor device 1D also suppresses breakdown due to the electric field of the drain voltage and reduces a decrease in withstand voltage by connecting source field plate 50 and source electrode 30 with air bridge wiring 80. A high-performance semiconductor device 1D is realized that includes source field plate 50 and reduces a decrease in withstand voltage.

[0092] In the manufacture of the semiconductor device 1D, after the step of Fig. 6(B) above, an air bridge resist 81 is formed on the interlayer insulating film 70 remaining between the source field plate 50 and the source electrode 30, following the example of the step of Fig. 7(A) above. Then, an air bridge wiring 80 connecting the source field plate 50 and the source electrode 30 is formed on the air bridge resist 81. Thereafter, the air bridge resist 81 is removed. The other steps can be similar to those described for the manufacture of the semiconductor device 1A above.

[0093] In the semiconductor device 1D, the process of partially removing the interlayer insulating film 70 to form the cavity 90 (FIG. 6(C)) can be omitted, making it possible to reduce the number of manufacturing steps. In the semiconductor device 1D, the thickness of the interlayer insulating film 70 and the height of the source electrode 30 may be adjusted according to the example of the third embodiment, so that the source field plate 50 is positioned lower than the source electrode 30. This may adjust the distance between the source field plate 50 and the gate electrode 20. In this case, after the step of FIG. 6(B) above, the source electrode uppermost layer 33 and the drain electrode uppermost layer 43 are formed using an electrode formation resist 93 (FIGS. 10(A)-FIG. 11(A)), and the air bridge wiring 80 is formed (FIGS. 11(B)-FIG. 11(C)), according to the example of the steps from FIG. 10(A) onwards.

[0094] The first to fourth embodiments have been described above. The semiconductor devices 1A, 1B, 1C, 1D, etc. described above can be applied to various electronic devices. As an example, the following describes the case where the semiconductor device having the above configuration is applied to a semiconductor package, a power factor correction circuit, a power supply device, and an amplifier.

[0095] [Fifth embodiment] Here, an example of application of the semiconductor device having the above-mentioned configuration to a semiconductor package will be described as the fifth embodiment.

[0096] Fig. 13 is a diagram illustrating an example of a semiconductor package according to the fifth embodiment, which diagrammatically shows a plan view of a main part of the example of the semiconductor package. The semiconductor package 200 shown in Fig. 13 is an example of a discrete package. The semiconductor package 200 includes, for example, the semiconductor device 1A (Figs. 3 and 4, etc.) as described in the first embodiment, a lead frame 210 on which the semiconductor device 1A is mounted, and a resin 220 that seals them.

[0097] The semiconductor device 1A is mounted on a die pad 210a of a lead frame 210 using, for example, a die attach material or the like (not shown). The semiconductor device 1A is provided with a pad 24 connected to the gate electrode 20, a pad 34 connected to the source electrode 30, and a pad 44 connected to the drain electrode 40. The pads 24, 34, and 44 are respectively connected to the gate lead 211, the source lead 212, and the drain lead 213 of the lead frame 210 using wires 230 made of Au, Al, or the like. The lead frame 210, the semiconductor device 1A mounted thereon, and the wires 230 connecting them are sealed with resin 220 so that parts of the gate lead 211, the source lead 212, and the drain lead 213 are exposed.

[0098] An external connection electrode connected to the source electrode 30 may be provided on the surface of the semiconductor device 1A opposite to the surface on which the pad 24 connected to the gate electrode 20 and the pad 44 connected to the drain electrode 40 are provided. The external connection electrode may be connected to the die pad 210a connected to the source lead 212 by using a conductive bonding material such as solder.

[0099] For example, the semiconductor device 1A described in the first embodiment is used, and a semiconductor package 200 having such a configuration is obtained. As described above, in the semiconductor device 1A, the source field plate 50 and the source electrode 30 are connected by the air bridge wiring 80, thereby suppressing breakdown due to the electric field of the drain voltage and suppressing a decrease in the breakdown voltage. Furthermore, in the semiconductor device 1A, a cavity 90 is provided between the gate electrode 20 and the source electrode 30 and between the semiconductor device 1A and the drain electrode 40, thereby suppressing a decrease in high frequency characteristics due to the addition of a capacitive component. This realizes a high-performance semiconductor device 1A including the source field plate 50. A high-performance semiconductor package 200 is realized by using such a semiconductor device 1A.

[0100] Although the semiconductor device 1A is taken as an example here, it is possible to obtain a semiconductor package in a similar manner using other semiconductor devices 1B, 1C, 1D, etc. [Sixth embodiment] Here, an example of application of the semiconductor device having the above-mentioned configuration to a power factor correction circuit will be described as a sixth embodiment.

[0101] Fig. 14 is a diagram for explaining an example of a power factor correction circuit according to the sixth embodiment. Fig. 14 shows an equivalent circuit diagram of the example of the power factor correction circuit. The power factor correction (PFC) circuit 300 shown in FIG. 14 includes a switch element 310, a diode 320, a choke coil 330, a capacitor 340, a capacitor 350, a diode bridge 360, and an AC power supply 370 (AC).

[0102] In the PFC circuit 300, a drain electrode of a switch element 310 is connected to an anode terminal of a diode 320 and one terminal of a choke coil 330. A source electrode of the switch element 310 is connected to one terminal of a capacitor 340 and one terminal of a capacitor 350. The other terminal of the capacitor 340 is connected to the other terminal of the choke coil 330. The other terminal of the capacitor 350 is connected to a cathode terminal of the diode 320. A gate driver is connected to the gate electrode of the switch element 310. An AC power supply 370 is connected between both terminals of the capacitor 340 via a diode bridge 360, and a DC power supply (DC) is taken out from between both terminals of the capacitor 350.

[0103] For example, the semiconductor devices 1A, 1B, 1C, 1D, etc. are used for the switch element 310 of the PFC circuit 300 having such a configuration. As described above, in the semiconductor devices 1A, 1B, 1C, 1D, etc., the source field plate 50 and the source electrode 30 are connected by the air bridge wiring 80, thereby suppressing breakdown due to the electric field of the drain voltage and suppressing a decrease in the breakdown voltage. Furthermore, in the semiconductor devices 1A, 1B, 1C, etc., a cavity 90 is provided between the gate electrode 20 and the source electrode 30 and between the semiconductor device 1A, 1B, 1C, etc. and the source electrode 30 and the drain electrode 40, thereby suppressing a decrease in high-frequency characteristics due to the addition of a capacitive component. This realizes high-performance semiconductor devices 1A, 1B, 1C, 1D, etc. that include the source field plate 50. A high-performance PFC circuit 300 is realized by using such semiconductor devices 1A, 1B, 1C, 1D, etc.

[0104] [Seventh embodiment] Here, an example in which the semiconductor device having the above-mentioned configuration is applied to a power supply device will be described as the seventh embodiment.

[0105] Fig. 15 is a diagram illustrating an example of a power supply device according to the seventh embodiment. Fig. 15 shows an equivalent circuit diagram of the example of the power supply device. The power supply device 400 shown in FIG. 15 includes a primary side circuit 410, a secondary side circuit 420, and a transformer 430 provided between the primary side circuit 410 and the secondary side circuit 420.

[0106] The primary side circuit 410 includes the PFC circuit 300 as described in the sixth embodiment, and an inverter circuit, for example, a full-bridge inverter circuit 440, connected between both terminals of the capacitor 350 of the PFC circuit 300. The full-bridge inverter circuit 440 includes a plurality of switch elements, for example, four switch elements 441, 442, 443, and 444.

[0107] The secondary side circuit 420 includes a plurality of switch elements, three of which, as an example here, are a switch element 421, a switch element 422, and a switch element 423. For example, the semiconductor devices 1A, 1B, 1C, 1D, etc. are used for the switch element 310 of the PFC circuit 300 included in the primary side circuit 410 of the power supply device 400 having such a configuration, and for the switch elements 441-444 of the full bridge inverter circuit 440. For example, normal MIS type field effect transistors using Si are used for the switch elements 421, 422, 423 of the secondary side circuit 420 of the power supply device 400.

[0108] As described above, in the semiconductor devices 1A, 1B, 1C, 1D, etc., the source field plate 50 and the source electrode 30 are connected by the air bridge wiring 80, thereby suppressing breakdown due to the electric field of the drain voltage and suppressing a decrease in the breakdown voltage. Furthermore, in the semiconductor devices 1A, 1B, 1C, etc., a cavity 90 is provided between the gate electrode 20 and the source electrode 30 and between the semiconductor device 1A, 1B, 1C, etc. and the source electrode 30 and the drain electrode 40, thereby suppressing a decrease in high frequency characteristics due to the addition of a capacitive component. This realizes high performance semiconductor devices 1A, 1B, 1C, 1D, etc. that include the source field plate 50. A high performance power supply device 400 is realized by using such semiconductor devices 1A, 1B, 1C, 1D, etc.

[0109] [Eighth embodiment] Here, an example of application of the semiconductor device having the above-mentioned configuration to an amplifier will be described as the eighth embodiment.

[0110] Fig. 16 is a diagram for explaining an example of an amplifier according to the eighth embodiment, showing an equivalent circuit diagram of the example of the amplifier. The amplifier 500 shown in FIG. 16 includes a digital predistortion circuit 510, a mixer 520, a mixer 530, and a power amplifier 540.

[0111] The digital predistortion circuit 510 compensates for nonlinear distortion of the input signal. The mixer 520 mixes the input signal SI, for which the nonlinear distortion has been compensated, with an AC signal. The power amplifier 540 amplifies the signal obtained by mixing the input signal SI with the AC signal. In the amplifier 500, for example, by switching a switch, the output signal SO can be mixed with the AC signal in the mixer 530 and sent to the digital predistortion circuit 510. The amplifier 500 can be used as a high-frequency amplifier or a high-power amplifier.

[0112] The above-mentioned semiconductor devices 1A, 1B, 1C, 1D, etc. are used in the power amplifier 540 of the amplifier 500 having such a configuration. As described above, in the semiconductor devices 1A, 1B, 1C, 1D, etc., the source field plate 50 and the source electrode 30 are connected by the air bridge wiring 80, thereby suppressing breakdown due to the electric field of the drain voltage and suppressing a decrease in the breakdown voltage. Furthermore, in the semiconductor devices 1A, 1B, 1C, etc., a cavity 90 is provided between the gate electrode 20 and the source electrode 30 and between the semiconductor device 1A, 1B, 1C, etc. and the source electrode 30 and the drain electrode 40, thereby suppressing a decrease in high frequency characteristics due to the addition of a capacitive component. This realizes high performance semiconductor devices 1A, 1B, 1C, 1D, etc. that include the source field plate 50. A high performance amplifier 500 is realized by using such semiconductor devices 1A, 1B, 1C, 1D, etc.

[0113] Various electronic devices to which the semiconductor devices 1A, 1B, 1C, 1D, etc. are applied (such as the semiconductor package 200, the PFC circuit 300, the power supply device 400, and the amplifier 500 described in the fifth to eighth embodiments) can be mounted in various electronic devices or electronic devices. For example, they can be mounted in various electronic devices or electronic devices such as computers (personal computers, supercomputers, servers, etc.), smartphones, mobile phones, tablet terminals, sensors, cameras, audio equipment, measuring devices, inspection devices, manufacturing devices, transmitters, receivers, and radar devices.

[0114] The following supplementary notes are further provided with respect to the above-described embodiment. (Appendix 1) A substrate; A gate electrode provided on a first surface side of the substrate; a source electrode and a drain electrode provided on both sides of the gate electrode on the first surface side of the substrate; a source field plate provided on the first surface side of the substrate between the gate electrode and the drain electrode and closer to the gate electrode than the drain electrode; an air bridge wiring that connects the source electrode and the source field plate; 13. A semiconductor device comprising:

[0115] (Note 2) A passivation film provided between the source electrode and the drain electrode on the first surface side of the substrate; an interlayer insulating film provided on the first surface side of the substrate and covering the passivation film and the gate electrode; 2. The semiconductor device of claim 1,

[0116] (Supplementary Note 3) The semiconductor device according to Supplementary Note 2, wherein the source field plate is provided on a side of the interlayer insulating film opposite to the substrate side. (Supplementary Note 4) The semiconductor device according to Supplementary Note 2, wherein cavities are provided between the interlayer insulating film and the source electrode, and between the interlayer insulating film and the drain electrode.

[0117] (Supplementary Note 5) The semiconductor device according to Supplementary Note 2, wherein a second surface of the source field plate opposite the substrate side is located closer to the substrate than a third surface of the source electrode opposite the substrate side.

[0118] (Note 6) A step of forming a gate electrode, and a source electrode and a drain electrode provided on both sides of the gate electrode, on a first surface side of a substrate; forming a source field plate on the first surface side of the substrate between the gate electrode and the drain electrode and closer to the gate electrode than to the drain electrode; forming an air bridge wiring connecting the source electrode and the source field plate; A method for manufacturing a semiconductor device comprising the steps of:

[0119] (Note 7) A step of forming a passivation film between the source electrode and the drain electrode on the first surface side of the substrate; forming an interlayer insulating film covering the passivation film and the gate electrode on the first surface side of the substrate; 7. A method for manufacturing a semiconductor device according to claim 6, comprising:

[0120] (Supplementary Note 8) The method for manufacturing a semiconductor device according to Supplementary Note 7, wherein the step of forming the source field plate includes the step of forming the source field plate on a side of the interlayer insulating film opposite to the substrate side.

[0121] (Appendix 9) The method for manufacturing a semiconductor device according to appendix 7, wherein the step of forming the interlayer insulating film includes a step of forming the interlayer insulating film so that cavities are provided between the interlayer insulating film and the source electrode, and between the interlayer insulating film and the drain electrode.

[0122] (Appendix 10) The method for manufacturing a semiconductor device described in Appendix 7, wherein the step of forming the source electrode includes a step of forming the source electrode such that a second surface of the source field plate opposite the substrate side is located closer to the substrate than a third surface of the source electrode opposite the substrate side.

[0123] (Appendix 11) A substrate; A gate electrode provided on a first surface side of the substrate; a source electrode and a drain electrode provided on both sides of the gate electrode on the first surface side of the substrate; a source field plate provided on the first surface side of the substrate between the gate electrode and the drain electrode and closer to the gate electrode than the drain electrode; an air bridge wiring that connects the source electrode and the source field plate; An electronic device comprising a semiconductor device including: [Explanation of symbols]

[0124] 1, 1A, 1B, 1C, 1D, 100 Semiconductor device 10, 110 Board 10a, 110a active area 10b, 110b element isolation area 11, 111 Base substrate 12, 112 Semiconductor layer 12a Channel Layer 12b Barrier layer 12c Cap Layer 13, 30a, 50a, 113 sides 20, 120 Gate electrode 21, 121 Gate Bus Line 24, 34, 44 pads 30, 130 Source electrode 31 Lower layer of source electrode 32 Source electrode upper layer 33 Top layer of source electrode 40, 140 Drain electrode 41 Lower part of drain electrode 42 Drain electrode upper layer 43 Drain electrode top layer 50, 150 Source Field Plate 60, 160 Passivation film 61, 91, 94, 161 Openings 70, 170 Interlayer insulating film 80 Air bridge wiring 81 Air bridge resist 90 hollow 93 Electrode formation resist 101 2DEG area 180 Wiring 200 Semiconductor Packages 210 Lead Frame 210a Die pad 211 Gate Lead 212 Source Read 213 Drain Lead 220 Resin 230 Wire 300 PFC circuit 310, 421, 422, 423, 441, 442, 443, 444 Switch elements 320 Diode 330 Choke Coil 340, 350 Capacitor 360 Diode Bridge 370 AC power supply 400 power supply 410 Primary circuit 420 Secondary circuit 430 Trans 440 Full-bridge inverter circuit 500 Amplifier 510 Digital Pre-Distortion Circuit 520, 530 Mixer 540 Power Amplifier

Claims

1. A substrate; a gate electrode provided on a first surface side of the substrate; a source electrode and a drain electrode provided on both sides of the gate electrode on the first surface side of the substrate; a source field plate provided on the first surface side of the substrate between the gate electrode and the drain electrode and closer to the gate electrode than the drain electrode; an air bridge wiring that connects the source electrode and the source field plate; 13. A semiconductor device comprising:

2. a passivation film provided between the source electrode and the drain electrode on the first surface side of the substrate; an interlayer insulating film provided on the first surface side of the substrate and covering the passivation film and the gate electrode; The semiconductor device according to claim 1 .

3. 3. The semiconductor device according to claim 2, wherein said source field plate is provided on a side of said interlayer insulating film opposite to said substrate side.

4. 3. The semiconductor device according to claim 2, wherein cavities are provided between said interlayer insulating film and said source electrode, and between said interlayer insulating film and said drain electrode.

5. 3. The semiconductor device according to claim 2, wherein a second surface of said source field plate opposite to said substrate side is located closer to said substrate side than a third surface of said source electrode opposite to said substrate side.

6. forming a gate electrode, and a source electrode and a drain electrode provided on either side of the gate electrode, on a first surface side of a substrate; forming a source field plate on the first surface side of the substrate between the gate electrode and the drain electrode and closer to the gate electrode than to the drain electrode; forming an air bridge wiring connecting the source electrode and the source field plate; A method for manufacturing a semiconductor device comprising the steps of:

7. A substrate; a gate electrode provided on a first surface side of the substrate; a source electrode and a drain electrode provided on both sides of the gate electrode on the first surface side of the substrate; a source field plate provided on the first surface side of the substrate between the gate electrode and the drain electrode and closer to the gate electrode than the drain electrode; an air bridge wiring that connects the source electrode and the source field plate; An electronic device comprising a semiconductor device including:

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