Gate drive device

Abstract

To provide a gate drive device that can increase the speed and reduce loss of the switching operation of a semiconductor switching element.SOLUTION: A gate drive device 600 includes a path RT1 connected to a gate terminal G and having gate resistors R1 and R2, a path RT2 connected to the gate terminal G in parallel with the path RT1 and having gate resistors R3 and R4, and control signal generators 403 and 404 that control a gate current when switching the switching state of a switching element 101 such that the gate current flows only through the path RT1 after flowing through both the paths RT1 and RT2. The inductance component of the path RT2 is set to a value larger than the inductance component of the path RT1 by inductance components L3 and L4.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a gate drive device for a semiconductor switching element. [Background technology]

[0002] Power semiconductor elements are used in various devices, for example, as switching elements in inverter circuits of power conversion devices. In such power semiconductor elements, switching loss occurs when the switching operation is turned on and off. For this reason, in power conversion devices, it is important to reduce the loss of the power semiconductor elements in order to reduce the size and increase the output density. For example, a multi-stage gate drive circuit that switches gate resistors is known as a configuration that can adjust the switching speed (see Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2022-171419 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the configuration described in Patent Document 1, the gate current attenuates significantly during switching operation, making it difficult to achieve low-loss driving at high speeds. [Means for solving the problem]

[0005] A gate driver according to one aspect of the present invention is a gate driver that applies a voltage to a gate terminal of a semiconductor switching element, and includes a first path connected to the gate terminal and having a first gate resistor, a second path connected to the gate terminal in parallel with the first path and having a second gate resistor, and an active gate control unit that controls a gate current when switching the switching state of the semiconductor switching element so that the gate current flows through both the first path and the second path, and then flows only through the first path, and an inductance component of the second path is set to a value larger than the inductance component of the first path. Effect of the Invention

[0006] According to the present invention, it is possible to increase the speed of the switching operation of a semiconductor switching element and reduce loss. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram illustrating an example of a power conversion device. [Diagram 2] FIG. 2 is a diagram showing a circuit configuration of the gate driver. [Diagram 3] FIG. 3 is a diagram showing an example of the waveforms of the signals when the transistors are turned on. [Figure 4] FIG. 4 is a diagram showing a comparative example of a gate driving device. [Diagram 5] FIG. 5 is a diagram showing an example of the waveforms of the signals at the time of turn-off. [Figure 6] FIG. 6 is a diagram showing the first modified example. [Figure 7] FIG. 7 is a diagram illustrating the second modification. [Figure 8] FIG. 8 is a diagram showing a second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, the embodiment of the present invention will be described with reference to the drawings. The following description and drawings are examples for explaining the present invention, and are omitted and simplified as appropriate for clarity of explanation. In addition, in the following description, the same or similar elements and processes are given the same reference numerals, and duplicate explanations may be omitted. Note that the contents described below are merely examples of the embodiment of the present invention, and the present invention is not limited to the following embodiment, and can be implemented in various other forms.

[0009] (First embodiment) 1 is a diagram illustrating an example of a power conversion device. In the first embodiment, a power conversion device 200 mounted on a vehicle 1000 will be described as an example. The power conversion device 200 drives an electric motor 300 mounted on the vehicle 1000. The vehicle 1000 is provided with a power storage device 100, and the power conversion device 200 converts DC power supplied from the power storage device 100 into AC power to drive the electric motor 300.

[0010] The electric motor 300 is, for example, a driving motor for rotating wheels. The electric motor 300 has three-phase coils connected in a predetermined pattern. The connection pattern is not limited to the Y pattern shown in FIG. 1, and other connection patterns such as a delta pattern may be used. The electric motor 300 is driven to rotate by applying a predetermined current pattern from the power conversion device 200 to the three-phase coils.

[0011] The power storage device 100 has a positive terminal 100a and a negative terminal 100b. The power conversion device 200 has a positive bus line 201p, a negative bus line 201n, a smoothing capacitor 110, and a three-phase switching arm 500 (U, V, W). The positive bus line 201p is connected to the positive terminal 100a of the power storage device 100. The negative bus line 201n is connected to the negative terminal 100b of the power storage device 100. Both ends of the smoothing capacitor 110 and the three-phase switching arm 500 (U, V, W) are connected to the positive bus line 201p and the negative bus line 201n.

[0012] Each of the three-phase switching arms 500 (U, V, W) is provided with an upper arm switching element 101 and a lower arm switching element 101. The switching element 101 is, for example, a power switching element, and for example, an IGBT or a MOSFET is used. Each switching element 101 has a freewheeling diode (or a body diode) 102 connected in parallel. The upper arm switching element 101 and the lower arm switching element 101 are connected in series. A connection point between the upper arm switching element 101 and the lower arm switching element 101 is connected to one end of a coil of a corresponding phase of the electric motor 300. In the example shown in FIG. 1, one switching element 101 is provided in each of the upper and lower arms, but a configuration in which multiple switching elements 101 are used in parallel may be used.

[0013] The power conversion device 200 includes a conversion control device 400 that controls the gate drive device 600. The conversion control device 400 outputs a control command P to each gate drive device 600 and controls each switching element 101 individually. The control command P is a pulse signal having a predetermined pulse width, and the conversion control device 400 performs PWM control on the switching elements 101. The control command P controls the switching elements 101 of the same phase to be alternately turned on / off within a range in which they are not turned on simultaneously. As a result, the DC power from the power storage device 100 is converted into AC power, and the electric motor 300 is rotated.

[0014] In this embodiment, a power conversion device 200 constituting an inverter as shown in FIG. 1 will be described as an example. However, the present invention is not limited to this and can also be applied to a DC / DC converter, an AC / AC converter, an AC / DC inverter, etc.

[0015] Fig. 2 shows a circuit configuration of a switching element 101 related to the lower arm of the U phase shown in Fig. 1 and a gate driver 600 provided for the switching element 101. Although not shown, the upper arm of the U phase and the upper and lower arms of the other phases (V and W phases) have the same configuration. In the following explanation, an example will be described in which the switching element used is a MOSFET.

[0016] An output unit 1 of the gate driver 600 is connected to the gate terminal G of the switching element 101, and a reference potential 2 is connected to the source terminal S of the switching element 101. An input unit 3 of the gate driver 600 is connected to the conversion control device 400. A control command P input from the conversion control device 400 to the gate driver 600 is input to the gates of the MOSFETs 11 and 12, and is also input to the control signal generating units 403 and 404. The gate driver 600 has two paths RT1 and RT2 connected to the gate terminal G of the switching element 101. The control circuits of the conversion control device 400 and the control signal generating units 403 and 404 have, for example, a CPU, a RAM, a ROM, a communication circuit, etc., inside, although not shown. The conversion control device 400 and the control signal generating units 403 and 404 may be configured as one control device.

[0017] The first path RT1 includes a wiring LN1 and a wiring LN2. The wiring LN1 includes a positive power supply N1, an on-side MOSFET 11, an on-side gate resistor R1, and a diode D1. The MOSFET 11 has a source connected to the positive power supply N1 and a drain connected to one end of the gate resistor R1. The other end of the gate resistor R1 is connected to the anode of the diode D1. The cathode of the diode D1 is connected to the gate terminal G.

[0018] The wiring LN2 has a negative power supply N2, an off-side MOSFET 12, an off-side gate resistor R2, and a diode D2. The source of the MOSFET 12 is connected to the negative power supply N2, and the drain is connected to one end of the gate resistor R2. The other end of the gate resistor R2 is connected to the cathode of the diode D2. The anode of the diode D2 is connected to the gate terminal G. Note that the configuration may be such that the diode D1 on the wiring LN1 or the diode D2 on the wiring LN2 is omitted. In this case, one end of the gate resistors R1 and R2 is connected to the gate terminal G.

[0019] On the other hand, the second path RT2 includes a wiring LN3 and a wiring LN4. The wiring LN3 includes a positive power supply N3, a MOSFET 13 for voltage boosting, a gate resistor R3, and an inductance component L3. The MOSFET 13 has a source connected to the positive power supply N3 and a drain connected to one end of the gate resistor R3. The other end of the gate resistor R3 is connected to the gate terminal G via the inductance component L3.

[0020] The wiring LN4 has a negative power supply N4, a MOSFET 14 for dropping a voltage, a gate resistor R4, and an inductance component L4. The source of the MOSFET 14 is connected to the negative power supply N4, and the drain is connected to one end of the gate resistor R4. The other end of the gate resistor R4 is connected to the gate terminal G via the inductance component L4. The input section of the MOSFET 13 is connected to the control signal generating section 403, and a control signal S3 is input from the control signal generating section 403. The input section of the MOSFET 14 is connected to the control signal generating section 404, and a control signal S4 is input from the control signal generating section 404.

[0021] The control signal generating units 403, 404 generate the control signals S3, S4 based on the control command P input from the conversion control device 400. Note that a configuration may be adopted in which the state of the switching element 101 is sensed and a state signal J is input to the control signal generating units 403, 404. In this case, the control signal generating units 403, 404 generate the control signals S3, S4 based on the control command P and the state signal J.

[0022] In this embodiment, the inductance component of the wiring LN3 is set to be larger than the inductance component of the wiring LN1 by an inductance component L3. Similarly, the inductance component of the wiring LN4 is set to be larger than the inductance component of the wiring LN2 by an inductance component L4. The inductance components L3 and L4 are set in a range of, for example, about 100 nH to 2000 nH.

[0023] The positive power supply N1 and the positive power supply N3 are basically set to the same potential, but may be set to different potentials. For example, in order to correct the forward voltage of the diode D1, the potential of the positive power supply N1 may be set to be higher than the potential of the positive power supply N3 by the forward voltage of the diode D1. The same applies to the potential setting of the negative power supply N2 and the negative power supply N4, which may be set to the same potential, or the potential of the negative power supply N4 may be set to be higher than the potential of the negative power supply N2 by the forward voltage of the diode D2.

[0024] Instead of using the MOSFETs 11 to 14 as switching elements, BJTs (Bipolar Junction Transistors) may be used.

[0025] The inductance components L3 and L4 may be disposed on the wirings LN3 and LN4. For example, the inductors may be disposed between the MOSFET 13 and the gate resistor R3 and between the MOSFET 14 and the gate resistor R4, or may be disposed separately on the wirings LN3 and LN4. The magnitude of the inductance components may be adjusted by adjusting the wiring length and width of the wirings LN1 to LN4. The gate resistors R3 and R4 or the MOSFETs 13 and 14 may be lead-type resistors, and the magnitude of the inductance components may be adjusted by changing the length of the lead wires.

[0026] Other methods for adjusting the inductance component include making the wiring spiral or zigzag, or locally narrowing part of the wiring. Furthermore, by implementing ferrite beads, the desired inductance component can be obtained even with short lead wires, making it possible to miniaturize the power supply circuit.

[0027] (Operation explanation at turn-on) FIG. 3 is a diagram showing an example of the waveforms of each signal when the switching element 101 is turned on. Waveform (A) shows a control command P from the conversion control device 400. Waveform (B) shows a control signal S3 from the control signal generating unit 403. Waveform (C) shows a gate current Ig of the switching element 101. Waveform (D) shows a gate voltage Vgs of the switching element 101. The thin solid line and dashed line of waveform (E) show the drain-source main voltage (hereinafter referred to as drain-source voltage) Vds of the switching element 101, and the thick solid line and dashed line show the drain current Ids. Waveform (F) shows the waveform of the power loss (=Vds×Ids) of the switching element 101. Note that the solid line shows the waveform in the embodiment, and the dashed line shows the waveform in the conventional case.

[0028] Here, the conventional case refers to, for example, a gate driver 610 having a configuration as shown in the comparative example of Fig. 4. The gate driver 610 is obtained by omitting the inductance components L3 and L4 of the second path RT2 and the diodes D1 and D2 of the first path RT1 from the gate driver 600 shown in Fig. 2.

[0029] As shown in the waveform (A) of FIG. 3, at time t0, a control command P(ON) for turning on the gate of the switching element 101 is input from the conversion control device 400 to the gate driver 600. When the control command P(ON) is input to the gate driver 600, the MOSFET 11 is turned on. In addition, based on the input control command P(ON), a control signal S3 (pulse command) for turning on the MOSFET 13 is input from the control signal generator 403 to the MOSFET 13 from the control signal generator 403. Since the MOSFET 13 is a P-type MOSFET, inversion is necessary, but here, the pulse command before inversion is shown. Therefore, the waveform of the control signal S3 is expressed by a waveform similar to that of the control signal S4 for the N-type MOSFET 14 with respect to the on / off of the control command P. Note that the rising edge of the control signal S3 should be set so as not to be delayed from the control command P, and preferably should be synchronized. Also, the control signal S3 may rise before the control command P.

[0030] At time t0, when the control signal S3 rises to ON, the gate current Ig of the switching element 101 starts to rise as shown in waveform (C). The gate current Ig is the sum of the gate currents on the first and second paths RT1 and RT2. As the gate current Ig rises, the gate voltage Vgs starts to rise as shown in waveform (D). In both the first embodiment and the comparative example, the gate current starts to flow simultaneously on the first path RT1 and the second path RT2 as shown by the solid and dashed lines. However, in the first embodiment, since additional inductance components L3 and L4 are present on the second path RT2, the gate current Ig rises more slowly than in the comparative example (dashed line), and accordingly the gate voltage Vgs also rises more slowly.

[0031] In the comparative example shown by the dashed line, the gate current Ig is larger than that in the present embodiment, so the gate capacitance is charged faster. Therefore, the gate voltage Vgs reaches the gate threshold voltage Vth earlier in the comparative example. In the comparative example, when the gate voltage Vgs reaches the gate threshold voltage Vth at time t1, the drain-source voltage Vds of the switching element 101 starts to decrease as shown by the thin dashed line in the waveform (E), and the drain current Ids starts to increase as shown by the thick dashed line in the waveform (E). On the other hand, in the present embodiment, the gate capacitance is charged slower than in the comparative example, so the gate voltage Vgs reaches the gate threshold voltage Vth at time t2 (>t1). At the same time, the drain-source voltage Vds starts to decrease, and the drain current Ids starts to increase. As shown in the waveform (F), loss of the semiconductor switching element occurs from the timing when the drain current Ids starts to increase.

[0032] In the comparative example, the gate current Ig is larger than in the present embodiment, so the gate current Ig reaches a peak value earlier. The gate current Ig is determined by dividing the difference between the gate voltage Vgs and the positive power supply of the switching element 101 by the gate resistance value. In the comparative example, the gate voltage Vgs rises faster than in the present embodiment, as shown in the waveform (D), so the difference between the gate voltage Vgs and the positive power supply also decreases earlier. Therefore, the gate current Ig after reaching the peak value in the comparative example is attenuated more strongly than in the embodiment. The rate of decrease of the drain-source voltage Vds and the rate of increase of the drain current Ids are proportional to the gate current Ig, so the change speed of the drain-source voltage Vds and the drain current Ids in the comparative example is slower than in the first embodiment.

[0033] Incidentally, in order to suppress the surge of the drain current Ids, it is necessary to switch the gate charging speed from the high-speed mode to the low-speed mode before the surge of the drain current Ids of the switching element 101 reaches its maximum value. That is, the MOSFET 13 is switched from the on state to the off state, the gate current flow of the second path RT2 is stopped, and the gate current flows only through the first path RT1, thereby reducing the gate current, thereby reducing the charging speed. This switching must be completed before the surge of the drain current Ids occurs. Therefore, it is necessary to turn off the control signal S3 within the period from the rise of the drain current Ids to the time t3 at which the drain current Ids reaches its maximum.

[0034] The main part of the time when the control signal S3 is in the ON state is the charging period until the gate voltage Vgs reaches the gate threshold voltage Vth. In the comparative example, since the period until the gate voltage Vgs reaches the gate threshold voltage Vth is short, the control signal S3 must be turned off at an earlier timing than in the first embodiment, as shown in the waveform (B). Therefore, the control signal S3 in the comparative example has a shorter pulse width than the control signal S3 in the first embodiment. That is, in the first embodiment, the charging time until the gate threshold voltage is reached is longer, and the gate drive speed can be switched with the control signal S3 having a longer pulse than in the conventional case.

[0035] The end timing of the control signal S3 is determined based on, for example, the control command P. Alternatively, the end timing of the control signal S3 may be determined based on the above-mentioned state signal J of the switching element 101. The state signal J is, for example, a rising edge of the rate of change of any of the gate current Ig, the gate voltage Vgs, the drain current Ids, and the drain-source main voltage Vds, or a falling edge of the rate of change of the drain-source voltage Vds or the drain current Ids.

[0036] As shown by the dashed line in waveform (C), in the comparative example, the gate current Ig rises at high speed and immediately decays. On the other hand, in the first embodiment, since the inductance components L3 and L4 are provided, it is possible to weaken the decay of the gate current Ig during switching as shown by the solid line. As a result, it is possible to improve the switching speed. The loss power shown in waveform (F) is expressed as the product of the drain-source voltage Vds and the drain current Ids. In the first embodiment, the period during which loss occurs is shortened due to the improved switching speed, so the amount of loss, which is the time integral value of the loss power, is smaller than in the comparative example shown by the dashed line. In other words, it is possible to reduce the loss at turn-on.

[0037] (Explanation of turn-off operation) FIG. 5 is a diagram showing an example of the waveforms of each signal when the switching element 101 is turned off. Waveform (A) shows a control command P from the conversion control device 400. Waveform (B) shows a control signal S4 from the control signal generating unit 404. Waveform (C) shows a gate current Ig of the switching element 101. Waveform (D) shows a gate voltage Vgs of the switching element 101. In waveform (E), a thin solid line and a dashed line show a drain-source voltage Vds of the switching element 101, and a thick solid line and a dashed line show a drain current Ids. Waveform (F) shows a waveform of the power loss (=Vds×Ids) of the switching element 101. Note that in FIG. 5 as well, the solid line shows the waveform in the embodiment (FIG. 2), and the dashed line shows the waveform in the comparative example (FIG. 4).

[0038] As shown in the waveform (A), at time t0, a control command P(OFF) for gate-off (OFF) of the switching element 101 is input from the conversion control device 400 to the gate drive device 600. When the control command P(OFF) is input to the gate drive device 600, the MOSFET 12 is turned on. Furthermore, based on the input control command P(OFF), a control signal S4 (pulse command) for turning on the MOSFET 14 is input from the control signal generation unit 404 to the MOSFET 14. Note that the rising edge of the control signal S4 should be set so as not to be delayed from the falling edge of the control command P, and preferably should be synchronized with it. Alternatively, the control signal S4 may rise before the falling edge of the control command P.

[0039] At time t0, when the control signal S4 rises to ON, a gate current Ig that discharges the gate capacitance of the switching element 101 starts to flow as shown in the waveform (C). The gate current Ig is the sum of the gate currents on the first and second paths RT1 and RT2. As the gate current Ig starts to flow, the gate voltage Vgs starts to decrease. In both the first embodiment and the comparative example, the gate current starts to flow simultaneously on the first and second paths RT1 and RT2 as shown by the solid and dashed lines. However, in the first embodiment, since additional inductance components L3 and L4 are present on the second path RT2, the increase in the value of the gate current Ig during discharge is more gradual than in the comparative example (dashed line), and accordingly the decrease in the gate voltage Vgs is also more gradual.

[0040] As shown in waveform (C), in the comparative example shown by the dashed line, the gate current (discharge current) Ig is larger than that in the present embodiment, so the discharge speed of the gate capacitance is faster. Therefore, as shown in waveform (D), the gate voltage Vgs in the comparative example reaches the Miller Plateau of the gate first. When the gate voltage Vgs in the comparative example shown by the dashed line reaches the Miller Plateau of the gate at time t1, the drain-source voltage Vds starts to rise, as shown by the thin dashed line in waveform (E).

[0041] On the other hand, in this embodiment in which the discharge speed of the gate capacitance is slow, the gate voltage Vgs reaches the Miller plateau of the gate at time t2 (>t1). As a result, the drain-source voltage Vds starts to rise at time t2, and as shown in the waveform (F), a loss occurs in the switching element 101 from this timing.

[0042] In the comparative example, the gate current Ig is larger than that in the present embodiment, so that the gate current Ig reaches a peak on the discharge side earlier than in the present embodiment, as shown in the waveform (C). The gate current Ig is determined by dividing the difference between the gate voltage Vgs and the negative power supply of the switching element 101 by the gate resistance value. In the comparative example, the gate voltage Vgs decreases faster than in the present embodiment, as shown in the waveform (D), so that the difference between the gate voltage Vgs and the negative power supply also decreases earlier. Therefore, the gate current Ig after reaching the peak value in the comparative example is attenuated more strongly than in the embodiment. Since the rate of increase of the drain-source voltage Vds is proportional to the magnitude of the gate current Ig, the rate of increase of the drain-source voltage Vds in the comparative example is slower than in the present embodiment.

[0043] Incidentally, before the surge of the drain-source voltage Vds of the switching element 101 reaches a maximum value, it is necessary to switch the gate discharge speed from a high-speed mode to a low-speed mode. Specifically, by switching the MOSFET 14 from an on state to an off state, the gate current flow in the second path RT2 is stopped and the gate current is caused to flow only in the first path RT1, thereby decreasing the gate current. This makes it possible to reduce the discharge speed.

[0044] The timing for switching from the high-speed mode to the low-speed mode must be completed before the surge of the drain-source voltage Vds occurs. In other words, the control signal S4 must be turned off within the period from the rise of the drain-source voltage Vds to time t3 when the drain-source voltage Vds reaches its maximum. The main part of the time until the control signal S4 is turned off is the discharge period until the gate voltage Vgs reaches the Miller plateau.

[0045] As shown in the waveform (D), the discharge period until the gate voltage Vgs reaches the Miller plateau is shorter in the comparative example than in the first embodiment. Therefore, in the comparative example, the control signal S4 must be turned off at an earlier timing than in the first embodiment. As a result, the pulse width of the control signal S4 (dashed line) in the comparative example is shorter than that of the control signal S4 (solid line) in the first embodiment. That is, similar to the case of the control signal S3, the first embodiment allows control with a longer pulse width than the comparative example, making design easier.

[0046] The end timing of the control signal S4 is determined based on, for example, the control command P. The end timing of the control signal S3 may also be determined based on the above-mentioned state signal J of the switching element 101. The state signal J is, for example, a falling edge of the rate of change of any of the gate current Ig, the gate voltage Vgs, the drain current Ids, and the drain-source main voltage Vds, or a rising edge of the rate of change of the drain-source voltage Vds or the drain current Ids.

[0047] Thus, even in the case of turn-off, in the comparative example, the gate current Ig rises at high speed and immediately decays, as shown by the dashed line in the waveform (C). On the other hand, in the first embodiment, since the inductance components L3 and L4 are provided, it is possible to weaken the decay of the gate current Ig during switching, as shown by the solid line. As a result, it is possible to improve the switching speed. Looking at the loss power (=Vds×Ids) in the waveform (F), in the first embodiment, the period during which loss occurs is shortened due to the improved switching speed, so the amount of loss, which is the time integral value of the loss power, is smaller than in the comparative example, as shown by the dashed line. In other words, it is possible to reduce the loss at turn-off.

[0048] As described above, when turning on, a current flows from the positive power supply N1 and the positive power supply N3 in FIG. 2 through the wiring LN1 of the first path RT1 and the wiring LN3 of the second path RT2 to the gate of the switching element 101. At that time, the potential on the gate terminal side of the inductance component L3 may become higher than the potential on the diode side of the gate resistor R1. In that case, a part of the current that should flow to the gate of the switching element 101 may flow in the direction of the gate resistor of the first path RT1. Therefore, the diode D1 is provided on the gate terminal side of the gate resistor R1 to prevent such a reverse flow. Also, when turning off, the potential on the gate terminal side may become lower than the potential on the diode side of the gate resistor R2, and the diode D2 is provided to prevent the reverse flow at that time.

[0049] In this way, by providing diodes D1 and D2 that limit the direction of gate current flow and preventing backflow to the first path RT1, it is possible to reduce loss on the first path RT1 due to backflow and suppress heat generation in the gate substrate. In addition, it is possible to efficiently charge and discharge the gate capacitance of the switching element 101, and it is possible to maintain a high gate charge and discharge speed.

[0050] (Variation 1) Fig. 6 is a diagram showing a first modified example of the first embodiment described above. In the first modified example, the inductance components L3 and L4 shown in Fig. 2 of the first embodiment are shared by an inductance component Lb. The wiring LN3 and the wiring LN4 are connected to the gate terminal G via the wiring LNb having the inductance component Lb. Moreover, the wiring LN1 and the wiring LN2 are connected to the gate terminal G via the wiring LNa.

[0051] By using the wiring LNb having the inductance component Lb, a common inductance component Lb is added to each of the wirings LN3 and LN4. The magnitude of the inductance component Lb is set so that the total inductance component of the wirings LN3 and LNb and the total inductance component of the wirings LN4 and LNb are both greater than the inductance component of the first path RT1.

[0052] By using the wiring LNb having the inductance component Lb as shown in Fig. 6, it is possible to reduce the number of components (inductors) and simplify the circuit. The on / off operations of the MOSFETs 13 and 14 at the time of turning on and off are the same as those in the first embodiment described above, and therefore the description thereof will be omitted. The configuration of the first modification also provides the same advantageous effects as those in the first embodiment.

[0053] (Variation 2) FIG. 7 is a diagram illustrating a second modified example of the first embodiment described above. In a gate driving device 600 of the second modified example, as shown in FIG. 7, a diode D3 is further provided between the positive power supply N3 and the gate terminal G in addition to the configuration of FIG. 2. The operation at the time of turn-on and turn-off is the same as that of the first embodiment described above. In the configuration of the second modified example, when the potential of the gate terminal G becomes higher than the positive power supply N3, the excess charge at the gate of the switching element 101 returns to the positive power supply N3. This makes it possible to prevent the gate from being overcharged.

[0054] Second embodiment FIG. 8 is a diagram showing a second embodiment of the present invention. In FIG. 2, the source of the MOSFET 13, which is a switching element, is connected to the positive power supply N3, but in FIG. 8, the source of the MOSFET 13 is connected to the drain of the MOSFET 11. Similarly, the source of the MOSFET 14 is connected to the drain of the MOSFET 12. In FIG. 8, the MOSFETs 13 and 14 provided on the wirings LN3 and LN4 are shown as switches. These switches may be BJTs (Bipolar Junction Transistors) instead of MOSFETs. Note that in FIG. 8, the symbols RT1 and RT2 indicating the first and second paths are omitted.

[0055] In the second embodiment, the current (gate current) flowing through the wiring LN3 of the second path is controlled by both MOSFETs 11 and 13, and the current flowing through the wiring LN4 is controlled by both MOSFETs 12 and 14. That is, a current flows through the wiring LN3 only when both MOSFETs 11 and 13 are on. In the case of the wiring LN4, a current flows only when both MOSFETs 12 and 14 are on.

[0056] In the second embodiment, if the MOSFET 13 is turned on before or at the same time as the MOSFET 11, the gate current can be automatically and simultaneously started to flow through the wiring LN1 and the wiring LN3. The same applies to the wirings LN2 and LN4. Therefore, by setting the on-timing of the MOSFETs 13 and 14 earlier than the on-timing of the MOSFETs 11 and 12, the pulse width of the control signals S3 and S4 for the MOSFETs 13 and 14 can be lengthened. This improves the controllability of the gate driver 600 and allows a slow-response control element to be mounted on the wirings LN3 and LN4 on the second path.

[0057] According to the embodiment and modified examples of the present invention described above, the following advantageous effects are achieved.

[0058] (1) As shown in Figs. 1 and 2, a gate driver 600 that applies a voltage to a gate terminal G of a switching element 101 includes a first path RT1 connected to the gate terminal G and having gate resistors R1 and R2, a second path RT2 connected to the gate terminal G in parallel with the first path RT1 and having gate resistors R3 and R4, and control signal generators 403 and 404 (active gate controllers) that control the gate current when switching the switching state of the switching element 101 so that the gate current flows only through the path RT1 after flowing through both the path RT1 and the path RT2. The inductance component of the path RT2 is set to a value larger than that of the path RT1. For example, as shown in Fig. 2, the inductance component of the path RT2 is set to be larger than that of the path RT1 by inductance components L3 and L4.

[0059] As described above, by setting the inductance component of the path RT2 to be larger than that of the path RT1, the attenuation of the gate current during switching can be weakened. As a result, the switching speed can be improved and the loss during switching can be reduced. Furthermore, even if the switching element 101 is a power element with a large built-in resistance, it can be driven at high speed. In the example shown in FIG. 2, the second path RT2 is provided with the charging line LN3 and the discharging line LN4, but a configuration in which only one of them is provided may be used.

[0060] (2) In the above (1), as shown in FIG. 2 etc., the path RT1 further includes diodes D1 and D2 that limit the direction of the gate current. This can prevent loss in the path RT1 due to the backflow of the gate current, and suppress heat generation in the gate substrate. In addition, the current flowing through the path RT2 can be efficiently used to charge and discharge the gate capacitance, and the gate charge and discharge speed can be improved.

[0061] (3) In the above (1), at least a part of the inductance component of the path RT2 may be configured with an inductor or ferrite beads. By adjusting the inductance components L3 and L4 using an inductor, the inductance components L3 and L4 can be easily and accurately adjusted. In addition, by mounting ferrite beads on the wiring to adjust the inductance components L3 and L4, a desired inductance component can be obtained even with a short wiring, and the power supply circuit can be made smaller.

[0062] (4) In the above (1), at least a part of the inductance components L3 and L4 in the path RT2 may be set by the wiring length of the path RT2 or the lead length of the component in the path RT2, which makes it easier to design the layout on the board.

[0063] (5) In the above (1), as shown in Figures 2, 3, etc., MOSFETs 11 and 12 (first control elements) are provided in path RT1 for allowing and blocking the passage of gate current, and MOSFETs 13 and 14 (second control elements) are provided in path RT2 for allowing and blocking the passage of gate current. When passing gate current through both path RT1 and path RT2, control signal generation units 403 and 404 (active gate control units) allow passage of current through MOSFETs 13 and 14 before or simultaneously with allowing passage of current through MOSFETs 11 and 12.

[0064] As described above, by permitting conduction through MOSFETs 13 and 14 at the same time as permitting conduction through MOSFETs 11 and 12, charging and discharging of the gate capacitance through path RT1 can be started at the same time as charging and discharging through path RT2. Furthermore, by starting conduction through MOSFETs 13 and 14 prior to conduction through MOSFETs 11 and 12, the pulse width required for controlling MOSFETs 13 and 14 can be made longer, improving the controllability of the gate driver 600. This makes it possible to mount a slow-response control element on path RT2.

[0065] (6) In the above (1), as shown in Figures 2, 3, 5, etc., MOSFETs 11 and 12 (first control elements) are provided on path RT1 for allowing and blocking the passage of a gate current, and MOSFETs 13 and 14 (second control elements) are provided on path RT2 for allowing and blocking the passage of a gate current. When controlling the gate current to flow only through path RT1, the control signal generation units 403 and 404 (active gate control units) block the passage of current through the MOSFETs 13 and 14 before the timing of a surge peak of the switching current (drain current Ids) or switching voltage (drain-source voltage Vds) of the switching element 101.

[0066] By cutting off the current flow through the MOSFETs 13 and 14 before the surge peak timing of the drain current Ids or the drain-source voltage Vds, the gate current flowing through the gate of the switching element 101 is reduced. This reduces the switching speed, making it possible to suppress the surge of the drain current Ids or the drain-source voltage Vds.

[0067] (7) In the above (1), as shown in FIG. 8 etc., MOSFETs 11, 12 (first control elements) are provided on a path RT1 opposite the gate terminal G across the gate resistors R1, R2, and allow and block the passage of a gate current, and MOSFETs 13, 14 (second control elements) are provided on a path RT2 (wirings LN3, LN4) and allow and block the passage of a gate current, one end of the path RT2 (wirings LN3, LN4) is connected between the gate resistors R1, R2 and the MOSFETs 11, 12, and the other end of the path RT2 is connected to the gate terminal G, and the conversion control device 400 and control signal generation units 403, 404 (active gate control units) control the allow and block of the passage of the gate current by the MOSFETs 11-14.

[0068] In the above configuration, the timings at which charging and discharging by the paths RT1 and RT2 start can be easily synchronized by setting the MOSFETs 13 and 14 in a conduction-permitted state before the conduction of the MOSFETs 11 and 12 is permitted. In addition, by starting the on-timing of the MOSFETs 13 and 14 before the on-timing of the MOSFETs 11 and 12, the pulse width required for controlling the MOSFETs 13 and 14 can be made longer, thereby improving the controllability of the gate driver 600. This makes it possible to mount a slow-response control element on the path RT2.

[0069] (8) In the above (1), as shown in FIG. 6 etc., the path RT2 includes a wiring LN3 having a gate resistor R3 for charging the gate capacitance of the switching element 101, a wiring LN4 having a gate resistor R4 for discharging the gate capacitance of the switching element 101, and a wiring LNb having one end connected to the wiring LN3 and the wiring LN4 and the other end connected to the gate terminal G, and the inductance component of the wiring consisting of the wiring LN3 and the wiring LNb and the inductance component of the wiring consisting of the wiring LN4 and the wiring LNb are each set to a value larger than the inductance component of the path RT1.

[0070] By using the wiring LNb having the inductance component Lb as shown in FIG. 6, the inductance component of the second path is shared, making it possible to reduce the number of parts (inductors) and simplify the circuit.

[0071] (9) In the above (1), as shown in FIG. 7 etc., the path RT2 includes a wiring LN3 that connects a positive power supply N3 (gate charge power supply) for charging the gate capacitance of the switching element 101 and the gate terminal G, and a diode D3 that is provided between the positive power supply N3 and the gate terminal G, with a cathode connected to the positive power supply N3 and an anode connected to the gate terminal G. When the voltage of the gate terminal G becomes higher than the voltage of the positive power supply N3, excess gate charge can be fed back to the positive power supply N3. This makes it possible to prevent overcharging of the gate.

[0072] The above-described embodiments and various modified examples are merely examples, and the present invention is not limited to these contents as long as the characteristics of the invention are not impaired. In addition, although various embodiments and modified examples have been described above, the present invention is not limited to these contents. Other aspects that are conceivable within the scope of the technical idea of ​​the present invention are also included in the scope of the present invention. [Explanation of symbols]

[0073] 11 to 14...MOSFET, 100...electric storage device, 101...switching element, 102...freewheel diode, 200...power conversion device, 300...electric motor, 400...conversion control device, 403, 404...control signal generation unit, 500...three-phase switching arm, 600, 610...gate drive device, 1000...vehicle, D1, D2, D3...diode, J...state signal, L3, L4, Lb...inductance component, LN1 to LN4, LNb...wiring, N1, N3...positive power supply, N2, N4...negative power supply, P...control command, R1 to R4...gate resistor, RT1, RT2...path, S3, S4...control signal

Claims

1. A gate driver that applies a voltage to a gate terminal of a semiconductor switching element, a first path connected to the gate terminal and having a first gate resistor; a second path connected in parallel with the first path to the gate terminal, the second path having a second gate resistor; an active gate control unit that controls a gate current when switching a switching state of the semiconductor switching element so that the gate current flows through both the first path and the second path and then flows only through the first path; A gate driver, wherein an inductance component of the second path is set to a value larger than an inductance component of the first path.

2. 2. The gate drive device according to claim 1, The first path further includes a diode that limits a direction of flow of the gate current.

3. 2. The gate drive device according to claim 1, A gate driver, wherein at least a portion of the inductance component of the second path is formed by an inductor or a ferrite bead.

4. 2. The gate drive device according to claim 1, A gate driver, wherein at least a portion of the inductance component in the second path is set by a wiring length of the second path or a lead length of a component in the second path.

5. 2. The gate drive device according to claim 1, a first control element provided in the first path for allowing and blocking the passage of the gate current; a second control element provided in the second path and configured to allow and block the passage of the gate current; The active gate control unit includes: a gate driver for allowing current to flow through both the first path and the second path by permitting current flow through the second control element prior to or simultaneously with permitting current flow through the first control element.

6. 2. The gate drive device according to claim 1, a first control element provided in the first path for allowing and blocking the passage of the gate current; a second control element provided in the second path and configured to allow and block the passage of the gate current; The active gate control unit includes: When controlling the gate current to flow only through the first path, A gate driver that cuts off current flow through the second control element before a timing of a surge peak of a switching current or a switching voltage of the semiconductor switching element.

7. 2. The gate drive device according to claim 1, a first control element that is provided on the first path on a side opposite to the gate terminal across the first gate resistor and that allows and blocks the passage of the gate current; a second control element provided in the second path and configured to allow and block the passage of the gate current; one end of the second path is connected between the first gate resistor and the first control element, and the other end of the second path is connected to the gate terminal; The active gate control unit controls the first control element and the second control element to allow and block the passage of the gate current.

8. 2. The gate drive device according to claim 1, The second pathway is a first wiring having a third gate resistor constituting a part of the second gate resistor and for charging a gate capacitance of the semiconductor switching element; a second wiring having a fourth gate resistor constituting a part of the second gate resistor and for discharging a gate capacitance of the semiconductor switching element; a third wiring having one end connected to the first wiring and the second wiring and the other end connected to the gate terminal; a gate driving device, wherein an inductance component of a wiring consisting of the first wiring and the third wiring, and an inductance component of a wiring consisting of the second wiring and the third wiring, are each set to a value larger than the inductance component of the first path.

9. 2. The gate drive device according to claim 1, The second pathway is a wiring that connects a gate charge power source for charging a gate capacitance of the semiconductor switching element to the gate terminal; a diode provided between the gate charge power supply and the gate terminal, the cathode of the diode being connected to the gate charge power supply and the anode of the diode being connected to the gate terminal; A gate drive device comprising:

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