Transistor and manufacturing method thereof, and integrated circuit

Abstract

To provide a transistor having a gate with extremely short length and an extremely thin carrier transportation layer.SOLUTION: A transistor comprises: a substrate having a flat uppermost face, a vertical face crossing with the uppermost face and extending below the uppermost face, and a lower stage almost parallel to the uppermost face and crossing with the vertical face; a conductive thin film formed in contact with the uppermost face of the substrate; an insulator film formed to cover at least the vertical face and an end of the conductive thin film; a two-dimensional semiconductor layer formed to cover the uppermost face, the vertical face and the lower stage face and overlaid to cover the conductive thin film and / or the insulator film at a portion, where the conductive thin film and / or the insulator film exist; a source electrode provided at a portion of the two-dimensional semiconductor layer to cover the uppermost face; and a drain electrode provided at a portion of the two-dimensional semiconductor layer to cover the lower stage face.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a transistor having an extremely short gate length and an extremely thin carrier transport layer, a method for manufacturing the same, and an integrated circuit. [Background technology]

[0002] To realize the next generation of mobile communication systems (so-called 6G and Beyond 5G), there is a demand for even faster analog front-end amplifiers and logic integrated circuits, which form the core of baseband. To achieve these speed increases, it is necessary to make the gate extremely short and the carrier transport layer (channel) extremely thin. To make the gate extremely short, there is a demand for technology that can shorten the gate length to the single-atom level. In addition, there is a demand for technology that can achieve the ultra-thinning of the carrier transport layer to the single-atom level.

[0003] Conventionally, lithography using ultraviolet light has been used in the manufacture of semiconductor integrated circuits, and in the future, technological developments are being made to advance ultra-fine features as an extension of conventional technology by using so-called extreme ultraviolet light (EUV), which is an even shorter wavelength of ultraviolet light. However, semiconductor manufacturing equipment using EUV is becoming increasingly large and expensive, and harmful substances are used, so it is expected that progress in EUV technology will become difficult in the near future.

[0004] In this situation, in response to the demand for extremely short gates and extremely thin carrier transport layers, a transistor having a monoatomic long gate and a channel made of a monoatomic layer of MoS2, which is a two-dimensional semiconductor, has been proposed (see, for example, Non-Patent Document 1). [Prior art documents] [Non-patent literature]

[0005] [Non-Patent Document 1] Fan Wu et al. Nature 603 (2022) 259 Summary of the Invention [Problem to be solved by the invention]

[0006] In the transistor described in Non-Patent Document 1, a graphene film formed on a metal foil by a CVD method is transferred to a substrate, and the transferred graphene is used as a gate. In addition, a two-dimensional semiconductor formed on a metal foil by a CVD method is transferred to a desired substrate. The transistor in Non-Patent Document 1 has three major problems. The first problem is that the graphene and two-dimensional semiconductor transferred from the metal foil to the substrate are wrinkled or do not completely adhere to the three-dimensional structure on the substrate surface. Therefore, the device performance value is lower than the theoretical value, and the device reliability is also low. The second problem is that the gate resistance is high. The high gate resistance is due to the use of a single layer of graphene as the gate, which prevents the transistor from being made faster. The third problem is that in existing device structures suitable for high-frequency applications, some structures and parts such as the gate electrode and the insulating layer are shortened or reduced to about several tens of nanometers or several nanometers, but the device structure and device layout composed of two-dimensional materials and substances with a layer thickness of one to a dozen atoms as in the present invention are not optimized. Because of these problems, transistors with monoatomic gate lengths have not been put to practical use until now.

[0007] The present invention has been made in view of the above, and aims to provide a transistor having a gate with an extremely short length (preferably at the monoatomic level) and a carrier transport layer with an extremely thin thickness (preferably at the monoatomic level), and a highly reliable manufacturing method thereof suitable for mass production. [Means for solving the problem]

[0008] A transistor according to an embodiment of the present invention includes a substrate having a top surface, a vertical surface intersecting with the top surface and extending downward from the top surface, and a lower surface that is substantially parallel to the top surface and intersects with the vertical surface, a conductive thin film formed in contact with the top surface of the substrate, an insulating film formed so as to cover at least the vertical surface and an end of the conductive thin film, a two-dimensional semiconductor layer formed so as to cover the top surface, the vertical surface, and the lower surface, and formed so as to cover the conductive thin film and / or the insulating film in a portion where the conductive thin film and / or the insulating film are present, a source electrode provided at a portion covering the top surface of the two-dimensional semiconductor layer, and a drain electrode provided at a portion covering the lower surface of the two-dimensional semiconductor layer. The top surface and / or the lower surface may be flat.

[0009] In the present invention, the transistor may further include a conductor shielding layer on the conductive thin film, and insulating layers may be provided on both the front and back surfaces of the shielding layer.

[0010] In the present invention, the substrate may have at least a top surface made of single crystal silicon carbide (SiC), and the conductive thin film may be graphene. Also, the conductive thin film may have a single layer at an end portion overlapping a ridge line where the top surface intersects with a vertical surface.

[0011] In the present invention, the substrate may have an inclined surface adjacent to the top surface and non-parallel to the top surface at an end opposite to the edge of the top surface that contacts the vertical surface, the conductive thin film may be formed from the top surface across the inclined surface, and the conductive thin film on the inclined surface may be multi-layered graphene.

[0012] In the present invention, the substrate may be a single crystal substrate of silicon carbide or a hybrid substrate in which a single crystal layer of silicon carbide is fabricated on an insulator.

[0013] In the present invention, the two-dimensional semiconductor layer is preferably formed of a material selected from the group consisting of graphene, transition metal dichalcogenide, indium oxide, boron phosphide, and boron arsenide.The two-dimensional semiconductor layer is particularly preferably formed of a transition metal dichalcogenide selected from the group consisting of molybdenum disulfide (MoS2), tungsten disulfide (WS2), and tungsten diselenide (WSe2).

[0014] In the present invention, the insulating film is preferably made of a material selected from the group consisting of hafnium oxide, silicon carbide, zirconium oxide, erbium oxide, aluminum oxide, and silicon carbide.

[0015] An integrated circuit according to an embodiment of the present invention includes a plurality of transistors according to claim 1 or 2. In the integrated circuit, the substrate may have two vertical surfaces facing the protruding portion on which the top surface is formed, and one conductive thin film and one source electrode may be shared by two transistors. Alternatively, the substrate may have two vertical surfaces facing each other on both sides of one lower surface, and one lower surface may be shared by two transistors.

[0016] A method for manufacturing a transistor according to an embodiment of the present invention includes the steps of preparing a substrate, forming a conductive thin film of 10 atomic layers or less on a flat top surface of the substrate, removing the conductive thin film and the upper part of the substrate from other parts while leaving the conductive thin film in a portion by microfabrication to form a vertical surface that intersects with the top surface and extends downward from the top surface, and a lower surface that is approximately parallel to the top surface and intersects with the vertical surface, depositing an insulating film so as to cover at least the vertical surface and the end of the conductive thin film, depositing a two-dimensional semiconductor layer so as to cover the top surface, the vertical surface, and the lower surface, and also to cover the conductive thin film and / or the insulating film in places where the conductive thin film and / or the insulating film are present, and forming a source electrode so as to overlap the part covering the conductive thin film in the two-dimensional semiconductor layer, and forming a drain electrode so as to overlap the part covering the lower surface in the two-dimensional semiconductor layer.

[0017] The present invention may further include a step of providing a shielding layer over the conductive thin film after the conductive thin film is formed and before the step of forming the vertical surface and the lower surface.

[0018] In the present invention, the substrate may have at least a top surface made of single crystal silicon carbide, and in the step of forming a conductive thin film, graphene may be formed as a conductive thin film on the top surface of the substrate. In the step of forming a conductive thin film, it is particularly preferable that the graphene conductive thin film is formed such that an end portion overlapping a ridge line where the top surface intersects with a vertical plane forms a single layer.

[0019] In the present invention, it is preferable to have a step of forming an inclined surface adjacent to the top surface and non-parallel to the top surface prior to the step of forming the conductive thin film, and in the step of forming the conductive thin film, the conductive thin film is formed from the top surface to the inclined surface, and the conductive thin film on the inclined surface preferably forms multiple layers of graphene.

[0020] In the present invention, the substrate may be a single crystal substrate of silicon carbide or a hybrid substrate in which a single crystal layer of silicon carbide is fabricated on an insulator.

[0021] In the present invention, the two-dimensional semiconductor layer is preferably formed of a material selected from the group consisting of graphene, transition metal dichalcogenide, indium oxide, boron phosphide, and boron arsenide.The two-dimensional semiconductor layer is particularly preferably formed of a transition metal dichalcogenide selected from the group consisting of molybdenum disulfide (MoS2), tungsten disulfide (WS2), and tungsten diselenide (WSe2).

[0022] In the present invention, the insulating film is preferably made of a material selected from the group consisting of hafnium oxide, silicon carbide, zirconium oxide, erbium oxide, aluminum oxide, and silicon carbide. Effect of the Invention

[0023] Transistors suitable for high frequency applications having extremely short gate lengths and carrier transport layers with extremely thin thicknesses can be realized, and such transistors can be manufactured with high reliability. [Brief description of the drawings]

[0024] [Figure 1] 1 is a cross-sectional view showing a basic structure of a transistor 1 according to a first embodiment of the present invention. [Diagram 2] 1 is a cross-sectional view showing the structure of an integrated circuit in which a plurality of transistors 1 are formed on one substrate. [Diagram 3] 1 is a perspective view illustrating a schematic three-dimensional structure of a transistor 1 according to a first embodiment. [Figure 4] 1 is a plan view showing an example of a layout in which electrode pads are provided on a transistor 1 according to a first embodiment. [Diagram 5] 1 is a schematic diagram of a layout for high output using a transistor 1 according to a first embodiment. [Figure 6] 2 is a diagram showing an example of a procedure for a method of manufacturing the transistor 1 according to the first embodiment. [Figure 7] 1 is a cross-sectional view showing a basic structure of a transistor 1a according to a second embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] Hereinafter, an embodiment of the present invention will be described. The same reference numerals are used to denote common components in the drawings, including those used to describe the background art.

[0026] [First embodiment] Fig. 1 is a cross-sectional view showing a basic structure of a transistor 1 according to a first embodiment of the present invention. Fig. 2 is a cross-sectional view showing a structure of an integrated circuit in which a plurality of transistors 1 are formed on one substrate. Fig. 3 is a perspective view showing a schematic three-dimensional structure of the transistor 1 according to the first embodiment. As shown in Fig. 1, the transistor 1 includes a substrate 2, a conductive thin film 3, a shielding layer 4, an insulating layer 5, an insulating film 6, a two-dimensional semiconductor layer 7, an electrode 8, and an electrode 9.

[0027] The substrate 2 serves as a base for forming the structure of the transistor 1. The substrate 2 is preferably a substrate having a high resistance of 10,000Ω or more at least on its surface. For example, a material containing silicon carbide may be used as the substrate 2, and at least the top surface 21 may be a single crystal silicon carbide substrate. More specifically, the substrate 2 may be a single crystal silicon carbide substrate, or a hybrid substrate in which a single crystal silicon carbide layer is formed on an insulator (e.g., single crystal Si, sapphire, etc.). When a substrate having a single crystal silicon carbide top surface 21 is used, a thin film of graphene (preferably a monoatomic layer) can be formed as the conductive thin film 3 on the top surface 21. When a material other than graphene is used as the conductive thin film 3, the substrate 2 may be made of silicon (Si), sapphire, a quartz glass substrate, a flexible substrate made of a film-like resin such as polyimide or PET (Polyethylene terephthalate), or a transparent conductive oxide such as ITO (Indium Tin Oxide) or FTO (Fluorine-doped Tin Oxide).

[0028] As shown in FIG. 1, the substrate 2 has a top surface 21, a vertical surface 22, and a lower surface 23 formed on one surface thereof. The top surface 21 is the uppermost flat surface of the substrate 2. The vertical surface 22 is a plane that intersects with the top surface 21 and extends downward from the top surface 21. In the example of FIG. 1, the vertical surface 22 and the top surface 21 are perpendicular to each other. The lower surface 23 intersects with the vertical surface 22 and is formed as a plane that is approximately parallel to the top surface 21. In the example of FIG. 1, the lower surface 23 and the vertical surface 22 are perpendicular to each other, and the top surface 21 and the lower surface 23 are parallel to each other. When the vertical surface 22 is a crystal layer, the surface of the vertical surface 22 is preferably a (0001) plane. The length from one end to the other end of the top surface 21 (L1 in FIG. 3) and the length from one end to the other end of the lower surface 23 (L2 in FIG. 3) are each preferably 100 nm to 5 μm. The height of the vertical surface (H in FIG. 3) is preferably 30 to 100 nm.

[0029] The conductive thin film 3 is an extremely thin conductive thin film of a single atomic layer or several atomic layers (10 atomic layers or less) formed in contact with the top surface 21 of the substrate 2. The thickness of the conductive thin film 3 is about several nm (preferably 5 nm) or less. The length from one end of the conductive thin film 3 to the other end is preferably about 100 nm to 5 μm in accordance with the length L1 of the top surface 21 of the substrate 2. A layered conductive material is suitable for the conductive thin film 3. Specifically, graphene, borophene which is a two-dimensional crystal of boron, a derivative of borophene, or the like may be used. In particular, graphene is suitable for the conductive thin film 3 because it can form a single-layer thin film on the (0001) surface of silicon carbide which is suitable for the substrate 2. Alternatively, titanium nitride (TiN) may be used for the conductive thin film 3. The conductive thin film 3 is provided so as to cover the entire top surface 21 of the substrate 2 up to the vicinity of the ridge where the top surface 21 and the vertical surface 22 intersect. An end (edge) 31 of the conductive thin film 3 overlapping the vicinity of the ridge where the top surface 21 and the vertical surface 22 intersect functions as a gate of the transistor 1. Moreover, a portion of the conductive thin film 3 other than the edge 31 functions as wiring from a gate electrode pad 10 (described later) to a gate.

[0030] The shielding layer 4 is a layer of a conductor such as a metal provided on the conductive thin film 3, and shields the electrode 8 from the conductive thin film 3. The shielding layer 4 is electrically connected to a predetermined ground potential (for example, 0 V). At least the front and back surfaces of the shielding layer 4 are provided with an insulating layer 5 to prevent the shielding layer 4 from shorting with the conductive thin film 3 or the electrode 8. The shielding layer 4 is preferably made of aluminum (Al) or nickel (Ni). When Al is used as the shielding layer 4, the natural oxide film formed on the surface of Al can be used as the insulating layer 5 as it is, and the manufacturing process can be simplified. When Ni is used as the shielding layer 4, it is necessary to form a separate insulating layer 5 to prevent shorting with the conductive thin film 3 or the electrode 8. Note that when it is not necessary to shield the electrode 8 from the conductive thin film 3 (for example, when signal interference between the electrode 8 and the conductive thin film 3 is not a problem), the transistor 1 does not need to include the shielding layer 4 and the insulating layer 5. The end surface 51 of the insulating layer 5 should be a plane that is approximately aligned with the vertical surface 22.

[0031] The insulating film 6 is a thin film of an insulator that functions as a gate insulating film of the transistor 1. As the insulating film 6, a high dielectric constant insulating film such as hafnium oxide, silicon carbide, zirconium oxide, erbium oxide, aluminum oxide, etc., a thin film of silicon carbide, etc. can be used. For high frequency applications exceeding 1 THz, a thin film of silicon carbide is suitable. In the example shown in FIG. 1, the insulating film 6 is formed so as to cover from the upper surface of the insulating layer 5 through the end surface 51, the edge 31, the vertical surface 22, and the lower surface 23. Note that, as long as the insulating film 6 covers at least the vertical surface 22, the edge 31, and the end surface 51 of the substrate 2, there are cases where it is not necessary to form the insulating film 6 on other parts. For example, in a configuration that includes the insulating layer 5 and the shielding layer 4, the insulating film 6 does not need to be provided on the insulating layer 5. On the other hand, in a configuration that does not include the insulating layer 5 and the shielding layer 4, it is necessary to provide the insulating film 6 also between the conductive thin film 3 and the electrode 8 to prevent a short circuit between the conductive thin film 3 and the electrode 8. Furthermore, if the substrate 2 has sufficient insulating properties, the insulating film 6 does not need to be provided on the lower surface .

[0032] The two-dimensional semiconductor layer 7 is a semiconductor layer that functions as a carrier transport layer of the transistor 1. The two-dimensional semiconductor layer 7 is formed so as to cover the top surface 21, the vertical surface 22, and the lower surface 23. The two-dimensional semiconductor layer 7 is formed so as to cover the conductive thin film 3, the shielding layer 4, the insulating layer 5, and / or the insulating film 6 in places where they are present. The two-dimensional semiconductor layer 7 can be made of graphene, transition metal dichalcogenides (e.g., molybdenum disulfide (MoS2), tungsten disulfide (WS2), tungsten diselenide (WSe2), etc.), indium oxide (In2O3), boron phosphide, boron arsenide, etc., each having a monoatomic layer or several atomic layers. For high-frequency applications exceeding 1 THz, graphene is suitable as the two-dimensional semiconductor layer 7. For high-frequency applications of about 300 GHz to 1 THz, transition metal dichalcogenides such as MoS2 and WS2 are suitable as the two-dimensional semiconductor layer 7. In relatively low frequency applications such as logic circuits, In2O3 and transition metal dichalcogenides are suitable for the two-dimensional semiconductor layer 7.

[0033] The electrode 8 and the electrode 9 are electrodes made of metals such as Au, Al, In, Bi, Ni, Pd, Ti, Pt, etc., or transparent conductive oxides such as ITO and FTO. The electrode 8 is provided so as to overlap a portion of the two-dimensional semiconductor layer 7 that covers the conductive thin film 3, and functions as a source electrode of the transistor 1. The electrode 9 is provided so as to overlap a portion of the two-dimensional semiconductor layer 7 that covers the lower surface 23, and functions as a drain electrode of the transistor 1.

[0034] In the transistor 1 having the basic structure described above, the surface on which the conductive thin film 3 is formed and the surface on which the two-dimensional semiconductor layer 7 covering the vertical surface 22 is formed are perpendicular to each other, and an edge 31 of the conductive thin film 3 faces the two-dimensional semiconductor layer 7 via the insulating film 6, so that the thickness of the conductive thin film 3 defines the gate length of the transistor 1. If the conductive thin film 3 is a monoatomic layer of graphene, the gate length of the transistor 1 can be shortened to 0.3 nm. Even if a material other than a monoatomic layer of graphene is used for the conductive thin film 3, a gate length of several nm or less corresponding to the thickness of the conductive thin film 3 can be achieved.

[0035] FIG. 2 is a cross-sectional view showing the structure of an integrated circuit in which a plurality of transistors 1 are formed on one substrate. The above-described structure of the transistor 1, which has an electrode 8 on the top surface 21 and an electrode 9 on the lower surface 23, and uses the edge 31 of the conductive thin film 3 as a gate, can be formed on both the left and right sides of the convex portion of the substrate 2 on which the top surface 21 is formed, so as to share the conductive thin film 3 and the electrode 8, as shown in FIG. 2. Alternatively, the transistors 1 can be formed on both the left and right sides of the lower surface 23, so as to share the electrode 9. In this way, an integrated circuit in which a plurality of transistors 1 are formed on the substrate 2 can be formed. By repeatedly forming a structure similar to that of FIG. 1 as shown in FIG. 2, a larger integrated circuit can be formed by integrating even more transistors 1 (six in the example of FIG. 2).

[0036] FIG. 3 is a perspective view showing a schematic three-dimensional structure of the transistor 1 according to the first embodiment. The cross-sectional structure of the transistor 1 shown in FIG. 1 is formed over a desired width W as shown in FIG. 3. The width W can be arbitrarily determined depending on the magnitude of the current to be passed through the transistor 1, but from the viewpoint of reliability, the width W is preferably about 30 to 50 μm. For example, when the allowable current amount per unit width of the channel is 1 A / mm and the width W is 50 μm, a current of 50 mA can be passed through one transistor 1 structure. When it is desired to pass a larger current, for example, the structure shown in FIG. 2 or the layout shown in FIG. 5 described later can be adopted to use multiple transistor 1 structures in parallel to substantially expand the width of the channel and realize a desired allowable current amount.

[0037] As shown in FIG. 4, the transistor 1 is provided with a plurality of electrode pads for connection to the outside. A source electrode pad 81 is provided overlapping the electrode 8 and is electrically connected to the electrode 8. A drain electrode pad 91 is provided overlapping the electrode 9 and is electrically connected to the electrode 9. A gate electrode pad 10 is provided outside the width W and is electrically connected to the conductive thin film 3. The source electrode pad 81, the drain electrode pad 91, and the gate electrode pad 10 are each formed with an area sufficient to allow wire bonding or bump formation, and facilitate connection of the source, drain, and gate of the transistor 1 to the outside, respectively. Although not shown in FIG. 4, an electrode pad for connecting the shielding layer 4 to an external ground potential may be further provided. The structure shown in FIG. 4 may be formed in an area of, for example, about 100 μm square.

[0038] 5(a)-(c) are schematic diagrams of the layout of the transistor 1 for high output. FIG. 5(a) is a schematic diagram of a layout in which the structure of FIG. 1 is provided on both sides of a common drain electrode 9 to increase output. Compared with the conventional device, it is possible to arrange and connect the two devices closer to each other, and it is possible to reduce the transmission loss and parasitic resistance of the connection wiring circuit, suppressing the power loss at high frequencies and enabling high output. FIG. 5(b) and (c) show the case where even more transistors 1 are arranged to achieve even higher output, and the allowable current increases in proportion to the number of arranged transistors, realizing high output. Furthermore, by changing the number and arrangement of the comb-shaped electrodes extending from the drain electrode pad 91 onto the electrode 9, the number of transistors 1 that operate and form a current path (channel layer) can be arbitrarily determined. Comparing the configuration of Fig. 5(b), in which the comb electrodes are thinned out, with the configuration of Fig. 5(c), in which comb electrodes are provided on all electrodes 9, the configuration of Fig. 5(c) forms twice as many current paths (channel layers), doubles the current value and mutual conductance (gm), and enables higher output. Note that in Fig. 5(b), electrodes 9 do not need to be provided in the locations where the comb electrodes are thinned out.

[0039] Next, with reference to FIG. 6, a method for manufacturing a transistor 1 having a structure in which a single layer of graphene is provided on a silicon carbide substrate will be described as an example of the transistor 1 according to this embodiment.

[0040] First, a substrate having a silicon carbide (0001) surface on the upper surface is prepared as the substrate 2 ((a) in FIG. 6). Next, a single-layer graphene layer that will become the conductive thin film 3 is formed on the upper surface of the substrate 2 ((b) in FIG. 6). The graphene layer can be graphened by thermal sublimation of Si atoms, chemical vapor deposition, molecular beam epitaxy, or the like. Next, a shielding layer 4 made of Al is formed on the conductive thin film 3. During the formation of the shielding layer 4 and the fine processing process, an insulating layer 5 made of a natural oxide film is formed on the shielding layer 4 so as to cover its surface ((c) in FIG. 6). When a material that does not form a natural oxide film other than Al is used as the shielding layer 4, it is advisable to form insulating layers above and below the shielding layer 4 to ensure insulation between the shielding layer 4 and the conductive thin film 3 and the electrode 8.

[0041] Next, microfabrication is performed by reactive ion etching or neutral particle beam etching using a chlorine-based gas or a fluorine-based gas, thereby digging down a part of the substrate 2 to form a vertical surface 22 and a lower surface 23 on the substrate 2, and the shielding layer 4 is processed to match the vertical surface 22 (FIG. 6(d)). The side surface of the shielding layer 4 is exposed during the microfabrication process, and an insulating layer 5 of a natural oxide film is formed again to cover the exposed surface. There is no graphene layer on the vertical surface 22 or the lower surface 23 formed by the microfabrication, but the conductive thin film 3 of single-layer graphene is left on the remaining top surface 21. Next, an insulating film 6 is deposited (FIG. 6(e)). In FIG. 6(e), the insulating film 6 is formed so as to cover the upper surface of the insulating layer 5, the end surface 51, the edge 31, the vertical surface 22, and the lower surface 23. Note that as long as the insulating film 6 covers at least the vertical surface 22, the edge 31, and the end surface 51 of the substrate 2, it may not be necessary to form the insulating film 6 on other parts. Next, the two-dimensional semiconductor layer 7 is deposited so as to cover the top surface 21, the vertical surface 22, and the lower surface 23 (FIG. 6(f)). At this time, the two-dimensional semiconductor layer 7 is formed so as to cover the conductive thin film 3, the shielding layer 4, the insulating layer 5, and / or the insulating film 6 in places where they are present. Then, an electrode 8 is formed so as to cover the conductive thin film 3 in the two-dimensional semiconductor layer 7, and an electrode 9 is formed so as to cover the lower surface 23 in the two-dimensional semiconductor layer 7 (FIG. 6(g)). As described above, the basic structure of the transistor 1 is completed at 41. A device capable of connecting to the outside can be obtained by providing a source electrode pad 81, a drain electrode pad 91, and a gate electrode pad 10 to the electrode 8, the electrode 9, and the conductive thin film 3, respectively.

[0042] The transistor 1 described above can have a gate length of a single atom (about 0.3 nm), and can achieve speeds that exceed those of the currently fastest high electron mobility transistor (InGaAs-HEMT) with a channel made of a compound semiconductor made of InGaAs. Even if the conductive thin film is a few atomic layers (for example, about 1 nm), it is possible to shorten the gate length and increase the speed compared to current transistors, which are approaching the limits of exposure equipment.

[0043] Since the conductive thin film 3 and the two-dimensional semiconductor layer 7 are grown directly on the top surface 21 and the insulating film 6, respectively, rather than being transferred from another substrate, they can be completely adhered to the three-dimensional structure of the substrate surface without wrinkling.

[0044] Furthermore, the transistor 1 according to this embodiment can utilize a two-dimensional semiconductor having a band gap approximately three times larger than that of InGaAs for the two-dimensional semiconductor layer 7, enabling high output performance that exceeds that of InGaAs-HEMTs by an order of magnitude or more.

[0045] Furthermore, the transistor 1 according to this embodiment has a high degree of freedom in substrate selection, allowing the use of Si with a silicon carbide thin film, silicon carbide, sapphire with a silicon carbide thin film, etc., as the substrate 2. This allows for application not only to ultra-high frequency devices, but also to large scale logic integrated circuits.

[0046] [Second embodiment] Next, a transistor 1a according to a second embodiment of the present invention will be described with reference to FIG. 7. If the gate resistance is high, the high frequency characteristics of the transistor are suppressed. However, when a single layer of graphene is used for the conductive thin film 3 in the transistor 1 having the structure of the first embodiment, the gate resistance is high due to its extremely thin thickness. In the transistor 1a according to this embodiment, the edge of the single layer of graphene is used as the gate electrode, and the graphene in the portion other than the vicinity of the edge is multi-layered to suppress the gate resistance. The feature of this embodiment is the configuration for multi-layering the graphene in the portion other than the vicinity of the edge in the first embodiment. Note that the rest is the same as the first embodiment described above, so the description here will be omitted.

[0047] FIG. 7 is a cross-sectional view showing a basic structure of a transistor 1a according to the second embodiment. The transistor 1a includes a substrate 2, a conductive thin film 3, a shielding layer 4, an insulating layer 5, an insulating film 6, a two-dimensional semiconductor layer 7, an electrode 8, and an electrode 9, similar to the transistor 1 according to the first embodiment. The substrate 2 used in the transistor 1a has a slope 24 in addition to a top surface 21, a vertical surface 22, and a lower surface 23. In the substrate 2, at least the top surface 21 and the slope 24 are single crystals of silicon carbide. The top surface 21 is preferably a (0001) surface of silicon carbide. The slope 24 is a surface that is non-parallel (inclined) to the top surface 21 and is provided adjacent to the top surface 21 at an end portion opposite to the edge of the top surface 21 that contacts the vertical surface 22. The slope angle of the slope 24 is arbitrary, but may be, for example, 45°, 22°, etc. The inclined surface 24 having such an inclination angle can be formed by appropriately adjusting the gas flow rate and the high frequency power (for example, a gas flow rate of 40 sccm and a high frequency power of 50 W) in reactive ion etching using Cl2. The inclination angle of the inclined surface 24 does not need to be constant, and may be formed as a curved surface, for example. Such an inclined surface 24 is provided prior to the formation of the conductive thin film 3. In this embodiment, the conductive thin film 3 is simultaneously formed from the top surface 21 to the inclined surface 24. The growth rate of graphene on the inclined surface 24 is faster than the growth rate of graphene on the top surface 21, which is the (0001) surface of silicon carbide, and therefore, while a single layer of graphene is grown on the top surface 21, multiple layers of graphene (preferably about 10 to 20 layers) are grown on the inclined surface 24. Therefore, the conductive thin film 3 in this embodiment is formed from the top surface 21 to the slope 24, and has a structure in which the vicinity of the edge 31 is made of single-layer graphene 32, while the vicinity of the edge 31 is made of multi-layer graphene 33 on the inner slope 24. The distance from the ridge where the top surface 21 and the vertical surface 22 of the substrate 2 intersect to the slope 24 (i.e., the length of the top surface 21) should be a sufficient distance (e.g., about several hundreds of nm) to prevent the formation of multi-layer graphene from extending to the vicinity of the edge 31.

[0048] The transistor 1a is configured by providing the conductive thin film 3 as described above with the shielding layer 4, insulating layer 5, insulating film 6, two-dimensional semiconductor layer 7, electrode 8, and electrode 9 similar to those in the first embodiment. Note that, although a recess is formed in the conductive thin film 3 due to the inclination of the slope 24 serving as the base, it is preferable to fill this recess with an insulating material or the like to form a flat surface before stacking the shielding layer 4, insulating film 6, two-dimensional semiconductor layer 7, etc.

[0049] In the transistor 1a configured as above, in addition to the same effects as the transistor 1 of the first embodiment, the carrier density increases due to the multi-layering of graphene constituting the conductive thin film 3, and therefore the resistance of the conductive thin film 3 as a whole can be reduced. Meanwhile, at the edge 31 of the conductive thin film 3, a single layer of graphene faces the two-dimensional semiconductor layer 7 via the insulating film 6 and functions as a gate electrode, so that the gate length of the transistor 1 can be set to one atom (approximately 0.3 nm).

[0050] Although the present embodiment and its specific examples have been described above, the present invention is not limited to these examples. Furthermore, those in which a person skilled in the art appropriately adds or removes components from or modifies the design of the above-described embodiment or its specific examples, or those in which the features of each embodiment are appropriately combined, are also included within the scope of the present invention as long as they include the gist of the present invention. [Explanation of symbols]

[0051] 1,1a transistor 2. Board 21 Top surface 22 Vertical plane 23 Lower Level 24 Slope 3. Conductive Thin Film 31 Edge 32 Single-layer graphene 33 Multilayer graphene 4 Shielding layer 5. Insulation layer 51 End face 6. Insulating film 7 Two-dimensional semiconductor layer 8,9 electrode 81 Source electrode pad 91 Drain electrode pad 10 Gate electrode pad

Claims

1. a substrate having a top surface, a vertical surface that intersects with the top surface and extends downward from the top surface, and a lower surface that is substantially parallel to the top surface and intersects with the vertical surface; a conductive thin film formed in contact with the top surface of the substrate; an insulating film formed so as to cover at least the vertical surface and an end portion of the conductive thin film; A two-dimensional semiconductor layer formed to cover the top surface, the vertical surface, and the lower surface, the two-dimensional semiconductor layer being formed so as to overlap the conductive thin film and / or the insulating film in a portion where the conductive thin film and / or the insulating film are present, and A source electrode provided at a portion covering the top surface of the two-dimensional semiconductor layer; a drain electrode provided at a portion covering the lower surface of the two-dimensional semiconductor layer; A transistor comprising:

2. A conductor shielding layer is further provided on the conductive thin film, An insulating layer is provided on both the front and back surfaces of the shielding layer.

2. The transistor according to claim 1 .

3. at least the top surface of the substrate is single crystal silicon carbide; The transistor according to claim 1 , wherein the conductive thin film is made of graphene.

4. 4. The transistor according to claim 3, wherein the conductive thin film of graphene has an end portion overlapping a ridge line where the top surface and the vertical surface intersect, the end portion being a single layer.

5. the substrate has an inclined surface adjacent to the top surface at an end opposite to an edge of the top surface that contacts the vertical surface and that is non-parallel to the top surface; the conductive thin film is formed from the top surface to the inclined surface, The conductive thin film on the inclined surface is a multi-layer graphene.

5. The transistor according to claim 4.

6. 3. The transistor according to claim 1, wherein the substrate is a single crystal substrate of silicon carbide or a hybrid substrate in which a single crystal layer of silicon carbide is formed on an insulator.

7. 3. The transistor of claim 1, wherein the two-dimensional semiconductor layer is formed of a material selected from the group consisting of graphene, transition metal dichalcogenides, indium oxide, boron phosphide, and boron arsenide.

8. The two-dimensional semiconductor layer is made of molybdenum disulfide (MoS ２ ), tungsten disulfide (WS ２ ), and tungsten diselenide (WSe ２ 8. The transistor according to claim 7, characterized in that it is formed from a transition metal dichalcogenide,

9. 3. The transistor according to claim 1, wherein the insulating film is made of a material selected from the group consisting of hafnium oxide, silicon carbide, zirconium oxide, erbium oxide, aluminum oxide, and silicon carbide.

10. 3. An integrated circuit comprising a plurality of transistors according to claim 1 or 2, the substrate has two vertical surfaces facing the protrusion on which the top surface is formed, an integrated circuit comprising: two of said transistors sharing one of said conductive thin films and one of said source electrodes;

11. 3. An integrated circuit comprising a plurality of transistors according to claim 1 or 2, the substrate has two vertical surfaces facing each other on both sides of one lower surface, An integrated circuit comprising: two of said transistors sharing one of said lower surfaces.

12. providing a substrate; forming a conductive thin film having 10 atomic layers or less on a flat top surface of the substrate; a step of removing the conductive thin film and an upper portion of the substrate from other portions while leaving the conductive thin film in a portion by microfabrication, thereby forming, on the substrate, a vertical surface that intersects with the top surface and extends downward from the top surface, and a lower surface vertical surface and a lower surface that are approximately parallel to the top surface and intersect with the vertical surface; depositing an insulating film so as to cover at least the vertical surface and an end portion of the conductive thin film; depositing a two-dimensional semiconductor layer so as to cover the top surface, the vertical surface, and the lower surface, and also to cover the conductive thin film and / or the insulating film in areas where the conductive thin film and / or the insulating film are present; forming a source electrode so as to overlap a portion of the two-dimensional semiconductor layer covering the conductive thin film, and forming a drain electrode so as to overlap a portion of the two-dimensional semiconductor layer covering the lower surface; A method for manufacturing a transistor comprising:

13. 13. The method of claim 12, further comprising the step of providing a shielding layer overlying the conductive thin film after forming the conductive thin film and before forming the vertical surface and the lower surface.

14. at least the top surface of the substrate is single crystal silicon carbide; The method according to claim 12 or 13, wherein in the step of forming the conductive thin film, graphene is formed as the conductive thin film on the uppermost surface of the substrate.

15. 14. The manufacturing method according to claim 12, wherein in the step of forming the conductive thin film, the graphene that is the conductive thin film is formed such that an end portion that overlaps a ridge line where the top surface and the vertical surface intersect is a single layer.

16. a step of forming an inclined surface adjacent to the top surface and non-parallel to the top surface, prior to the step of forming the conductive thin film; 16. The method of claim 15, wherein in the step of forming the conductive thin film, the conductive thin film is formed from the top surface to the inclined surface, and the conductive thin film on the inclined surface forms a multi-layer graphene.

17. 14. The method according to claim 12, wherein the substrate is a single crystal substrate of silicon carbide or a hybrid substrate in which a single crystal layer of silicon carbide is formed on an insulator.

18. 14. The method according to claim 12 or 13, wherein the two-dimensional semiconductor layer is formed of a material selected from the group consisting of graphene, transition metal dichalcogenides, indium oxide, boron phosphide, and boron arsenide.

19. The two-dimensional semiconductor layer is made of molybdenum disulfide (MoS ２ ), tungsten disulfide (WS ２ ), and tungsten diselenide (WSe ２ 20. The method according to claim 18, characterized in that the transition metal dichalcogenide is any one of the transition metal dichalcogenides.

20. 14. The method according to claim 12, wherein the insulating film is made of a material selected from the group consisting of hafnium oxide, silicon carbide, zirconium oxide, erbium oxide, aluminum oxide, and silicon carbide.

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