Backward compatibility by alteration of latency of instruction execution

Abstract

To provide a method and a system for achieving backward compatibility of a new CPU with a legacy CPU.SOLUTION: A new device executing an application on a new CPU determines whether the application is for a legacy device having a legacy CPU. When the application is for the legacy device, the new CPU executes the application by disabling a selected feature of the new CPU that is not present on the legacy CPU, or altering a latency of instruction execution of the new CPU so as to match or approximate a latency of the legacy CPU, or altering algorithmic details of operation of one or more units of the new CPU so as to match or approximate algorithmic details of operation of corresponding units of the legacy CPU.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] This application claims priority to commonly assigned U.S. Provisional Patent Application No. 14 / 810,334, filed July 27, 2015, the entire contents of which are incorporated herein by reference.

[0002] Aspects of the present disclosure relate to the execution of computer applications on a computer system. In particular, aspects of the present disclosure relate to a system or method for providing backward compatibility for applications / titles designed for older versions of a computer system. [Background technology]

[0003] Modern computer systems often use many different processors for various computing tasks. For example, a modern computer may have many central processing units (CPUs), as well as a graphics processing unit (GPU) dedicated to certain computational tasks in a graphics pipeline, or a unit dedicated to audio digital signal processing, all of which may be part of an accelerated processing unit (APU), which may include other units as well. These processors are connected to various types of memory using buses that may be internal to the APU or located externally on the computer's motherboard.

[0004] It is common for a set of applications to be written for a computer system such as a game console or a smartphone (the "legacy device"), and when a variant or more advanced version of the computer system is released (the "new device"), the applications of the legacy device should preferably run perfectly on the new device without recompilation or any modification to take into account the properties of the new device. This aspect of the new device, as contained within its hardware architecture, firmware, and operating system, is often referred to as "backwards compatibility." Summary of the Invention [Problem to be solved by the invention]

[0005] Backward compatibility is often achieved through binary compatibility, where a new device can run programs written for a legacy device. However, if the real-time behavior of a category of devices is critical to the operation of the device, as is the case for game consoles or smartphones, significant differences in the operating speed of the new device may prevent the new device from being backward compatible with the legacy device. Problems preventing backward compatibility arise when the new device is less powerful than the legacy device, and this also applies when the new device is more powerful or has different performance characteristics compared to the legacy device.

[0006] It is from this perspective that aspects of the present disclosure arise. [Means for solving the problem]

[0007] The teachings of the present disclosure can be readily understood by considering the following detailed description in conjunction with the accompanying drawings. [Brief description of the drawings]

[0008] [Figure 1] FIG. 2 is a block diagram illustrating an example of a central processing unit (CPU) core that may be configured to operate in a backward compatibility mode in accordance with an aspect of the present disclosure. [Diagram 2] FIG. 1 is a flow diagram illustrating an example of a possible process flow for operating a CPU in a backward compatibility mode according to an aspect of the present disclosure. [Diagram 3] FIG. 1 is a block diagram of a device having a CPU configured to operate in a backward compatibility mode in accordance with an aspect of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Although the following detailed description contains many specific details for purposes of illustration, one of ordinary skill in the art will appreciate that numerous variations and modifications to the following details are within the scope of the invention. Accordingly, exemplary embodiments of the invention described below are set forth without any loss of generality to, and without imposing limitations on, the claimed invention. introduction

[0010] [Introduction] Even if the CPU of the new device is binary compatible with the legacy device (i.e., capable of running programs written for the legacy device), differences in performance characteristics between the CPU of the new device and the CPU of the legacy device may cause errors in the legacy applications, resulting in the new device not being backward compatible.

[0011] If the new device's CPU is less powerful than the legacy device's CPU, many errors may occur in the legacy application due to an inability to meet real-time deadlines imposed by display timing, audio stream output, etc. If the new device's CPU is significantly more powerful than the legacy device's CPU, many errors may occur in the legacy application as a result of never having tried such high speed operation. For example, in a producer-consumer model, if a data consumer (e.g., a CPU) runs faster than expected, the data consumer may try to access data before the data producer (e.g., some other component of a computer) allows data access. Alternatively, if a data producer (e.g., a CPU) runs faster than expected, the data producer may overwrite data that is still in use by the data consumer (e.g., some other component of a computer).

[0012] In addition, because the speed at which code is executed by a CPU depends on the characteristics of the particular code being executed, the performance gains of a CPU in a new device over a legacy device may depend on the particular code being executed. This can cause problems in the producer-consumer model described above, where the producer and consumer are both CPUs but execute the code of the legacy application at relative speeds that were never matched on the legacy hardware.

[0013] [Example] Aspects of the present disclosure describe computer systems and methods that may enable a greater degree of backward compatibility with legacy computer systems.

[0014] In embodiments of the present disclosure, when executing in backward compatibility mode ("BC mode"), certain resources for the CPU are restricted and various aspects of the CPU's operation are modified.

[0015] Due to various resource limitations, the performance of the CPU in BC mode is much closer to that of the legacy CPU, resulting in fewer errors in legacy applications due to unexpected performance characteristics of the CPU.

[0016] In addition, certain features of the CPU that are not present on the legacy CPU are disabled in BC mode, the latency of instruction execution of the CPU is changed in BC mode to equal or approach that of the legacy CPU, and algorithmic details of the operation of various units of the CPU may be changed in BC mode to match or approach the algorithmic details of the operation of those units of the legacy CPU, so that the performance of the new CPU when in BC mode is much closer to that of the legacy CPU, resulting in fewer errors in legacy applications due to unexpected performance characteristics of the new CPU.

[0017] The following describes various aspects of the present disclosure relating to the general architecture of the CPU, as well as limiting certain resources, disabling features, altering latency, and modifying algorithmic details of operation when in BC mode.

[0018] Figure 1 illustrates a generic architecture of a CPU core 100. The CPU core 100 typically includes a branch prediction unit 102 that attempts to predict whether a branch will be taken, and also (in the event that the branch is taken) the target address of the branch. The more correct these predictions are, the more efficient the speculatively executed code will be, so highly accurate branch prediction is highly desirable. The branch prediction unit 102 may include highly specialized subunits such as a return address stack 104 that tracks return addresses from subroutines, an indirect target array 106 that tracks the destinations of indirect branches, and a branch target buffer 108 and associated prediction logic that tracks the past history of branches to more accurately predict the result address of the branch.

[0019] According to certain aspects of the present disclosure, in BC mode, the size of the indirect target array 106, the size of the return address stack 104, or the size of the branch target buffer 108 of the new CPU may be reduced to match or more closely approximate their respective sizes in the legacy CPU. For clarity, this reduction takes the form of reducing the available portion of the resource, such as reducing the number of calls and associated returns that can be traced by not allowing the use of a portion of the return address stack, with the full resource being available when leaving BC mode.

[0020] According to certain aspects of the present disclosure, in BC mode, the algorithmic details of the operation of the branch target buffer 108 of the new CPU, and its associated prediction logic, may be modified to match those of the legacy CPU. By way of example and not by way of limitation, if the legacy CPU is limited in its ability to track the behavior of branch instructions that are close to each other, the new CPU in BC mode may match the behavior of the legacy CPU. Or, if the legacy CPU uses a substantially different style of branch prediction logic (e.g., a saturating counter rather than an adaptive predictor), the new CPU may include the logic of the legacy CPU and enable it in BC mode.

[0021] According to certain aspects of the present disclosure, even if the branch target buffer 108 and its associated prediction logic of the new CPU included a dedicated loop predictor, the dedicated loop predictor of the new CPU may be disabled in BC mode because a dedicated loop predictor does not exist on the legacy CPU.

[0022] The CPU core 100 typically includes an instruction fetch and decode unit 110, which includes an instruction fetch unit 112, an instruction byte buffer 114, and an instruction decode unit 116. The CPU core 100 also typically includes a number of instruction-related caches and an instruction translation lookaside buffer (ITLB) 120. These may include an ITLB cache hierarchy 124 that caches virtual addresses to physical address translation information, such as page table entries and page directory entries. This information is used to translate the virtual addresses of instructions to physical addresses, allowing the instruction fetch unit 112 to load instructions from the cache hierarchy. By way of example and not limitation, program instructions may be cached according to a cache hierarchy that includes a level 1 instruction cache (L1I-cache) 122 that resides within the core, as well as other cache levels 176 that reside outside the CPU core 100, which are first searched for program instructions using the physical address of the instruction. If the instruction is not found, the instruction is loaded from the system memory 101. Depending on the architecture, there may also be a micro-op cache 126 that contains decoded instructions, as described below.

[0023] In certain aspects of the present disclosure, the size or associativity of the L1I-cache 124, micro-op cache 126, or various levels of the ITLB cache hierarchy 122 during BC mode may be altered to match or more closely approximate their respective size and associativity in the legacy CPU. By way of example and not by way of limitation, altering the size, e.g., shrinking, of the ITLB cache hierarchy 124 may involve (1) reducing the number of levels, or (2) changing the size (e.g., cache size, block size, number of blocks in a set) of one or more levels. Changing the associativity of a cache may involve, for example, operating a fully associative cache as a 4-way or 2-way cache. Aspects of the present disclosure include implementations in which the size or associativity of an instruction-related cache or ITLB is reduced, although the present disclosure is not limited to such implementations. For example, a legacy CPU may have a larger cache that is lower associative in the legacy CPU (e.g., 2-way instead of 4-way). In such cases, the new CPU may run in BC mode, with corresponding expanded cache sizes and reduced associativity to match or approximate the behavior of the caches on the legacy CPU.

[0024] Once program instructions are fetched, they are typically placed in an instruction byte buffer 114 to await processing by the instruction fetch and decode unit 110. Because decoding can be a very complex process and it is difficult to decode multiple instructions each cycle, there may be restrictions on instruction alignment or instruction type that limit the number of instructions that can be decoded in a cycle. Depending on the architecture, the decoded instructions may be placed in a micro-op cache 126 (if one exists on modern CPUs), so that the decode stage can be avoided on subsequent uses of the program instructions.

[0025] In certain aspects of the present disclosure, the algorithmic details of the operation of the instruction fetch and decode unit 110 of the new CPU during BC mode may be modified to match those of the legacy CPU. By way of example and not by way of limitation, if the legacy CPU restricts decoding of instructions by opcodes within a particular region in the instruction byte buffer 114, the new CPU may similarly restrict decoding.

[0026] In certain aspects of the present disclosure, if micro-op cache 126 is present on the new CPU and not present on the legacy CPU, then in BC mode the micro-op cache 126 of the new CPU may be invalidated.

[0027] Decoded instructions are typically passed to other units for dispatch and scheduling 130. These units may use retirement queues 132 to track the status of instructions through the rest of the CPU pipeline. Register renaming may also occur due to the limited number of general purpose and SIMD registers available on many CPU architectures. In register renaming, physical registers 140 are assigned to represent logical registers (also known as architectural registers) as they occur in the stream of instructions being executed. The physical registers 140 include a single instruction multiple data (SIMD) register bank 142 and a general purpose (GP) register bank 144 that may be much larger in size than the size of the logical registers available on a particular CPU architecture, which may result in significant performance improvements. After register renaming 134 occurs, instructions are typically placed in a scheduling queue 136 where a number of instructions may be selected for execution by an execution unit 150 each cycle (based on dependencies).

[0028] In certain aspects of the disclosure, when in BC mode, the size of a CPU's retirement queue 132, scheduling queue 136, or SIMD register bank 142 or GP register bank 144 may be reduced to match or more closely approximate their respective sizes in a legacy CPU. For clarity, this reduction takes the form of reducing the available portion of a resource, such as limiting the number of physical registers available to an application in BC mode, with the entire register bank available to the application when leaving BC mode.

[0029] Execution units 150 typically include SIMD pipes 152, which perform multiple parallel operations on multiple data fields contained in the 128-bit or larger SIMD registers contained in SIMD register bank 142, arithmetic logic units (ALUs) 154, which perform multiple logical, arithmetic, and miscellaneous operations on the GPRs contained in GP register bank 144, and address generation units (AGUs) 156, which calculate addresses where memory is to be stored or loaded. There may be multiple instances of each type of execution unit, and the instances may have different capabilities, for example a particular SIMD pipe 152 may be capable of performing floating point multiplication operations but not capable of performing floating point addition operations.

[0030] In certain aspects of the present disclosure, the available number of ALUs, AGUs, or SIMD pipes during BC mode may be reduced to match or more closely approximate the respective number of such units present on a legacy CPU.

[0031] In certain aspects of the present disclosure, the latency of instruction execution of the new CPU when in BC mode may be changed to be equal to or closer to the latency of the legacy CPU. For example, the latency of a division operation on the new CPU when in BC mode may be extended (e.g., by computing the result more slowly or by delaying the transfer of the result to a subsequent stage of the pipeline) to match or more closely approximate the latency of a division operation on the legacy CPU.

[0032] Store and load operations are typically buffered in a store queue 162 and a load queue 164, allowing many memory operations to be performed in parallel. To support memory operations, the CPU core 100 typically includes a number of data-related caches and a Data Translation Lookaside Buffer (DTLB) 170. A DTLB cache hierarchy 172 caches virtual addresses to physical address translations, such as page table entries and page directory entries, which are used to translate virtual addresses for memory operations to physical addresses so that data can be stored or loaded from system memory. Data is typically cached in a Level 1 Data Cache (L1D-Cache) 174, which resides within the core, as well as other cache levels 176, which reside outside the core 100.

[0033] In certain aspects of the disclosure, the size and associativity of the L1D-cache 174, or various levels of the DTLB cache hierarchy 172, during BC mode may be reduced to match or more closely resemble their respective sizes and associativity in a legacy CPU. In certain aspects of the disclosure, the size (e.g., the number of allowable outstanding store or load operations) of the CPU's store queue 162 or load queue 164 during BC mode may be reduced to match or more closely resemble their respective sizes in a legacy CPU.

[0034] 2 is a flow diagram illustrating an example of a possible process flow of a method according to an aspect of the disclosure. The method begins at 201, for example, by loading an application into a system having a new CPU. As shown at 210, a determination is made whether the application was designed for the new CPU or for a previous version of the system, via inspection of a software ID, software checksum, metadata associated with the software, media type, or other mechanism. Such a determination may be performed in software running on the system or in the system's hardware. Once it is determined that the loaded application is intended for the new CPU, the system may operate normally, as shown at 220. For example, the CPU may operate normally without limiting available resources, disabling features, modifying instruction execution latencies, or modifying algorithm details to match or approximate the behavior of the legacy CPU.

[0035] If it is determined that the loaded application is intended for a legacy CPU, the CPU runs in BC mode by restricting selected available resources (242), disabling selected features not present on the legacy CPU (244), modifying instruction execution latency (246), or modifying algorithm details (248), or a combination of two or more of these, to match or approximate the behavior of the legacy CPU. Examples of these possibilities are described above.

[0036] By way of example and not by way of limitation, the BC mode may be implemented by suitable configuration of the new CPU's hardware, by suitable configuration of the operating system running the CPU, or by some combination of both, to operate the CPU with limited selected resources (242). For example, as described above, in the BC mode the size of the CPU's indirect target array 106, the size of the return address stack 104, or the size of the branch target buffer 108 may be reduced to match or more closely resemble the respective sizes in the legacy CPU. By way of example and not by way of limitation, the associated hardware may be configured to allow the operating system or CPU firmware in the BC mode to reduce the size of the indirect target array 106 to match or more closely resemble the respective sizes in the legacy CPU. The following pseudocode illustrates an example of how this may be implemented: void function BC_mode_indirect_target_array_size if BC_mode is true { set indirect_target_array_size to reduced_indirect_target_array_size }

[0037] The size of the return address stack 104, or the size of the branch target buffer 108, or other available resources may also be reduced in a similar manner.

[0038] Similarly, certain hardware resources present on the new CPU but not on the legacy CPU (e.g., micro-op cache 126) may be configured to be disabled by the operating system or CPU firmware in BC mode in order to operate the CPU with selected features disabled (244), or hardware resources present on the new CPU but not on the legacy CPU may be configured to be ignored by applications in BC mode.

[0039] By way of example and not by way of limitation, to operate the CPU by modifying (246) the latency of instruction execution of the new CPU to match or approximate the latency of the legacy CPU, the hardware of execution unit 150 may be configured to add the equivalent of “non-op” instructions in BC mode to obtain the desired latency in BC mode.

[0040] By way of example and not by way of limitation, the new CPU is operated by modifying (248) algorithmic details of operation of one or more units of the new CPU. By way of example and not by way of limitation, algorithmic details of operation of the branch prediction unit 102 may be modified in BC mode. For example, as previously described, if the legacy CPU is limited in its ability to track the behavior of branch instructions close to each other, the branch prediction unit 102 may be configured in BC mode to match the behavior of the legacy CPU. Alternatively, if the legacy CPU uses a substantially different style of branch prediction logic (e.g., a saturating counter rather than an adaptive predictor), the branch prediction unit 102 of the new CPU may include the logic of the legacy CPU and enable it in BC mode. In another embodiment, algorithmic details of operation of the instruction fetch and decode unit 110, dispatch and scheduling unit 130, or execution unit 150 of the new CPU may be configured similar to the legacy logic and enabled in BC mode.

[0041] 3, an illustrative embodiment of a system 300 configured to operate in accordance with aspects of the present disclosure is depicted. According to aspects of the present disclosure, the system 300 may be an embedded system, a mobile phone, a personal computer, a tablet computer, a portable gaming device, a workstation, a gaming console, and the like.

[0042] System 300 generally includes a central processing unit (CPU) 320, which may include a CPU core and other functionality of the type depicted in Figure 1 and described above. By way of example and not limitation, CPU 320 may be part of an accelerated processing unit (APU) 310, which includes CPU 320 and a graphics processing unit (GPU) 330 on a single chip. In alternative embodiments, CPU 320 and GPU 330 may be implemented as separate hardware components on separate chips.

[0043] System 300 may also include memory 340. Memory 340 may optionally include a main memory unit accessible by CPU 320 and GPU 330. CPU 320 and GPU 330 may each include one or more processor cores, e.g., one core, two cores, four cores, eight cores, or more than eight cores. CPU 320 and GPU 330 are configured to access one or more memory units using a data bus 390, and in some implementations it may be convenient for system 300 to include two or more different buses.

[0044] The memory 340 may include one or more memory units in the form of integrated circuits providing addressable memory, such as, for example, RAM and DRAM. The memory includes executable instructions configured to implement the method of Fig. 2 upon a determination to operate the CPU 320 in BC mode when running an application originally written to run on a legacy CPU. In addition, the memory 340 may include dedicated graphics memory for temporarily storing graphics resources, graphics buffers, or other graphics data for a graphics rendering pipeline.

[0045] CPU 320 may be configured to execute CPU code, which may include an operating system (OS) 321 or an application 322 (e.g., a video game). OS 321 may be configured to perform certain functions that cause CPU 320 to operate in BC mode, as described above. The CPU code may include a graphics application programming interface (API) 324 that issues drawing commands or calls to programs executed by GPU 330 based on the state of application 322. The CPU code may also perform physics simulations and other functions. Portions of the code for one or more of OS 321, application 322, or API 324 may be stored in memory 340, a cache internal or external to the CPU, or mass storage accessible by CPU 320.

[0046] System 300 may also include well-known support functions 350 that may communicate with other components of the system, for example, via bus 390. Such support functions may include, but are not limited to, input / output (I / O) elements 352, one or more clocks 356 that may include separate clocks for the CPU and GPU, and one or more levels of cache 358 that may be external to CPU 320. System 300 may optionally include mass storage device 360, such as a disk drive, CD-ROM drive, flash memory, tape drive, or Blu-ray drive, for storing programs and / or data. In one embodiment, mass storage device 360 ​​may receive a computer-readable medium 362 that includes a legacy application originally designed to run on a system with a legacy CPU. Alternatively, legacy application 362 (or a portion thereof) may be stored in memory 340 or may be partially stored in cache 358.

[0047] The device 300 may also include a display unit 380 that presents the rendered graphics 382 prepared by the GPU 330 to a user. The device 300 may also include a user interface unit 370 that facilitates interaction between the system 100 and a user. The display unit 380 may be in the form of a flat panel display, a cathode ray tube (CRT) screen, a touch screen, a head mounted display (HMD), or other device capable of displaying text, numbers, graphical symbols, or images. The display 380 may display the rendered graphics 382 processed by the various techniques described herein. The user interface 370 may include one or more peripherals, such as a keyboard, a mouse, a joystick, a light pen, a game controller, a touch screen, and / or other devices that may be used in conjunction with a graphical user interface (GUI). In certain embodiments, for example when the application 322 includes a video game or other graphics intensive application, the state and underlying content of the graphics of the application 322 may be determined at least in part by user input through the user interface 370.

[0048] The system 300 may also include a network interface 372 that allows the device to communicate with other devices over a network. The network may be, for example, a local area network (LAN), a wide area network such as the Internet, a personal area network such as a Bluetooth network, or other types of networks. Various of the components shown and described may be implemented in hardware, software, or firmware, or some combination of two or more of these.

[0049] According to aspects of the disclosure, CPU 320 may include hardware components, such as those of CPU core 100 of FIG. 1 , that are operable in BC mode to restrict selected available resources (242), disable selected features not present on the legacy CPU (244), modify instruction execution latency (246), or modify algorithm details (248), or a combination of two or more of these, to match or approximate the behavior of a legacy CPU, as described above with respect to FIG. 2 .

[0050] Aspects of the present disclosure overcome problems related to backward compatibility that arise when a program written for a legacy system is run on a newer, more powerful system: by running the new CPU in BC mode, restricting selected available resources, disabling selected features not present on the legacy CPU, modifying instruction execution latency, or modifying algorithm details, or a combination of two or more of these, the new CPU can match or approximate the behavior of the legacy CPU.

[0051] While the above is a complete description of the preferred embodiment of the present invention, various alternatives, modifications, and equivalents may be used. Thus, the scope of the present invention should not be determined with reference to the foregoing description, but instead with reference to the appended claims along with their full scope of equivalents. Any feature described herein, whether desirable or not, may be combined with any other feature described herein, whether desirable or not. In the following claims, the indefinite article "A" or "An" refers to the quantity of one or more nouns following the article, unless otherwise noted. As used herein, in listing alternative elements, the term "or" is used in an inclusive sense unless otherwise noted, e.g., "X or Y" covers only X, only Y, or both X and Y. Two or more elements listed as alternatives may be combined together. The appended claims should not be construed as including means-plus-function limitations unless such limitations are expressly recited in a given claim using the expression "means for."

Claims

1. determining by a new device running an application on a new CPU whether the application is intended for a legacy device having a legacy CPU; if the new device determines that the application is for the legacy device, modifying the associativity of the cache on the new CPU to match or approximate the associativity of the cache on the legacy CPU and executing the application on the new CPU; The method includes:

2. 2. The method of claim 1, wherein running the application on the new CPU with an associativity of a cache on the new CPU to match or approximate an associativity of a cache on the legacy CPU comprises running the application on the new CPU with an associativity of an L1 cache on the new CPU to match or approximate an associativity of an L1 cache on the legacy CPU.

3. 2. The method of claim 1, wherein running the application on the new CPU with an associativity of a cache on the new CPU to match or approximate an associativity of a cache on the legacy CPU comprises running the application on the new CPU with an associativity of a micro-op cache on the new CPU to match or approximate an associativity of a micro-op cache on the legacy CPU.

4. 2. The method of claim 1, wherein running the application on the new CPU with cache associativity on the new CPU changed to match or approximate a cache associativity on the legacy CPU comprises running the application on the new CPU with an ITLB cache hierarchy associativity on the new CPU changed to match or approximate a cache associativity on the legacy CPU.

5. 5. The method of claim 4, wherein running the application on the new CPU by changing the associativity of an ITLB cache hierarchy on the new CPU to match or approximate the associativity of an ITLB cache hierarchy on the legacy CPU includes reducing a size of the ITLB cache hierarchy on the new CPU.

6. 6. The method of claim 5, wherein reducing a size of an ITLB cache hierarchy on the new CPU comprises reducing a number of levels of an ITLB cache hierarchy on the new CPU.

7. 6. The method of claim 5, wherein reducing a size of an ITLB cache hierarchy on the new CPU comprises resizing one or more levels of an ITLB cache hierarchy on the new CPU.

8. 8. The method of claim 7, wherein modifying a size of one or more levels of an ITLB cache hierarchy on the new CPU includes modifying a cache size, a block size, and a number of blocks in a set of an ITLB cache hierarchy on the new CPU.

9. 2. The method of claim 1, wherein running the application on the new CPU with an associativity of a cache on the new CPU to match or approximate an associativity of a cache on the legacy CPU includes operating a fully associative cache on the new CPU as a four-way cache.

10. 2. The method of claim 1, wherein running the application on the new CPU with an associativity of a cache on the new CPU to match or approximate an associativity of a cache on the legacy CPU includes operating a fully associative cache on the new CPU as a two-way cache.

11. the cache on the legacy CPU is larger and less associative than the cache on the new CPU; 2. The method of claim 1, wherein changing the associativity of a cache on the new CPU to match or approximate the associativity of a cache on the legacy CPU and running the application on the new CPU includes reducing a cache size of a cache on the new CPU and reducing the associativity of the cache on the new CPU to match or approximate a behavior of the cache on the legacy CPU.

12. 1. A system comprising a new central processing unit (CPU) configured to execute instructions of an application, the new CPU having a logic unit; the new CPU is configured to determine whether the application is for a legacy device having a legacy CPU, and when it is determined that the application is for the legacy device, change the associativity of a cache on the new CPU to match or approximate the associativity of a cache on the legacy CPU, and execute the application on the new CPU; The new CPU is configured to execute the application by modifying algorithmic details of operation of an instruction decode unit of the new CPU to match or approximate algorithmic details of operation of an instruction decode unit of the legacy CPU, thereby modifying algorithmic details of operation of one or more units of the new CPU to match or approximate algorithmic details of operation of a corresponding unit of the legacy CPU. system.

13. 13. The system of claim 12, wherein the new CPU is configured to change the associativity of an L1 cache on the new CPU to match or approximate the associativity of an L1 cache on the legacy CPU and execute the application on the new CPU by changing the associativity of the cache on the new CPU to match or approximate the associativity of the cache on the legacy CPU.

14. 13. The system of claim 12, wherein the new CPU is configured to run the application on the new CPU by changing the associativity of a micro-op cache on the new CPU to match or approximate the associativity of a micro-op cache on the legacy CPU and running the application on the new CPU, thereby changing the associativity of a cache on the new CPU to match or approximate the associativity of a cache on the legacy CPU.

15. 13. The system of claim 12, wherein the new CPU is configured to change the associativity of an ITLB cache hierarchy on the new CPU to match or approximate the associativity of an ITLB cache hierarchy on the legacy CPU and execute the application on the new CPU by changing the associativity of the cache on the new CPU to match or approximate the associativity of the cache on the legacy CPU.

16. 16. The system of claim 15, wherein the new CPU is configured to execute the application on the new CPU by reducing the size of the ITLB cache hierarchy on the new CPU to change the associativity of the ITLB cache hierarchy on the new CPU to match or approximate the associativity of the ITLB cache hierarchy on the legacy CPU.

17. 17. The system of claim 16, wherein reducing a size of an ITLB cache hierarchy on the new CPU comprises reducing a number of levels of an ITLB cache hierarchy on the new CPU.

18. 17. The system of claim 16, wherein reducing a size of the ITLB cache hierarchy on the new CPU comprises resizing one or more levels of the ITLB cache hierarchy on the new CPU.

19. 20. The system of claim 18, wherein modifying a size of one or more levels of an ITLB cache hierarchy on the new CPU includes modifying a cache size, a block size, and a number of blocks in a set of an ITLB cache hierarchy on the new CPU.

20. 13. The system of claim 12, wherein the new CPU is configured to run the application on the new CPU by operating a fully associative cache on the new CPU as a four-way cache, thereby changing the associativity of the cache on the new CPU to match or approximate the associativity of the cache on the legacy CPU.

21. 13. The system of claim 12, wherein the new CPU is configured to run the application on the new CPU by operating a fully associative cache on the new CPU as a two-way cache, thereby changing the associativity of the cache on the new CPU to match or approximate the associativity of the cache on the legacy CPU.

22. the cache on the legacy CPU is larger and less associative than the cache on the new CPU; 13. The system of claim 12, wherein the new CPU is configured to execute the application on the new CPU by changing the associativity of the cache on the new CPU to match or approximate the associativity of the cache on the legacy CPU by reducing a cache size of the cache on the new CPU and reducing the associativity of the cache on the new CPU to match or approximate the behavior of the cache on the legacy CPU.

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