Semiconductor device

Abstract

To provide a semiconductor device capable of more properly arranging a chip.SOLUTION: A semiconductor device according to an embodiment comprises a substrate, a first laminate, a second laminate, a first adhesion layer, a second adhesion layer, a first wire, and a second wire. The substrate includes a first surface. The first laminate includes a plurality of first semiconductor chips. The second laminate is positioned in a position different from the first laminate in an in-plane direction of the first surface, and includes a plurality of second semiconductor chips. The first adhesion layer is provided in the lower part of each of the plurality of first semiconductor chips. The second adhesion layer is provided in the lower part of each of the plurality of second semiconductor chips. The first wire electrically connects the first semiconductor chips and the second semiconductor chips to each other. The second wire electrically connects the substrate and the second semiconductor chips. A thickness of the first adhesion layer provided in the bottommost first semiconductor chip differs from a thicknesses of other first adhesion layers.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present embodiment relates to a semiconductor device. [Background technology]

[0002] In a package structure of a semiconductor device, a semiconductor chip having a high aspect ratio (the ratio of the width of the long side to the width of the short side) may be mounted. It may be difficult to properly arrange a semiconductor chip with a high aspect ratio in a semiconductor package. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2012-129464 A [Patent Document 2] JP 2014-53538 A [Patent Document 3] JP 2020-53655 A [Patent Document 4] International Publication No. 2022 / 034854 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor device capable of more appropriately arranging chips is provided. [Means for solving the problem]

[0005] The semiconductor device according to the present embodiment includes a substrate, a first stack, a second stack, a first adhesive layer, a second adhesive layer, a first wire, and a second wire. The substrate has a first surface. The first stack has a plurality of first semiconductor chips. The second stack is provided at different positions in the in-plane direction of the first surface from the first stack, and has a plurality of second semiconductor chips. The first adhesive layer is provided below each of the plurality of first semiconductor chips. The second adhesive layer is provided below each of the plurality of second semiconductor chips. The first wire electrically connects the first semiconductor chip and the second semiconductor chip to each other. The second wire electrically connects the substrate and the second semiconductor chip. The thickness of the first adhesive layer provided below the lowermost first semiconductor chip is different from the thicknesses of the other first adhesive layers. [Brief description of the drawings]

[0006] [Figure 1] 1 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a first embodiment. [Diagram 2] 1 is a top view showing an example of the configuration of a semiconductor device according to a first embodiment. [Diagram 3] 4 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a first comparative example of the first embodiment. FIG. [Figure 4] 10 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a second comparative example of the first embodiment. FIG. [Diagram 5] 4 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a first modified example of the first embodiment. FIG. [Figure 6] FIG. 11 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a second embodiment. [Figure 7] FIG. 11 is a top view showing an example of the configuration of a semiconductor device according to a second embodiment. [Figure 8] FIG. 11 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a first modified example of the second embodiment. [Figure 9] FIG. 13 is a top view showing an example of the configuration of a semiconductor device according to a first modified example of the second embodiment. [Figure 10] FIG. 13 is a top view showing an example of the configuration of a semiconductor device according to a second modified example of the second embodiment. [Figure 11] FIG. 13 is a top view showing an example of bonding wire connection in a second modified example of the second embodiment. [Figure 12] FIG. 11 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a third modified example of the second embodiment. [Figure 13] FIG. 11 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a fourth modified example of the second embodiment. [Figure 14] FIG. 13 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a fifth modified example of the second embodiment. [Figure 15] FIG. 13 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a sixth modified example of the second embodiment. [Figure 16] FIG. 13 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a seventh modified example of the second embodiment. [Figure 17] FIG. 13 is a cross-sectional view showing an example of the configuration of a semiconductor device according to an eighth modified example of the second embodiment. [Figure 18] FIG. 11 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a third embodiment. [Figure 19] FIG. 13 is a top view showing an example of the configuration of a semiconductor device according to a third embodiment. [Figure 20] FIG. 13 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a first modified example of the third embodiment. [Figure 21] FIG. 13 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a second modified example of the third embodiment. [Figure 22] FIG. 13 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a third modified example of the third embodiment. [Figure 23] FIG. 13 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a fourth modified example of the third embodiment. [Figure 24] FIG. 13 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a fifth modified example of the third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The present invention is not limited to this embodiment. The drawings are schematic or conceptual, and the ratio of each part is not necessarily the same as the actual one. In the specification and drawings, elements similar to those described above with respect to the previous drawings are given the same reference numerals, and detailed descriptions are omitted as appropriate.

[0008] (First embodiment) Fig. 1 is a cross-sectional view showing an example of the configuration of a semiconductor device 1 according to the first embodiment. Fig. 2 is a top view showing an example of the configuration of a semiconductor device 1 according to the first embodiment. Line AA in Fig. 2 shows a cross section corresponding to the cross-sectional view in Fig. 1.

[0009] The semiconductor device 1 includes a wiring board 10, stacked bodies S1a, S1b, S2a, and S2b, a semiconductor chip 40, bonding wires 81 and 82, and a sealing resin 91. The semiconductor device 1 is, for example, a package of a NAND type flash memory.

[0010] 1 shows an X direction and a Y direction parallel to and perpendicular to the surface of the substrate (wiring substrate 10), and a Z direction perpendicular to the surface of the substrate (wiring substrate 10). In this specification, the +Z direction is treated as the upward direction, and the -Z direction is treated as the downward direction. The -Z direction may or may not coincide with the direction of gravity.

[0011] The wiring board 10 may be a printed circuit board or an interposer including a wiring layer (not shown) and an insulating layer (not shown). For the wiring layer, a low-resistance metal such as copper (Cu), nickel (Ni) or an alloy thereof is used. For the insulating layer, an insulating material such as glass epoxy resin is used. The wiring board 10 may have a multilayer wiring structure formed by laminating a plurality of wiring layers and a plurality of insulating layers. The wiring board 10 may have a through electrode penetrating its front and back surfaces, for example, like an interposer.

[0012] A solder resist layer is provided on the wiring layer on the surface (face F10a) of the wiring board 10. The solder resist layer is also used as an insulating layer to protect the wiring layer and suppress short-circuit defects. Pads 17 and 18 are provided on the surface of the wiring board 10. The pads 17 and 18 are wiring layers exposed from the solder resist layer. The pad 17 is electrically connected to the laminate S1a. The pad 18 is electrically connected to the laminate S2b. The pads 17 and 18 are, for example, gold (Au) plated electrodes. In addition, pads (not shown) connected to a metal material 70 described later are also provided on the surface of the wiring board 10.

[0013] A solder resist layer is provided on the wiring layer on the back surface (face F10b) of the wiring board 10. The wiring layer exposed from the solder resist layer is provided with connection bumps 13. The connection bumps 13 are provided to electrically connect the wiring board 10 to other components (not shown).

[0014] The laminates S1a and S1b each have a semiconductor chip 20 and an adhesive layer 21. The adhesive layer 21 is, for example, a DAF (Die Attachment Film) or an NCP (Non Conductive Paste). The laminate S1a is a laminate in which a plurality of semiconductor chips 20 are stacked while being shifted in a direction (for example, a -X direction) perpendicular to the stacking direction (Z direction). The laminate S1b is a laminate in which a plurality of semiconductor chips 20 are stacked while being shifted in a direction (for example, a +X direction) perpendicular to the stacking direction (Z direction). The laminates S1a and S1b are provided on a surface F10a.

[0015] The semiconductor chip 20 is, for example, a memory chip including a NAND type flash memory. The semiconductor chip 20 has a semiconductor element (not shown) on its surface (upper surface, surface F20a). The semiconductor element may be, for example, a memory cell array and its peripheral circuit (CMOS (Complementary Metal Oxide Semiconductor) circuit). The memory cell array may be a three-dimensional memory cell array in which a plurality of memory cells are arranged three-dimensionally. In FIG. 1, each of the stacks S1a and S1b has the semiconductor chip 20 as two stacked memory chips. However, the number of stacked semiconductor chips may be three or more.

[0016] The laminates S2a and S2b each have a semiconductor chip 30 and an adhesive layer 31. The adhesive layer 31 is, for example, a DAF (Die Attachment Film) or an NCP (Non Conductive Paste). The laminate S2a is a laminate in which a plurality of semiconductor chips 30 are stacked while being shifted in a direction (for example, a -X direction) perpendicular to the stacking direction (Z direction). The laminate S2b is a laminate in which a plurality of semiconductor chips 30 are stacked while being shifted in a direction (for example, a +X direction) perpendicular to the stacking direction (Z direction). The laminates S2a and S2b are provided in positions in the X direction approximately parallel to the surface F10a from the position of the laminate S1 on the surface F10a.

[0017] The semiconductor chip 30 is, for example, a memory chip including a NAND type flash memory. The semiconductor chip 30 has a semiconductor element (not shown) on its surface (upper surface, surface F30a). The semiconductor element may be, for example, a memory cell array and its peripheral circuit (CMOS circuit). The memory cell array may be a three-dimensional memory cell array in which a plurality of memory cells are arranged three-dimensionally. In FIG. 1, each of the stacks S1a and S1b has the semiconductor chip 30 as two stacked memory chips. However, the number of stacked semiconductor chips may be three or more.

[0018] The semiconductor chip 40 is, for example, a controller chip that controls a memory chip. A semiconductor element (not shown) is provided on a surface F40b of the semiconductor chip 40 facing the wiring substrate 10. The semiconductor element may be, for example, a CMOS (Complementary Metal Oxide Semiconductor) circuit constituting the controller. An electrode pillar (not shown) electrically connected to the semiconductor element is provided on the surface F40b, which is the back surface (lower surface) of the semiconductor chip 40. The electrode pillar is made of, for example, a low-resistance metal material such as copper, nickel, or an alloy thereof.

[0019] The semiconductor chip 40 is provided on the face F10a. The semiconductor chip 40 is provided, for example, between the stacks S1a and S2b.

[0020] A metal material 70 is provided around the electrode pillars serving as connection bumps. The electrode pillars are electrically connected to the wiring layer exposed at the openings of the solder resist layer via the metal material 70. For the metal material 70, a low-resistance metal material such as solder, silver, copper, or the like is used. The metal material 70 electrically connects the electrode pillars of the semiconductor chip 40 and the wiring layer of the wiring board 10.

[0021] A resin layer 80 is provided in the area around the metal material 70 and in the area between the semiconductor chip 40 and the wiring substrate 10. The resin layer 80 is, for example, a hardened underfill resin, and covers and protects the periphery of the semiconductor chip 40.

[0022] The bonding wire 81 is connected to any pad of the wiring substrate 10 and the semiconductor chip 20. The bonding wire 82 is connected to any pad of the wiring substrate 10 and the semiconductor chip 30. The bonding wires 81 and 82 are, for example, gold (Au) wires. In order to connect with the bonding wires 81 and 82, the semiconductor chips 20 and 30 are stacked with a shift by the amount of the pads 20p and 30p.

[0023] Furthermore, the sealing resin 91 seals the stacked bodies S1a, S1b, S2a, and S2b, the semiconductor chip 40, and the bonding wires 81 and 82. As a result, the semiconductor device 1 is configured such that the stacked bodies S1a, S1b, S2a, and S2b and the semiconductor chip 40 are mounted on the wiring substrate 10 as one semiconductor package.

[0024] Next, the configurations of the stacked bodies S1a, S1b, S2a, and S2b and the semiconductor chip 40 will be described in detail.

[0025] 2, the semiconductor chip 20 is arranged so that the short sides are approximately parallel to the X direction and the long sides are approximately parallel to the Y direction. Therefore, the multiple semiconductor chips 20 are stacked with a shift in the short side direction of the semiconductor chip 20. The semiconductor chip 20 has an elongated shape when viewed from above. Alternatively, the short sides of the semiconductor chip 20 may be approximately parallel to the Y direction and the long sides may be approximately parallel to the X direction.

[0026] As shown in FIG. 1, the stacked bodies S1a and S1b are arranged side by side in the short side direction of the semiconductor chip 20.

[0027] Each of the stacks S1a and S1b has two stacked layers of semiconductor chips 20. The bottom semiconductor chips 20 of the stacks S1a and S1b are provided at different positions on the face F10a. The number of stacked semiconductor chips 20 may be three or more.

[0028] The multiple bonding wires 81 electrically connect the multiple semiconductor chips 20 to each other. The stacked bodies S1a and S1b are electrically connected to each other via the bonding wires 81. The bonding wires 81 connect the multiple semiconductor chips 20 to each other in a single stroke, for example.

[0029] Moreover, the thickness of the adhesive layer 21 provided under the lowest semiconductor chip 20 in the stack S1b is different from the thicknesses of the other adhesive layers 21. More specifically, the adhesive layer 21 provided under the lowest semiconductor chip 20 in the stack S1b is thicker than the other adhesive layers 21.

[0030] The adhesive layer 21 provided under the lowest semiconductor chip 20 of the stack S1b covers at least a portion of the semiconductor chip 40. This allows the stack S1b and the semiconductor chip 40 to be disposed close to each other, thereby making it possible to further reduce the package area.

[0031] The adhesive layer 21 provided under the semiconductor chip 20 at the bottom of the laminate S1b covers at least a part of the bonding wire 81 that electrically connects the semiconductor chip 20 at the bottom of the laminate S1a to the wiring board 10. This allows the laminates S1a and S1b to be disposed close to each other, thereby making it possible to further reduce the package area.

[0032] 2, the semiconductor chip 30 is arranged so that the short sides are approximately parallel to the X direction and the long sides are approximately parallel to the Y direction. Therefore, the multiple semiconductor chips 30 are stacked with a shift in the short side direction of the semiconductor chip 30. The semiconductor chip 30 has an elongated shape when viewed from above. Alternatively, the short sides of the semiconductor chip 30 may be approximately parallel to the Y direction and the long sides may be approximately parallel to the X direction.

[0033] As shown in FIG. 1, the stacked bodies S2a and S2b are arranged side by side in the direction of the short side of the semiconductor chip 30.

[0034] Each of the stacks S2a and S2b has two stacked layers of semiconductor chips 30. The bottom semiconductor chips 30 of the stacks S2a and S2b are provided at different positions on the face F10a. The number of stacked semiconductor chips 30 may be three or more.

[0035] The multiple bonding wires 82 electrically connect the multiple semiconductor chips 30 to each other. The stacked bodies S2a and S2b are electrically connected to each other via the bonding wires 82. The bonding wires 82 connect the multiple semiconductor chips 30 to each other in a single stroke, for example.

[0036] Moreover, the thickness of the adhesive layer 31 provided under the lowest semiconductor chip 30 of the stack S2a is different from the thicknesses of the other adhesive layers 31. More specifically, the adhesive layer 31 provided under the lowest semiconductor chip 30 of the stack S2a is thicker than the other adhesive layers 31.

[0037] The adhesive layer 31 provided under the semiconductor chip 30 in the lowest layer of the stack S2a covers at least a portion of the semiconductor chip 40. This allows the stack S2a and the semiconductor chip 40 to be disposed close to each other, thereby making it possible to further reduce the package area.

[0038] The adhesive layer 31 provided under the semiconductor chip 30 at the bottom of the laminate S2a covers at least a part of the bonding wire 82 that electrically connects the semiconductor chip 30 at the bottom of the laminate S2b to the wiring board 10. This allows the laminates S2a and S2b to be disposed close to each other, thereby making it possible to further reduce the package area.

[0039] As described above, according to the first embodiment, the thickness of the adhesive layer 21 provided under the lowest semiconductor chip 20 in the stack S1b is different from the thickness of the other adhesive layers 21. The thickness of the adhesive layer 31 provided under the lowest semiconductor chip 30 in the stack S2a is different from the thickness of the other adhesive layers 31. This allows the semiconductor chips 20, 30 to be more appropriately arranged in the package.

[0040] In the first embodiment, the multiple laminates S1a, S1b arranged at different positions on the face F10a are electrically connected to each other via bonding wires 81. The multiple laminates S2a, S2b arranged at different positions on the face F10a are electrically connected to each other via bonding wires 82. This avoids multi-stage stacking, and provides multiple electrically connected laminates at relatively low levels.

[0041] Also, as shown in Fig. 2, semiconductor chips 20, 30 having a high ratio of the width of the long side to the width of the short side (aspect ratio) may be used. As will be described later, even when semiconductor chips 20, 30 having a high aspect ratio are used, the semiconductor chips 20, 30 can be more appropriately arranged in a package. Note that the aspect ratio of the semiconductor chips 20, 30 shown in Fig. 2 is an example.

[0042] The ratio (aspect ratio) of the width of the long side to the width of the short side of the semiconductor chips 20 and 30 is equal to or greater than a predetermined value. The predetermined value is, for example, 3. For example, the smaller the width of the short side, the larger the aspect ratio becomes. The predetermined value may be, for example, 5 or 10.

[0043] The pads of the semiconductor chip 20 constituting the stack S1a are on the right side of the chip (one of the long sides) when viewed from above, and the pads of the semiconductor chip 20 constituting the stack S1b are on the left side of the chip (the long side closer to the stack S1a) when viewed from above.

[0044] When the same semiconductor chip is used for the stack S1a and the stack S1b, the orientation of the semiconductor chip needs to be reversed between the stack S1a and the stack S1b in order to arrange them in this way. Specifically, the chip needs to be rotated 180° in the in-plane direction.

[0045] Therefore, different chips may be used for the semiconductor chip 20 constituting the laminate S1a and the semiconductor chip 20 constituting the laminate S1b. In this case, the semiconductor chip 20 constituting the laminate S1b and the semiconductor chip 20 constituting the laminate S1a may have the same internal chip configuration but different pad arrangements.

[0046] The same applies to the laminates S2a and S2b.

[0047] The thick adhesive layers 21, 31 may be provided under at least one of the semiconductor chips 20, 30 at the bottom level.

[0048] Furthermore, the semiconductor chip 40 may be connected by wire bonding, not limited to flip chip connection, in which case the thick adhesive layers 21 and 31 bury the wires.

[0049] 3 is a cross-sectional view showing an example of the configuration of a semiconductor device 1a according to a first comparative example of the first embodiment. The first comparative example of the first embodiment differs from the first embodiment in that the thickness of the adhesive layer 21 is the same. In addition, since FIG. 3 describes the laminate S1 in detail, the configuration other than the wiring board 10 and the laminate S1 in FIG. 1 is omitted.

[0050] The semiconductor device 1a includes a stacked body S1. The stacked body S1 includes semiconductor chips 20 stacked in four levels.

[0051] The smaller the width of the short side (X direction) of the semiconductor chip 20, that is, the higher the aspect ratio, the more likely it is that the higher semiconductor chip 20 will tilt relative to the wiring substrate 10. This is because the area over which the lower semiconductor chip 20 supports the upper semiconductor chip 20 during die bonding of the semiconductor chips 20 becomes smaller. As a result, it becomes difficult to stack the semiconductor chips 20 in a higher tier.

[0052] In contrast to this, in the first embodiment, stacks S1a, S1b, S2a, and S2b, which are lower than the stack S1 in Fig. 3, are arranged side by side in the short side direction of the semiconductor chips 20 and 30. This allows the semiconductor chips 20 and 30 to be more appropriately arranged even when the semiconductor chips 20 and 30 have a high aspect ratio. Therefore, the semiconductor chips 20 and 30 can be more appropriately arranged in the package.

[0053] 4 is a cross-sectional view showing an example of the configuration of a semiconductor device 1b according to a second comparative example of the first embodiment. The second comparative example of the first embodiment differs from the first embodiment in that the aspect ratio of the semiconductor chips 20 and 30 is relatively low.

[0054] The semiconductor device 1b includes stacked bodies S1 and S2. The stacked body S1 has four stacked semiconductor chips 20. The stacked body S2 has four stacked semiconductor chips 30. The stacked body S1 is provided above the semiconductor chip 40, and the stacked body S2 is provided on the stacked body S1.

[0055] Since the aspect ratio of the semiconductor chips 20 and 30 is relatively low, the width of the short side of the semiconductor chips 20 and 30 is relatively large. The semiconductor chip 40 is embedded in the adhesive layer 21 provided below the semiconductor chip 20.

[0056] In contrast, in the first embodiment, since the aspect ratio of the semiconductor chips 20 and 30 is relatively high, the semiconductor chip 40 is not completely embedded in the adhesive layers 21 and 31. A part of the semiconductor chip 40 is covered by the multiple semiconductor chips 20 and 30. This allows the semiconductor chips 20 and 30 to be more appropriately arranged in the package.

[0057] (First Modification of the First Embodiment) 5 is a cross-sectional view showing an example of the configuration of a semiconductor device 1 according to a first modification of the first embodiment. The first modification of the first embodiment differs from the first embodiment in that a spacer 110 is provided above the semiconductor chip 40.

[0058] The semiconductor device 1 further includes a spacer 110 and an adhesive layer 111 .

[0059] The spacer 110 is provided above the semiconductor chip 40. The spacer 110 may contain, for example, Si, or may contain a resin such as PI (Polyimide).

[0060] An adhesive layer 111 is provided underneath the spacer 110 .

[0061] The stacked bodies S1b and S2a are provided on the spacer 110. The stacked bodies S1b and S2a are disposed so as to overlap at least a portion of the semiconductor chip 40 when viewed from the Z direction.

[0062] The semiconductor chip 40 is provided on the face F10a so as to be covered (embedded) in the adhesive layer 111.

[0063] As in the first modification of the first embodiment, a spacer 110 may be provided above the semiconductor chip 40. The semiconductor device 1 according to the first modification of the first embodiment can obtain the same effects as the first embodiment.

[0064] Second embodiment Fig. 6 is a cross-sectional view showing an example of the configuration of the semiconductor device 1 according to the second embodiment. Fig. 7 is a top view showing an example of the configuration of the semiconductor device 1 according to the second embodiment. Line BB in Fig. 7 indicates a cross section corresponding to the cross-sectional view in Fig. 6. The second embodiment differs from the first embodiment in that a spacer 110 is provided and the semiconductor chips 20 are arranged side by side on the spacer 110.

[0065] In the examples shown in FIGS. 6 and 7, the semiconductor chip 30 is not shown.

[0066] The semiconductor device 1 further includes a spacer 110, an adhesive layer 111, and a bonding wire 81a.

[0067] The spacer 110 is provided on the face F10a. The spacer 110 may contain, for example, Si, or may contain a resin such as PI.

[0068] An adhesive layer 111 is provided underneath the spacer 110 .

[0069] The bonding wire 81a electrically connects the semiconductor chip 20 on the left side in Fig. 6 to the wiring board 10. The semiconductor chip 20 on the left side in Fig. 6 receives a reference voltage (power supply / ground) from the bonding wire 81a.

[0070] 6 receives signals and a reference voltage (power supply / ground) from the wiring board 10 via bonding wires 81. The leftmost semiconductor chip 20 is far from the connection point between the rightmost semiconductor chip 20 and the wiring board 10. By providing bonding wires 81a capable of supplying a reference voltage, the power supply can be strengthened.

[0071] The multiple semiconductor chips 20 are provided at different positions on the spacer 110. That is, the multiple semiconductor chips 20 are arranged side by side on the spacer 110. The multiple semiconductor chips 20 are provided so as to be in contact with the upper surface (the same surface) of the spacer 110 via the adhesive layer 21.

[0072] The semiconductor chip 20 has a plurality of pads 20p to be connected to bonding wires 81.

[0073] The bonding wires 81 electrically connect the semiconductor chips 20 that are in contact with the spacer 110 to each other via the adhesive layer 21 .

[0074] The semiconductor chip 40 is provided on the face F10a so as to be covered (embedded) in the adhesive layer 111.

[0075] 7, the four semiconductor chips 20 are arranged in the same direction when viewed from the Z direction. That is, the multiple semiconductor chips 20 are arranged so that the arrangement of the pads 20p is the same when viewed from the Z direction.

[0076] As the connection bumps 13, for example, eight connection bumps 13 for I / O (Input / Output) (IO_0 to IO_7) are provided.

[0077] As described above, according to the second embodiment, the multiple semiconductor chips 20 are provided at different positions on the spacer 110. The bonding wires 81 electrically connect the multiple semiconductor chips 20 in contact with the spacer 110 to each other via the adhesive layer 21. This allows the semiconductor chips 20, 30 to be more appropriately arranged in the package.

[0078] There are cases where a semiconductor chip 20 having a relatively high aspect ratio is used, as shown in Fig. 7. As described with reference to Fig. 3, there are cases where it is difficult to stack semiconductor chips 20 having a relatively high aspect ratio in multiple layers.

[0079] In contrast, in the second embodiment, the semiconductor chips 20 are not stacked. This allows the semiconductor chips 20, 30 to be more appropriately arranged even when high aspect ratio semiconductor chips 20, 30 are used. Therefore, the semiconductor chips 20, 30 can be more appropriately arranged in the package.

[0080] In addition, since the semiconductor chips 20 are not stacked, there is no need to thin the semiconductor chips 20, 30, and the semiconductor chips 20, 30 can be made thicker. This improves pick-up performance and reduces chip cracking during pick-up, etc. Furthermore, the cross-sectional structure inside the package is simplified, which simplifies the package warpage shape. This makes it easier to control package warpage.

[0081] Furthermore, since the width of the semiconductor chip 20 in the short side direction is short, the bonding wires 81 connecting the semiconductor chips 20 can be prevented from becoming long.

[0082] (First modified example of the second embodiment) Fig. 8 is a cross-sectional view showing an example of the configuration of a semiconductor device 1 according to a first modified example of the second embodiment. Fig. 9 is a top view showing an example of the configuration of a semiconductor device 1 according to a first modified example of the second embodiment. Line CC in Fig. 9 indicates a cross section corresponding to the cross-sectional view in Fig. 8. The first modified example of the second embodiment differs from the second embodiment in that some of the semiconductor chips 20 are provided in a different orientation.

[0083] 8, some of the four semiconductor chips 20 are arranged in different orientations when viewed from the Z direction. More specifically, some of the four semiconductor chips 20 are arranged such that the arrangement of the pads 20p is inverted when viewed from the Z direction. The two left semiconductor chips 20 are arranged such that the orientation of the semiconductor chips 20 when viewed from the Z direction is rotated (inverted) by 180° compared to the two right semiconductor chips 20.

[0084] As the connection bumps 13, for example, 16 I / O connection bumps 13 are provided. In the first modified example of the second embodiment, the I / O connections are divided between the two semiconductor chips 20 on the left side and the two semiconductor chips 20 on the right side. In this case, twice as many I / O connection bumps are provided as compared with the second embodiment in which four semiconductor chips 20 are connected. This allows the semiconductor chips 20 to operate in parallel. For example, the power consumption is doubled, but the operating speed can be doubled.

[0085] As in the first modification of the second embodiment, the orientation of some of the semiconductor chips 20 may be different. The semiconductor device 1 according to the first modification of the second embodiment can obtain the same effects as the second embodiment.

[0086] (Second modified example of the second embodiment) 10 is a top view showing an example of the configuration of a semiconductor device 1 according to a second modification of the second embodiment. The second modification of the second embodiment differs from the first modification of the second embodiment in that a bonding wire 81b is provided to connect the pads 20p for the reference voltage to each other.

[0087] The semiconductor device 1 further includes a bonding wire 81b. The bonding wire 81b electrically connects the pads 20p of the semiconductor chips 20 arranged to be rotated (flipped) by 180 degrees. The bonding wire 81b is not connected to the pads 20p for signals such as I / O and DQ / DQS, but is connected to the pads 20p for a reference voltage (power supply / ground).

[0088] 10, the pads 20p for the reference voltage (ground VSS) are electrically connected via bonding wires 81b between the two left semiconductor chips 20 and the two right semiconductor chips 20. On the other hand, the pads 20p for signals (IO_0) are not connected between the two left semiconductor chips 20 and the two right semiconductor chips 20.

[0089] Fig. 11 is a top view showing an example of the connection of bonding wires 81, 81b in the second modified example of the second embodiment. Note that Fig. 11 shows pads 20p for reference voltage (power supply VEXT / ground VSS), and does not show pads 20p for signals. Although not shown, the pads 20p for signals are arranged between the pads 20p for power supply VEXT / ground VSS.

[0090] As shown in FIG. 11, depending on the arrangement of the pads 20p, it may be difficult to connect them by the bonding wire 81b. For example, the pad 20p for the power supply VEXT of the left semiconductor chip 20 may not be arranged at a position facing the pad 20p for the power supply VEXT of the right semiconductor chip 20. For example, the same chip is used for the right and left semiconductor chips 20, and the right semiconductor chip 20 is rotated 180 degrees from the left semiconductor chip 20. In this case, the pad 20p for the power supply VEXT of the right semiconductor chip 20 may not be connected by the bonding wire 81b. Similarly, the pad 20p for the ground VSS of the left semiconductor chip 20 may not be arranged at a position facing the pad 20p for the ground VSS of the right semiconductor chip 20. In this case, the pad 20p for the ground VSS of the right semiconductor chip 20 may not be connected by the bonding wire 81b.

[0091] As in the second modification of the second embodiment, a bonding wire 81b may be provided to connect the pads 20p for the reference voltage to each other. The semiconductor device 1 according to the second modification of the second embodiment can obtain the same effects as those of the first modification of the second embodiment.

[0092] (Third modified example of the second embodiment) 12 is a cross-sectional view showing an example of the configuration of a semiconductor device 1 according to a third modification of the second embodiment. The third modification of the second embodiment differs from the first modification of the second embodiment in that a member 120 is provided between the semiconductor chips 20.

[0093] 12, the orientations of some of the semiconductor chips 20 are different, but the orientations of all of the semiconductor chips 20 may be the same.

[0094] The semiconductor device 1 further includes a member 120. The member 120 is provided so as to fill the gaps between the semiconductor chips 20. The member 120 includes, for example, a resin.

[0095] As in the third modification of the second embodiment, a member 120 may be provided between the semiconductor chips 20. The semiconductor device 1 according to the third modification of the second embodiment can obtain the same effects as those of the first modification of the second embodiment.

[0096] (Fourth Modification of the Second Embodiment) 13 is a cross-sectional view showing an example of the configuration of a semiconductor device 1 according to a fourth modification of the second embodiment. The fourth modification of the second embodiment differs from the first modification of the second embodiment in that some of the semiconductor chips 20 are not diced (individuated).

[0097] Dicing is not performed between the two semiconductor chips 20 on the left side shown in Fig. 13. Similarly, dicing is not performed between the two semiconductor chips 20 on the right side. The two semiconductor chips 20 are cut out from the wafer while remaining connected, and are mounted on the wiring substrate 10. This can further simplify the process.

[0098] As in the fourth modification of the second embodiment, dicing (individualization) may not be performed between some of the semiconductor chips 20. The semiconductor device 1 according to the fourth modification of the second embodiment can obtain the same effects as those of the first modification of the second embodiment.

[0099] (Fifth Modification of the Second Embodiment) 14 is a cross-sectional view showing an example of the configuration of a semiconductor device 1 according to a fifth modification of the second embodiment. The fifth modification of the second embodiment differs from the second embodiment in that a semiconductor chip 20a is further provided on the wiring substrate 10.

[0100] The semiconductor device 1 further includes a semiconductor chip 20a. The semiconductor chip 20a is provided at a position on the face F10a different from the spacer 110. The semiconductor chip 20a is provided adjacent to the spacer 110, for example. The shape of the semiconductor chip 20a is approximately the same as the shape of the semiconductor chip 20, for example.

[0101] The bonding wires 81 electrically connect the semiconductor chip 20, which is in contact with the spacer 110 via the adhesive layer 21, to the semiconductor chip 20a.

[0102] Furthermore, since the width in the short side direction of the semiconductor chip 20a is short, it is possible to prevent the bonding wires 81 connecting the semiconductor chip 20 and the semiconductor chip 20a from becoming long.

[0103] As in the fifth modification of the second embodiment, a semiconductor chip 20a may be further provided on the wiring substrate 10. The semiconductor device 1 according to the fifth modification of the second embodiment can obtain the same effects as the second embodiment.

[0104] (Sixth Modification of the Second Embodiment) 15 is a cross-sectional view showing an example of the configuration of a semiconductor device 1 according to a sixth modification of the second embodiment. The sixth modification of the second embodiment differs from the fifth modification of the second embodiment in that the semiconductor chip 20a is thicker.

[0105] The height of the upper surface of the semiconductor chip 20a is approximately the same as the height of the upper surface of the semiconductor chip 20. This allows the lengths of the bonding wires 81 connecting the semiconductor chips 20 and 20a and the bonding wires 81 connecting the semiconductor chips 20 to each other to be approximately the same.

[0106] The semiconductor chip 20a may be thick, as in the sixth modification of the second embodiment. The semiconductor device 1 according to the sixth modification of the second embodiment can obtain the same effects as those of the fifth modification of the second embodiment.

[0107] (Seventh Modification of the Second Embodiment) 16 is a cross-sectional view showing an example of the configuration of a semiconductor device 1 according to a seventh modification of the second embodiment. The seventh modification of the second embodiment differs from the sixth modification of the second embodiment in that no bonding wire 81a is provided.

[0108] The bonding wire 81a does not have to be provided as in the seventh modification of the second embodiment. The semiconductor device 1 according to the seventh modification of the second embodiment can obtain the same effects as those of the sixth modification of the second embodiment.

[0109] (Eighth Modification of the Second Embodiment) 17 is a cross-sectional view showing an example of the configuration of a semiconductor device 1 according to an eighth modification of the second embodiment. The eighth modification of the second embodiment differs from the first modification of the second embodiment in that a semiconductor chip 20b is further provided on the semiconductor chip 20.

[0110] The semiconductor device 1 further includes a semiconductor chip 20b. The semiconductor chip 20b is provided on the semiconductor chip 20. The semiconductor chip 20b is disposed, for example, so as to straddle the multiple semiconductor chips 20. The shape of the semiconductor chip 20b is, for example, substantially the same as the shape of the semiconductor chip 20.

[0111] The bonding wires 81 electrically connect the semiconductor chip 20 and the semiconductor chip 20b.

[0112] As in the eighth modification of the second embodiment, a semiconductor chip 20b may be further provided on the semiconductor chip 20. The semiconductor device 1 according to the eighth modification of the second embodiment can obtain the same effects as those of the first modification of the second embodiment.

[0113] Third embodiment Fig. 18 is a cross-sectional view showing an example of the configuration of the semiconductor device 1 according to the third embodiment. Fig. 19 is a top view showing an example of the configuration of the semiconductor device 1 according to the third embodiment. The line DD in Fig. 19 shows a cross section corresponding to the cross-sectional view in Fig. 18.

[0114] The semiconductor device 1 includes stacked bodies S1 and S2. The stacked body S1 has four stacked semiconductor chips 20. The stacked body S2 has four stacked semiconductor chips 30. The stacked bodies S1 and S2 are provided at different positions on the face F10a. More specifically, the bottom semiconductor chips 20 and 30 are provided at different positions on the face F10a.

[0115] The semiconductor chip 40 is provided on the face F10a so that at least a portion of the semiconductor chip 40 is covered with the multiple adhesive layers 21. In the example shown in Fig. 19, since the aspect ratios of the semiconductor chips 20 and 30 are relatively high, the long sides (X direction) of the semiconductor chip 40 protrude in the X direction from both sides of the stacked body S1 when viewed from the Z direction.

[0116] The adhesive layers 21, 31 provided below the lowest semiconductor chips 20, 30 that cover the semiconductor chip 40 may be thicker and made of a different material than the other adhesive layers 21, 31. The adhesive layers 21, 31 provided below the lowest semiconductor chips 20, 30 are preferably soft, for example, so as to easily cover the semiconductor chip 40.

[0117] As described above, according to the third embodiment, the semiconductor chip 40 is provided on the face F10a so that at least a portion of the semiconductor chip 40 is covered with the multiple adhesive layers 21, 31. This allows the semiconductor chips 20, 30 to be more appropriately arranged in the package. In addition, the package area can be made smaller.

[0118] The semiconductor chip 40 is rectangular when viewed from the Z direction. A rectangle has a longer perimeter than a square for the same area. Therefore, when the semiconductor chip 40 is connected to the wiring board 10 by wire bonding, it is preferable that the semiconductor chip 40 is rectangular when viewed from the Z direction.

[0119] As described with reference to FIG. 4, when the aspect ratio of the semiconductor chip 20 is relatively low, the semiconductor chip 40 is embedded by the adhesive layer 21 provided under the semiconductor chip 20.

[0120] In contrast, in the third embodiment, since the aspect ratios of the semiconductor chips 20 and 30 are relatively high, a portion of the semiconductor chip 40 is covered by the multiple stacked bodies S1 and S2. This allows the semiconductor chips 20 and 30 to be more appropriately arranged in the package.

[0121] (First modified example of the third embodiment) 20 is a cross-sectional view showing an example of the configuration of a semiconductor device 1 according to a first modification of the third embodiment. The first modification of the third embodiment differs from the third embodiment in that the width of the long side of the semiconductor chip 40 is different.

[0122] In the example shown in FIG. 20, the long sides (X direction) of the semiconductor chip 40 protrude in the X direction from both sides of the stacks S1 and S2 when viewed from the Z direction.

[0123] As in the first modification of the third embodiment, the width of the long side of the semiconductor chip 40 may be different. The semiconductor device 1 according to the first modification of the third embodiment can obtain the same effects as the third embodiment.

[0124] (Second modified example of the third embodiment) 21 is a cross-sectional view showing an example of the configuration of a semiconductor device 1 according to a second modification of the third embodiment. The second modification of the third embodiment differs from the third embodiment in that semiconductor chips 20c and 30c are further provided on the wiring substrate 10.

[0125] In the example shown in FIG. 21, the semiconductor chips 20 and 30 are each provided in one stage.

[0126] The semiconductor device 1 further includes semiconductor chips 20c and 30c. The semiconductor chips 20c and 30c are provided at positions on the face F10a different from the semiconductor chips 20, 30 and 40. The shapes of the semiconductor chips 20c and 30c are substantially the same as the shapes of the semiconductor chips 20 and 30, for example.

[0127] The semiconductor chip 20c is electrically connected to the semiconductor chip 20 via bonding wires 81. The semiconductor chip 20c is provided, for example, adjacent to the semiconductor chip 20. Since the aspect ratios of the semiconductor chips 20 and 20c are relatively high, it is easy to arrange the semiconductor chips 20 and 20c side by side.

[0128] The semiconductor chip 30c is electrically connected to the semiconductor chip 30 via bonding wires 82. The semiconductor chip 30c is provided, for example, adjacent to the semiconductor chip 30. Since the aspect ratios of the semiconductor chips 30 and 30c are relatively high, it is easy to arrange the semiconductor chips 30 and 30c side by side.

[0129] In addition, since the width of the semiconductor chip 20c in the short side direction is short, it is possible to prevent the bonding wire 81 connecting between the semiconductor chip 20 and the semiconductor chip 20c from becoming long. Since the width of the semiconductor chip 30c in the short side direction is short, it is possible to prevent the bonding wire 82 connecting between the semiconductor chip 30 and the semiconductor chip 30c from becoming long.

[0130] As in the second modification of the third embodiment, semiconductor chips 20c, 30c may be further provided on the wiring substrate 10. The semiconductor device 1 according to the second modification of the third embodiment can obtain the same effects as the third embodiment.

[0131] (Third modified example of the third embodiment) 22 is a cross-sectional view showing an example of the configuration of a semiconductor device 1 according to a third modified example of the third embodiment. The third modified example of the third embodiment differs from the second modified example of the third embodiment in that the semiconductor chips 20 and 30 are stacked. That is, the third modified example of the third embodiment is also a combination of the third embodiment and the second modified example of the third embodiment.

[0132] 22, the semiconductor chip 20c is electrically connected to the bottom semiconductor chip 20 via a bonding wire 81. The semiconductor chip 30c is electrically connected to the bottom semiconductor chip 30 via a bonding wire 82.

[0133] As in the third modification of the third embodiment, the semiconductor chips 20 and 30 may be stacked. The semiconductor device 1 according to the third modification of the third embodiment can obtain the same effects as those of the second modification of the third embodiment.

[0134] (Fourth Modification of the Third Embodiment) 23 is a cross-sectional view showing an example of the configuration of a semiconductor device 1 according to a fourth modification of the third embodiment. The fourth modification of the third embodiment differs from the third modification of the third embodiment in that the semiconductor chips 20c and 30c are stacked.

[0135] 23, two tiers of semiconductor chips 20, 20a, 30, and 30a are provided. The second tier semiconductor chip 20c is electrically connected to the bottom tier semiconductor chip 20 via a bonding wire 81. The second tier semiconductor chip 30c is electrically connected to the bottom tier semiconductor chip 30 via a bonding wire 82.

[0136] As in the fourth modification of the third embodiment, the semiconductor chips 20c and 30c may be stacked. The semiconductor device 1 according to the fourth modification of the third embodiment can obtain the same effects as those of the third modification of the third embodiment.

[0137] (Fifth Modification of the Third Embodiment) 24 is a cross-sectional view showing an example of the configuration of a semiconductor device 1 according to a fifth modification of the third embodiment. The fifth modification of the third embodiment differs from the third embodiment in that the number of semiconductor chips 20, 30 covering the semiconductor chip 40 is different.

[0138] The semiconductor device 1 includes stacked bodies S1a, S1b, S2a, and S2b. The stacked bodies S1a, S1b, S2a, and S2b are provided at different positions on the face F10a.

[0139] Each of the stacked bodies S1a and S1b has two stacked levels of semiconductor chips 20. The stacked bodies S1a and S1b are electrically connected to each other via bonding wires 81.

[0140] Each of the stacked bodies S2a and S2b has two stacked levels of semiconductor chips 30. The stacked bodies S2a and S2b are electrically connected to each other via bonding wires .

[0141] The semiconductor chip 40 is provided on the face F10a so that at least a portion of the semiconductor chip 40 is covered by the adhesive layers 21 and 31 of the stacks S1a, S1b, S2a and S2b.

[0142] As in the fifth modified example of the third embodiment, the number of semiconductor chips 20, 30 covering the semiconductor chip 40 may be changed. The semiconductor device 1 according to the fifth modified example of the third embodiment can obtain the same effects as the third embodiment.

[0143] In the above embodiment, it is possible to appropriately arrange a semiconductor chip having an aspect ratio of 3 or more and less than 5. It is possible to appropriately arrange a semiconductor chip having an aspect ratio of 5 or more and less than 10. It is possible to appropriately arrange a semiconductor chip having an aspect ratio of 10 or more and less than 15.

[0144] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and spirit of the invention. [Explanation of symbols]

[0145] 1 semiconductor device, 10 wiring board, 20 semiconductor chip, 20a semiconductor chip, 20b semiconductor chip, semiconductor chip 20c, 20p pad, 21 adhesive layer, 30 semiconductor chip, 30p pad, 31 adhesive layer, 40 semiconductor chip, 81 bonding wire, 82 bonding wire, 110 spacer, 111 adhesive layer, F10a surface, S1 laminate, S2 laminate

Claims

1. a substrate having a first surface; a first stack having a plurality of first semiconductor chips; a second stack provided at a different position from the first stack in an in-plane direction of the first surface, the second stack having a plurality of second semiconductor chips; a first adhesive layer provided under each of the first semiconductor chips; a second adhesive layer provided under each of the second semiconductor chips; a first wire electrically connecting the first semiconductor chip and the second semiconductor chip to each other; a second wire electrically connecting the substrate and the second semiconductor chip; Equipped with A semiconductor device, wherein the thickness of the first adhesive layer provided under the first semiconductor chip in the lowest stage is different from the thicknesses of the other first adhesive layers.

2. a third semiconductor chip provided on the first surface; The semiconductor device according to claim 1 , wherein the first adhesive layer, which has a thickness different from a thickness of the other first adhesive layers, covers at least a portion of the third semiconductor chip.

3. The semiconductor device according to claim 1 , wherein the first adhesive layer, which has a thickness different from a thickness of the other first adhesive layers, covers at least a portion of the second wire.

4. When viewed in a direction substantially perpendicular to the first surface, the first semiconductor chip and the second semiconductor chip have an elongated shape, The first semiconductor chip has a plurality of pads arranged along one of two long sides, a plurality of pads provided on the second semiconductor chip are provided along one of two long sides which is closer to the first semiconductor chip; The semiconductor device according to claim 1 .

5. a substrate having a first surface; A spacer provided on the first surface; a first semiconductor chip provided on the spacer; a second semiconductor chip provided on the spacer so as not to overlap the first semiconductor chip when viewed in a direction substantially perpendicular to the first surface; a first adhesive layer provided under the first semiconductor chip; a second adhesive layer provided under the second semiconductor chip; a third adhesive layer provided under the spacer; a third semiconductor chip provided on the first surface so as to be covered with the third adhesive layer; a first wire electrically connecting at least one of the first semiconductor chip and the second semiconductor chip to the substrate; A semiconductor device comprising:

6. the first semiconductor chip has a plurality of first pads connected to the first wires or to second wires that electrically connect the first semiconductor chip and the second semiconductor chip; the second semiconductor chip has a plurality of second pads connected to the first wires or the second wires; 6. The semiconductor device according to claim 5, wherein, when viewed from a direction approximately perpendicular to the first surface, the first semiconductor chip has an elongated shape, and the plurality of first pads are provided along one of two long sides, and the second semiconductor chip has an elongated shape, and the plurality of second pads are provided along the long side of the two long sides that is farther from the first semiconductor chip.

7. the first semiconductor chip has a plurality of first pads connected to the first wires or to second wires that electrically connect the first semiconductor chip and the second semiconductor chip; the second semiconductor chip has a plurality of second pads connected to the first wires or the second wires; When viewed in a direction substantially perpendicular to the first surface, the first semiconductor chip has an elongated shape, and the first pads are provided along one of two long sides of the first semiconductor chip.

6. The semiconductor device according to claim 5, wherein the second semiconductor chip has an elongated shape, and the second pads are provided along one of two long sides that is closer to the first semiconductor chip.

8. a fourth semiconductor chip provided on the first surface so as not to overlap the spacer when viewed from a direction substantially perpendicular to the first surface; a third wire electrically connecting the first semiconductor chip, which is in contact with the spacer via the first adhesive layer, to the fourth semiconductor chip; The semiconductor device according to claim 5 , further comprising:

9. a substrate having a first surface; a plurality of first semiconductor chips provided on the first surface; a plurality of first adhesive layers provided under the respective first semiconductor chips; a second semiconductor chip provided on the first surface such that at least a portion of the second semiconductor chip is covered by at least one of the first adhesive layers; A semiconductor device comprising:

10. 10. The semiconductor device according to claim 9, further comprising a fifth semiconductor chip provided on the first surface so as not to overlap with the first semiconductor chip and the second semiconductor chip when viewed from a direction approximately perpendicular to the first surface, and electrically connected to the first semiconductor chip via a wire.

11. 11 . The semiconductor device according to claim 1 , wherein a ratio of a width of a long side to a width of a short side of the first semiconductor chip is 3 or more and less than 5.

12. 11 . The semiconductor device according to claim 1 , wherein a ratio of a width of a long side to a width of a short side of the first semiconductor chip is 5 or more and less than 10.

13. 11 . The semiconductor device according to claim 1 , wherein a ratio of a width of a long side to a width of a short side of the first semiconductor chip is equal to or greater than 10 and less than 15.

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