Memory system

Abstract

To realize a memory system with which it is possible to efficiently execute time-out processing on numerous received commands.SOLUTION: A controller of the memory system manages an extension pointer including a pointer indicating a slot in which a next command is stored and a cycle counter which is updated in response to an event that the pointer is updated to a value smaller than the current value. The controller identifies a first time range in which a terminal time matches a time preceding the current time by a specific time each time a first time elapses, and acquires an extension pointer stored in a first entry corresponding to the first time range among a plurality of entries. The controller identifies one or more commands stored in a first queue within the first time range by using the first extension pointer. The controller aborts the identified one or more commands.SELECTED DRAWING: Figure 17

Description

[Technical field]

[0001] SUMMARY OF THE DISCLOSURE Embodiments of the present invention relate to a memory system comprising a non-volatile memory. [Background technology]

[0002] In recent years, memory systems equipped with nonvolatile memories have become widespread. As one of such memory systems, for example, a solid-state drive (SSD) equipped with a nonvolatile memory such as a NAND flash memory and a controller that controls the nonvolatile memory is known.

[0003] A controller of the memory system controls the memory system based on a command issued and received from an external host. The memory system executes a timeout process to abort a command that has been issued for a period of time that exceeds a predetermined period of time.

[0004] In a memory system capable of receiving a large number of commands, a technique is required that can efficiently execute such timeout processing. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] U.S. Pat. No. 10,860,511 [Patent Document 2] US Patent Application Publication No. 2022 / 0113909 [Patent Document 3] US Patent Application Publication No. 2022 / 0350536 Summary of the Invention [Problem to be solved by the invention]

[0006] An object of the present invention is to provide a memory system capable of efficiently executing timeout processing for a large number of received commands. [Means for solving the problem]

[0007] According to an embodiment, a memory system includes a memory and a controller. The controller controls the memory. The memory system is connectable to an external host. The controller is capable of executing a process according to a command received from the host via a first queue including a plurality of slots each capable of storing a command. The controller manages an extended pointer including a pointer indicating a slot in which a command is to be stored next among the plurality of slots, and a cycle counter that is updated in response to the pointer being updated to a value smaller than a current value. The controller manages a first table including a plurality of entries, each of which corresponds to one of a plurality of continuous time ranges in units of a first time. The controller selects one of the plurality of entries each time the first time elapses. The controller stores an extended pointer including a pointer indicating a slot in which a command is to be stored next among the plurality of slots, and a cycle counter in the selected entry. Each time the first time elapses, the controller specifies a first time range whose end time coincides with a time a specific time before the current time. The controller obtains an extension pointer stored in a first entry of the plurality of entries that corresponds to the first time range. The controller identifies one or more commands stored in the first queue during the first time range using the first extension pointer. The controller aborts the identified one or more commands. [Brief description of the drawings]

[0008] [Figure 1] 1 is a block diagram showing an example of the configuration of an information processing system including a memory system according to an embodiment. [Diagram 2] 1 is a diagram showing an example of a plurality of states of a submission queue used in an information processing system including a memory system according to an embodiment. [Diagram 3] 1 is a diagram showing the flow of command processing executed in an information processing system including a memory system according to an embodiment. [Figure 4] 1A and 1B are diagrams showing examples of time slots used in a memory system according to an embodiment. [Diagram 5] 1 is a diagram showing an example of an extended pointer used in a memory system according to an embodiment; [Figure 6] 1 is a diagram showing an example of a first state of a virtual submission queue managed in a memory system according to an embodiment. [Figure 7] 11 is a diagram showing an example of a second state of a virtual submission queue managed in the memory system according to the embodiment. FIG. [Figure 8] 13 is a diagram showing an example of a third state of a virtual submission queue managed in the memory system according to the embodiment. FIG. [Figure 9] 13 is a diagram showing an example of a fourth state of a virtual submission queue managed in the memory system according to the embodiment. FIG. [Figure 10] 1A is a diagram showing a first example of comparing extension pointers in a virtual submission queue managed in a memory system according to an embodiment. FIG. [Figure 11] 11 is a diagram showing a second example of comparing extension pointers in a virtual submission queue managed in the memory system according to the embodiment. FIG. [Figure 12] 1 is a diagram showing an example of the configuration of a fetch command management table used in the memory system according to the embodiment. [Figure 13] 1 is a diagram showing an example of the configuration of a time slot management table used in the memory system according to the embodiment; [Figure 14] 1 is a diagram showing an example of a first state of a time slot management table in which a plurality of extension pointers are stored in a memory system according to an embodiment. FIG. [Figure 15] 11 is a diagram showing an example of a second state of the time slot management table in which a plurality of extension pointers are stored in the memory system according to the embodiment. FIG. [Figure 16] 11 is a diagram showing a modified example of the fetch command management table used in the memory system according to the embodiment. [Figure 17] 1 is a diagram showing an example of a relationship between a virtual submission queue managed in a memory system according to an embodiment and a plurality of time slots. [Figure 18] 1 is a diagram showing an example of management of issued commands in a memory system according to an embodiment. [Figure 19] 11A and 11B are diagrams showing an example of timing of a timeout process in the memory system according to the embodiment. [Figure 20] 11 is a sequence diagram showing an example of a procedure of command processing executed in the memory system and the host according to the embodiment. [Figure 21] 11 is a flowchart showing an example of a procedure for updating a submission queue extension tail pointer executed in the memory system according to the embodiment. [Figure 22] 11 is a flowchart showing an example of a procedure for a process of recording a submission queue extension tail pointer executed in a memory system according to an embodiment. [Figure 23] 1 is a flowchart showing a first example of a procedure of a timeout process executed in the memory system according to the embodiment. [Figure 24] 11 is a flowchart showing a second example of a procedure of a timeout process executed in the memory system according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment will be described with reference to the drawings.

[0010] 1 is a block diagram showing an example of the configuration of an information processing system 1 including a memory system according to an embodiment. The information processing system 1 includes a host (host device) 2 and a memory system 3.

[0011] The host 2 is an information processing device. The host 2 is, for example, a personal computer, a server computer, or a mobile device. The host 2 accesses the memory system 3. Specifically, the host 2 issues a write command to the memory system 3, which is a command for writing data. The host 2 also issues a read command to the memory system 3, which is a command for reading data. Furthermore, the host 2 also issues an admin command to the memory system 3, which is a command for managing the memory system 3. The host 2 may also issue other types of commands to the memory system 3 when accessing the memory system 3.

[0012] The memory system 3 is a storage device connectable to the host 2. The memory system 3 is realized, for example, as a solid-state drive (SSD). The memory system 3 includes a non-volatile memory. The memory system 3 is capable of writing data to the internal non-volatile memory. The memory system 3 is also capable of reading data from the internal non-volatile memory.

[0013] Communication between the memory system 3 and the host 2 is performed via a bus 10. The bus 10 is a transmission line that connects the host 2 and the memory system 3. The bus 10 is, for example, a PCI express (registered trademark) (PCIe (registered trademark)) bus. Via this bus, the host 2 can read and write to the RAM 411 of the memory system 3, and the memory system 3 can read and write to the RAM 22 of the host 2.

[0014] As a standard of a logical interface for connecting the host 2 and the memory system 3, for example, NVM express TM (NVMe TM) standard may be used. In the NVMe standard interface, communication between the host 2 and the memory system 3 is performed using a pair of queues including at least one submission queue (SQ) and a completion queue (CQ) associated with the at least one submission queue (SQ). This pair of queues is called a submission queue / completion queue pair (SQ / CQ pair). Also, one completion queue may correspond to multiple submission queues.

[0015] Next, the configuration of the host 2 will be described.

[0016] The host 2 includes a CPU 21, a RAM 22, and a memory interface (memory I / F) 23. The CPU 21, the RAM 22, and the memory I / F 23 are interconnected via an internal bus 20. The memory interface (memory I / F) 23 may also be called a root port.

[0017] The CPU 21 is, for example, a processor. The CPU 21 executes software (host software) loaded into the RAM 22 from the memory system 3 or another storage device connected to the host 2. The host software includes, for example, an operating system, a file system, and an application program.

[0018] The RAM 22 is, for example, a volatile memory. The RAM 22 is also referred to as a main memory, a system memory, or a host memory. The RAM 22 is, for example, a dynamic random access memory (DRAM). A part of the storage area of ​​the RAM 22 is used to store submission queues (SQ) 221-0, ..., 221-v and completion queues (CQ) 222-0, ..., 222-w. In addition, another part of the storage area of ​​the RAM 22 is used to store submission queue host head pointers (SQHHP) 223-0, ..., 223-v, submission queue host tail pointers (SQHTP) 224-0, ..., 224-v, and completion queue host head pointers (CQHHP) 225-0, ..., 225-w.

[0019] Each of the submission queues 221-0, ..., 221-v is a queue for storing a command issued by the host 2 to the memory system 3. That is, each of the submission queues 221-0, ..., 221-v is a queue used by the host 2 to issue a command (input / output (I / O) command, admin command) to the memory system 3. The I / O command is a command for writing data to the nonvolatile memory of the memory system 3 or reading data from the nonvolatile memory. Each of the submission queues 221-0, ..., 221-v includes a plurality of slots. Each of the plurality of slots can store one command. In addition to the command, a command identifier (CID) that allows the host 2 to identify the issued command by combining it with a submission queue ID that identifies the submission queue can also be stored. The host 2 creates a submission queue in the RAM 22 of the host 2. The host 2 also issues a submission queue create command to the memory system 3. A submission queue (SQ) base address indicating the storage location in the RAM 22 where each of the submission queues is created, the size of each of the created submission queues, and an identifier (completion queue ID) of a completion queue associated with each of these submission queues, i.e., where a completion notification of a command issued using this submission queue is written, are notified to the memory system 3 by a submission queue create command. The SQ base address is, for example, an address indicating a storage location on the RAM 22 corresponding to the first slot of multiple slots included in the corresponding submission queue. The size of the submission queue is, for example, the number of multiple slots included in the corresponding submission queue. The host 2 manages the submission queues 221-0, ..., 221-v using the SQHHP 223-0, ..., 223-v and the SQHTP 224-0, ..., 224-v. For example, submission queue 221-n corresponds to SQHHP 223-n and SQHTP 224-n (where n is any integer from 0 to v).The initial value of SQHHP223-n indicates the head of the queue, but thereafter, it is a latest pointer that indicates the slot notified by the memory system 3 to the host 2, and the pointer indicates the next slot in which the latest fetched command is stored. SQHTP224-n indicates an empty slot in which a new command will be stored next among the multiple slots of the submission queue 221-n. Hereinafter, a case will be described in which the host 2 issues an I / O command to the memory system 3 using a submission queue used to issue an I / O command. The "command" described below is, for example, an I / O command. However, in this embodiment, the same process can be performed even if an admin command or another type of command is issued from the host 2 to the memory system 3 instead of an I / O command.

[0020] The completion queues 222-0, ..., 222-w are queues for storing completion responses indicating the results of command processing. That is, the completion queues 222-0, ..., 222-w are used to receive completion responses from the memory system 3. The completion response includes the ID of the submission queue to which the corresponding command was issued, the CID of the command, and a status indicating that the command processing was successful or failed. The completion response is also referred to as a command completion, a command completion notification, or a command completion. Each of the completion queues 222-0, ..., 222-w includes a plurality of slots. Each of the plurality of slots is capable of storing one completion response. The host 2 creates a completion queue in the RAM 22 of the host 2. The host 2 also issues a completion queue create command to the memory system 3. A completion queue (CQ) base address indicating the storage location in the RAM 22 where the completion queue is created, the size of the completion queue, etc. are notified to the memory system 3 by a completion queue create command. The CQ base address is an address indicating a storage location on the RAM 22 corresponding to the first slot of the multiple slots included in the corresponding completion queue. The size of the completion queue is the number of multiple slots included in the completion queue. The host 2 uses the CQHHP 225-0, ..., 225-w to manage the completion queues 222-0, ..., 222-w. For example, the completion queue 222-m corresponds to the CQHHP 225-m (where m is any integer from 0 to w). The CQHHP 225-m is a pointer indicating the slot in which the next completion response to be processed is stored among the multiple slots of the completion queue 222-m. In addition, the host 2 does not directly receive the completion queue Tail Pointer from the memory system 3. Instead, each slot in the completion queue has a field called a Phase Tag Bit, and the memory system 3 inverts the value of this bit from the value before the overwrite every time it overwrites a slot.For example, if the initial state is zero, then this bit is set to 1 when writing completion information to the completion queue. The host 2 reads the value of this bit for each slot in turn, and can determine that the slot where this bit has changed to 0 is the slot indicated by the Tail Pointer of that completion queue. Once the memory system 3 has written to the last slot in the completion queue, it then writes to the first slot in the queue, but this time the Phase Tag Bit is set to 0. After the host 2 has also completed the completion process down to the end of the completion queue, it moves the read destination to the beginning of the queue, and can determine that the slot where the value of this bit has changed to 1 is the slot indicated by the Tail Pointer of that completion queue.

[0021] That is, the memory system 3 inverts the value of the Phase Tag Bit to be written each time the write destination moves to the top of the completion queue. The host 2 also inverts the value of the Phase Tag Bit to be compared each time the read destination moves to the top of the completion queue.

[0022] The memory interface 23 is a communication interface circuit that executes communication with the memory system 3. The memory interface 23 is realized by, for example, a PCIe controller.

[0023] Next, the internal configuration of the memory system 3 will be described. In the following, it is assumed that the nonvolatile memory included in the memory system 3 is realized by a NAND type flash memory. Note that the NAND type flash memory may be other flash memories or other nonvolatile memories such as MRAM, ReRAM, FeRAM, and phase change memory.

[0024] The memory system 3 includes a controller 4 and a non-volatile memory 5 .

[0025] The controller 4 is a memory controller. The controller 4 is a control circuit such as a System-on-a-Chip (SoC). The controller 4 is electrically connected to the nonvolatile memory 5. The controller 4 processes each I / O command received from the host 2 to execute a read process for reading data from the nonvolatile memory 5 and a write process for writing data to the nonvolatile memory 5. For example, a Toggle interface or an Open NAND Flash Interface (ONFI) is used as a physical interface connecting the controller 4 and the nonvolatile memory 5. The functions of each part of the controller 4 can be realized by dedicated hardware, a processor that executes a program, or a combination of the dedicated hardware and the processor.

[0026] The nonvolatile memory 5 may be a two-dimensional flash memory or a three-dimensional flash memory. The nonvolatile memory 5 includes a plurality of blocks. Each of the plurality of blocks is the minimum unit of a data erase operation. Each of the plurality of blocks is also referred to as a memory block or a physical block. Each of the plurality of blocks includes a plurality of pages. Each of the plurality of pages is each unit of a data write operation and a data read operation. A page includes a set of memory cells connected to the same word line. A page is also referred to as a physical page.

[0027] The non-volatile memory 5 includes a plurality of memory chips 51-0, ..., 51-y. The memory chips are also called dies, memory dies, flash dies, or flash chips. Each of these memory chips is realized as a NAND-type flash memory chip.

[0028] Next, the internal configuration of the controller 4 will be described. The controller 4 includes, for example, a host interface (host I / F) 41, a CPU 42, a timer 43, a NAND interface (NAND I / F) 44, a cycle counter control circuit 45, a static RAM (SRAM) 46, and a dynamic RAM (DRAM) 47. The host I / F 41, the CPU 42, the timer 43, the NAND I / F 44, the cycle counter control circuit 45, the SRAM 46, and the DRAM 47 are interconnected via an internal bus 40.

[0029] The host interface 41 is a communication interface circuit that executes communication with the host 2. The host interface 41 executes communication with the host 2, for example, via the memory interface 23 of the host 2. The host interface 41 is realized by, for example, a PCIe controller. The host interface 41 includes a RAM 411. The host interface 41 may also be called an end point.

[0030] The RAM 411 is a volatile memory. The RAM 411 includes a plurality of submission queue tail pointers (SQTPs) 4111-0, ..., 4111-v, and a plurality of completion queue head pointers (CQHPs) 4112-0, ..., 4112-w.

[0031] SQTP4111-0, ..., 4111-v are pointers corresponding to the submission queues 221-0, ..., 221-v, respectively. Also, SQTP4111-0, ..., 4111-v are values ​​stored in a submission queue (SQ) tail doorbell register in the storage area of ​​the RAM 411. The doorbell register is a storage area in the RAM 411 that, when written from outside via the I / F, generates an interrupt in the CPU 42 or notifies hardware such as the cycle counter control circuit 45 to start, so that an operation corresponding to the write can be started promptly.

[0032] For example, SQTP 4111-n is a pointer indicating the first slot in which the next new command is stored among the multiple slots in the submission queue 221-n. In other words, the slot indicated by SQTP is an empty slot in which no command is stored. The value of SQTP is updated by the host 2 performing write access to the SQ tail doorbell register. This activates the cycle counter control circuit 45 to update SQETP, and also activates the command fetch unit 421 to fetch a new command if possible.

[0033] CQHP4112-0, ..., 4112-w are pointers corresponding to the completion queues 222-0, ..., 222-w, respectively. CQHP4112-0, ..., 4112-w are values ​​stored in a completion queue (CQ) head doorbell register in the storage area of ​​the RAM 411. For example, CQHP4112-m indicates the next slot after the last slot processed by the host 2 among the multiple slots of the completion queue 222-m. The value of the CQHP is updated by the host 2 writing accessing the CQ head doorbell register. By updating the CQHP, the memory system 3 can advance the CQTP to the position just before the CQHP. In other words, even if the completion queue is full and a new completion notification cannot be issued, an interrupt occurs when the host 2 updates the CQHP, and the memory system 3 can immediately start the completion notification operation.

[0034] The CPU 42 is a processor. The CPU 42 loads a control program (firmware) stored in the non-volatile memory 5 or a ROM (not shown) into the SRAM 46. The CPU 42 then executes the firmware to perform various processes. The CPU 42 may load the firmware into the DRAM 47 instead of the SRAM 46.

[0035] The CPU 42, for example, as a flash translation layer (FTL), manages data stored in the non-volatile memory 5 and manages blocks included in the non-volatile memory 5. The management of data stored in the non-volatile memory 5 includes, for example, management of mapping information. The CPU 42 uses the mapping information of an L2P table (not shown) to manage the mapping between each logical address and each physical address in units of a management size. The management size is, for example, 4 KiB. The logical address is an address used by the host 2 to specify data stored in the non-volatile memory 5. For example, a logical block address (LBA) is used as the logical address. The physical address is an address used by the controller 4 and the non-volatile memory 5 to specify a storage location in the non-volatile memory 5.

[0036] In the non-volatile memory 5, data can be written to a page in a block only once per program / erase cycle of the block. That is, new data cannot be directly overwritten to a memory location (physical memory location) in a block where data has already been written. Therefore, when updating data already written to a physical memory location in a block, the controller 4 writes the new data to an unwritten page (free page) in the block (or another block) and treats the previous data as invalid data. In other words, the controller 4 writes update data corresponding to a logical address to a different physical memory location, not to the physical memory location where the previous data corresponding to the logical address is stored. The controller 4 then updates the L2P table to associate the logical address with a physical address indicating the different physical memory location.

[0037] The management of blocks contained in the nonvolatile memory 5 includes management of defective blocks (bad blocks) contained in the nonvolatile memory 5, wear leveling, and garbage collection (GC).

[0038] The CPU 42 includes a command fetch unit 421 and a timeout processing unit 422 .

[0039] The command fetch unit 421 executes a command fetch process. The command fetch process is a process of identifying a slot in which a command to be fetched is stored among a plurality of slots in a plurality of submission queues 221-0, ..., 221-v, and fetching the command stored in the identified slot. For example, the command fetch unit 421 fetches a command from a slot indicated by an SQHP 461-n among a plurality of slots in a submission queue 221-n. Then, the command fetch unit 421 stores information about the fetched command in a fetch command management table 464-n. The information about the fetched command includes at least the contents and CID of the fetched command. The contents of the command include information indicating the type of the command, a logical address specified by the command, and the like. When the command is fetched, the command fetch unit advances the SQHP 461-n by one. This operation is repeated until the upper limit of commands that can be fetched is reached or until SQHP 461-n reaches SQTP 4111-n, that is, until submission queue 221-n is empty. If the upper limit of commands that can be fetched is reached, a new command is fetched as soon as the fetched command is completed.

[0040] The command fetch unit 421 also includes an arbitration mechanism (not shown). This arbitration mechanism is a mechanism that selects a submission queue from which a command is to be fetched from the multiple submission queues 221-0, ..., 221-v of the host 2. The arbitration mechanism is, for example, a round robin arbitration mechanism or a weighted round robin arbitration mechanism.

[0041] The timeout processing unit 422 executes a timeout process. The timeout process is a process of identifying a command that has been issued by the host 2 and has reached a specific time (hereinafter referred to as a timeout time) since it was issued, and aborting the identified command. Here, the time that has elapsed since the command was issued is the time that has elapsed since the command was stored in the submission queue and a new SQTP was written to the corresponding submission queue tail doorbell register 4111. The timeout time is specified by the host 2 for each submission queue, for example. Hereinafter, the timeout time corresponding to the submission queue 221-n is referred to as a timeout time TOn. In addition, the timeout processing unit 422 periodically executes a timeout process for each of the submission queues 221-0, ..., 221-v. For example, the timeout processing unit 422 executes a timeout process for the submission queue 221-n every time a time Tn elapses. Tn is also referred to as a first time. The timeout processing unit 422 may set the time interval at which the timeout process is executed to a different time interval for each submission queue. That is, the timeout processing unit 422 executes timeout processing for commands issued via the submission queue 221-n every time the first time Tn elapses. Here, the timeout processing unit 422 can set the first time Tn so that the timeout time TOn is an integer multiple of the first time Tn (that is, TOn=Mn×Tn, where Mn is an integer equal to or greater than 1). In addition, the timeout processing unit 422 executes timeout processing for commands issued via the submission queue 221-m every time the second time Tm elapses.

[0042] The timer 43 is a hardware circuit that counts time. The timer 43 has, for example, a timer tick Tc. The timer 43 may issue a notification to other components of the controller 4 every time the timer tick Tc elapses. The timer tick Tc is also referred to as a third time. For example, a first time Tn corresponding to the submission queue 221-n and a second time Tm corresponding to the submission queue 221-m may each be set to an integer multiple of the third time Tc.

[0043] The NAND interface 44 is a circuit that controls the nonvolatile memory 5. The NAND interface 44 includes a plurality of memory controllers 441-0, ..., 441-x. Each of the plurality of memory controllers 441-0, ..., 441-x is electrically connected to one or more memory chips among the plurality of memory chips 51-0, ..., 51-y included in the nonvolatile memory 5.

[0044] The cycle counter control circuit 45 is a hardware circuit that controls a cycle counter for each submission queue. The cycle counter indicates one of a plurality of cycles in which commands are stored in a plurality of slots of the submission queue. In one cycle, a command is repeatedly issued and fetched, so that a command is stored once in each slot from the first slot to the last slot of the submission queue. Then, when the slot in which the next command to be issued should be stored becomes the first slot, a cycle is shifted to the next cycle. That is, the cycle counter corresponds to the number of times that the SQTP has gone around the slots of the submission queue. When the SQTP4111-n is updated to a value smaller than the value of the SQTP4111-n before the update, the cycle counter control circuit 45 starts operation by the function of the doorbell register and updates the cycle counter corresponding to the submission queue 221-n. When the cycle counter corresponding to the submission queue 221-n is a value other than the upper limit value, the cycle counter control circuit 45 increments the cycle counter by one. Furthermore, when the cycle counter corresponding to the submission queue 221-n is at the upper limit value, the cycle counter control circuit 45 updates the cycle counter to an initial value. The upper limit value of the cycle counter is determined based on at least one of the number of slots included in the corresponding submission queue, the timeout time, and the number of commands issued via the corresponding submission queue that the controller 4 can process during the timeout time.

[0045] The SRAM 46 is a volatile memory. The storage area of ​​the SRAM 46 is used, for example, as a working area of ​​the CPU 42. The SRAM 46 also includes storage areas for storing a plurality of submission queue head pointers (SQHP) 461-0, ..., 461-v, a plurality of completion queue tail pointers (CQTP) 462-0, ..., 462-w, submission queue extension tail pointers (SQETP) 463-0, ..., 463-v, fetch command management tables 464-0, ..., 464-v, and first EPs 465-0, ..., 465-v.

[0046] SQHP461-0, ..., 461-v are pointers corresponding to the submission queues 221-0, ..., 221-v, respectively. For example, SQHP461-n indicates a slot in which the next command to be fetched is stored among the multiple slots of the submission queue 221-n. When the controller 4 fetches one command from the slot of the submission queue 221-n indicated by SQHP461-n, the controller 4 updates the value of SQHP461-n. At this time, if the SQHP461-n before the update indicates a slot other than the last slot of the submission queue 221-n, the controller 4 increments SQHP461-n by 1. On the other hand, if the SQHP461-n before the update indicates the last slot of the submission queue 221-n, the controller 4 updates SQHP461-n to a value indicating the first slot of the submission queue 221-n. When sending a completion response after updating SQHP 461-n, the controller 4 stores in the completion response the identifier of the submission queue corresponding to the submission queue 221-n (submission queue ID) and the updated value of SQHP 461-n. In this way, the controller 4 notifies the host 2 of the updated value of SQHP 461-n. At this time, the command corresponding to the completion response may be a command fetched from a slot of the submission queue 221-n, or may be a command fetched from a slot of another submission queue.

[0047] CQTP462-0, ..., 462-w are pointers corresponding to the completion queues 222-0, ..., 222-w, respectively. For example, CQTP462-m indicates the slot in which the next new completion response is stored among the multiple slots of the completion queue 222-m. In other words, the slot indicated by CQTP is an empty slot in which no command is stored. The controller 4 updates CQTP462-m in response to completion of preparation for issuing one completion response to the completion queue 222-m. At this time, if the CQTP462-m before the update indicates a slot other than the last slot of the completion queue 222-m, the controller 4 increments CQTP462-m by 1. On the other hand, if the CQTP462-m before the update indicates the last slot of the completion queue 222-m, the controller 4 updates the CQTP462-m to a value indicating the first slot of the completion queue 222-m. Then, the controller 4 stores the prepared completion response in the completion queue 222-m. Also, when the host 2 is ready to issue two or more completion responses, the host 2 may collectively update the value of CQTP462-m by the number of prepared command completions. After updating the CQTP462-m, the memory system 3 generates an interrupt to the host 2 through the memory I / F 23, so that the host 2 can know that at least one CQTP462 has been updated. Depending on the type of interrupt, the ID of the completion queue can be notified together with the interrupt, so in that case, the host can identify the completion queue in which the CQTP4114 has been updated.

[0048] SQETP463-0, ..., 463-v are extended pointers corresponding to the submission queues 221-0, ..., 221-v, respectively. The extended pointers include a pointer field and a cycle counter field. For example, the pointer field of SQETP463-n indicates SQTP4111-n corresponding to the submission queue 221-n. Also, the cycle counter field of SQETP463-n indicates the cycle counter corresponding to the submission queue 221-n. SQETP463-n is updated in response to an update of SQTP4111-n.

[0049] The fetch command management tables 464-0, ..., 464-v correspond to the submission queues 221-0, ..., 221-v, respectively. The fetch command management tables 464-0, ..., 464-v are tables used to manage commands received (fetched) from the host 2 and information related to the time range in which the commands were issued. The fetch command management tables 464-0, ..., 464-v each include a plurality of entries. Each of the plurality of entries in the fetch command management table 462-n stores at least the contents of the command fetched from the submission queue 221-n. For example, each of the plurality of entries in the fetch command management table 464-n stores the contents of the command fetched from the submission queue 221-n and an EP indicating the slot in which the command is stored. Alternatively, each of the plurality of entries in the fetch command management table 464-n stores the contents of the command fetched from the submission queue 221-n and information indicating the time slot corresponding to the command. The multiple time slots are multiple consecutive time ranges of the first time unit. A command issued during a certain time slot is associated with that time slot. Details of the time slot will be described later.

[0050] The first EP 465-0, ..., 465-v are extension pointers temporarily saved from the time slot management table 471-0, ..., 471-v described later. The first EP 465-n corresponds to the submission queue 221-n and is an extension pointer saved from the time slot management table 471-n. The first EP 465-n is the SQETP 463-n at the end time of the time slot immediately before the time slot that is the timeout target. The first EP 465-0, ..., 465-v will be described in detail later. Since the first EP is used immediately for calculation and is no longer needed thereafter, it may be loaded into a register of the CPU 42, which is a calculation machine, if possible.

[0051] The DRAM 47 is a volatile memory. A part of the storage area of ​​the DRAM 47 is used to store time slot management tables 471-0, . . . , 471-v. The DRAM 47 may be located outside the controller 4, not inside the controller 4.

[0052] Each of the time slot management tables 471-0, ..., 471-v corresponds to the submission queues 221-0, ..., 221-v. The time slot management tables 471-0, ..., 471-v are tables used to manage the correspondence between the time slots and the extension pointers. Each of the time slot management tables 471-0, ..., 471-v includes a plurality of entries. Each of the plurality of entries corresponds to one time slot. In each entry, the SQETP at the end time of the corresponding time slot is stored. That is, every time Tn elapses, the SQETP 463-n is stored in order in one of the entries of the time slot management table 471-n. And, the command corresponding to the slot one before the slot indicated by the SQETP stored in the entry corresponding to a certain time slot is the latest command among the commands issued by the end time of the time slot. Here, the case where time slot management tables 471-0, . . . , 471-v are stored in DRAM 47 has been described, but time slot management tables 471-0, .

[0053] Next, a configuration example of a submission queue will be described. Fig. 2 is a diagram showing a plurality of states of a submission queue 221-n used in an information processing system 1 including a memory system 3 according to an embodiment. Here, the number of slots included in the submission queue 221-n is SIZEn, and the submission queue 221-n includes slots SLT0 to SLT SIZEn-1. This diagram shows a state recognized by the memory system 2, but a state recognized by the host 2 is one in which SQHP461-n is replaced with SQHHP223-n (not shown) and SQTP4111-n is replaced with SQHTP224-n.

[0054] 2A shows an empty submission queue 221-n, that is, none of the multiple slots in the submission queue 221-n are stored and are empty slots.

[0055] At this time, both SQHP461-n and SQTP4111-n indicate the same slot (here, slot SLT2). For example, since SQHP461-n and SQTP4111-n indicate the same slot, the controller 4 determines that the submission queue 221-n is empty and does not store a command. In other words, the controller 4 determines that the submission queue 221-n is a submission queue that does not store a fetchable command. Similarly, since SQHHP223-n and SQHTP224-n indicate the same slot, the host 2 also determines that the submission queue 221-n is empty and does not store a command. Then, the host 2 specifies that the slot SLT2 indicated by SQHTP224-n is the slot that can store the next new command.

[0056] Fig. 2(b) shows the submission queue 221-n in which two commands are stored. The submission queue 221-n in Fig. 2(b) is in a state where two commands are stored in the submission queue 221-n in Fig. 2(a).

[0057] 2(a), the host 2 goes to the state of (b) and write-accesses the submission queue tail doorbell register SQTP4111-n to update SQTP4111-n by incrementing it by 2. As a result, SQTP4111-n becomes a value indicating slot SLT4, and goes to the state of (b) when viewed from the memory system 3. The host 2 may write-access the submission queue tail doorbell register SQTP4111-n of the RAM 411 every time it stores one command in the submission queue 221-n, or may store multiple commands in the submission queue 221-n and then write-access the submission queue tail doorbell register SQTP4111-n of the RAM 411 to update SQTP4111-n all at once.

[0058] Slots SLT2 and SLT3 of the submission queue 221-n are "occupied" because commands are stored therein. When SQHP461-n and SQTP4111-n have different values, the controller 4 determines that fetchable commands are stored in the submission queue 221-n. The controller 4 identifies the number of commands stored in the submission queue 221-n from the difference between SQHP461-n and SQTP4111-n. Here, since the difference between SQHP461-n and SQTP4111-n is 2 and SQHP461-n indicates slot SLT2, the controller 4 determines that fetchable commands are stored in slots SLT2 and SLT3.

[0059] Fig. 2(c) shows the submission queue 221-n in a full state. When SIZEn-3 commands are further stored in the submission queue 221-n in Fig. 2(b), the submission queue 221-n becomes full.

[0060] When a command is stored in slot SLT SIZEn-1 of the submission queue 221-n, the next slot in which a new command should be stored becomes slot SLT0. Therefore, SQTP4111-n is updated to a value indicating slot SLT SIZEn-1, and then to a value indicating slot SLT0. Due to this configuration, the submission queue 221-n is also called a circular queue. Then, when a command is stored in slot SLT0, the host 2 updates SQTP461-n to a value indicating slot SLT1. The host 2 (and the controller 4) determines that the submission queue 221-n is full when the value of SQHTP224-n (SQTP4111-n) is a value indicating the slot immediately before the slot indicated by SQHHP223-n (SQHP461-n). The host 2 does not store a command in the slot SLT1 of the submission queue 221-n until the SQHHP 223-n is updated by a notification from the memory system 3 and the submission queue 221-n is no longer full.

[0061] Here, the configuration of one of the submission queues 221-n among the submission queues 221-0, ..., 221-v has been described as an example, but the configuration of the completion queues 222-0, ..., 222-w can also be realized by a similar circular queue.

[0062] However, host 2 does not directly manage the tail pointer of the completion queue, and the pointer that points to the slot where the value of the Phase Tag Bit has changed becomes the tail pointer that host 2 can recognize.

[0063] Next, command processing will be described. Fig. 3 is a diagram showing the flow of command processing executed in the information processing system 1 including the memory system 3 according to the embodiment. Here, a case will be described in which the host 2 issues a command via the submission queue 221-n, the controller 4 of the memory system 3 processes the issued command, and transmits a completion response corresponding to the processed command via the completion queue 222-m.

[0064] Step 1: The host 2 stores one or more new commands to be sent to the memory system 3 in one or more free slots in the submission queue 221-n. The one or more new commands are stored in one or more free slots starting from the slot indicated by the current value of SQHTP 224-n. The new commands stored in the submission queue 221-n may be a write command, a read command, or other command. In FIG. 2, each command stored in the submission queue 221-n is represented as "CMD".

[0065] Step 2: The host 2 updates the value of SQHTP 224-n. The host 2 increments the value of SQHTP 224-n by the number of commands stored in step 1.

[0066] Step 3: To notify the controller 4 of the memory system 3 that one or more new commands have been stored in the submission queue 221-n, the host 2 write-accesses the submission queue tail doorbell register in the memory system 3 corresponding to this submission queue 221-n, and updates the value of SQTP4111-n corresponding to this submission queue 221-n. The value of SQTP4111-n is updated to the updated value of SQHTP224-n. Such an update of SQTP4111-n via the doorbell register triggers the controller 4 to start processing each of the commands stored in the submission queue 221-n.

[0067] Step 4: The controller 4 updates SQETP463-n in response to the update of SQTP4111-n. The controller 4 compares the updated SQTP4111-n stored in the SQ tail doorbell register with the pre-update SQTP4111-n stored in the pointer field of the SQETP. If the updated SQTP4111-n is smaller than the pre-update SQTP4111-n, the controller 4 determines that SQTP4111-n has moved from the last slot (e.g., slot SLT SIZEn-1) to the first slot (e.g., slot SLT0), and updates the cycle counter. At this time, if the cycle counter is at the upper limit, the controller 4 sets the cycle counter to an initial value (usually the minimum value, zero). If the cycle counter is other than the upper limit, the controller 4 increments the cycle counter by one. Then, the controller 4 records the updated cycle counter and the updated SQTP as the updated SQETP 463-n. On the other hand, if the updated SQTP 4111-n is equal to or greater than the pre-update SQTP 4111-n, the controller 4 simply stores the updated SQTP 4111-n in the pointer field of the SQETP 463-n.

[0068] Step 5: The controller 4 can recognize the number of new commands stored in the submission queue 221-n from the difference between the new value of SQTP 4111-n and the value of SQHP 461-n. The controller 4 fetches one or more arbitrary number of commands from the submission queue 221-n.

[0069] Step 6: The controller 4 updates the fetch command management table 464-n so that information on the fetched command is stored in the fetch command management table 464-n. The controller 4 selects one of the invalidated entries in the fetch command management table 464-n as an entry in which information on the fetched command is stored. Then, the controller 4 stores the content of the command, the CID, and an extension pointer indicating the slot of the submission queue 221-n in which the command was stored in the entry. The content of each command fetched in step 5 can be managed using the fetch command management table 464-n. Also, each command fetched in step 5 may be temporarily stored in a storage area of ​​the SRAM 46 different from the fetch command management table 464-n. When commands are fetched one by one, that is, when a command in a slot indicated by the SQEHP is fetched and the SQEHP is advanced one by one each time, the extension pointer is the SQEHP at the time of fetching. Alternatively, the controller 4 stores the content of the command and information indicating the time slot in which the command is included in one entry of the fetch command management table 464-n. The information indicating the time slot is, for example, a value indicating one entry included in the time slot management table 471-n to which the time slot is associated.

[0070] Step 7: The controller 4 updates the value of the SQHP 461-n corresponding to the submission queue 221-n so that the value is increased by the number of commands fetched in step 5.

[0071] Step 8: The controller 4 executes each of the fetched commands. With some exceptions, the order in which the commands are executed is not limited, and the commands may be executed in an order different from the order in which they were fetched. In the process of executing each command, the controller 4 writes data in the RAM 22 of the host 2 to the non-volatile memory 5, or writes data in the non-volatile memory 5 to the RAM 22 of the host 2, as necessary.

[0072] Step 9: When the processing of a certain command is completed, the controller 4 updates the fetch command management table 464-n so as to invalidate one entry in the fetch command management table 464-n corresponding to the command whose processing has been completed. The invalidated entry becomes an entry in which new information can be stored.

[0073] Step 10: The controller 4 stores the new response indicating the completed command, the ID of the submission queue in which the command was stored and the corresponding CID, the completion status of the command, the updated SQHP of a certain submission queue and the ID of that queue, in the next free slot of the completion queue 222-m. This free slot is the slot indicated by the CQTP 462-m before being updated in step 10. In FIG. 2, each of the completion responses stored in the completion queue 222-m is represented as "CPL". The completion queue 222-m is associated with the submission queue 221-n from which the completed command was fetched, and the completion response of the command issued in the submission queue 221-n is always performed in the completion queue 222-m.

[0074] Step 11: Then, the controller 4 updates the CQTP462-m corresponding to the completion queue 222-m, and increments the value of this CQTP462-m by 1. In steps 10 and 11, the case where the CQTP462-m is updated after the completion response is stored in the completion queue 222-m has been described, but the controller 4 may store the completion response in the completion queue 222-m after updating the CQTP462-m.

[0075] Step 12: The controller 4 sends an interrupt to the host 2. The controller 4 may send an interrupt to the host 2 including an interrupt vector corresponding to the completion queue 222-m in which the completion response was stored in step 11, to notify the host 2 that a new completion response has been stored in the completion queue 222-m.

[0076] Step 13: Host 2 obtains the completion response from the slot indicated by the current value of CQHHP225-m, processes the obtained completion response, identifies the request source of this command from the submission queue ID and CID included in the completion response, and returns a completion response to that request.

[0077] Step 14: The host 2 updates the SQHHP based on the submission queue ID and the value of the SQHP included in the completion response processed in step 13. The submission queue ID is, for example, an identifier corresponding to the submission queue 221-n. The submission queue ID and the value of the SQHP included in the completion response may be information regarding the value of the SQHP updated in response to fetching of a command other than the command corresponding to this completion response. The submission queue ID may also be an identifier indicating a submission queue other than the submission queue 221-n. However, the submission queue ID and the SQHHP included in one completion response correspond to one submission queue.

[0078] Step 15: In response to processing one completion response in step 13, the host 2 updates the CQHHP 225-m and increments the CQHHP 225-m by 1. At this time, if the CQHHP 225-m before the update indicates a slot other than the last slot of the completion queue 222-m, the controller 4 increments the CQHHP 225-m by 1. On the other hand, if the CQHHP 225-m before the update indicates the last slot of the completion queue 222-m, the controller 4 updates the CQHHP 225-m to a value indicating the first slot of the completion queue 222-m. This is repeated until the slot immediately before the value of the Phase Tag Bit is inverted, and the completion response is sent in step 13. After processing two or more completion responses, the host 2 may update CQHHP225-m so that the value of CQHHP225-m is incremented by the number of command completions that have been processed.

[0079] Step 16: The host 2 write-accesses the completion queue head doorbell register in the memory system 3 corresponding to the completion queue 222-m, and updates the value of CQHP4112-m. The value of CQHP4112-m is updated to the value of CQHHP225-m updated in step 15.

[0080] Next, a time slot will be described with reference to Fig. 4. The time slot is used in the memory system 3 according to the embodiment.

[0081] The controller 4 manages a plurality of time slots for each submission queue. For example, the controller 4 manages a plurality of time slots corresponding to the submission queue 221-n. The plurality of time slots corresponding to the submission queue 221-n are a plurality of continuous time ranges in units of the first time Tn. One time slot is a time range of the first time Tn.

[0082] 4 shows a time starting from 0 and a number of time slots corresponding to the submission queue 221-n. Hereinafter, a time slot corresponding to the submission queue 221-n and corresponding to the range from time (t-1)×Tn to time t×Tn is represented as TSn,t, where t is an integer.

[0083] The controller 4 manages commands issued to the submission queue 221-n during a certain time slot by associating them with the time slot. Specifically, the controller 4 associates commands issued to the submission queue 221-n from the time (t-1)×Tn has elapsed until time t×Tn is reached with the time slot TSn,t. That is, a command issued to the submission queue 221-n at time (t-1)×Tn is not associated with the time slot TSn,t but is associated with the time slot TSn,t-1. And a command issued to the submission queue 221-n at time t×Tn is associated with the time slot TSn,t.

[0084] The controller 4 executes the timeout process in units of time slots. When the timeout time TOn is Mn×Tn, the controller 4 executes the timeout process for the commands that have not been processed among the commands corresponding to the time slot TSn,t at the time (t+Mn)×Tn. Here, Mn is an integer of 1 or more. At this time, the time that has elapsed since the command corresponding to the time slot TSn,t was issued to the submission queue 221-n is equal to or more than Mn×Tn and is less than (Mn+1)×Tn. In other words, at the time (t+Mn)×Tn, the time that has elapsed since the command corresponding to the time slot TSn,t was issued to the submission queue 221-n is equal to or more than Mn×Tn.

[0085] By using such time slots, the controller 4 does not need to manage the time that has passed since each of the multiple commands received (fetched) was issued to the submission queue. In particular, in a memory system 3 that processes a large number of commands in parallel at once, it is possible to avoid the need to measure the time that has passed since each command whose processing is incomplete was issued.

[0086] In this way, the controller 4 simultaneously times out multiple commands contained in one time slot. Therefore, the time from when a command is issued to the submission queue 221-n until it times out can take a value greater than or equal to Mn×Tn and less than (Mn+1)×Tn. Therefore, the accuracy of the time until a command actually times out relative to the timeout time TOn (=Mn×Tn) is expressed as ((Mn+1)×Tn-Mn×Tn) / (Mn×Tn)=1 / Mn. From this, even if the timeout time is changed, the accuracy of the timeout can be kept constant by fixing Mn and changing Tn.

[0087] The time slot TSn,t described here treats commands issued in the time range from time (t-1)×Tn to time t×Tn as a group of commands issued at time t×Tn. On the other hand, when the time slot TSn,t treats commands issued in the time range from time t×Tn to before time (t+1)×Tn is reached as a group of commands issued at time t×Tn, Mn is an integer of 2 or more. And, commands that time out at time (t+Mn)×Tn are commands issued in the time range from time t×Tn to before time (t+1)×Tn is reached. The time that has passed since these commands were issued to the submission queue 221-n is greater than (Mn-1)×Tn and less than or equal to Mn×Tn.

[0088] Next, an extended pointer (EP) will be described. Fig. 5 is a diagram showing an example of an extended pointer used in the memory system 3 according to the embodiment.

[0089] The extended pointer includes a cycle counter and a pointer. The extended pointer corresponds to a slot of one virtual submission queue. One virtual submission queue slot may correspond to one command. The extended pointer is a pointer that is an extension of the submission queue tail (or head) pointer. The extended pointer is a pointer for identifying a command that may be subject to timeout processing. In particular, the extended pointer is a pointer that is extended for identifying a command that cannot be identified by a pointer indicating a slot of the submission queue because it has already been fetched from the submission queue. For example, the extended pointer includes a cycle counter field in which information indicating the cycle counter is stored, and a pointer field in which information indicating the pointer is stored. Alternatively, the extended pointer may be realized by a bit string consisting of upper bits that are the cycle counter field and lower bits that are the pointer field.

[0090] The cycle counter indicates the number of times the pointer has gone around the circular queue. For example, the cycle counter corresponding to SQTP4111-n of the submission queue 221-n is incremented by 1 by the cycle counter control circuit 45 when the value of the updated SQTP4111-n stored in the submission queue tail doorbell register is smaller than the SQTP before the update. At this time, when the value of the cycle counter before the update is the upper limit value, the cycle counter control circuit 45 sets the cycle counter to the initial value instead of incrementing by 1.

[0091] The upper limit value MAXCC of the cycle counter corresponding to the submission queue 221-n is determined based on at least one of the size of the submission queue 221-n, the timeout time TOn, and the command processing speed of the memory system 3. For example, the upper limit value MAXCC of the cycle counter needs to be a value that enables the extension pointer to cover MAXCYCLE, which is the integer obtained by rounding up the maximum number of commands that the host 2 can issue during the timeout time TOn and dividing it by the size of the submission queue 221-n, and adding 1 to the integer. Here, the maximum number of commands that the host 2 can issue during the timeout time TOn is the sum of the maximum number of commands that the controller 4 can fetch from the submission queue 221-n during the timeout time TOn and the size of the submission queue 221-n.

[0092] Specifically, the size of the submission queue 221-n is SIZEn, the timeout time is TOn [s], and the command processing speed of the memory system 3 is MaxCom [1 / s]. In this case, the maximum number MAXFN of the number of commands that the controller 4 can fetch from the submission queue 221-n before the timeout time TOn has elapsed is equal to the maximum number of commands that can be processed by the controller 4 of the memory system 3 during the timeout time TOn. That is, MAXFN is TOn x MaxCom. And the maximum number of commands that the host 2 can issue during the timeout time TOn is MAXFN + SIZEn. Therefore, MAXCYCLE is (TOn x MaxCom + SIZEn) / SIZEn + 1. And the upper limit value MAXCC of the cycle counter is set to a value that determines the width of a field such that the extension pointer is a size that can store the calculated MAXCYCLE (for example, MAXCC = 2^ (field width) - 1).

[0093] Here, by setting MaxCom based on a command that can be processed quickly among practical commands, the upper limit value of the cycle counter can be suppressed compared to when an impractical command is processed. This makes it possible to reduce the width of the cycle counter field. An example of a command that can be processed quickly among practical commands is a plurality of read commands that specify data of the minimum unit size and specify consecutive logical addresses. Also, an example of a command that can be processed quickly among impractical commands is a command that is specified by an undefined code indicating the command type, and generates an error indicating that the command is undefined.

[0094] The pointer indicates one of the multiple slots in the submission queue.

[0095] Next, an example of a virtual submission queue will be described. The submission queue extended head pointer (SQEHP) shown below has the same value as the submission queue extended tail pointer (SQETP) at the end of the time slot that is one older than the time slot that is the target of the timeout. An extended pointer with a cycle counter value of j and a pointer value of k is represented as EP(j,k) (where 0≦j≦MAXCC-1 and 0≦k≦SIZEn-1).

[0096] FIG. 6 is a diagram showing an example of a first state of a virtual submission queue managed in the memory system 3 according to the embodiment. Each of a plurality of slots included in the virtual submission queue corresponds to one possible value of the extension pointer. Therefore, the number of slots included in the virtual submission queue corresponding to the submission queue 221-n is determined by the upper limit value MAXCC-1 (vertical axis, the number of 0 to MAXCC-1) of the cycle counter corresponding to the submission queue 221-n and the size of the submission queue 221-n (horizontal axis, the number of 0 to SIZEn-1). The submission queue 221-n in FIG. 6 is in a full state. And, all the commands issued via the submission queue 221-n and in the virtual submission queue have not yet been fetched and are incomplete.

[0097] SQHP461-n indicates slot SLT SIZEn-1, and SQTP4111-n indicates slot SLT SIZEn-2. Since SQTP4111-n indicates the slot immediately preceding the slot indicated by SQHP461-n, the submission queue 221-n is full. At this time, slot SLT SIZEn-2 indicated by SQTP4111-n is an empty slot.

[0098] The extension pointer corresponding to SQHP461-n and SQEHP463-n is EP(0,SIZEn-1). The slot corresponding to EP(0,SIZEn-1) is the last slot of the submission queue 221-n. Therefore, the next command is stored in the first slot of the submission queue 221-n. In other words, after EP(0,SIZEn-1), the pointer indicating the position of the slot in which the command is stored is updated to its initial value, and at this time, the cycle counter of the extension pointer is incremented by 1 to become EP(1,0).

[0099] Then, when commands are issued until the submission queue 221-n becomes full, the extension pointers corresponding to SQTP4111-n and SQETP463-n are EP(1,SIZEn-2). The extension pointers corresponding to the submission queue 221-n on the RAM 22 of the host 2 (i.e., the slots corresponding to the real memory) are pointers included in the extension pointer range from EP(0,SIZEn-1) to EP(1,SIZEn-2). The other extension pointers correspond to virtual free slots that do not correspond to the storage area of ​​the RAM 22, among the slots of the virtual submission queue 221-n.

[0100] Fig. 7 is a diagram showing an example of a second state of a virtual submission queue 221-n managed in the memory system 3 according to the embodiment. The example of the second state in Fig. 7 shows a point in time after the first state shown in Fig. 6, when the timeout time TOn has elapsed and before the timeout process is executed. Here, during the timeout time TOn, a command of MAXFN has been fetched from the submission queue 221-n, and a command of SIZEn has been newly issued by the host 2. Therefore, the submission queue 221-n remains full even after TOn has elapsed.

[0101] Specifically, the extension pointer corresponding to SQEHP is EP(0,SIZEn-1). The extension pointer corresponding to SQHP461-n is EP(MAXCC-2,1). Therefore, the extension pointers included in the extension pointer range from EP(0,SIZEn-1) to EP(MAXCC-2,0) correspond to virtual slots that may correspond to commands that have been fetched and whose processing has not yet been completed. Virtual slots that may correspond to commands that have been fetched and whose processing has not yet been completed correspond to either commands that have been fetched and whose processing has not yet been completed, or commands that have been fetched and whose processing has been completed.

[0102] In addition, the extension pointer corresponding to SQTP4111-n and SQETP463-n is EP(MAXCC-1,0). Therefore, the extension pointers included in the range of the extension pointers from EP(MAXCC-2,1) to EP(MAXCC-1,0) correspond to multiple slots of the submission queue 221-n on the RAM 22 of the host 2.

[0103] Next, FIG. 8 shows an example of a third state of a virtual submission queue when the extension pointer corresponding to SQEHP is EP(0,0) and the maximum number of commands that the host 2 can issue have been issued to the submission queue 221-n within the timeout period TOn.

[0104] In this case, the extension pointers included in the extension pointer range from EP(0,0) to EP(MAXCC-3,1) correspond to virtual slots that may correspond to commands that have been fetched and whose processing has not yet been completed. Also, the extension pointer that corresponds to SQTP4111-n and SQETP463-n is EP(MAXCC-2,1). Therefore, the extension pointers included in the extension pointer range from EP(MAXCC-3,2) to EP(MAXCC-2,1) correspond to multiple slots of the submission queue 221-n on the RAM 22 of the host 2.

[0105] Next, FIG. 9 shows an example of the fourth state of a virtual submission queue when the extension pointer corresponding to SQEHP is EP(j+2,SIZEn-2) and the maximum number of commands that the host 2 can issue have been issued to the submission queue 221-n within the timeout period TOn.

[0106] First, the extension pointers included in the range of the extension pointer from EP(j+2,SIZEn-2) to EP(MAXCC-1,SIZEn-1) are slots to which a command that has already been fetched and is not yet processed may correspond. When commands are stored up to the slot corresponding to EP(MAXCC-1,SIZEn-1) and the slot in which the next command should be stored becomes the top slot, the controller 4 associates the top slot with the extension pointer including the updated cycle counter. At this time, since the value of the cycle counter before the update is MAXCC-1 (i.e., the upper limit value), the controller 4 updates the cycle counter to 0 (i.e., the initial value). As a result, the extension pointer corresponding to the slot in which the next command should be stored becomes EP(0,0). Thereafter, as the issuance of commands and the command fetching proceed, the cycle counter and the pointer are updated sequentially.

[0107] 9, the extension pointer corresponding to SQHHP 223-n managed by host 2 is EP(j, k+2), and the extension pointer corresponding to SQHTP 224-n managed by host 2 is EP(j+1, k+1). Since SQHTP 224-n indicates the slot immediately preceding the slot indicated by SQHHP 223-n, submission queue 221-n is full as viewed from host 2. Therefore, host 2 determines that it cannot issue a new command to submission queue 221-n.

[0108] At this time, the controller 4 has fetched one or more commands ((SIZEn-2)-(k+2) commands) from the submission queue 221-n and updated SQHP461-n, but has not yet notified the host 2 of the updated value of SQHP461-n. Therefore, the extension pointer corresponding to SQHP461-n is EP(j,SIZEn-2), which is different from SQHHP223-n.

[0109] In addition, the host 2 stores a command in the slot of the submission queue 221-n corresponding to EP(j+1,k), but has not yet performed write access to the submission queue tail doorbell register. Therefore, the extension pointer corresponding to SQTP4111-n and SQETP463-n managed by the controller 4 is EP(j+1,k), unlike SQHTP224-n.

[0110] As a result, the slot indicated by the SQTP 4111-n is different from the slot immediately preceding the slot indicated by the SQHP 461-n, and therefore the controller 4 does not determine that the submission queue 221-n is full.

[0111] In reality, the slot in which the next command to be fetched by the controller 4 is stored corresponds to EP(j,SIZEn-2) indicated by the SQHP, and the slot in which the next command should be stored by the host 2 after the SQHHP has progressed due to the SQHP being notified to the host 2 is EP(j+1,k+1) indicated by the SQHTP.

[0112] 9, the extension pointers included in the extension pointer range from EP(j+2,SIZEn-2) to EP(MAXCC-1,SIZEn-1) and the extension pointer range from EP(0,0) to EP(j,k+1) correspond to virtual slots that may correspond to commands that have been fetched but whose processing has not yet been completed. Hereinafter, an extension pointer range that spans the end of the extension pointer and the start of the extension pointer, such as from EP(j+2,SIZEn-2) to EP(j,k+1), will be referred to as a range including the warp of the extension pointer.

[0113] In this way, when an extended pointer is warped, it may not be possible to directly calculate whether or not a certain extended pointer is included in the range between two extended pointers. Therefore, two methods for comparing and calculating extended pointers taking warping into account will be described below.

[0114] First, the first method will be described with reference to Fig. 10. Fig. 10 is a diagram showing a first example of comparing extension pointers in a virtual submission queue managed in the memory system 3 according to the embodiment. The values ​​of the extension pointers in Fig. 10 before applying the first method are the same as the values ​​of the extension pointers shown in Fig. 9.

[0115] In the first method, the controller 4 adds MAXCC to the cycle counter of the warped extension pointer from the perspective of the SQEHP. In other words, among the slots of the virtual submission queue, an extension pointer that has a cycle counter less than the cycle counter of the SQEHP is regarded as the warped extension pointer. This extends the cycle counter of the extension pointer after the cycle counter is updated to the initial value to more than MAXCC.

[0116] At this time, an extension pointer whose original cycle counter is 0 (for example, EP(0,0)) is calculated as an extension pointer whose cycle counter is MAXCC (for example, EP(MAXCC,0)). Then, SQHHP223-n corresponds to EP(MAXCC+j,k+2), SQHP461-n corresponds to EP(MAXCC+j,SIZEn-2), SQTP4112-n corresponds to EP(MAXCC+j+1,k), and SQHTP224-n corresponds to EP(MAXCC+j+1,k+1). An extension pointer between EP(j+2,SIZEn-2) and EP(MAXCC+j,k+1) corresponds to a virtual slot to which a command that has been fetched and whose processing has not yet been completed may correspond. An extension pointer included in the range between EP(MAXCC+j,k+2) and EP(MAXCC+j+1,k+1) corresponds to a plurality of slots of the submission queue 221-n on the RAM 22 of the host 2.

[0117] In this way, the extended pointer to which the first method is applied is a continuous extended pointer without warping, so that the extended pointer can be directly compared and calculated. However, the upper limit value of the cycle counter of the extended pointer to which the first method is applied can be approximately twice the value of the original cycle counter. Therefore, a field larger in size than the original cycle counter field is required to temporarily store the extended pointer used for calculation.

[0118] Next, the second method will be described with reference to Fig. 11. In the second method, the cycle counter of another extension pointer is subtracted based on the cycle counter of the SQEHP. Fig. 11 is a diagram showing a second example of comparing extension pointers in a virtual submission queue managed in the memory system 3 according to the embodiment.

[0119] The controller 4 subtracts the cycle counter value included in the SQEHP before calculation from the cycle counter of each extension pointer. Specifically, it subtracts j+2, which is the cycle counter of the SQEHP, from the cycle counter of each extension pointer. This makes it possible to shift other extension pointers as well, so as to shift the cycle counter of the SQEHP to its initial value.

[0120] The extension pointer of the SQEHP after the subtraction (i.e., SQEHP-(j+2,0)) becomes EP(0,SIZEn-2). The SQEHP after the subtraction contains the initial cycle counter.

[0121] At the extension pointer of SQHHP223-n after the subtraction (i.e., SQHHP-(j+2,0)), the cycle counter underflows (i.e., EP(-2,k+2)). Therefore, as the reverse process of when the extension pointer wraps around, MAXCC is added to the cycle counter. Therefore, SQHHP223-n after the subtraction becomes EP(MAXCC-2,k+2). Note that since SQHHP is in the host 2, the memory system 3 is not aware of it, so this calculation is not actually performed.

[0122] Since the extension pointer of SQHP461-n after the subtraction (that is, SQHP-(j+2,0)) underflows, MAXCC is further added to the cycle counter, resulting in EP(MAXCC-2,SIZEn-2).

[0123] Since the extension pointer of SQTP4111-n after the subtraction (ie, SQTP-(j+2,0)) underflows, MAXCC is further added to the cycle counter, resulting in EP(MAXCC-1,k).

[0124] Then, the extension pointer of SQHTP224-n after the subtraction (i.e., SQHTP-(j+2,2)) underflows, so MAXCC is further added to the cycle counter, resulting in EP(MAXCC-1,k+1). Note that since SQHTP is in the host 2, the memory system 3 does not know about it, so this calculation is not actually performed.

[0125] In this way, the extended pointer to which the second method is applied is a continuous extended pointer without warping, so the extended pointer can be directly compared and calculated. The maximum value of the extended pointer to which the second method is applied is MAXCC-1, which is the same as before the subtraction. Therefore, the size of the extended pointer does not change even when the second method is applied.

[0126] In the following description, when two or more extension pointers are compared, the first method or the second method described with reference to Figures 10 and 11 may be used.

[0127] Next, a configuration example of the fetch command management table 464-n will be described. Fig. 12 is a diagram showing a configuration example of the fetch command management table 464-n used in the memory system 3 according to the embodiment. Here, the fetch command management table 464-n used when the extension pointer corresponding to each command is managed is shown.

[0128] The fetch command management table 464-n corresponds to the submission queue 221-n. The fetch command management table 464-n includes multiple entries, each of which corresponds to one command. The number of entries included in the fetch command management table 464-n is, for example, MAXFN (the maximum number of commands that can be fetched within the timeout period TOn). Each entry stores the contents of the submission queue entry and an extension pointer.

[0129] The content of the submission queue entry is information indicating the content of the corresponding command. The content of the submission queue entry includes, for example, information indicating the type of command, a logical address specified by the command, a command ID, and a CID. If the corresponding command is a write command, the content of the submission queue entry includes, for example, information indicating the write command, a logical address corresponding to the write data, an address on the RAM 22 where the write data is stored, a CID, etc. Also, if the corresponding command is a read command, the content of the submission queue entry includes, for example, information indicating the read command, a logical address corresponding to the read data, an address on the RAM 22 where the read data is to be stored, a CID, etc.

[0130] The extension pointer indicates the slot of the submission queue 221-n in which the corresponding command was stored. The extension pointer includes the SQHP461-n at the time the command was fetched, and a cycle counter. When SQTP4111-n indicates a slot after SQHP461-n, the same value as the cycle counter included in SQETP463-n is used as this cycle counter, and when SQTP4111-n indicates a slot before SQHP461-n, the value obtained by subtracting 1 from the cycle counter included in SQETP463-n is used.

[0131] When the controller 4 fetches a command from the submission queue 221-n, it selects one free entry from among the multiple entries contained in the fetch command management table 464-n. Then, the controller 4 stores the content of the submission queue entry and the extension pointer related to the fetched command in the selected entry. Then, it advances the SQHP by one.

[0132] When the processing of the fetched command is completed, the controller 4 invalidates the entry in the fetch command management table 464-n corresponding to the command. When invalidating an entry in the fetch command management table 464-n, the controller 4 deletes the contents of the entry. Alternatively, the controller 4 may have information in each entry indicating whether the entry in the fetch command management table 464-n is valid or not, and may invalidate the entry by updating the entry to a value indicating invalidity, and set the entry to a state in which information on a new command can be stored. Therefore, a valid entry in the fetch command management table 464-n corresponds to a command that has been fetched and whose processing has not been completed. Hereinafter, a case where information stored in an entry in the fetch command management table 464-n is deleted when the entry is invalidated will be described.

[0133] Next, a configuration example of the time slot management table 471-n will be described. Fig. 13 is a diagram showing a configuration example of the time slot management table 471-n used in the memory system 3 according to the embodiment.

[0134] The time slot management table 471-n corresponds to the submission queue 221-n. The time slot management table 471-n includes a plurality of entries, each of which corresponds to one time slot. For example, when the timeout time TOn is expressed as Mn×Tn, the time slot management table 471-n has (Mn+1) entries. Each entry stores the SQETP 463-n for each Tn. The initial value of each entry is, for example, the initial value of the extension pointer. The initial value of the extension pointer includes, for example, a cycle counter indicating 0 and a pointer indicating the slot SLT0.

[0135] For example, when Tn has elapsed since the start of operation, the controller 4 selects the entry with row number 0 as the entry in which the extension pointer corresponding to the first time slot TSn,1 should be stored. Then, after temporarily saving information indicating the extension pointer previously stored in the selected entry to the first EP 465-n of the SRAM 46, the controller 4 stores the current SQETP 463-n in the entry with row number 0. In other words, the SQETP 463-n stored in the entry of the time slot management table 471-n is the SQETP 463-n at the end time of the time slot corresponding to this entry.

[0136] Thereafter, each time Tn elapses, the controller 4 selects a new entry, and stores SQETP 463-n at that time in the selected entry as an extension pointer corresponding to the time slot at that time.

[0137] When (Mn+1)×Tn has elapsed since the start of operation, the controller 4 selects the entry with row number Mn as the entry in which the extension pointer corresponding to time slot TSn, Mn+1 should be stored. Then, after temporarily saving information indicating the extension pointer previously stored in the selected entry to the first EP 465-n of SRAM 46, the controller 4 stores the current SQETP 463-n in the entry with row number Mn. Here, the extension pointer saved in SRAM 46 is the initial value.

[0138] Furthermore, when (Mn+1)×Tn has elapsed since the start of operation, timeout time TOn (=Mn×Tn) has elapsed since the end time of the first time slot TSn,1. At this time, controller 4 designates time slot TSn,1 as the time slot subject to timeout. Furthermore, when the coefficient of the timeout time is Mn and the number of entries contained in time slot management table 471-n is Mn+1, after (Mn+1)×Tn has elapsed since the start of operation, controller 4 may determine that the entry next to the entry in which new SQETP 463-n is stored is the entry corresponding to the time slot subject to timeout.

[0139] Then, the controller 4 acquires an extension pointer (hereinafter referred to as a first extension pointer (EP)) corresponding to the time slot immediately preceding the time slot to be timed out, which is the extension pointer saved in the SRAM 46, and an extension pointer (hereinafter referred to as a second extension pointer) corresponding to the time slot to be timed out from the entry corresponding to the time slot to be timed out. For example, when the first extension pointer and the second extension pointer are different, the controller 4 searches for a command corresponding to the time slot to be timed out. The command corresponding to the time slot to be timed out is a command stored in a slot included in the range from the slot indicated by the first extension pointer to the slot immediately preceding the slot indicated by the second extension pointer.

[0140] Furthermore, if the first extension pointer and the second extension pointer are the same, no command has been issued during the time slot that is the target of the timeout, and therefore the controller 4 determines that timeout processing is unnecessary.

[0141] Next, a configuration example of the time slot management table 473-n when the time has progressed to S×Tn (S is an integer greater than Mn+1) will be described. Fig. 14 is a diagram showing an example of a first state of the time slot management table 473-n used in the memory system 3 according to the embodiment.

[0142] In FIG. 14, the entry corresponding to row number 0 corresponds to time slot TSn, S-2, and stores SQETP463-n of time (S-2)×Tn.

[0143] The entry corresponding to row number 1 corresponds to time slot TSn, S-1, and stores SQETP463-n of time (S-1)×Tn.

[0144] The entry corresponding to row number 2 corresponds to time slot TSn,S, and stores SQETP463-n at time S×Tn.

[0145] The entry corresponding to row number 3 corresponds to time slot TSn, S-Mn, and stores SQETP463-n of time (S-Mn)×Tn.

[0146] The entry corresponding to row number 4 corresponds to time slot TSn, S-Mn+1, and stores SQETP463-n of time (S-Mn+1)×Tn.

[0147] The entry corresponding to row number Mn-1 corresponds to time slot TSn, S-4, and stores SQETP463-n at the time (S-4)×Tn.

[0148] The entry corresponding to row number Mn corresponds to time slot TSn, S-3, and stores SQETP463-n at the time (S-3)×Tn.

[0149] At this time, the entry corresponding to the latest time slot is the entry corresponding to row number 2. The time slot to be timed out is TSn,S-Mn, and the entry corresponding to the time slot to be timed out is the entry corresponding to row number 3. The controller 4 acquires the extension pointer stored in the entry corresponding to row number 3 as the second EP. In addition, before the extension pointer corresponding to time slot TSn,S is stored in the entry corresponding to row number 2, the controller 4 saves the extension pointer of time slot TSn,S-Mn-1 stored in the entry corresponding to row number 2 in SRAM 46 as the first EP.

[0150] If the first EP and the second EP have the same value, the controller 4 determines that no command was issued between the timeout target TSn and S-Mn. If the first EP and the second EP have different values, the controller 4 identifies a command corresponding to an extension pointer included in the range from the first EP to the extension pointer immediately before the second EP, and executes a timeout process to abort the identified command. A command that was stored (or is being stored) in a slot of a virtual submission queue indicated by a certain extension pointer is called a command corresponding to that extension pointer.

[0151] Next, a configuration example of the time slot management table 471-n in the case where one command is issued in the time slot TSn, S-Mn, and the time progresses to S×Tn without issuing a subsequent command will be described. Fig. 15 is a diagram showing an example of a second state of the time slot management table 471-n used in the memory system 3 according to the embodiment.

[0152] 15, the entry corresponding to row number 0 corresponds to time slot TSn, S-2, and stores SQETP463-n of time (S-2) × Tn. The value of the extended pointer stored in this entry is X, and X includes, for example, a cycle counter indicating C and a pointer indicating P.

[0153] The entry corresponding to row number 1 corresponds to time slot TSn, S-1, and stores SQETP463-n of time (S-1) x Tn. The value of the extension pointer stored in this entry is X.

[0154] The entry corresponding to row number 2 is an entry updated at time S×Tn. The entry corresponding to row number 2 before the update corresponds to time slot TSn,S-(Mn+1), and stores SQETP463-n at time (S-(Mn+1))×Tn. The value of the extension pointer stored in the entry before the update is X-1. X-1 includes, for example, a cycle counter indicating C and a pointer indicating (P-1). The extension pointer before the update stored in the entry corresponding to row number 2 is temporarily stored in SRAM 46 when the entry is updated. The entry corresponding to row number 2 after the update corresponds to time slot TSn,S, and stores SQETP463-n at time S×Tn. The value of the extension pointer stored in the entry after the update is X.

[0155] The entry corresponding to row number 3 corresponds to the time slot TSn, S-Mn, and stores SQETP463-n of time (S-Mn) x Tn. The value of the extension pointer stored in this entry is X.

[0156] The entry corresponding to row number 4 corresponds to the time slot TSn, S-Mn+1, and stores SQETP463-n of the time (S-Mn+1)×Tn. The value of the extension pointer stored in this entry is X.

[0157] The entry corresponding to row number Mn-1 corresponds to time slot TSn, S-4, and stores SQETP463-n at the time (S-4) x Tn. The value of the extension pointer stored in this entry is X.

[0158] The entry corresponding to row number Mn corresponds to time slot TSn, S-3, and stores SQETP463-n at the time (S-3) x Tn. The value of the extension pointer stored in this entry is X.

[0159] At this time, the entry corresponding to the latest time slot is the entry corresponding to row number 2. The time slot to be timed out is TSn,S-Mn, and the entry corresponding to the time slot to be timed out is the entry corresponding to row number 3. The controller 4 acquires the extension pointer stored in the entry corresponding to row number 3 as the second EP. The controller 4 also acquires the extension pointer stored in the entry corresponding to row number 2 before the update as the first EP from the SRAM 46. This first EP corresponds to the time slot TSn,S-(Mn+1). The controller 4 determines that the command corresponding to the extension pointer included in the range from the first EP to the extension pointer immediately before the second EP is the command to be timed out. Here, since the value of the first EP is X-1 and the value of the second EP is X, one command corresponding to X-1 (i.e., the first EP) is the command corresponding to the time slot TSn,S-(Mn+1). Only one command corresponding to the first EP is a command that can be the target of the timeout process.

[0160] The controller 4 judges whether or not there is an EP that is equal to or greater than the first EP and equal to or less than the EP immediately preceding the second EP among the extension pointers stored in the fetch command management table 462-n. Here, the controller 4 judges whether or not information on a command corresponding to an EP that is equal to or greater than the first EP and equal to or less than the EP immediately preceding the second EP is stored in the fetch command management table 464-n. The command whose information is stored in the fetch command management table 464-n is a command that has been fetched from the submission queue 221-n and has not yet been processed. Therefore, the controller 4 executes a timeout process for the corresponding command. As a result, the controller 4 aborts the corresponding command. The processing of the aborted command is interrupted, and a completion response including information indicating that it has been aborted is issued to the host 2.

[0161] Also, if the command corresponding to the EP is still stored in the submission queue 221-n, the controller 4 fetches the corresponding command. Then, the controller 4 aborts the fetched command. If the EP is equal to or greater than the extension pointer corresponding to the current SQHP, the controller 4 determines that the command corresponding to the EP is still stored in the submission queue 221-n and that the command subject to timeout is stored in the submission queue 221-n. Note that when checking the EPs one by one starting from the first EP, if the extension pointer reaches the current SQHP at a certain point, all the EPs up to the EP before the second EP are stored in the submission queue 221-n, so there is no need to repeat the determination.

[0162] Next, as a method of searching for a command corresponding to a time slot that is a timeout target, a case will be described in which the correspondence between the command and the information indicating the time slot is managed in the fetch command management table 464-0, ..., 464-v. Fig. 16 is a diagram showing a modified example of the fetch command management table 464-n used in the memory system 3 according to the embodiment. Here, each of a plurality of entries in the fetch command management table 464-n stores the row number of the time slot management table 471-n corresponding to the time slot corresponding to each command.

[0163] The fetch command management table 464-n corresponds to the submission queue 221-n. The fetch command management table 464-n includes a plurality of entries, each of which corresponds to one command. The number of entries included in the fetch command management table 464-n is, for example, MAXFN. Each entry stores the contents of the submission queue entry and the row number of the time slot management table 471-n.

[0164] The content of a submission queue entry is information indicating the content of the corresponding command.

[0165] The row number of the time slot management table 471-n is information indicating the row number of the time slot management table 471-n corresponding to the time slot including the time when the corresponding command was issued to the submission queue 221-n.

[0166] When the controller 4 fetches one command from the submission queue 221-n, the controller 4 selects one free entry from among the multiple entries in the fetch command management table 464-n, and associates the fetched command with the selected entry.

[0167] The controller 4 stores information indicating the contents of the fetched command and the row number of the time slot management table 471-n in the associated entry. Here, the controller 4 holds the stored row number of the time slot management table 471-n during startup, and its initial value is the row number of the rows of the time slot management table 471-n that is written first. This row number is used by the controller 4 to specify the row number of the time slot management table 471-n when the controller 4 fetches a subsequent command. Specifically, the controller 4 determines whether or not the extension pointer corresponding to the fetched command is smaller than the extension pointer corresponding to the row number of the time slot management table 471-n it holds. If the extension pointer corresponding to the fetched command is smaller than the extension pointer corresponding to the row number of the time slot management table 471-n it holds, the controller 4 determines that the fetched command corresponds to the same time slot as the command fetched last time. Then, the controller 4 stores the row number of the time slot management table 471-n it holds in the associated entry. If the extension pointer corresponding to the fetched command is the extension pointer corresponding to the row number of the held timeslot management table 471-n, the controller 4 acquires the extension pointer corresponding to the row number obtained by adding 1 to the row number of the held timeslot management table 471-n, and compares it with the extension pointer corresponding to the re-fetched command. The controller 4 continues until the extension pointer corresponding to the fetched command becomes smaller than the extension pointer corresponding to the row number of the timeslot management table 471-n, and stores the row number one before the row number in the timeslot management table 471-n when this condition is satisfied in the associated entry, and updates the initial value row number of the held timeslot management table 471-n.

[0168] When the processing of a fetched command is completed, the controller 4 invalidates the entry in the fetch command management table 464-n corresponding to that command. Therefore, a valid entry in the fetch command management table 464-n corresponds to a command that has been fetched but whose processing has not been completed.

[0169] By using such a fetch command management table 464-n, the size of the storage area required for the fetch command management table 464-n can be reduced compared to the case where an extension pointer is stored in each entry. This is because the size of the field indicating the row number of the time slot management table 471-n is smaller than the size of the extension pointer field. Furthermore, when identifying a command to be timed out, the controller 4 does not determine whether the EP corresponding to each command is in the range of the first EP or more and the EP immediately before the second EP or less, but determines whether the row number corresponding to each command matches the row number corresponding to the time slot to be timed out. Therefore, the controller 4 does not need to perform the comparison of the extension pointers using the first method or the second method described above, and can perform the timeout process faster.

[0170] However, when such a fetch command management table 464-n is used, the controller 4 needs to convert the extension pointer into a row number of the time slot management table 471-n every time a command is fetched. Therefore, the resources required for command fetch processing may increase due to an increase in the number of accesses to the time slot management table 471-n and temporarily storing the row number of the time slot management table 471-n corresponding to the previously fetched command.

[0171] Next, the time slots corresponding to each of the multiple slots of the virtual submission queue 221-n will be described. Fig. 17 is a diagram showing an example of the relationship between the virtual submission queues managed in the memory system 3 according to the embodiment and the multiple time slots.

[0172] The SQ extended head pointer (SQEHP) points to EP(j+2,SIZEn-2). The EHP points to the first slot of virtual slots that may correspond to commands that have been fetched but are not yet completed, but the command in the slot pointed to by the EHP itself has been fetched but is not yet completed, and the command in the slot beyond that has been fetched but may be both completed and incomplete. When the command in the slot pointed to by the EHP is completed, the EHP is updated to an EP that points to the slot corresponding to the next command that has been fetched but is not yet completed. When there are no more commands that have been fetched but are not yet completed, the EHP advances to the same location as the SQHP. If a new command is fetched here, only the SQHP advances, and the EHP again points to the slot corresponding to the command that has been fetched but is not yet completed.

[0173] The SQ host head pointer (SQHHP) corresponds to EP(j, k+2). The SQHHP is an SQHP managed by the host 2. The SQHHP indicates the memory position of the oldest slot in the memory area corresponding to the submission queue 221-n on the RAM 22 where the host 2 must still hold data.

[0174] The SQ head pointer (SQHP) corresponds to EP(j, SIZEn-2). The SQHP is managed by the controller 4. The HP indicates the slot in which the next command to be fetched is stored.

[0175] The SQ extension tail pointer (SQETP) indicates EP(j+1,k). SQETP is an extension pointer corresponding to the SQTP managed by the controller 4. SQETP indicates the slot in which the next command to be issued should be stored. Therefore, from the perspective of the controller 4, the slot immediately before the slot indicated by SQETP is the slot in which the latest command is stored.

[0176] The SQ host tail pointer (SQHTP) corresponds to EP(j+1,k+1). The SQHTP is an SQTP managed by the host 2, and indicates the slot in which the next command to be issued is stored. Since the SQHTP indicates the slot immediately preceding the slot indicated by the SQHHP, the submission queue 221-n is in a full state as viewed from the host 2. Therefore, the SQHTP in FIG. 17 indicates a slot in which no command is stored, among the multiple slots of the full-state submission queue 221-n.

[0177] A time slot TSn,N-Mn is the time range from time (t+(N-Mn-1))×Tn to time (t+(N-Mn))×Tn. A command corresponding to a time slot TSn,N-Mn is a command stored in a slot included in the range from EP(j+2,SIZEn-2) to EP(j+3,k-1).

[0178] Time slot TSn,N-Mn+1 is the time range from time (t+(N-Mn))×Tn to time (t+(N-Mn+1))×Tn. The command corresponding to time slot TSn,N-Mn+1 is the command stored in the slot included in the range from EP(j+3,k) to EP(j+3,SIZEn-2).

[0179] Time slot TSn,N-Mn+2 is the time range from time (t+(N-Mn+1))×Tn to time (t+(N-Mn+2))×Tn. Of the commands corresponding to time slot TSn,N-Mn+2, the first issued command is the command stored in the slot indicated by EP(j+3,SIZEn-1).

[0180] And time slot TSn,K-9 is the time range from time (t+(K-10))×Tn to time (t+(K-9))×Tn. Of the commands corresponding to time slot TSn,K-9, the last issued command is the command stored in the slot indicated by EP(MAXCC-2,0).

[0181] No command has been issued in the time range corresponding to time slot TSn,K-8, so there is no EP corresponding to time slot TSn,K-8 in FIG.

[0182] Time slot TSn,K-7 is the time range from time (t+(K-8))×Tn to time (t+(K-7))×Tn. The command corresponding to time slot TSn,K-7 is the command stored in the slot included in the range from EP(MAXCC-2,1) to EP(MAXCC-2,k+1).

[0183] No command has been issued in the time range corresponding to time slot TSn,K-6, so there is no EP corresponding to time slot TSn,K-6 in FIG.

[0184] Time slot TSn,K-5 is the time range from time (t+(K-6))×Tn to time (t+(K-5))×Tn. The command corresponding to time slot TSn,K-5 is the command stored in the slot included in the range from EP(MAXCC-2,k+2) to EP(MAXCC-1,1).

[0185] Time slot TSn,K-4 is the time range from time (t+(K-5))×Tn to time (t+(K-4))×Tn. The command corresponding to time slot TSn,K-4 is the command stored in the slot included in the range from EP(MAXCC-1,2) to EP(MAXCC-1,k+3).

[0186] Time slot TSn,K-3 is the time range from time (t+(K-4))×Tn to time (t+(K-3))×Tn. The command corresponding to time slot TSn,K-3 is the command stored in the slot included in the range from EP(MAXCC-1,SIZEn-3) to EP(0,k).

[0187] Time slot TSn,K-2 is the time range from time (t+(K-3))×Tn to time (t+(K-2))×Tn. The command corresponding to time slot TSn,K-2 is a command stored in a slot included in the range from EP(0,k+1) to EP(1,0).

[0188] Time slot TSn,K-1 is the time range from time (t+(K-2))×Tn to time (t+(K-1))×Tn. The command corresponding to time slot TSn,K-1 is the command stored in the slot included in the range from EP(1,1) to EP(1,SIZEn-3).

[0189] A time slot TSn,K is the time range from time (t+(K-1))×Tn to time (t+K)×Tn. Of the commands corresponding to a time slot TSn,K, the first issued command is the command stored in the slot indicated by EP(1,SIZEn-2).

[0190] And time slot TSn,N-2 is the time range from time (t+(N-3))×Tn to time (t+(N-2))×Tn. Of the commands corresponding to time slot TSn,N-2, the last issued command is the command stored in the slot indicated by EP(j,1).

[0191] The time slot TSn,N-1 is the time range from time (t+(N-2))×Tn to time (t+(N-1))×Tn. The command corresponding to the time slot TSn,N-1 is the command stored in the slot included in the range from EP(j,2) to EP(j,SIZEn-1).

[0192] A time slot TSn,N is the time range from time (t+(N-1))×Tn to time (t+N)×Tn. The command corresponding to the time slot TSn,N is a command stored in a slot included in the range from EP(j+1,0) to EP(j+1,k-1).

[0193] Time slot TSn,N+1, not shown, is the time range from time (t+N)×Tn to time (t+N+1)×Tn. If host 2 writes the value of SQHTP in EP(j+1,k+1) to the SQTP doorbell register by time (t+N+1)×Tn, the command contained in EP(j+1,k) will be the command corresponding to time slot TSn,N+1. If the writing to the doorbell register is delayed, the command will be the command corresponding to the time slot according to that time.

[0194] Next, a search for a command in a timeout process will be described. FIG. 18 is a diagram showing an example of management of issued commands in the memory system 3 according to the embodiment. For the sake of explanation, FIG. 18 shows both the row number LN of the time slot management table 471-n and the extension pointer EP for each entry of the fetch command management table 464-n. The row number LN(N) is a row number indicating an entry of the time slot management table 471-n corresponding to the time slot TSn,N. The extension pointer EP(X) stored in the entry of the fetch command management table 464-n is an extension pointer indicating the slot SLT X of the virtual submission queue 221-n. The entry of the fetch command management table 464-n only needs to hold either the row number or the extension pointer. In addition, instead of the row number used in FIG. 18, a time slot number indicating a time slot may be used, and instead of the extension pointer, a slot number indicating a slot of the virtual submission queue 221-n may be used.

[0195] 18, time slot management table 471-n has Mn+1 entries. Extended pointer EP(N) stored in an entry of time slot management table 471-n is SQETP 463-n at the end time of time slot TSn,N.

[0196] The 0th entry before the update of the time slot management table 471-n corresponds to the time slot TSn,N-1. The extension pointer stored in the 0th entry before the update is EP(N-1) indicating SQETP463-n at the end time of the time slot TSn,N-1. EP(N-1) indicates the slot SLT X-3 of the virtual submission queue 221-n. Moreover, the 0th entry after the update corresponds to the time slot TSn,N+Mn. The extension pointer stored in the 0th entry after the update is EP(N+Mn) indicating SQETP461-n at the end time of the time slot TSn,N+Mn. EP(N+Mn) indicates the slot SLT Z of the virtual submission queue 221-n.

[0197] The entry in the first row corresponds to the time slot TSn,N. The extension pointer stored in the entry in the first row is EP(N) indicating the SQETP 461-n at the end time of the time slot TSn,N. EP(N) indicates the slot SLT X of the virtual submission queue 221-n.

[0198] The entry on the second row corresponds to time slot TSn,N+1. The extension pointer stored in the entry on the second row is EP(N+1) indicating SQETP463-n at the end time of time slot TSn,N+1. The entry on the third row corresponds to time slot TSn,N+2. The extension pointer stored in the entry on the third row is EP(N+2) indicating SQETP463-n at the end time of time slot TSn,N+2. The entry on the third row corresponds to time slot TSn,N+2.

[0199] The entry in the Mnth row corresponds to the time slot TSn,N+Mn-1. The extension pointer stored in the entry in the Mnth row is EP(N+Mn-1) that indicates SQETP463-n at the end time of the time slot TSn,N+Mn-1.

[0200] The fetch command management table 464-n holds information about commands that have been fetched from the submission queue 221-n and have not yet been processed. Here, we will explain both the row number and the extension pointer of the time slot management table 471-n that can be stored in the entry of the fetch command management table 464-n.

[0201] The command corresponding to the first entry in the fetch command management table 464-n is a read command. The fetch data includes information indicating that it is a read command and an LBA range from LBA G to LBA H. The first entry holds either a row number LN(N+5), which is the row number of the time slot management table 471-n corresponding to the time slot TSn,N+5, or an extension pointer EP(X+3) indicating the slot SLT X+3 of the virtual submission queue 221-n.

[0202] The command corresponding to the second entry in the fetch command management table 464-n is a read command. The fetch data includes information indicating that it is a read command and the logical address range from LBA A to LBA B. The second entry holds either a row number LN(N), which is the row number of the time slot management table 471-n corresponding to the time slot TSn,N, or an extension pointer EP(X-3) indicating the slot SLT X-3 of the virtual submission queue 221-n.

[0203] The command corresponding to the third entry in the fetch command management table 464-n is a write command. The fetch data includes information indicating that it is a write command and the logical address range from LBA C to LBA D. The third entry holds either a row number LN(N) which is the row number of the time slot management table 471-n corresponding to the time slot TSn,N, or an extension pointer EP(X-1) which indicates the slot SLT X-1 of the virtual submission queue 221-n.

[0204] The command corresponding to the fourth entry in the fetch command management table 464-n is a write command. The fetch data includes information indicating that it is a write command and a logical address range from LBA E to LBA F. The fourth entry holds either a row number LN(N+2) which is the row number of the time slot management table 471-n corresponding to the time slot TSn,N+2, or an extension pointer EP(X+1) which indicates the slot SLT X+1 of the virtual submission queue 221-n.

[0205] Moreover, a plurality of slots from slot SLT X-3 to slot SLT Z are slots of a virtual submission queue 221-n indicated by an extension pointer.

[0206] The slot SLT X-3 is a slot indicated by the extension pointer EP(N-1) corresponding to the time slot TSn,N-1, and is the first virtual slot of commands that have been fetched from the submission queue 221-n but are not yet processed, and is a virtual slot to which commands that have been fetched but are not yet processed may correspond thereafter. In other words, it is also a virtual slot to which commands that have been completed may correspond thereafter.

[0207] A slot SLT X is a slot indicated by an extension pointer EP(N) corresponding to a time slot TSn,N.

[0208] Slot SLT Y is the slot indicated by SQHP461-n.

[0209] Slot SLT Z is a slot indicated by the extension pointer EP(N+Mn) corresponding to SQTP4111-n and time slot TSn,N+Mn. Since it is the slot indicated by SQTP at the time of this drawing, it is still empty from the viewpoint of memory system 3.

[0210] At the end time of time slot TSn,N+Mn, the controller 4 designates time slot TSn,N as a time slot subject to timeout. The controller 4 executes timeout processing for commands that have not yet been processed among the commands corresponding to time slot TSn,N.

[0211] First, a case will be described where a command subject to timeout is identified using the extension pointer stored in the fetch command management table 464-n. The controller 4 acquires the saved extension pointer EP(N-1) corresponding to the time slot TSn,N-1 immediately preceding the time slot TSn,N subject to timeout, and the extension pointer EP(N) corresponding to the time slot TSn,N subject to timeout. The controller 4 then uses the acquired extension pointer EP(N) and extension pointer EP(N-1) to identify the command subject to timeout.

[0212] The controller 4 identifies the range of virtual slots that may correspond to commands for which processing has not yet been completed. This range is from the extension pointer EP(N-1) to the slot immediately preceding the extension pointer EP(N). In other words, it is from slot SLT X-3 to slot SLT X-1.

[0213] Next, the controller 4 identifies the extension pointers that indicate the slots included in the range from slot SLT X-3 to slot SLT X-1 among the extension pointers stored in the fetch command management table 464-n. As a result, the controller 4 identifies the commands corresponding to the second entry storing the extension pointer EP(X-3) that indicates slot SLT X-3 and the third entry storing the extension pointer EP(X-1) that indicates slot SLT X-1 as the commands that are subject to timeout. In some cases, EP(N) may be after SQHP. In this case, the commands corresponding to the slots from SQHP to the slot just before EP(N) are also the commands that are subject to timeout, and are fetched and immediately aborted. This occurs when the fetch command management table 464-n is full and the timeout is reached without the commands in the submission queue 221-n being fetched. At this time, the commands in the fetch command management table 464-n have been aborted earlier, so there is space in the fetch command management table 464-n, and it is possible to fetch a new command for the abort process.

[0214] On the other hand, the controller 4 may use the row number of the time slot number management table 471-n stored in the fetch command management table 464-n when identifying the command to be timed out. In this case, when the controller 4 identifies that the time slot to be timed out is TSn,N, it identifies an entry that stores the row number LN(N) corresponding to the time slot TSn,N among the multiple entries in the fetch command management table 464-n. Then, the controller 4 executes timeout processing for the command corresponding to the identified entry. As a result, the controller 4 identifies that the commands corresponding to the second entry and the third entry that store the row number LN(N) are the commands to be timed out. Note that even in this case, if EP(N) is after SQHP, it is necessary to fetch and abort the commands stored in the slots from SQHP to one before EP(N) as described above.

[0215] Next, control of the timing of timeout processing for a plurality of submission queues will be described. Fig. 19 is a diagram showing an example of the timing of timeout processing in the memory system 3 according to the embodiment. Here, it is assumed that the timeout processing is executed for each of two submission queues, the submission queue 221-0 and the submission queue 221-1.

[0216] First, every time the time T0 elapses, the controller 4 determines whether or not there is a command that is subject to timeout among the commands issued via the submission queue 221-0.

[0217] Moreover, every time the time T1 elapses, the controller 4 determines whether or not there is a command that is subject to timeout among the commands issued via the submission queue 221-1.

[0218] Each of the times T0 and T1 is set to an integer multiple of the interval time Tc of the timer 43. For example, the controller 4 sets the time T0 to 2×Tc and the time T1 to 4×Tc. In this case, the controller 4 can set the frequency at which the timeout process is executed for the submission queue 221-0 to twice the frequency at which the timeout process is executed for the submission queue 221-1. Furthermore, the length of a time slot in the submission queue 221-0 is half the length of a time slot in the submission queue 221-1.

[0219] The controller 4 sets the timeout time TO0 of the command issued via the submission queue 221-0 to M0×T0. M0 is, for example, an integer equal to or greater than 1. Therefore, the timeout time TO0 is also an integer multiple of the interval time Tc. Moreover, the controller 4 sets the timeout time TO1 of the command issued via the submission queue 221-1 to M1×T1. M1 is, for example, an integer equal to or greater than 1. Thus, the timeout time TO1 is also an integer multiple of the interval time Tc.

[0220] Furthermore, the controller 4 may shift the start timing of the times T0 and T1 in units of Tc. For example, the controller 4 starts counting the time T1 in the submission queue 221-1 after Tc has elapsed since starting counting the time T0 in the submission queue 221-0. This allows the controller 4 to set the timeout process for the submission queue 221-0 and the timeout process for the submission queue 221-1 to be executed at different times.

[0221] FIG. 19 shows the timing of the timeout process when time T0 is set to 2×Tc, time T1 is set to 4×Tc, time T0 starts from 0×Tc, and time T1 starts from 1×Tc.

[0222] For the submission queue 221-0, counting of the time T0 starts at time 0×Tc. Then, the controller 4 executes timeout processing at times 2×Tc, 4×Tc, 6×Tc, 8×Tc, and 10×Tc.

[0223] For the submission queue 221-1, counting of the time T1 starts at time 1×Tc. Then, the controller 4 executes timeout processing at times 5×Tc and 9×Tc.

[0224] In this way, by setting different times T0, ..., Tv for each of the multiple submission queues 221-0, ..., 221-v, the controller 4 can set a time interval for executing timeout processing for each submission queue. This allows the controller 4 to reduce the possibility of timeout processing for multiple submission queues concentrating at the same time, depending on the time that is set.

[0225] Next, the flow of command processing will be described. Fig. 20 is a sequence diagram showing an example of a procedure of command processing executed in the memory system 3 and the host 2 according to the embodiment. Here, it is assumed that the host 2 and the memory system 3 transmit and receive a command and a completion response via the submission queue 221-n and the completion queue 222-m. The host 2 starts command processing in response to the preparation of a command to be transmitted to the memory system 3.

[0226] First, the host 2 stores a prepared command in the submission queue 221-n (step S101). At this time, the host 2 issues the command by storing the command in a slot indicated by the SQHTP 224-n.

[0227] The host 2 updates the SQHTP 224-n (step S102). As a result, the host 2 increments the SQHTP 224-n by the number of commands issued in S101.

[0228] The host 2 updates SQTP4111-n, which is the submission queue tail doorbell register (step S103). The host 2 sets SQTP4111-n to the value of SQHTP224-n updated in S102.

[0229] The memory system 3 updates SQETP463-n (step S104). If the value of SQTP4111-n updated in S103 is smaller than the value of SQTP4111-n before the update, the memory system 3 increments the cycle counter included in SQETP463-n by 1. Then, the memory system 3 updates SQETP463-n using SQTP4111-n updated in S103.

[0230] The memory system 3 fetches a command from the submission queue 221-n (step S105). Specifically, it reads the contents of the slot pointed to by the SQHP 461-n. The memory system 3 identifies the number of unfetched commands stored in the submission queue 221-n from the difference between the SQTP 4111-n updated in S103 and the SQHP 461-n. It also identifies the number of invalid entries in the fetch command management table 464-n corresponding to the submission queue 221-n. If the identified number of unfetched commands is greater than the number of invalid entries, it fetches commands equal to the number of invalid entries, otherwise it fetches commands equal to the number of unfetched commands. The commands that could not be fetched at this time are fetched after an invalid entry occurs.

[0231] The memory system 3 updates the fetch command management table 464-n so as to store information about the command fetched in S105 (step S106). The memory system 3 stores, for example, the contents of the fetched command, the ID of the submission queue 221-n in which the fetched command was stored, the CID written in the slot of the submission queue 221-n in which the fetched command was stored, and an extension pointer indicating the slot in the fetch command management table 464-n. Alternatively, instead of the extension pointer indicating the slot of the submission queue 221-n in which the fetched command was stored, information indicating a time slot corresponding to the fetched command may be stored in the fetch command management table 464-n.

[0232] The memory system 3 updates the SQHP 461-n (step S107). The memory system 3 increments the SQHP 461-n by the number of commands fetched in S105.

[0233] The memory system 3 executes the processing of the command fetched in S105 (step S108).

[0234] When the processing of the command being executed in S108 is completed, the memory system 3 issues a completion response corresponding to the command whose processing has been completed to the host 2 (step S109). The completion response includes the SQHP that has not yet been notified to the host 2 after being updated, the submission queue ID indicating the SQ corresponding to that SQHP, the ID of the submission queue in which the completed command was issued, the CID of that command, and the Phase Tag Bit. The memory system 3 stores the completion response in the completion queue 222-m of the host 2.

[0235] The memory system 3 updates the CQTP462-m (step S110).

[0236] The memory system 3 updates the fetch command management table 464-n (step S111). The memory system 3 invalidates the entry in the fetch command management table 464-n corresponding to the command whose processing has been completed.

[0237] The memory system 3 notifies the host 2 of an interrupt for notifying that the completion response has been issued (step S112). The interrupt may include a completion queue ID indicating the completion queue 222-m in which the completion response was stored in S111.

[0238] The host 2 processes the completion response in response to the interrupt notification in S112 (step S113). The host 2 executes the processing of the completion response stored in the completion queue indicated by the completion queue ID included in the interrupt. If the interrupt does not include a completion queue ID, a non-empty completion queue is identified from the value of the Phase Tag Bit and the value of CQHHP, and the updated entry included in that queue is processed to execute the completion response. The command prepared in step S101 can be identified from the submission queue ID and CID to which the command was issued, which are included in the completion response, and the host 2 executes the completion processing of the prepared command.

[0239] The host 2 updates the SQHHP managed by the host 2 based on the submission queue ID and SQHP included in the completion response processed in S113 (step S114). The host 2 updates the SQHHP to the value of the SQHP included in the completion response.

[0240] The host 2 updates the CQHHP 225-m (step S115). The host 2 increments the CQHHP 225-m based on the number of completion responses processed in S113.

[0241] The host 2 performs write access to the completion queue head doorbell register in the memory system 3 and updates the CQHP4112-m (step S116). The host 2 updates the CQHP4112-m to the CQHHP225-m updated in S115.

[0242] Next, an update process of the submission queue extension tail pointer (SQETP) will be described. Fig. 21 is a flowchart showing an example of the procedure of the update process of the submission queue extension tail pointer executed in the memory system 3 according to the embodiment. Here, a case is assumed in which a command is issued from the host 2 to the controller 4 of the memory system 3 via the submission queue 221-n. In response to the SQTP4111-n stored in the submission queue tail doorbell register being updated to a new value by the host 2, the controller 4 starts the update process of SQETP463-n.

[0243] The controller 4 acquires SQTP4111-n (hereinafter referred to as updated SQTP4111-n) from the SQ tail doorbell register (step S201).

[0244] The controller 4 acquires the SQTP (hereinafter referred to as the SQTP before update) from the pointer field of the SQETP 463-n (step S202).

[0245] The controller 4 judges whether the value of SQTP 4111-n after the update acquired in S201 is smaller than the value of SQTP before the update acquired in S202 (step S203). In this way, the controller 4 judges whether the value of the pointer has wrapped around from the value indicating the last slot of the submission queue 221-n to the value indicating the first slot in the current update of SQTP 4111-n.

[0246] If the updated SQTP4111-n value acquired in S201 is smaller than the pre-update SQTP value acquired in S202 (Yes in S203), the controller 4 judges whether the cycle counter is equal to the upper limit value (MAXCC-1) (step S204). This cycle counter is the value set in the cycle counter field of SQETP463-n.

[0247] If the cycle counter is not at the upper limit value (No in S204), the controller 4 increments the value set in the cycle counter field of SQETP463-n by 1 (step S205).

[0248] If the cycle counter is at the upper limit value (Yes in S204), the controller 4 sets the value of the cycle counter field of the SQETP 463-n to an initial value (step S206).

[0249] Then, the controller 4 sets the value of the pointer field of SQETP 463-n to the updated value of SQTP 4111-n (step S207), and ends the update process of SQETP.

[0250] Furthermore, if the updated value of SQTP4111-n obtained in S201 is greater than or equal to the pre-update value of SQTP4111-n obtained in S202 (No in S203), the controller 4 skips steps S204 to S206, sets the value of the pointer field of SQETP463-n to the updated value of SQTP4111-n (step S207), and terminates the update process of SQETP463-n.

[0251] In this way, the controller 4 updates the SQETP 463-n including the cycle counter in response to the host 2 updating the SQTP 4111-n.

[0252] Next, the update process of the time slot management table including the timeout process will be described. FIG. 22 is a flowchart showing the procedure of the process of recording the submission queue extension tail pointer executed in the memory system 3 according to the embodiment. Here, the update process of the time slot management table 471-n corresponding to the submission queue 221-n will be described. At this time, it is assumed that the current time is a time when the timeout time TOn or more has elapsed since the information on the first time slot was stored in the entry of the time slot management table 471-n. In addition, the number of multiple entries included in the time slot management table 471-n is Mn+1, and the timeout time TOn is Tn×Mn. Here, the controller 4 starts the update operation of the time slot management table 471-n every time Tn elapses.

[0253] The controller 4 saves the extension pointer (EP) stored in the entry corresponding to the time slot one older than the time slot to be timed out to the first EP 465-n of the SRAM 46 (step S301). Since the number of entries included in the time slot management table 471-n is Mn+1, the entry to be updated next is the entry corresponding to the time slot one older than the time slot to be timed out. In other words, the controller 4 saves the EP stored in the entry to be updated next to the first EP 465-n of the SRAM 46. If the time slot to be timed out is the first time slot, the EP to be saved indicates the initial value.

[0254] The controller 4 records the current SQETP 463-n in the time slot management table 471-n (step S302). The controller 4 records the current SQETP 463-n in the entry where the EP was saved in S301.

[0255] The controller 4 executes a timeout process (step S303). An example of a specific procedure for the timeout process will be described later with reference to FIGS.

[0256] The controller 4 deletes the EP saved in S301 (step S304).

[0257] In this way, the controller 4 stores the SQETP 461-n corresponding to the submission queue 221-n in the time slot management table 471-n every time Tn elapses. This allows the controller 4 to record the SQETP 463-n at the end time of each time slot corresponding to the submission queue 221-n.

[0258] Next, a description will be given of the timeout processing executed in S303 of Fig. 22 when an extension pointer is stored in the fetch command management table. Fig. 23 is a flowchart showing a first example of the procedure of the timeout processing executed in the memory system 3 according to the embodiment.

[0259] The controller 4 acquires the EP (first EP 465-n) saved in S301 of Fig. 22 from the SRAM 46 (step S401). The first EP 465-n is SQETP 463-n at the end time of the time slot one earlier than the time slot to be timed out, or an initial value.

[0260] The controller 4 acquires an EP (second EP) corresponding to the time slot to be timed out from the time slot management table 471-n (step S402). The second EP is SQETP 463-n at the end time of the time slot to be timed out.

[0261] The controller 4 determines whether or not the first EP 465-n acquired in S401 matches the second EP acquired in S402 (step S403).

[0262] If the first EP 465-n and the second EP match (Yes in S403), the controller 4 determines that there is no command corresponding to the time slot that is the target of the timeout, and ends the timeout process.

[0263] If the first EP 465-n and the second EP do not match (No in S403), the controller 4 determines whether or not the fetch command management table 464-n contains a command associated with an EP included in the range from the first EP 465-n to the EP just before the second EP (step S404).

[0264] If the fetch command management table 464-n contains a command associated with an EP included in the range from the first EP 465-n to the EP immediately before the second EP (Yes in S404), the controller 4 aborts the command (step S405). The controller 4 interrupts the process corresponding to the command, and issues a completion response corresponding to the command to the host 2. The issued completion response includes information indicating that the command has been aborted.

[0265] The controller 4 updates the fetch command management table 464-n so as to invalidate the entry corresponding to the command aborted in S405 (step S406).

[0266] If the fetch command management table 464-n does not contain a command associated with an EP included in the range from the first EP 465-n to the EP immediately preceding the second EP (No in S404), the controller 4 skips the steps of S405 and S406.

[0267] Then, the controller 4 judges whether the second EP is a value larger than the EP corresponding to the current SQHP 461-n (step S407).

[0268] If the second EP is larger than the EP corresponding to the current SQHP 461-n (Yes in S407), the controller 4 determines that a command subject to timeout is stored in the submission queue 221-n. Then, the controller 4 fetches the command subject to timeout from the submission queue 221-n (step S408). The controller 4 aborts the command fetched in S408 (step S409). The controller 4 issues a completion response corresponding to the command fetched in S408 to the host 2. The issued completion response includes information indicating that the command fetched in S408 has been aborted.

[0269] Moreover, if the second EP is equal to or smaller than the EP corresponding to the current SQHP 461-n (No in step S407), the controller 4 ends the timeout process.

[0270] In this way, the controller 4 can identify commands that are subject to timeout processing by using the extension pointers stored in the time slot management table 472-n and the extension pointers stored in the fetch command management table 464-n. Then, the controller 4 can abort all the commands that correspond to the time slots that are subject to timeout processing.

[0271] Next, a description will be given of the timeout processing executed in S303 of Fig. 22 when information indicating a time slot is stored in the fetch command management table. Fig. 24 is a flowchart showing a second example of the procedure of the timeout processing executed in the memory system 3 according to the embodiment. Here, it is assumed that the row number of the time slot management table is stored in the fetch command management table as information indicating a time slot.

[0272] The controller 4 acquires the first EP 465-n saved in S301 of Fig. 22 from the SRAM 46 (step S501). The first EP 465-n is the SQETP 463-n at the end time of the time slot one earlier than the time slot to be timed out, or the initial value.

[0273] The controller 4 acquires the second EP from the time slot management table 471-n (step S502). The second EP is SQETP 463-n at the end time of the time slot that is the timeout target.

[0274] The controller 4 determines whether or not the first EP 465-n acquired in S501 matches the second EP acquired in S502 (step S503).

[0275] If the first EP 465-n and the second EP match (Yes in S503), the controller 4 determines that there is no command corresponding to the time slot that is the target of the timeout, and ends the timeout process.

[0276] If the first EP 465-n and the second EP do not match (No in S503), the controller 4 acquires the row number of the time slot management table 471-n corresponding to the time slot that is the target of the timeout (step S504).

[0277] The controller 4 determines whether or not there is a command associated with the line number acquired in S504 in the fetch command management table 464-n (step S505).

[0278] If there is a command associated with the line number acquired in S504 (Yes in S505), the controller 4 aborts the corresponding command (step S506). The controller 4 interrupts the process corresponding to the corresponding command, and issues a completion response corresponding to the command to the host 2. The issued completion response includes information indicating that the corresponding command has been aborted. Then, the controller 4 updates the fetch command management table 464-n so as to invalidate the entry corresponding to the command aborted in S506 (step S507).

[0279] If there is no command associated with the line number obtained in S504 (No in S505), the controller 4 skips the steps of S506 and S507.

[0280] Then, the controller 4 determines whether the second EP is greater than the EP corresponding to the current SQHP 461-n (step S508).

[0281] If the second EP is greater than the EP corresponding to the current SQHP 461-n (Yes in S508), the controller 4 determines that a command subject to timeout is stored in the submission queue 221-n. Then, the controller 4 fetches the command subject to timeout from the submission queue 221-n (step S509).

[0282] The controller 4 aborts the command fetched in S408 (step S510). The controller 4 issues a completion response corresponding to the command fetched in S408 to the host 2. The issued completion response includes information indicating that the command fetched in S408 has been aborted.

[0283] Moreover, if the second EP is equal to or smaller than the EP corresponding to the current SQHP 4111-n (No in step S508), the controller 4 ends the timeout process.

[0284] In this way, the controller 4 can identify commands that are subject to timeout processing by using the row numbers of the time slot management table 471-n stored in the fetch command management table 464-n. Then, the controller 4 can abort all the commands that correspond to the time slots that are subject to timeout processing.

[0285] As described above, in the memory system 3 according to the embodiment, the controller 4 groups issued commands in units of time slots. Then, the controller 4 identifies a time slot that is a timeout target, identifies commands stored in the submission queue during the identified time slot, and executes a timeout process to abort the identified command.

[0286] This eliminates the need for the controller 4 to manage the time that has elapsed since each issued command was stored in the submission queue.

[0287] In addition, the controller 4 manages an extension pointer to identify each command issued during the time slot that is the target of the timeout. The extension pointer is a pointer that can identify each command that can be issued until the timeout time has elapsed.

[0288] The extended pointer includes a pointer indicating one of the slots included in the submission queue, and a cycle counter corresponding to the number of times the pointer has gone around the slots of the submission queue. The cycle counter control circuit 45 of the controller 4 updates the cycle counter when the updated SQTP is smaller than the SQTP before the update.

[0289] When the SQTP is the value immediately before the SQHP corresponding to the same submission queue, the submission queue is determined to be full, so host 2 cannot update the SQTP to overtake the SQHP.

[0290] Furthermore, the SQHHP managed by the host 2 is updated based on the value of the SQHP included in the completion response issued by the controller 4. The host 2 can store commands in slots in the submission queue until the value indicated by the SQTP for the slot immediately preceding the slot indicated by this updated SQHP becomes equal to the value indicated by the SQTP.

[0291] For this reason, the maximum value by which host 2 can increment SQTP in one write access is the size of the submission queue minus 1. Therefore, in cases where SQETP is updated when SQTP is updated, an update failure of the cycle counter cannot occur.

[0292] The controller 4 manages time slots corresponding to each of the multiple issued commands. For example, if the time slots corresponding to each of the multiple issued commands were directly recorded, it would be necessary to record information indicating the number of time slots equal to the number of slots in the virtual submission queue, which would consume a large amount of resources in the volatile memory (e.g., SRAM 46) of the memory system 3. In addition, the amount of consumed resources depends on the size of the submission queue and the upper limit value of the cycle counter, and the larger the size of the submission queue, the greater the amount of consumed resources.

[0293] However, when managing time slots corresponding to multiple issued commands using an extended pointer and a time slot management table 471-n as in the memory system 3 according to the embodiment, the number of rows of entries required in the time slot management table 471-n corresponds to the number of time slots. The number of time slots is a very small number compared to the number of slots in a virtual submission queue. Therefore, the memory system 3 according to the embodiment can reduce memory resources required for timeout processing by using an extended pointer and a time slot management table 471-n.

[0294] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0295] 1...information processing system, 2...host, 3...memory system, 4...controller, 5...non-volatile memory, 10...bus, 20...internal bus, 21...CPU, 22...RAM, 23...memory interface, 40...internal bus, 41...host interface, 42...CPU, 43...timer, 44...NAND interface, 45...cycle counter control circuit, 46...SRAM, 47...DRAM, 421...command fetch unit, 422...timeout processing unit.

Claims

1. Memory, A controller for controlling the memory, the controller being connectable to an external host.

1. A memory system comprising: The controller: a first queue including a plurality of slots each capable of storing a command received from the host, and a process corresponding to the command received through the first queue; managing an extension pointer including a pointer indicating a slot among the plurality of slots in which a command will be stored next, and a cycle counter that is updated in response to the pointer being updated to a value smaller than a current value; managing a first table including a plurality of entries, each of which corresponds to one of a plurality of consecutive time ranges in units of a first time; selecting one entry from the plurality of entries each time the first time period elapses; storing an extension pointer in the selected entry, the extension pointer including a pointer indicating a slot in which a command will be stored next among the plurality of slots, and a cycle counter; identifying a first time range each time the first time elapses, the first time range having an end time corresponding to a time that is a particular time before the current time; obtaining a first extension pointer stored in a first entry corresponding to the first time range among the plurality of entries; using the first extension pointer to identify one or more commands stored in the first queue during the first time range; and configured to abort the identified one or more commands. Memory system.

2. The controller: further identifying a second time range immediately preceding the first time range; obtaining a second extension pointer stored in a second entry corresponding to the second time range among the plurality of entries; skipping a timeout process including a process of identifying one or more commands stored in the first queue during the first time range and aborting the identified one or more commands if the first extension pointer and the second extension pointer are the same; When the first extension pointer and the second extension pointer are different, the timeout process is executed using the first extension pointer and the second extension pointer.

2. The memory system of claim 1.

3. The controller: When fetching a first command from the first queue, storing the contents of the first command and an extension pointer corresponding to the first command in one entry of a plurality of entries of a second table, the extension pointer including a cycle counter when the first command is fetched and the pointer indicating a slot of the first queue in which the first command was stored; Each time the first time period elapses, determining whether there is one or more entries among the multiple entries of the second table, in which an extension pointer is stored that is equal to or greater than the second extension pointer corresponding to the second time range and is equal to or less than a third extension pointer indicating a slot of the first queue one slot before the first extension pointer corresponding to the first time range; configured to abort one or more commands corresponding to the one or more entries.

3. The memory system of claim 2.

4. The controller: When fetching a first command from the first queue, storing the content of the first command and information indicating the time range including the time when the first command was stored in the first queue in one entry of a plurality of entries in a second table; Each time the first time period elapses, determining whether or not there is one or more entries in which information indicating the first time range is stored among the multiple entries in the second table; configured to abort one or more commands corresponding to the one or more entries.

3. The memory system of claim 2.

5. The controller: If one or more second commands of the identified one or more commands are stored in the first queue and processing has not been completed, interrupting the processing of the second command; sending a first completion response to the host indicating that processing of the second command was unsuccessful; invalidating an entry corresponding to the second command among the multiple entries of the second table; When one or more third commands among the one or more identified commands are stored in the first queue, Fetching the third command; and transmitting a second completion response to the host indicating that processing of the third command has failed without performing processing of the third command.

5. The memory system according to claim 3.

6. The controller: when the pointer indicating the slot in which the command is to be stored next among the plurality of slots is updated to a value smaller than the value of the pointer before the update, determining whether the cycle counter value is an upper limit value; If the cycle counter is not at its upper limit, incrementing the cycle counter by one; if the value of the cycle counter is an upper limit value, updating the cycle counter to an initial value.

2. The memory system of claim 1.

7. the upper limit value of the cycle counter is determined based on at least one of the number of the plurality of slots, the specific time, and the number of the commands that the controller can process during the specific time.

7. The memory system of claim 6.

8. The controller: In response to completing processing of the fetched first command, and invalidating an entry corresponding to the first command among a plurality of entries in the second table.

5. The memory system according to claim 3.

9. The controller receives a command from the host via the first queue or the second queue, Managing the first time corresponding to the first queue and the second time corresponding to the second queue; executing a timeout process for a command received via the first queue each time the first time period elapses; and executing the timeout process for the command received via the second queue every time the second time elapses.

3. The memory system of claim 2.

10. The controller: The second time is calculated after a time that is an integer multiple of a third time has elapsed from the time when the first time is calculated, The first time and the second time are each an integer multiple of the third time.

10. The memory system of claim 9.

11. The specific time is an integer multiple of the first time.

2. The memory system of claim 1.

12. The first table is having at least one entry equal to a number obtained by dividing the specific time by the first time, 12. The memory system of claim 11.

13. The memory system includes: Further comprising a volatile memory, The first table is a number of entries equal to one plus the specific time divided by the first time; The controller: Each time the first time period elapses, When there is no free entry in the first table, a fourth extension pointer stored in a second entry corresponding to a time range immediately before the first time range among the multiple entries in the first table is saved in the volatile memory; configured to overwrite a current extension pointer value to an entry corresponding to an oldest time range among the plurality of entries in the first table.

12. The memory system of claim 11.

14. The controller: Each time the first time period elapses, and identifying one or more commands stored in the first queue during the first time range using the saved fourth extension pointer and a fifth extension pointer stored in the first entry corresponding to the first time range.

14. The memory system of claim 13.

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