Data processing system and data processing method

Abstract

To efficiently use resources in FPGA by eliminating auxiliary processing circuits that are provided in an FPGA circuit in preparation for software error and do not operate in normal processing.SOLUTION: A data processing system includes a computing unit comprising a programmable device, and an arithmetic processing unit connected to the computing unit. The computing unit includes: a plurality of processing circuits that executes, in parallel, data processing instructions provided from the arithmetic processing unit; an error detection unit which detects software error generated in a processing circuit executing a data processing instruction; and a processing circuit selection unit which selects a processing circuit to execute the data processing instruction from among the plurality of processing circuits. The processing circuit selection unit identifies a processing circuit in which the software error occurred, on the basis of the software error detected by the error detection unit, and selects a processing circuit to execute the data processing instruction, excluding the processing circuit in which the software error occurred, out of the plurality of processing circuits.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a data processing system and a data processing method. [Background technology]

[0002] A functional device, a function maintenance method, and a function maintenance program are provided that can continuously maintain functions for functional devices such as FPGAs (Field-Programmable Gate Arrays) that perform required functions through programming. The device has multiple functional units, and maintains functions by switching from a functional unit where a failure has occurred to a functional unit on standby. The device has multiple functional units, a failure detection unit, and a switching unit, and sets an operating functional unit and a standby functional unit. That is, the functional unit where a failure has occurred is placed on standby, and the standby functional unit is operated. Thus, an invention is disclosed that can maintain continuous functions without the system stopping due to a failure occurring in a functional unit, and that can increase the reliability of the system by maintaining functions. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2006-53873 Summary of the Invention [Problem to be solved by the invention]

[0004] Due to the structure of FPGAs, radiation such as neutrons and alpha rays can cause soft errors in which bits are inverted in the data written to the configuration memory (hereafter referred to as CRAM). When a soft error occurs in an FPGA, the circuit configuration changes. As a result, an FPGA in which a soft error occurs may cause the device to malfunction or output incorrect calculation results until the inverted bit is corrected. Because the output of an FPGA while a soft error is occurring is unreliable, it is necessary to correct the error and retry the commands before and after the error occurred.

[0005] When incorporating FPGAs into mission-critical systems, one method is to provide resistance to failures caused by soft errors by preparing a spare processing circuit (standby system) in addition to the processing circuit that normally operates. This method requires the implementation of an inactive spare system, and there is a problem in that implementing a spare system that does not operate during normal processing consumes FPGA circuit resources. [Means for solving the problem]

[0006] The object of the present invention is achieved by a data processing system including a computing unit configured with a programmable device and an arithmetic processing unit connected to the computing unit, the computing unit having a plurality of processing circuits each executing in parallel data processing instructions provided from the arithmetic processing unit, an error detection unit detecting a soft error occurring in a processing circuit executing a data processing instruction, and a processing circuit selection unit selecting a processing circuit from the plurality of processing circuits to execute the data processing instruction, the processing circuit selection unit identifying a processing circuit in which a soft error has occurred based on a soft error detection result from the error detection unit, and selecting a processing circuit from the plurality of processing circuits to execute the data processing instruction excluding the processing circuit in which the soft error has occurred. Effect of the Invention

[0007] According to the present invention, a redundant data processing system that effectively utilizes the capacity of semiconductors can be realized.

[0008] Problems, configurations and effects other than those described above will become apparent from the following description of the embodiments. [Brief description of the drawings]

[0009] [Figure 1] Example of a system configuration diagram according to an embodiment of the present invention [Diagram 2] Example of hardware configuration of a computing machine according to an embodiment of the present invention [Diagram 3]Example of DMAC in the embodiment of the present invention [Figure 4] An example of a detailed configuration of a computing device according to an embodiment of the present invention. [Diagram 5] Example of command processing in the embodiment of the present invention [Figure 6] Example of error handling process in the embodiment of the present invention [Figure 7] An example of a sequence when a soft error occurs in an embodiment of the present invention. [Figure 8] Example of processing sequence when an uncorrectable error occurs in the embodiment of the present invention [Figure 9] Example of IP error count management table in the embodiment of the present invention [Figure 10] Example of a DMAC management table according to an embodiment of the present invention [Figure 11] Example of IP management table in the embodiment of this invention DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each drawing for explaining the embodiments, the same components are given the same names and reference numerals, and the repeated description will be omitted.

[0011] The present invention is not limited to the following examples, and includes various modifications and equivalent configurations within the spirit of the appended claims. For example, the above-mentioned examples have been described in detail to clearly explain the present invention, and the present invention is not necessarily limited to those including all of the described configurations.

[0012] In addition, the processing units described in the embodiments may be realized in hardware, for example by designing some or all of them as integrated circuits, or may be realized in software by a processor interpreting and executing a program that realizes each function.

[0013] The tables, areas, etc. described in the embodiments may be a database (DB) or may be data stored in the main memory. EXAMPLES

[0014] 1 is an example of a system configuration diagram according to an embodiment of the present invention. The data processing system 1 includes a CPU (Central Processing Unit) 2, a main memory 3, a processor (FPGA (Field-Programmable Gate Array)) 4, and a host IF (Interface) 5. The CPU 2 and the processor 4 share a data bus for the main memory 3, and each of them accesses data in the main memory 3 through the data bus.

[0015] The CPU 2 includes a host command processing unit 7 that receives host processing requests from the host IF 5 and analyzes the commands contained in the requests, a computing unit processing unit 8 that performs communication processing of the commands and their processing results with the computing unit 4, and a control unit 9 that controls command processing in the system 1.

[0016] These control and processing units may be stored in the main memory 3 and executed by the CPU 2, or may be realized by hardware.

[0017] The computing device 4 includes one or more DMACs (Direct Memory Access Controllers) 17, a DMAC selection unit 13 that selects the DMAC 17 that executes DMA command processing, a DMAC management table 14 that stores DMAC status information and the like, and a command control unit 19 that transmits and receives DMA commands between the CPU 2 and the DMAC selection unit 13. Each DMAC 17 also includes a plurality of processing circuits 18 that execute data processing based on DMA commands, an IP selection unit 15 that selects a processing circuit, and an IP management table 16 that stores status information and the like of the processing circuits.

[0018] Furthermore, DMAC 17 selected by DMAC selection unit 13 executes DMA with main memory 3 when processing data based on a DMA command. That is, DMAC 17 directly reads commands from command / execution result storage area 10 with main memory 3 and stores command execution results, and reads data for command processing from data storage area 11 and stores processed data.

[0019] In this embodiment, when the processor 4 is equipped with only one DMAC 17, the DMAC selector 13 is not necessarily required.

[0020] The main memory 3 includes a command / execution result storage area 10 for storing details of the DMA command and the results of its execution, a data storage area 11 for storing data before and after the processing of the DMA command by the processing circuit, and an IP error count management table 12 for managing the number of errors in the processing circuit.

[0021] The CPU 2 and the computing device 4 are connected via a PCIe (Peripheral Component Interconnect express) interface, etc. However, the connection may use other communication protocols.

[0022] FIG. 2 shows an example of the hardware configuration of a computing machine according to an embodiment of the present invention.

[0023] The CPU 2 is connected to a computing device 4. In this example, a PCIe 22 and an Internal Bus Switch 23 are implemented in the computing device, and are connected to a DMAC selection unit 13. The DMAC selection unit 13 is connected to a plurality of DMACs 17, and the DMACs 17 include an IP group (processing circuit group) 26 in which a plurality of processing circuits 18 are implemented. As will be described later with reference to FIG. 4, each processing circuit 18 is provided in a corresponding IP control unit, but is illustrated in a simplified manner in FIG. 1 to FIG. 3 for the purpose of explaining the functions.

[0024] An IP selection unit (arbiter) 15 selects a processing circuit 18 that executes a DMA command from these processing circuits.

[0025] The SEU (Single Event Upset) detection and correction mechanism 28 corrects errors in the processing circuit 18. Specifically, the SEU detection and correction mechanism 28 periodically performs a cyclic check of a CRAM (not shown) in which the circuit configuration of the FPGA included in the computing device 4 is stored, and when an error in the processing circuit 18 is detected, the mechanism corrects the error.

[0026] 3 shows an example of a DMAC in an embodiment of the present invention. Here, the explanation will be given on the assumption that one DMAC 17 is selected by the DMAC selection unit 13 to execute a DMA command.

[0027] The DMAC 17 selected by the DMAC selection unit 13 reads information about the DMA command from the command / execution result storage area 10 of the main memory 3 by DMA transfer based on the DMA command, and reads processing data from the data storage area 11 based on the acquired DMA command.

[0028] The IP selection unit 15 in the selected DMAC 17 receives the DMA command and data to be processed, and sends it to the processing circuit 18 selected as the data processing target. In FIG. 3, IP0 is shown as being selected among the processing circuits 18. The selected processing circuit IP0 executes the DMA command, and outputs the command execution result and the processed data. The selected DMAC 17 uses DMA to store the command execution result and the processed data in the command / execution result storage area 10 and the data storage area 11, respectively. If the selected processing circuit IP0 generates an error during command processing, it is excluded from the selection list, and another processing circuit that is a candidate for selection is selected to continue command processing.

[0029] 4 shows an example of a detailed configuration of the computing device 4 in an embodiment of the invention. The DMAC 17 includes a receiving unit 42 that receives a DMA command from the DMAC selecting unit 13, a transmitting unit 43 that transmits the processing result of the processing circuit 18 to the DMAC selecting unit 13, and an IP selecting unit 15 that selects the processing circuit 18 that executes the DMA command and outputs the DMA command.

[0030] Each IP control unit 41 is provided with a processing circuit 18 and an error detection circuit 45 that detects soft errors that occur in the processing circuit 18. The error detection circuit 45 detects the occurrence of a soft error by detecting a change in the circuit configuration of the processing circuit 18. Methods for detecting a change in the circuit configuration include (1) adding an error correction code to the transmission path inside the processing circuit, (2) instantly expanding compressed data and comparing the obtained result with the original data (if the processing circuit 18 supports data compression and expansion), and (3) verifying an error detection code that has been added in advance when decoding data (if the processing circuit 18 supports data encryption and decryption), but other methods may also be used.

[0031] Next, the tables used in this embodiment will be described with reference to FIGS.

[0032] 9 is an example of IP error count management table 12 in an embodiment of the present invention. IP error count management table 12 is stored in main memory 3, and includes a #DMAC number 111 column for identifying each DMAC, an #IP number 112 column for identifying each processing circuit in each DMAC, a number of errors 113 column for the processing circuit corresponding to the #IP number, and an error count threshold value 115 column for the processing circuit corresponding to the #IP number.

[0033] The IP error count management table 12 is referred to by the control unit 19 of the CPU 2, and stores the number of error occurrences 113 for each processing circuit 18 included in each DMAC. When the number of error occurrences 113 reaches a predetermined number, the table is used to set an arbiter participation disabled column 134 of the IP management table 16, which will be described later, to 1 (ON) to exclude the corresponding DMAC from selection.

[0034] 10 is an example of DMAC management table 14 in an embodiment of the present invention. DMAC management table 14 is stored in processor 4, and includes a #DMAC number 121 column, a Busy 122 column indicating whether all processing circuits belonging to the DMAC corresponding to the #DMAC number are in process, and a command receivable column 123 indicating whether the DMAC corresponding to the #DMAC number is able to receive a command. If the system has multiple DMACs, the DMAC selection unit 13 uses this table to manage the use of the DMACs. When all of the processing circuits 18 in the DMAC are busy, all of the processing circuits 18 set the Busy column 122 to ON (1) to prevent the DMAC from being selected. In this example, when all of the processing circuits 18 are busy, the command receivable column 123 is set to No to prevent the DMAC from being selected.

[0035] A column may be provided for registering the number of processing circuits 18 possessed by the DMAC and the number of processing circuits 18 currently processing, and when the DMAC selection unit selects a DMAC, the number of processing circuits 18 currently processing may be incremented by 1, and when the processing of a processing circuit 18 is completed, the number of processing circuits 18 currently processing may be decremented by 1 to determine the usage rate of the processing circuits 18 in the DMAC, thereby enabling the selection of a DMAC with a low usage rate.

[0036] In addition, when the amount of data processing required for each process by the host varies greatly, instead of counting the number of processes, a column for counting the amount of data processed may be provided, and the DMAC to be used may be selected based on the amount of data processing.

[0037] In addition, by providing load information indicating the proportion of processing circuits 18 that are in use among the processing circuits 18 held by the DMAC, and performance information indicating the processing speed of the DMAC, it is possible to know which DMAC has a high usage priority and which has a low usage priority, thereby enabling the system to be operated efficiently.

[0038] Furthermore, a different type of processing circuit 18 may be installed for each DMAC, and the DMAC may be selected according to the processing requested by the host.

[0039] 11 is an example of IP management table 16 in an embodiment of the present invention. IP management table 16 is provided for each DMAC, and includes an in-processing column 132 indicating whether processing is in progress for each processing circuit 18 in each DMAC, a cyclic correction waiting column 133 indicating whether cyclic correction is awaiting, an arbiter participation not possible column 134 indicating whether processing is not possible, and a command receivable column 135 indicating whether commands can be received.

[0040] If all the fields 132-134 are OFF (0), the command receivable field is set to Yes, indicating that the processing circuit 18 is capable of processing. In addition, by storing information such as the type and version of the processing circuit 18, it is possible to represent a processing circuit 18 that can be used and a processing circuit 18 with a high priority for use.

[0041] Next, the command processing operation in the system of this embodiment will be described with reference to FIG.

[0042] The host command processing unit 7 of the CPU 2 receives a processing request from the host, analyzes the host command included in the request, and passes the analysis result to the control unit 9. The host command is an instruction to read or write specified data from a logical storage area provided by the system 1 and accessible by the host, and the storage area is set in correspondence with the main memory 3.

[0043] The control unit 9 identifies a DMA command (hereinafter, DMA command) that corresponds to the received host command and involves data processing with the computing device 4, and the data that is to be processed by the DMA command (hereinafter, target data), and stores the DMA command in a command execution result storage area 10 of the main memory 3, and the target data in a data storage area 11.

[0044] Examples of instructions by a DMA command include "read plain text from address XX (in main memory 3) and write the compressed data to address XX" and "read compressed data from address XX (in main memory 3), decompress it, and write it to address XX." In this embodiment, the address of the data to be processed specified by the DMA command is directly used as the address of the data storage area 11. With this configuration, it is possible to access the address of the command execution result storage area 10 where the DMA command is stored, and identify the address of the data storage area 11 where the data to be processed is stored by referring to the DMA command.

[0045] Thereafter, the computing device processing unit 8 transmits a command receipt notification including the address of the DMA command stored in the command execution result storage area 10 to the computing device 4 (S50). Note that the command receipt notification does not have to include the address of the DMA command. In this case, the address of the command execution result storage area 10 where the DMA command is stored may be determined in advance in the system 1, and the command control unit 19 that receives the command receipt notification in the computing device 4 may access that address and read out the DMA command.

[0046] In the computing device 4, the command receipt notification is sent to the command control unit 19 via the PCIe 22 and the Internal Bus Switch 23. Based on the address of the command execution result storage area 10 included in the notification, the command control unit 19 reads out the DMA command from the main memory 3 and the data to be processed based on the DMA command, and sends them to the DMAC selection unit 13. Having received the DMA command and the data to be processed, the DMAC selection unit 13 refers to the command receivable column 123 of the DMAC management table 14 and determines whether there is a DMAC 17 that can receive the command (S51). Here, the fact that the DMAC is able to receive a command means that there is at least one processing circuit 18 that is not blocked and that can process data in the DMAC.

[0047] When there is a DMAC 17 capable of receiving the command (Yes in S51), the DMAC selection unit 13 selects one of the DMACs 17 capable of receiving the command and transmits the DMA command and the data to be processed. The condition for selecting a DMAC may be to select the first DMAC found capable of receiving the command, but if the load status of the DMACs is checked and a DMAC with a low load is selected, the processing can be distributed, which contributes to improving the processing efficiency.

[0048] If there is no DMAC 17 that can receive the command (No in S51), for example if the processing circuits 18 in all the DMACs 17 are processing a command, the DMAC selection unit 13 continues monitoring until it finds a DMAC 17 in which the processing has been completed in any of the processing circuits 18 and the Busy column 122 in the DMAC management table 14 has become OFF (0).

[0049] In the selected DMAC 17, the DMA command and the data to be processed are received by the receiver 42 and output to the IP selector 15. When the IP selector 15 receives the DMA command and the data to be processed, it refers to the command receivable column 135 of the IP management table 16 and determines whether or not there is a processing circuit 18 capable of receiving a command among the processing circuits 18 to be selected (S52). The presence of a processing circuit 18 capable of receiving a command means that there is a processing circuit 18 capable of processing data that is not in the middle of processing, is not waiting for cyclic correction, and is not unable to participate in the arbiter.

[0050] When there is a processing circuit 18 capable of receiving a command (Yes in S52), the IP selection unit 15 selects one of the processing circuits 18 capable of receiving a command and transmits a command receipt notification. Regarding the selection of the processing circuit 18, if a processing circuit with fewer errors is selected based on information such as the number of times an error has occurred, this leads to a reduction in errors and makes it possible to perform processing more efficiently.

[0051] If there is no processing circuit 18 capable of receiving a command (No in S52), the IP selection unit 15 continues monitoring until a processing circuit 18 in which the command receivable column 135 of the IP management table 16 has become Yes is found.

[0052] When the IP selection unit 15 selects a processing circuit 18 capable of receiving a command, it passes the DMA command and data to be processed to the corresponding IP control unit 41. When the IP control unit 41 transmits to the selected processing circuit 18, the processing circuit 18 starts processing the command (S53).

[0053] When processing a command, the processing circuit 18 performs DMA to access an address in the data storage area 11 where the data to be processed is stored. Specifically, the receiving unit 42 receives the data read from the address, the processing circuit 18 processes the data, and notifies the transmitting unit 43 of the completion of the processing. Upon receiving the completion notification from the processing circuit 18, the transmitting unit 43 transmits the processed data to the main storage memory 3, thereby executing DMA.

[0054] 5, the data to be processed read from the data storage area 11 is received by the receiving unit 42, and when the data is output to the selected processing circuit 18 via the IP selecting unit 15, data processing is performed based on the DMA command. When the processing circuit 18 ends the processing normally (No in S54), it transmits a DMA command including the processing result of the command to the command control unit 19 via the IP selecting unit 15 and the DMAC selecting unit 13, and transmits the processed data to the transmitting unit 43.

[0055] The transmitting unit 43 transmits and writes the processed data directly to the address in the data storage area 11 where the data to be processed is stored. The command control unit 19 also transmits the processing result and the address in the command execution result storage area 10 where the DMA command is stored to the CPU 2 (S57).

[0056] The processing result is received by the calculation processing unit 8 in the CPU 2, and the control unit 9 writes the response result to the address in the command execution result storage area 10 where the DMA command is stored. The control unit 9 then transmits the processing result to the host via the host IF 5.

[0057] If the processing circuit 18 generates an error (including an error caused by a soft error) during command processing (Yes in S54), the corresponding error detection circuit 45 detects the error and notifies the IP selection unit 15. The IP selection unit 15, which receives the error notification, transmits an error DMA command including the number of the processing circuit in which the error occurred to the command control unit 19. The command control unit 19 transmits the error DMA command to the computing device processing unit 8 of the CPU 2, and after receiving the DMA command, the control unit 9 of the CPU 2 executes error handling processing (S55). Details of the error handling processing will be described later with reference to FIG. 6.

[0058] The IP selection unit 15 sets the cyclic correction waiting column 133 corresponding to the processing circuit 18 in which the error occurred in the IP management table 16 to ON (1), and sets the command receivable column 135 to No.

[0059] The SEU detection and correction mechanism 28 periodically performs a cyclic correction check of the CRAM, and corrects the error in the processing circuit 18 in which an error occurred at a cyclic correction period of the order of several hundred milliseconds (S56). When the error correction is completed, the IP selection unit 15 sets the cyclic correction waiting column 133 in the IP management table 16 corresponding to the processing circuit 18 in which the error occurred to OFF (0), and if the corresponding processing column 132 and arbiter participation not allowed column 134 are also OFF (0), sets the command receiving possible column 135 to Yes.

[0060] Also, the error detection circuit 45 may reset the arbiter participation disabled column 134 of the IP management table 16 at a predetermined period, for example, a cyclic correction period, so as to select the corresponding processing circuit 18. By such processing, it becomes possible to effectively use the available processing circuits 18.

[0061] 6 shows an example of the error handling process S55 of the CPU 2. When an error DMA command is received from the IP selection unit 15 of the DMAC 17 in which an error has occurred (S60), the control unit 9 increments the error occurrence count 113 of the corresponding processing circuit in the IP error count management table 12 (FIG. 9) by 1 (S61). It is determined (S62) whether the error occurrence count of the processing circuit is equal to or greater than the error count threshold in the IP error count management table 12, and if it is equal to or greater than the error count threshold, it accesses the setting register 81 of the DMAC 17 to which the error command was transmitted, and turns ON the flag in the arbiter participation not allowed 134 column in the IP management table 16 (FIG. 11) corresponding to the processing circuit 18 in which the error has occurred (S63). Thereafter, unless the arbiter participation not allowed column 134 is reset to OFF (0), the processing circuit 18 in question is excluded from the selection target by the IP selection unit 15. The allocation of processes to the processing circuits 18 is performed with reference to the DMAC management table 14 and the IP management table 16. The entities of the DMAC management table 14 and the IP management table 16 exist in the registers of the processor 4.

[0062] The computing device processing unit 8 refers to the setting register 81 in the DMAC and requests a retry of the DMA command (S65). That is, the computing device processing unit 8 again sends a command receipt notification including the address of the DMA command stored in the command execution result storage area 10 to the computing device 4, and thereafter the command processing operation is performed again according to the flow described in Fig. 5. Alternatively, the command control unit 19 of the computing device 4 may transmit the DMA command with an error to the CPU 2, and then access the address in the command execution result storage area 10 where the DMA command is stored, and execute the DMA command again.

[0063] If the number of error occurrences is not equal to or greater than the threshold in S62, the control unit 9 retries the command.

[0064] Fig. 7 shows an example of a sequence when a soft error occurs in an embodiment of the present invention. In Fig. 7, it is assumed that there is only one DMAC 17 in the computing device 4, or that the DMAC 17 that processes the host command has already been selected from among a plurality of DMACs 17.

[0065] When a command receipt notification including the address of the DMA command stored in the command execution result storage area 10 is received from the calculator processing unit 8 of the CPU 2, the command control unit 19 of the calculator 4 reads out the DMA command (hereinafter referred to as the command in Figures 7 and 8) and the data to be processed from the main memory 3 based on the address, and transmits them to the DMAC selection unit 13 (S71).

[0066] When the IP selection unit 15 in the DMAC 17 receives the DMA command and data to be processed, it refers to the IP management table 16 to select a processing circuit 18 that will process the command, and transfers the data to the selected processing circuit 18 (S72). In this example, IP_0 of the DMAC 17 is selected. When a soft error occurs in IP_0 and the circuit configuration changes, a corresponding error detection circuit (not shown) detects the failure and notifies the IP selection unit 15 of the error (S73). The IP selection unit 15 returns an error DMA command (hereinafter referred to as an error command in Figs. 7 and 8) including the number of the processing circuit in which the error occurred to the command control unit 19 (S74).

[0067] When command control unit 19 receives an error DMA command, it transmits it to CPU 2 and requests a retry of the DMA command. When a command acceptance notification is sent again from calculation unit processing unit 8 of CPU 2 in response to the retry, command control unit 19 transmits the DMA command and the data to be processed read from main memory 3 again to DMAC 17, and IP selection unit 15 receives them (S75).

[0068] The IP selection unit 15 selects a processing circuit IP_x where no error has occurred and transfers the command (S76). When IP_x correctly processes the command and completes data processing of the requested content, it writes the data processing result to the data storage area 11 by DMA and returns a DMA command including the processing result as a normal response to the IP selection unit 15 (S77). The IP selection unit 15 returns the DMA command to the command control unit 19 (S78). During this time, the SEU detection and correction mechanism 28 corrects the correctable error in the cyclic correction period (S79) in IP_0 where the error has occurred (S80). The IP selection unit 15 does not consider IP_0 as a selection candidate for a certain period of time equal to or greater than the cyclic correction period, and adds it to the selection candidates after the certain period of time has elapsed.

[0069] 8 shows an example of a processing sequence when an uncorrectable error occurs in an embodiment of the present invention. In this example, a sequence for a system with multiple DMACs is shown, but the sequence can also be applied to a system with one DMAC.

[0070] When a command receipt notification including the address of the DMA command stored in command execution result storage area 10 is received from calculation unit processing unit 8 of CPU 2 (S82), command control unit 19 of calculation unit 4 reads the DMA command and the data to be processed from main memory 3 based on the address, and transmits them to DMAC selection unit 13 (S83). DMAC selection unit 13 refers to DMAC management table 14, selects DMAC_0 as DMAC 17 that will process the command, and transmits the DMA command and the data to be processed (S84).

[0071] The IP selection unit 15 receives a DMA command and data to be processed in DMAC_0, selects a processing circuit IP_0, executes command processing, and receives notification of fault detection based on a soft error and transmits an error command (S85-S88). Since this series of operations is similar to that shown in FIG. 7, detailed explanation will be omitted, but the error DMA command transmitted by the IP selection unit 15 includes the number of the processing circuit IP_0 in which the error occurred as well as the number of the selected DMAC_0.

[0072] When command control unit 19 receives a command acceptance notification again from calculation unit processing unit 8 of CPU 2 based on the command retry request (S92), it reads the DMA command and the data to be processed from main memory 3 and transmits them again to DMAC selection unit 13 of calculation unit 4 (S93). If DMAC selection unit 13 selects DMAC_0 again, the DMA command and the data to be processed are transmitted to IP selection unit 15 (S94). Since processing circuit IP_0 is recognized as a selection target if error correction has been performed, when IP selection unit 15 selects processing circuit IP_0 again, command processing is executed (S95).

[0073] If the error correction by the processing circuit IP_0 has failed, that is, if the error is uncorrectable, an error DMA command is sent back again via the IP selection unit 15 and the DMAC selection unit 13 (S96-S98).

[0074] When an error DMA command is received, the control unit 9 of the CPU 2 increments the occurrence count value of the processing circuit IP_0 in the error occurrence count 113 column corresponding to DMAC_0 and the processing circuit IP_0 in the IP error count management table 12, and compares the occurrence count with the corresponding error count threshold 115. If the occurrence count is equal to or greater than the threshold, the arbiter participation disabled column 134 of the processing circuit IP_0 in the IP management table 16 stored in the DMAC internal setting register 81 of DMAC_0 is set to 1 (ON), and the command reception enabled column 135 is set to No (S101). Thereafter, the IP selection unit 15 recognizes the processing circuit IP_0 as unable to receive commands, and does not select it.

[0075] According to the sequence example described above, when an error command is generated a specified number of times for a processing circuit IP_0 in which a soft error that cannot be repaired by correction processing has occurred, the processing circuit is permanently excluded from selection. Therefore, command processing is continued by other processing circuits capable of receiving commands, and an infinite loop of command retries caused by the selection of the processing circuit IP_0 can be prevented.

[0076] By controlling the arbiter participation of the processing circuit 18 using the setting register 81 in the DMAC, it becomes easier to determine the arbiter participation conditions using the information registered in the IP error count management table 12 to conditions that meet the needs of the system performing soft error processing.

[0077] Although it is not necessary to block the processing circuit 18 after one error correction failure, it may be blocked when the number of error correction failures reaches a predetermined number. Furthermore, since the processing circuit 18 that has been blocked once is operated again, it can be used again within a predetermined period of time. The conditions for blocking the processing circuit 18 and the conditions for using it again can be adjusted appropriately according to the system to which it is applied.

[0078] According to the above-described embodiment, the FPGA computing unit 4 includes one or more DMACs 17, and each DMAC 17 includes a plurality of processing circuits 18 that process commands from the host 150, and an IP selection unit 15 that selects a processing circuit 18 that can execute the command upon receiving the command. When a soft error occurs in a processing circuit 18 that is executing a command and the circuit configuration is changed, the error in the processing circuit 18 is notified to the IP selection unit 15, and upon receiving the notification, the IP selection unit 15 can exclude the processing circuit 18 from the selection targets and select another executable processing circuit 18. Therefore, even if a soft error occurs in a processing circuit that is executing a command, command execution can be continued in the other executable processing circuits, and the influence of malfunction of the FPGA due to the occurrence of a soft error can be reduced.

[0079] Since each processing circuit 18 can execute commands in parallel as a processing system operating normally, the utilization efficiency of the FPGA circuit resources is improved compared to a case where an inactive spare circuit is provided. Also, if the DMAC 17 is equipped with N processing circuits, the system can be prevented from going down until an error occurs in N-1 processing circuits.

[0080] Furthermore, the SEU detection and correction mechanism 28 performs error correction processing during a cyclic correction period for the processing circuit 18 in which an error has occurred, and restores the circuit configuration. By setting the processing circuit 18 to be selectable by the IP selection unit 15 again after the period has elapsed, the redundancy of the processing circuit 18 is quickly restored, and the impact of malfunction of the FPGA due to the occurrence of a soft error can be further reduced.

[0081] Furthermore, the control unit 19 of the CPU 2 counts and monitors the number of errors occurring in each processing circuit 18 by receiving an error command from the processing circuit 18 in which an error has occurred, and sets a processing circuit in which an error occurrence is detected a prescribed number of times or more as blocked so that it cannot be selected by the IP selection unit 15 in the same DMAC 17. This makes it possible to avoid an infinite loop of command retries caused by a processing circuit in which an uncorrectable error that cannot be repaired by error correction has occurred being set as selectable after error correction has been performed, thereby improving availability when an uncorrectable error occurs. [Explanation of symbols]

[0082] 1 data processing system, 2 CPU, 3 main memory, 4 computing unit (FPGA), 5 host IF, 7 host command processing unit, 8 computing unit processing unit, 9 processing request reception unit, 10 command execution result storage area, 11 data storage area, 12 IP error count management table, 13 DMAC selection unit, 14 DMAC management table, 15 IP selection unit, 16 IP management table, 17 DMAC, 18 processing circuit, 19 command control unit

Claims

1. A data processing system including a processor configured with a programmable device and an arithmetic processing unit connected to the processor, The computing device includes: a plurality of processing circuits each of which executes in parallel data processing instructions provided by the arithmetic processing unit; an error detection unit that detects a soft error that occurs in a processing circuit that is executing a data processing instruction; a processing circuit selection unit that selects a processing circuit to execute a data processing instruction from among the plurality of processing circuits; a processing circuit selection unit that identifies a processing circuit in which a soft error has occurred based on a soft error detection result from the error detection unit, and selects a processing circuit from among the plurality of processing circuits to execute a data processing instruction, excluding the processing circuit in which the soft error has occurred.

2. the computing device has an error detection and correction circuit that detects soft errors in the plurality of processing circuits at a specific period and corrects the detected soft errors; 2. The data processing system according to claim 1, wherein the processing circuit selection unit selects a processing circuit in which a soft error has occurred as a processing circuit to be selected as a processing circuit for executing a data processing instruction after the period has elapsed since the processing circuit in which the soft error has occurred is identified.

3. 2. The data processing system according to claim 1, wherein, when a soft error occurs a prescribed number of times or more in a particular processing circuit, said processing circuit selection unit does not select said processing circuit as a processing circuit for executing a data processing instruction.

4. In the computing device, the plurality of processing circuits are classified into a plurality of processing circuit groups, 4. The data processing system according to claim 1, wherein the processing circuit selection section is provided corresponding to each processing circuit group.

5. the computing machine has a processing circuit group selection unit that selects a processing circuit group that is to execute a data processing instruction from among the plurality of processing circuit groups, 5. The data processing system according to claim 4, wherein the processing circuit group selection section selects a processing circuit group that is to execute a data processing instruction based on an execution status of the data processing instruction in a processing circuit belonging to each processing circuit group.

6. A data processing method in a data processing system including a processor configured with a programmable device and a processor connected to the processor, The computing device includes: a plurality of processing circuits each of which executes in parallel data processing instructions provided by the arithmetic processing unit; an error detection unit that detects a soft error that occurs in a processing circuit that is executing a data processing instruction; a processing circuit selection unit that selects a processing circuit to execute a data processing instruction from among the plurality of processing circuits; The error detection unit detects an occurrence of a soft error in a processing circuit that is executing a data processing instruction, a processing circuit selection unit that identifies a processing circuit in which a soft error has occurred based on a soft error detection result from the error detection unit, and selects a processing circuit from among the plurality of processing circuits that is to execute the data processing instruction, excluding the processing circuit in which the soft error has occurred.

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