Image sensor

Abstract

To provide an image sensor including means of efficiently connecting between floating diffusion regions.SOLUTION: An image sensor according to the present invention includes a first substrate having a first surface and a second surface on the opposite side of the first surface and including a pixel array region including a plurality of active regions on the first surface, an element separation part disposed in the first substrate on the first surface side and separating the active regions on the first surface, a plurality of floating diffusion regions existing in the active regions of the first substrate, and a floating diffusion region connecting part that is at least partially embedded in the element separation part and connects at least two of the floating diffusion regions.SELECTED DRAWING: Figure 6A

Description

[Technical field]

[0001] The present invention relates to an image sensor. [Background technology]

[0002] An image sensor is a semiconductor device that converts an optical image into an electrical signal. Image sensors are classified into CCD (Charge Coupled Device) type and CMOS (Complementary Metal Oxide Semiconductor) type. CMOS type image sensors are abbreviated as CIS (CMOS imagesensor). CIS has a number of pixels arranged two-dimensionally. Each pixel includes a photodiode that converts incident light into an electrical signal, and a floating diffusion region that temporarily stores the electrical signal generated by the photodiode through photoelectric conversion. The floating diffusion regions are connected to one source follower gate, and the electrical signal is output to the outside through the source follower gate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2022-172451 A Summary of the Invention [Problem to be solved by the invention]

[0004] SUMMARY OF THE PRESENT DISCLOSURE The present invention has been made in view of the above-mentioned conventional techniques, and an object of the present invention is to provide an image sensor having an efficient connection means between floating diffusion regions. [Means for solving the problem]

[0005] In order to achieve the above-mentioned object, an image sensor according to one embodiment of the present invention includes a first substrate having a first surface and a second surface opposite to the first surface, the first substrate including a pixel array region having a plurality of active regions on the first surface; an element isolation portion disposed in the first substrate on the first surface side and isolating each of the plurality of active regions on the first surface; a plurality of floating diffusion regions located within the plurality of active regions of the first substrate; and a floating diffusion region connection portion at least a portion of which is embedded in the element isolation portion and connecting at least two of the plurality of floating diffusion regions.

[0006] In order to achieve the above object, an image sensor according to another aspect of the present invention includes a first substrate having a first surface and a second surface opposite to the first surface, the first substrate including a pixel array region including a plurality of sub-unit pixels and a peripheral region, an anti-reflection structure disposed on the second surface, a pixel separator disposed on the first substrate and isolating the plurality of sub-unit pixels from each other, a color filter disposed on the anti-reflection structure, a first interlayer insulating film disposed on the first surface of the first substrate, a first wiring disposed in the first interlayer insulating film, a second interlayer insulating film disposed below the first interlayer insulating film, a second wiring disposed in the second interlayer insulating film, and a second substrate disposed below the second interlayer insulating film, the substrate includes: an isolation portion located within the first substrate and extending from the first surface toward the second surface to isolate each of the active regions of the first surface; a plurality of floating diffusion regions formed in the active regions of the first substrate; a floating diffusion region connection portion embedded in the isolation portion to connect at least two of the floating diffusion regions; and a cover insulating film formed on an upper surface of the floating diffusion region connection portion and having a contact hole exposing an upper surface of the floating diffusion region connection portion, wherein a portion of the first wiring corresponds to a source follower gate electrode of a source follower transistor, and the source follower gate electrode is connected to the floating diffusion region connection portion through the contact hole.

[0007] In order to achieve the above-mentioned object, an image sensor according to yet another aspect of the present invention includes a first substrate having a first surface and a second surface opposite to the first surface, the first substrate including a plurality of pixel array regions including a plurality of sub-unit pixels and a peripheral region, an anti-reflection structure disposed on the second surface, a pixel separation portion disposed on the first substrate and separating the plurality of sub-unit pixels from each other, a color filter disposed on the anti-reflection structure, a first interlayer insulating film disposed on the first surface of the first substrate, a first wiring disposed in the first interlayer insulating film, and a second substrate disposed below the first interlayer insulating film. the first substrate includes a second interlayer insulating film disposed below the second substrate, a second wiring disposed in the second interlayer insulating film, a third interlayer insulating film disposed below the second interlayer insulating film, a third wiring disposed in the third interlayer insulating film, and a third substrate t disposed below the third interlayer insulating film, the first substrate includes: an element isolation portion located within the first substrate and extending from the first surface toward the second surface to isolate each of a plurality of active regions of the first surface; a plurality of floating diffusion regions formed in the plurality of active regions of the first substrate; and a floating diffusion region connecting portion embedded in the element isolation portion to connect at least two of the plurality of floating diffusion regions, a portion of the second wiring corresponding to a source follower gate electrode of a source follower transistor, and the source follower gate electrode is connected to the floating diffusion region connecting portion through a through via that penetrates the second substrate. Effect of the Invention

[0008] According to the image sensor of the present invention, by arranging the floating diffusion region connecting portion that connects the floating diffusion regions within the element isolation portion, it is possible to reduce coupling between wirings and improve the freedom of wiring arrangement. [Brief description of the drawings]

[0009] [Figure 1] 1 is a block diagram illustrating an image sensor according to an embodiment; [Diagram 2] 1 is a circuit diagram of an active pixel sensor array of an image sensor according to one embodiment. [Diagram 3] FIG. 2 is a plan view of an image sensor according to an embodiment. [Figure 4] FIG. 4 is a cross-sectional view taken along the line AA′ in FIG. [Diagram 5] 2 is an enlarged plan view showing the arrangement of a transfer gate, a floating diffusion region, a floating diffusion region connection portion, a source follower gate, and the like in an image sensor according to an embodiment. [Figure 6A] 6 is a cross-sectional view taken along line AA' in FIG. 5, and corresponds to a P1 area in FIG. [Figure 6B] FIG. 6 is a cross-sectional view taken along line BB' in FIG. 5. [Figure 6C] 6 is a cross-sectional view taken along line CC' in FIG. 5. [Figure 7A] 5A to 5C are cross-sectional views illustrating a method of forming a floating diffusion region connection portion of an image sensor according to an embodiment. [Figure 7B] 5A to 5C are cross-sectional views illustrating a method of forming a floating diffusion region connection portion of an image sensor according to an embodiment. [Figure 7C] 5A to 5C are cross-sectional views illustrating a method of forming a floating diffusion region connection portion of an image sensor according to an embodiment. [Figure 7D] 5A to 5C are cross-sectional views illustrating a method of forming a floating diffusion region connection portion of an image sensor according to an embodiment. [Figure 8A] 10A to 10C are cross-sectional views illustrating a method of forming a floating diffusion region connection portion of an image sensor according to another embodiment. [Figure 8B] 10A to 10C are cross-sectional views illustrating a method of forming a floating diffusion region connection portion of an image sensor according to another embodiment. [Figure 8C] 10A to 10C are cross-sectional views illustrating a method of forming a floating diffusion region connection portion of an image sensor according to another embodiment. [Figure 8D] 10A to 10C are cross-sectional views illustrating a method of forming a floating diffusion region connection portion of an image sensor according to another embodiment. [Figure 9] 11 is a cross-sectional view of an image sensor according to another embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, specific examples of the embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention can be embodied in various different forms and is not limited to the embodiments described herein.

[0011] The drawings and description are to be regarded as illustrative in nature and not restrictive.Like reference characters refer to like elements throughout.

[0012] In the drawings, the size and thickness of each component may be arbitrarily illustrated for convenience of explanation, and the present invention is not necessarily limited to those shown in the drawings. In the drawings, the thickness of layers, films, plates, regions, etc. may be exaggerated for clarity. In the drawings, the thickness of some layers and regions may be exaggerated for convenience of explanation.

[0013] As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0014] In the specification and claims, the term "and / or" is intended to include any combination of the terms "and" and "or" for the purposes of its meaning and interpretation. For example, "A and / or B" is to be interpreted as meaning "A, B, or A and B."

[0015] In the specification and claims, the phrase "at least one of" is intended to include "at least one selected from the group of" for the purposes of its meaning and interpretation. For example, "at least one of A and B" can be understood to mean "A, B, or A and B."

[0016] Terms such as first and second may be used herein to describe various components, but such components are not limited by such terms. Such terms are used only to distinguish one element from another. For example, a first component may be named a second component, and similarly, a second component may be named a first component, without departing from the scope of the present invention.

[0017] When an element such as a layer, film, region, or substrate is referred to as being "on" another element, it may be directly on the other element, or there may be intermediate elements present. In contrast, when an element is described as being "directly on" another element, there are no intermediate elements present. Also, throughout the specification, the term "on" a target element means located above or below the target element, and does not necessarily mean located "above" the target element relative to the opposite direction of gravity.

[0018] For example, spatially relative terms "below," "above," and the like are used to facilitate describing the relationship between one element or component and other components as depicted in the figures. Spatially relative terms are intended to include other orientations in the device in use or operation in addition to the orientation depicted in the figures. For example, if the devices depicted in the figures were inverted, a device that is located "below" another device could be located "above" the other device. Thus, the exemplary term "below" can include both lower and upper positions. Devices can also be oriented in other directions, and therefore spatially relative terms can be interpreted differently depending on the orientation.

[0019] When an element (or region, layer, portion, etc.) is described in the specification as being "connected" or "bonded" to another element, it means that it is directly disposed, connected, or bonded to the other element, or there are intervening elements disposed therebetween.

[0020] The terms "coupled to" or "bonded to" include physical or electrical connections or couplings.

[0021] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person of ordinary skill in the art to which the present invention belongs. Terms as defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0022] FIG. 1 is a block diagram illustrating an image sensor according to an embodiment.

[0023] Referring to FIG. 1, the image sensor includes an active pixel sensor array 1001, a row decoder 1002, a row driver 1003, a column decoder 1004, a timing generator 1005, a correlated double sampler (CDS) 1006, an analog to digital converter (ADC) 1007, and an input / output buffer (I / O buffer) 1008.

[0024] The active pixel sensor array 1001 includes a number of unit pixels arranged two-dimensionally, and converts optical signals into electrical signals. The active pixel sensor array 1001 is driven by a number of driving signals, such as a pixel selection signal, a reset signal, and a charge transfer signal, from a row driver 1003. The converted electrical signals are provided to a correlated double sampler 1006.

[0025] The row driver 1003 provides a plurality of driving signals for driving a plurality of unit pixels to the active pixel sensor array 1001 according to the result of decoding by the row decoder 1002. When the unit pixels are arranged in a matrix form, a driving signal is provided for each row.

[0026] A timing generator 1005 provides timing and control signals to the row decoder 1002 and the column decoder 1004 .

[0027] The correlated double sampler (CDS) 1006 receives, holds, and samples the electrical signal generated by the active picket cell sensor array 1001. The correlated double sampler 1006 double samples a specific noise level and a signal level due to an electrical signal, and outputs a difference level corresponding to the difference between the noise level and the signal level.

[0028] An analog-to-digital converter (ADC) 1007 converts an analog signal corresponding to the difference level output from the correlated double sampler 1006 into a digital signal and outputs it.

[0029] The input / output buffer 1008 latches the digital signals, and the latched signals are sequentially output to a video signal processor (not shown) according to the results of decoding by the column decoder 1004 .

[0030] FIG. 2 is a circuit diagram of an active pixel sensor array of an image sensor according to one embodiment.

[0031] 1 and 2, the active pixel sensor array 1001 includes a plurality of unit pixels UP, which are arranged in a matrix. Each unit pixel UP includes a transfer transistor TX. Each unit pixel UP further includes some or all of logic transistors (RX, SX, DX). The logic transistors are a reset transistor RX, a selection transistor SX, and a source follower transistor DX. The transfer transistor TX includes a transfer gate (transfer gate line or transfer gate electrode) TG. The transfer gate TG is a dual transfer gate in which two transfer gates form a pair. Each unit pixel UP further includes a photoelectric conversion unit PD and a floating diffusion region FD. Each unit pixel UP includes one or more photoelectric conversion units PD. In an embodiment, each unit pixel UP includes a first sub-unit pixel UP1 and a plurality of second sub-unit pixels UP2. The first sub-unit pixel UP1 includes a photoelectric conversion unit PD, a transfer transistor TX, a floating diffusion region FD, a reset transistor RX, a source follower transistor DX, and a selection transistor SX. Each of the second sub-unit pixels UP2 includes a photoelectric conversion unit PD, a floating diffusion region FD, and a transfer gate TG that selectively connects the photoelectric conversion unit PD to the floating diffusion region FD. The floating diffusion region FD of each of the second sub-unit pixels UP2 is connected to the floating diffusion region FD of the first sub-unit pixel UP1 via a floating diffusion region connection unit 19 described with reference to FIG. 5 and FIGS. 6A to 6C. Each of the second sub-unit pixels UP2 shares the logic transistors (RX, DX, SX) of the first sub-unit pixel UP1. The logic transistors (RX, SX, DX) share the sub-unit pixels (UP1, UP2) with each other. For example, each unit pixel UP includes one first sub-unit pixel UP1 and seven second sub-unit pixels UP2, and the eight sub-unit pixels (UP1, UP2) share one set of logic transistors (RX, SX, DX). However, the present invention is not limited thereto.In one embodiment, each unit pixel includes eight sub-unit pixels having a photoelectric conversion section, a floating diffusion region, and a transfer transistor selectively connecting the photoelectric conversion section and the floating diffusion region, and logic transistors (RX, SX, and DX) are arranged in a divided manner in some or all of the eight sub-unit pixels (hereinafter, the first sub-unit pixel UP1 and the second sub-unit pixel UP2 are represented by the reference symbol UP).

[0032] The photoelectric conversion unit PD generates and accumulates photoelectric charges in proportion to the amount of light incident from the outside. The photoelectric conversion unit PD includes one of a photodiode, a phototransistor, a photogate, a pin photodiode, and a combination thereof. The transfer transistor TX transfers the charge generated in the photoelectric conversion unit PD to the floating diffusion region FD. The floating diffusion region FD receives the charge generated in the photoelectric conversion unit PD and cumulatively stores it. The source follower transistor DX is controlled according to the amount of photoelectric charge accumulated in the floating diffusion region FD.

[0033] The reset transistor RX periodically resets the charge stored in the floating diffusion region F. The drain electrode of the reset transistor RX is connected to the floating diffusion region FD, and the source electrode is connected to the power supply voltage V. DD When the reset transistor RX is turned on, the power supply voltage V DD is applied to the floating diffusion region FD. Therefore, when the reset transistor RX is turned on, the charge stored in the floating diffusion region FD is discharged and the floating diffusion region FD is reset.

[0034] The source follower transistor DX, which includes a source follower gate (source follower gate line or source follower gate electrode) SF, acts as a source follower buffer amplifier. The source follower transistor DX amplifies the potential change in the floating diffusion region FD and outputs it to the output line (V OUT ) to output.

[0035] A selection transistor SX including a selection gate (selection gate line) SEL selects a sub-unit pixel UP to be read out on a row-by-row basis. When the selection transistor SX is turned on, a potential change in the floating diffusion region FD is transmitted to the output line (V OUT ) is output.

[0036] FIG 3 is a plan view of an image sensor according to an embodiment. FIG 4 is a cross-sectional view taken along line AA' in FIG 3. FIG 5 is an enlarged plan view showing an arrangement of a transfer gate, a floating diffusion region, a floating diffusion region connector, a source follower gate, and the like in an image sensor according to an embodiment. FIG 6A is a cross-sectional view taken along line AA' in FIG 5, which corresponds to region P1 in FIG 4. FIG 6B is a cross-sectional view taken along line BB' in FIG 5. FIG 6C is a cross-sectional view taken along line CC' in FIG 5.

[0037] 3 and 4, the image sensor 500 according to the present embodiment has a structure in which a first sub-chip CH1 and a second sub-chip CH2 are bonded together. The first sub-chip CH1 is disposed on the second sub-chip CH2. The first sub-chip CH1 includes a first substrate 1. The first substrate 1 is, for example, a silicon single crystal wafer, a silicon epitaxial layer, or a silicon-on-insulator (SOI) substrate. The first substrate 1 is, for example, doped with impurities of a first conductivity type. For example, the first conductivity type is a P type. The first substrate 1 includes a front surface 1a and a rear surface 1b facing each other. In this specification, the front surface 1a is named a first surface 1a, and the rear surface 1b is named a second surface 1b. The first substrate 1 includes a pixel array region APS, an optical black region OB, and a peripheral region ER.

[0038] The pixel array region APS and the optical black region OB each include a plurality of sub-unit pixels UP. Each sub-unit pixel UP is one of the first sub-unit pixel UP1 or the second sub-unit pixel UP2 depending on whether the logic transistors (RX, SX, DX) are arranged as described above with reference to FIG. 2. The optical black region OB surrounds the pixel array region APS. The peripheral region ER surrounds the pixel array region APS and the optical black region OB. The peripheral region ER includes a contact region BR1, a via region BR2, and a pad region PR. The via region BR2 is located between the contact region BR1 and the pad region PR. The pad region PR is located at the outermost edge of the peripheral region ER.

[0039] In the pixel array region APS and the optical black region OB, a first pixel isolation part DTI1 is arranged in the first substrate 1 to isolate / define the unit pixels UP. The first pixel isolation part DTI1 penetrates the first substrate 1 and extends to the contact region BR1 in the peripheral region ER. The first pixel isolation part DTI1 has a mesh-like shape in plan view.

[0040] In the peripheral region ER, rear contacts BCA, rear vias BVS, and rear conductive pads PAD are arranged on the rear surface 1b of the first substrate 1. The rear vias BVS include a first rear via BVS(1) and a second rear via BVS(2).

[0041] The first pixel isolation portion DTI1 and the second pixel isolation portion DTI2 are each located inside a deep trench 22 formed from the front surface 1a toward the back surface 1b of the first substrate 1. The first pixel isolation portion DTI1 and the second pixel isolation portion DTI2 are FDTI (Frontside Deep Trench Isolation). The first pixel isolation portion DTI1 and the second pixel isolation portion DTI2 each include a buried insulating pattern 12, an isolation insulating film 14, and an isolation conductive pattern 16. The buried insulating pattern 12 is interposed between the isolation conductive pattern 16 and the first interlayer insulating film IL. The isolation insulating film 14 is interposed between the isolation conductive pattern 16 and the first substrate 1, and between the buried insulating pattern 12 and the first substrate 1.

[0042] The buried insulating pattern 12 and the isolation insulating film 14 are formed of an insulating material having a refractive index different from that of the first substrate 1. The buried insulating pattern 12 and the isolation insulating film 14 include, for example, silicon oxide. The isolated conductive pattern 16 is spaced apart from the first substrate 1. The isolated conductive pattern 16 includes a polysilicon film or a silicon germanium film doped with an impurity. The impurity doped in the polysilicon or silicon germanium film is, for example, one of boron, silver, and arsenic. Alternatively, the isolated conductive pattern 16 includes a metal film.

[0043] 4, the first pixel isolation portion DTI1 and the second pixel isolation portion DTI2 each have a horizontal cross-sectional area that narrows from the front surface 1a toward the rear surface 1b of the first substrate 1. The second pixel isolation portion DTI2 is also called a "substrate isolation portion."

[0044] Photoelectric conversion units PD are arranged in the first substrate 1. The photoelectric conversion units PD are doped with impurities of a second conductivity type opposite to the first conductivity type. The second conductivity type is, for example, N type. The N type impurities doped in the photoelectric conversion units PD form a PN junction with P type impurities doped in the surrounding first substrate 1 to provide a photodiode. Two or more photoelectric conversion units PD are arranged in one sub-unit pixel UP.

[0045] In the first substrate 1, a shallow trench isolation STI is disposed adjacent to the front surface 1a. The isolation STI is penetrated by a first pixel isolation DTI1. The isolation STI defines an active region ACT adjacent to the front surface 1a in each sub-unit pixel UP. The active region ACT is provided for the transistors (TX, RX, DX, SX) of FIG. 2. A floating diffusion region connection portion 19 that connects between floating diffusion regions FD described later is embedded and located inside the isolation STI. The floating diffusion region connection portion 19 penetrates the first pixel isolation DTI1 that penetrates the isolation STI, or extends along the first pixel isolation DTI1. The floating diffusion region connection portion 19 includes a polysilicon film or a silicon germanium film doped with impurities, or a metal.

[0046] Referring to FIG. 4, in each unit pixel UP, a transmission gate TG is disposed on a front surface 1a of a first substrate 1. A portion of the transmission gate TG extends into the first substrate 1. The transmission gate TG is a vertical type. Alternatively, the transmission gate TG may be a planar type that does not extend into the first substrate 1 and has a flat shape. The transmission gate TG is a dual transmission gate that is a pair of two separated from each other. A gate oxide film Gox is interposed between the transmission gate TG and the first substrate 1.

[0047] A floating diffusion region FD is disposed in the first substrate 1 on one side of the transmission gate TG. A plurality of floating diffusion regions FD are electrically connected via floating diffusion region connection parts 19. For example, as shown in FIG. 5, eight floating diffusion regions FD are connected via one floating diffusion region connection part 19. The number of floating diffusion regions FD connected via the floating diffusion region connection part 19 is the same as the number of sub-unit pixels UP sharing the source follower transistor DX. The floating diffusion region FD is, for example, a part of the first substrate 1 doped with a second conductive type impurity, and is polysilicon, silicon germanium, or metal doped with the second conductive type impurity. The floating diffusion region connection part 19 is, for example, polysilicon, silicon germanium, or metal doped with the second conductive type impurity.

[0048] The image sensor 500 is a rear-side light receiving image sensor. Light is incident on the inside of the first substrate 1 through a microlens ML located on the rear surface 1b of the first substrate 1. The incident light generates electron-hole pairs at a PN junction. The electrons thus generated move to the photoelectric conversion unit PD. When a voltage is applied to the transfer gate TG, the electrons move to the floating diffusion region FD.

[0049] A first unit pixel UP(1) and a second unit pixel UP(2) are arranged in the optical black area OB of the first substrate 1. In the first unit pixel UP(1), a black photoelectric conversion unit PD' is provided in the first substrate 1. In the second unit pixel UP(2), a dummy area PD" is provided in the first substrate 1. The black photoelectric conversion unit PD' is doped with impurities of a second conductivity type different from the first conductivity type. The second conductivity type is, for example, N type. The pixel array area APS includes a plurality of unit pixels UP. The black photoelectric conversion unit PD' has a structure similar to that of the photoelectric conversion unit PD, but does not perform the same operation as the photoelectric conversion unit PD (i.e., the operation of receiving light and generating an electrical signal). The dummy area PD" is not doped with impurities. The signal generated in the dummy area PD" is then used as information for removing noise.

[0050] The first sub-chip CH1 further includes a first interlayer insulating film IL1 disposed on the front surface 1a. The first interlayer insulating film IL1 is formed as a multilayer film of at least one film selected from a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and a porous low dielectric film. A first wiring 15 is disposed between or inside the first interlayer insulating films IL1. The floating diffusion region connecting portion 19 is connected to the first wiring 15 by a contact plug. The contact plug penetrates a portion of the first interlayer insulating film IL1 (lowest layer) closest to the front surface 1a in the first interlayer insulating film IL1 in the pixel array region APS.

[0051] The second sub-chip CH2 includes a second substrate SB2, a peripheral transistor PTR arranged thereon, and a second interlayer insulating film IL2 covering these. A second wiring 217 is arranged in the second interlayer insulating film IL2. The second sub-chip CH2 includes a circuit for storing an electrical signal generated in the first sub-chip CH1.

[0052] 4, an anti-reflection structure AL is disposed on the rear surface 1b of the first substrate 1. The anti-reflection structure AL includes a first insulating film A1, a conductive film A2, a second insulating film A3, and a third insulating film A4, which are stacked in this order. The first insulating film A1, the second insulating film A3, and the third insulating film A4 each include a different material. In one embodiment, the first insulating film A1 includes aluminum oxide, the second insulating film A3 includes silicon oxide, and the third insulating film A4 includes hafnium oxide. The conductive film A2 is an electrically conductive film and includes titanium oxide.

[0053] In this specification, the first insulating film A1 is named "first antireflection film", the conductive film A2 is named "second antireflection film", the second insulating film A3 is named "third antireflection film", and the third insulating film A4 is named "fourth antireflection film".

[0054] The first substrate 1 has a first refractive index n1, the first insulating film A1 has a second refractive index n2, the conductive film A2 has a third refractive index n3, and the second insulating film A3 has a fourth refractive index n4. The average value of the second refractive index n2 and the third refractive index n3 {(n2+n3) / 2) is smaller than the first refractive index n1 and larger than the fourth refractive index n4. The first refractive index n1 is 4.0 to 4.4. The second refractive index n2 is 2.0 to 3.0. The third refractive index n3 is 2.2 to 2.8. The fourth refractive index n4 is 1.0 to 1.9.

[0055] The first insulating film A1 has a first thickness T1, the conductive film A2 has a second thickness T2, the second insulating film A3 has a third thickness T3, and the third insulating film A4 has a fourth thickness T4. Here, the second thickness T2 is greater than each of the first thickness T1 and the fourth thickness T4, and is smaller than the third thickness T3. The first thickness T1 is 10 Å to 100 Å. The second thickness T2 is 100 Å to 600 Å. The third thickness T3 is 600 Å to 900 Å. The fourth thickness T4 is 20 Å to 200 Å.

[0056] Due to the relationship between the refractive indices and / or the relationship between the thicknesses, the light L1 incident on the microlens ML can be refracted and passed through the multi-layer structure of the anti-reflection structure AL to efficiently enter the photoelectric conversion unit PD, thereby increasing the light receiving rate and providing the image sensor 500 with clear image quality.

[0057] In the image sensor 500 according to the present embodiment, the antireflection structure AL is made of titanium oxide (TiO 2 ), but titanium oxide (TiO 2 The conductive film A2 made of ZnO 2 , ZnO 3 , and ZnO 4 , reduces the reflectance of all color lights overall, and further reduces the reflectance of blue light in particular, thereby increasing the quantum efficiency (QE) of the blue pixel.

[0058] The first insulating film A1 also serves as a negative fixed charge film, which can reduce dark current and white spots.

[0059] In addition, a predetermined negative potential (voltage) can be applied to the conductive film A2 to accumulate holes (h+) generated by light incident through the back surface near the back surface 1b of the first substrate 1. This can further improve the dark current and white spots.

[0060] 3 and 4, in the contact region BR1, a back contact BCA is arranged on the back surface 1b of the first substrate 1. In the via region BR2, a first back surface via BVS(1) is arranged on the back surface 1b of the first substrate 1. In the pad region PR, a back surface 1b of the first substrate 1 is arranged with a back conductive pad PAD and a second back surface via BVS(2). A predetermined number of the second back surface vias BVS(2) are grouped together and arranged around the back conductive pad PAD. The second back surface vias in each group are arranged in two columns or two rows, and the corresponding back conductive pads among the back conductive pads are arranged in the space between the two columns or two rows.

[0061] Referring to FIG. 4, the back contact BCA penetrates the anti-reflection structure AL and at least a portion of the first substrate 1. The back contact BCA is disposed inside the first back trench 46. The back contact BCA includes a first conductive pattern 52a and a first metal pattern 54a. The first conductive pattern 52a conformally covers the side and bottom of the first back trench 46 and contacts and is electrically connected to the conductive film A2 of the anti-reflection structure AL. The first conductive pattern 52a has a single layer or a multi-layer structure of at least one of a titanium film, a titanium nitride film, and a tungsten film. The first metal pattern 54a includes, for example, aluminum. The first metal pattern 54a fills the first back trench 46.

[0062] The back contact BCA is in contact with the isolated conductive pattern 16 of the first pixel isolation unit DTI1. The back contact BCA is connected to the first back via BVS(1) through the back connection wiring 52b to receive a predetermined negative potential, which is then applied to the isolated conductive pattern 16 of the first pixel isolation unit DTI1. The isolated conductive pattern 16 serves as a common bias line. This allows holes present on the surface of the first substrate 1 in contact with the first pixel isolation unit DTI1 to be captured, thereby enhancing the dark current improvement effect.

[0063] The first back vias BVS(1) are disposed in the first holes H1. The first back vias BVS(1) partially penetrate the anti-reflection structure AL, the first substrate 1, the first interlayer insulating film IL1, and the second interlayer insulating film IL2. The first back vias BVS(1) connect a part of the first wiring 15 of the first subchip CH1 to a part of the second wiring 217 of the second subchip CH2. The first back vias BVS(1) conformally fill the inner walls and bottom surfaces of the first holes H1. The first back vias BVS(1) include the same material as the first conductive pattern 52a and have the same thickness. The first back vias BVS(1) have a single-layer or multi-layer structure of at least one of a titanium film, a titanium nitride film, and a tungsten film.

[0064] One of the first back vias BVS(1) is electrically connected to one of the back contacts BCA by one of the back connection wires 52b. The back connection wire 52b includes the same material as the first conductive pattern 52a and has the same thickness. The back connection wire 52b has a single layer or a multi-layer structure of at least one of a titanium layer, a titanium nitride layer, and a tungsten layer.

[0065] The back conductive pad PAD is disposed inside the second back trench 60. The back conductive pad PAD includes a second conductive pattern 52c and a second metal pattern 54b. The second conductive pattern 52c conformally covers the side and bottom of the second back trench 60. The second conductive pattern 52c includes the same material as the first conductive pattern 52a and has the same thickness. The second conductive pattern 52c has a single layer or multi-layer structure of at least one of a titanium layer, a titanium nitride layer, and a tungsten layer. The second metal pattern 54b includes, for example, aluminum. The second metal pattern 54b fills the second back trench 60.

[0066] The second back vias BVS(2) are disposed in the second holes H2. The second back vias BVS(2) partially penetrate the first insulating film A1, the first substrate 1, the first interlayer insulating film IL1, and the second interlayer insulating film IL2 of the anti-reflection structure AL. The second back vias BVS(2) are connected to a part of the second wiring 217. Although not shown, the second back vias BVS(2) may be connected to a part of the first wiring 15. The second back vias BVS(2) conformally fill the inner wall and bottom surface of the second holes H2. The second back vias BVS(2) include the same material as the first conductive pattern 52a and have the same thickness. The second back vias BVS(2) have a single layer or multi-layer structure of at least one of a titanium layer, a titanium nitride layer, and a tungsten layer. One of the second back vias BVS(2) is electrically connected to one of the back conductive pads PAD by one of the back connecting wires 52c.

[0067] In the peripheral region ER, a first optical black pattern 52p is disposed on the anti-reflection structure AL. The first optical black pattern 52p includes the same material as the first conductive pattern 52a and has the same thickness. The first optical black pattern 52p has a single layer or a multi-layer structure of at least one of a titanium layer, a titanium nitride layer, and a tungsten layer.

[0068] In the pixel array region APS, a light-shielding grid pattern 48a is disposed on the anti-reflection structure AL. A low-refractive grid pattern 50a is disposed on the light-shielding grid pattern 48a. The light-shielding grid pattern 48a and the low-refractive grid pattern 50a overlap the first pixel isolation unit DTI1 and have a grid shape in plan view. The light-shielding grid pattern 48a includes at least one of titanium and titanium nitride. The low-refractive grid patterns 50a all have the same thickness and include the same organic material. The low-refractive grid patterns 50a have a refractive index smaller than that of the color filters CF1 and CF2. For example, the low-refractive grid patterns 50a have a refractive index of about 1.3 or less. The light-shielding grid pattern 48a and the low-refractive grid pattern 50a prevent crosstalk between adjacent sub-unit pixels UP.

[0069] In the pixel array region APS, color filters CF1, CF2 are disposed between the low-refractive grid patterns 50a. The color filters CF1, CF2 each have one of blue, green, and red. As another example, the color filters CF1, CF2 may include other colors such as cyan, magenta, and yellow. In the image sensor according to the present embodiment, the color filters CF1, CF2 are arranged in a Bayer pattern. As another example, the color filters CF1, CF2 are arranged in a 2×2 Tetra pattern, a 3×3 Nona pattern, or a 4×4 Hexadeca pattern. The color filters CF1, CF2 have a one-to-one correspondence with the unit pixels UP or a pair-wise correspondence with the unit pixels UP. For example, one unit pixel UP is disposed at a position corresponding to each of the color filters CF1 and CF2, or two adjacent unit pixels UP are disposed, or four adjacent unit pixels UP are disposed.

[0070] A capping pattern CFR is disposed on the first low refraction protection pattern 50b filling the inside of the first back via BVS(1) and the second low refraction protection pattern 50c filling the inside of the second back via BVS(2). The capping pattern CFR includes, for example, a photoresist material.

[0071] A protective film 56 is conformally disposed on the low refraction grid pattern 50a, the first conductive pattern 52a, the first metal pattern 54a, the second conductive pattern 52c, the rear connecting wire 52b, the first optical black pattern 52p, the capping pattern CFR, and the low refraction residual pattern 50r.

[0072] The second optical black pattern CFB is disposed on the protective film 56. The second optical black pattern CFB includes, for example, the same material as the blue color filter.

[0073] In the pixel array region APS, microlenses ML are disposed on the color filters (CF1, CF2). The edges of the microlenses ML are in contact with each other and connected. The microlenses ML form an array. The microlenses ML are also called a "microlens array."

[0074] 5, 6A, 6B and 6C, an active region ACT, a transfer gate TG, a floating diffusion region FD and a photoelectric conversion unit PD are located in each of the sub-unit pixels UP.

[0075] The active region ACT is partitioned by the element isolation portion STI and is divided into a plurality of portions even within one sub-unit pixel UP. For example, as shown in Fig. 5, a first active region ACT1 and a second active region ACT2 are located within one sub-unit pixel UP, and some or all of logic transistors (RX, SX, DX) including a source follower transistor DX are located in the first active region ACT1, and a transfer transistor TX is located in the second active region ACT2.

[0076] The transfer gates TG of the gate electrodes of the transfer transistors TX are positioned so that two of them form a pair and at least a portion of them overlap the second active region ACT2.

[0077] The floating diffusion region FD is located on one side of the second active region ACT2, and the floating diffusion regions FD of two adjacent sub-unit pixels UP are located to face each other with the element isolation part STI therebetween.

[0078] In the element isolation portion STI, a floating diffusion region connection portion 19 is located, which electrically connects the floating diffusion regions FD. For example, the floating diffusion region connection portion 19 is embedded in the element isolation portion STI, and the upper surface of the floating diffusion region connection portion 19 is lower than the upper surface of the element isolation portion STI. The floating diffusion region connection portion 19 includes a trunk portion 191, a first branch portion 192 extending from the trunk portion 191 and connected to the source follower gate SF, and a second branch portion 193 extending from the trunk portion 191 and connected to the floating diffusion region FD. The floating diffusion region connection portion 19 connects eight floating diffusion regions FD to each other, for example, as shown in FIG. 5. The number of floating diffusion regions FD connected to one floating diffusion region connection portion 19 may be less than or more than eight. The floating diffusion region connection portion 19 includes, for example, polysilicon or silicon germanium doped with a second conductive type impurity, or a metal such as aluminum, copper, or silver. The floating diffusion region connecting portion 19 fills a part of the groove formed in the element isolation portion STI, and the cover insulating film CI covers the floating diffusion region connecting portion 19. The cover insulating film CI fills the remaining part of the groove formed in the element isolation portion STI, and the upper surface of the cover insulating film CI coincides with the upper surface of the element isolation portion STI, but is not limited thereto. In some embodiments, the cover insulating film CI is an insulating film located on the element isolation portion STI. In one embodiment, the floating diffusion region connecting portion 19 includes a trunk portion 191 extending in a first direction D1, a first branch portion 192 extending in a second direction D2 and connecting the trunk portion 191 to the source follower gate electrode SF, and a second branch portion 193 extending in the second direction D2 and connecting to a corresponding floating diffusion region FD among the plurality of floating diffusion regions FD. The plurality of floating diffusion regions FD include a first floating diffusion region group FD1 and a second floating diffusion region group FD2. The first floating diffusion region group FD1 is spaced apart from the second floating diffusion region group FD2 in the second direction D2. In plan view, a portion of the isolation portion STI is disposed in the space between the first floating diffusion region group FD1 and the second floating diffusion region group FD2. The trunk portion 191 is disposed in the space between the first floating diffusion region group FD1 and the second floating diffusion region group FD2. For example, the trunk portion 191 is embedded in the isolation portion STI between the first floating diffusion region group FD1 and the second floating diffusion region group FD2.In one embodiment, the unit pixel UP includes a plurality of transistors including a transfer transistor TX, a source follower transistor DX, a reset transistor RX, and a selection transistor SX. The unit pixel UP includes a plurality of photoelectric conversion units (e.g., eight photoelectric conversion units), a plurality of first active regions ACT1, and a plurality of second active regions ACT2. At least one of the source follower transistor DX, the reset transistor RX, and the selection transistor SX is disposed in one or more of the plurality of first active regions ACT1. The transfer transistor TX is disposed in the plurality of second active regions ACT2. Each transfer transistor TX selectively couples each of the plurality of photoelectric conversion units PD to a corresponding floating diffusion region FD among the plurality of floating diffusion regions FD.

[0079] 6A, the floating diffusion region connector 19 contacts the first substrate 1 between the element isolation region STI and the floating diffusion region FD. In some embodiments, as shown in FIG. 6B, the floating diffusion region connector 19 is surrounded by the element isolation region STI and the floating diffusion region FD and does not contact the first substrate 10.

[0080] 5 and 6C, a gate insulating film GI is located on the front surface 1a of the first substrate 1, and a source follower gate SF is located on the gate insulating film GI. The gate insulating film GI is made of the same material as the gate oxide film Gox between the transfer gate TG and the first substrate 1. In some embodiments, the gate insulating film GI is made of a different material from the gate oxide film Gox. The source follower gate SF, which is the gate electrode of the source follower transistor DX, is located across two adjacent first active regions ACT1. That is, the two first active regions ACT1 realize one source follower transistor DX. The source follower gate SF is polysilicon or silicon germanium doped with second conductive type impurities, or a metal.

[0081] A contact hole CA penetrating the cover insulating film CI and the gate insulating film GI is located on the first branch portion 192 of the floating diffusion region connector 19, and the source follower gate SF is connected to the floating diffusion region connector 19 through the contact hole CA.

[0082] As described above, by positioning the floating diffusion region connecting portion 19 in the element isolation portion STI, it is possible to reduce electrostatic coupling formed with the wiring located in the interlayer insulating film, and to increase the degree of freedom in wiring arrangement. For example, when a wiring overlaps the floating diffusion region connecting portion 19 embedded in the element isolation portion STI, the parasitic capacitance therebetween is reduced, and therefore the wiring can be arranged without any restrictions on the position of the floating diffusion region connecting portion 19.

[0083] 7A-7D are cross-sectional views illustrating a method of forming a floating diffusion region connection portion of an image sensor according to an embodiment.

[0084] Referring to FIG. 7A, a photoelectric conversion unit PD is formed by performing an ion implantation process on the first substrate 1, and an isolation unit STI is formed on the front surface 1a of the first substrate 1 to define an active region. The isolation unit STI is formed by a shallow trench isolation process. The isolation unit STI and a part of the first substrate 1 are etched to form a deep trench. An isolation insulating film 14 is conformally formed on the front surface 1a of the first substrate 1, and the deep trench is filled with a conductive material, and then an etch-back process is performed to form an isolation conductive pattern 16 inside the deep trench. Then, a buried insulating pattern 12 is formed on the isolation conductive pattern 16, and the isolation insulating film 14 on the front surface 1a is removed to expose the front surface 1a. Thus, a pixel isolation unit DTI is formed. In FIGS. 7A to 7D, the isolation insulating film 14 and the buried insulating pattern 12 on the upper end of the pixel isolation unit DTI are illustrated without distinction from the surrounding isolation unit STI, but depending on the embodiment, there is a boundary surface between them.

[0085] Then, a floating diffusion region FD is formed on the front surface 1a of the first substrate 1 by performing a conventional process, and a groove GR in which a floating diffusion region connection portion 19 is to be located is formed in the element isolation portion STI by a method such as photoetching.

[0086] 7B, the groove GR is partially filled with polysilicon or metal to form a preliminary floating diffusion region connection portion 19P. The preliminary floating diffusion region connection portion 19P is formed by a process such as film deposition, plating, CMP, and / or etch-back.

[0087] 7C, a photosensitive material is applied and developed to form a photosensitive material pattern PRP that exposes only the preliminary floating diffusion region connector 19P, and second conductive impurity ions are doped to form the floating diffusion region connector 19. This process can be omitted when the floating diffusion region connector 19 is made of metal.

[0088] 7D, a cover insulating film CI is conformally formed on the photosensitive material pattern PRP and the floating diffusion region connector 19, and the photosensitive material pattern PRP is removed by ashing, thereby removing the cover insulating film CI thereon. Thus, the cover insulating film CI covering the floating diffusion region connector 19 is formed. Alternatively, the photosensitive material pattern PRP may be removed, and the cover insulating film CI may be deposited or applied, or the surfaces of the first substrate 1 and the floating diffusion region connector 19 may be oxidized to form an oxide film. Then, the cover insulating film CI filling the groove GR on the floating diffusion region connector 19 is left and the remaining part is removed by a method such as CMP. Alternatively, the cover insulating film CI placed on the front surface 1a of the first substrate 1 may be used as an interlayer insulating film IL1 or a gate insulating film GI without being removed.

[0089] Then, a transmission gate TG, a source follower gate SF, etc. are formed by carrying out normal processes.

[0090] 8A to 8D are cross-sectional views illustrating a method of forming a floating diffusion region connector of an image sensor according to another embodiment.

[0091] Referring to FIG. 8A, a photoelectric conversion unit PD is formed by performing an ion implantation process on the first substrate 1, and an isolation unit STI is formed on the front surface 1a of the first substrate 1 to define an active region. The isolation unit STI is formed by a shallow trench isolation process. The isolation unit STI and a part of the first substrate 1 are etched to form a deep trench. An isolation insulating film 14 is conformally formed on the front surface 1a of the first substrate 1, and the deep trench is filled with a conductive material, and then an etch-back process is performed to form an isolation conductive pattern 16 inside the deep trench. In addition, a buried insulating pattern 12 is formed on the isolation conductive pattern 16, and the isolation insulating film 14 on the front surface 1a can be removed to expose the front surface 1a. As a result, a pixel isolation unit DTI is formed. Although FIGS. 8A to 8D show that the isolation insulating film 14 and the buried insulating pattern 12 on the upper end of the pixel isolation unit DTI are integrated with the surrounding isolation unit STI without distinction, there is a boundary between them depending on the embodiment.

[0092] Next, a floating diffusion region FD is formed on the front side 1a of the first substrate 1 by carrying out a normal process, and a photosensitive material pattern PRP is formed through a photolithography process. The first substrate 1 is etched using this as a mask to form a groove GR in which the floating diffusion region connection portion 19 is to be located in the element isolation portion STI.

[0093] Referring to FIG. 8B, polysilicon is deposited on the photoresist pattern PRP and the groove GR to form a preliminary floating diffusion region connection layer 19L.

[0094] Next, referring to FIG. 8C, the preliminary floating diffusion region connection layer 19L is doped with impurity ions of the second conductivity type.

[0095] Next, referring to FIG. 8D, the photoresist pattern PRP is removed by ashing together with the preliminary floating diffusion region connecting portion layer 19L thereon, thereby forming the floating diffusion region connecting portion 19. Then, as shown in FIG.

[0096] 7D, a cover insulating film CI may be deposited or applied, or an oxide film may be formed by oxidizing the surfaces of the first substrate 1 and the floating diffusion region connector 19. Then, the remaining portions disposed on the front surface 1a of the first substrate 1 are removed by a method such as CMP, leaving only the cover insulating film CI filling the groove GR on the floating diffusion region connector 19. Alternatively, the cover insulating film CI disposed on the front surface 1a of the first substrate 1 may be used as an interlayer insulating film IL1 or a gate insulating film GI without being removed.

[0097] Then, a transmission gate TG, a source follower gate SF, etc. are formed by carrying out normal processes.

[0098] FIG. 9 is a cross-sectional view of an image sensor according to another embodiment.

[0099] The image sensor 503 according to the embodiment of FIG. 9 has a structure in which first to third sub-chips (CH1 to CH3) are bonded in order.

[0100] The first sub-chip CH1 preferably has an image sensing function. The first sub-chip CH1 includes a first substrate 1. The first substrate 1 is, for example, a silicon single crystal wafer, a silicon epitaxial layer, or an SOI (silicon on insulator) substrate. The first substrate 1 is, for example, doped with impurities of a first conductivity type. For example, the first conductivity type is P-type. The first substrate 1 includes a front surface 1a and a rear surface 1b facing each other. In this specification, the front surface 1a is named the first surface 1a, and the rear surface 1b is named the second surface 1. The first substrate 1 includes a pixel array region APS, an optical black region OB, and a peripheral region ER.

[0101] The pixel array region APS and the optical black region OB each include a plurality of unit pixels UP. A plurality of microlenses ML are positioned in the pixel array region APS, each corresponding to one of the unit pixels UP.

[0102] The optical black area OB surrounds the pixel array area APS. The peripheral area ER surrounds the pixel array area APS and the optical black area OB. The peripheral area ER includes a pad area PR. The pad area PR is located at the outermost edge of the peripheral area ER.

[0103] In the pixel array region APS and the optical black region OB, a first pixel isolation part DTI1 is disposed in the first substrate 1 to isolate / define the unit pixels UP. The first pixel isolation part DTI1 extends to the contact region BR1 in the peripheral region ER. The first pixel isolation part DTI1 has a mesh shape in plan view. A second pixel isolation part DTI2 is disposed in the first substrate 1 in the peripheral region ER.

[0104] The first pixel isolation portion DTI1 and the second pixel isolation portion DTI2 are located inside a deep trench 22 formed from the front surface 1a to the back surface 1b of the first substrate 1. The first pixel isolation portion DTI1 and the second pixel isolation portion DTI2 are FDTI (Frontside Deep Trench Isolation). The first pixel isolation portion DTI1 and the second pixel isolation portion DTI2 each include a buried insulating pattern 12, an isolation insulating film 14, and an isolation conductive pattern 16. The buried insulating pattern 12 is interposed between the isolation conductive pattern 16 and the first interlayer insulating film IL1. The isolation insulating film 14 is interposed between the isolation conductive pattern 16 and the first substrate 1 and between the buried insulating pattern 12 and the first substrate 1.

[0105] The buried insulating pattern 12 and the isolation insulating film 14 are formed of an insulating material having a refractive index different from that of the first substrate 1. The buried insulating pattern 12 and the isolation insulating film 14 include, for example, silicon oxide. The isolated conductive pattern 16 is spaced apart from the first substrate 1. The isolated conductive pattern 16 includes a polysilicon film or a silicon germanium film doped with an impurity. The impurity doped in the polysilicon or silicon germanium film is, for example, one of boron, silver, and arsenic. Alternatively, the isolated conductive pattern 16 includes a metal film.

[0106] The first pixel isolation portion DTI1 and the second pixel isolation portion DTI2 each have a horizontal cross-sectional area that narrows from the front surface 1a toward the rear surface 1b of the first substrate 1. The second pixel isolation portion DTI2 is also named a "substrate isolation portion."

[0107] Photoelectric conversion units PD are arranged in the first substrate 1. The photoelectric conversion units PD are doped with impurities of a second conductivity type opposite to the first conductivity type. The second conductivity type is, for example, N type. The N type impurities doped in the photoelectric conversion units PD form a PN junction with the P type impurities doped in the surrounding first substrate 1 to provide a photodiode.

[0108] A first isolation portion STI1 is arranged in the first substrate 1 adjacent to the front surface 1a. The first isolation portion STI1 is penetrated by a first pixel isolation portion DTI1. The first isolation portion STI1 defines an active area adjacent to the front surface 1a. The active area is provided for the transistors (TX, RX, DX, SX) of FIG. 2.

[0109] 9, in each sub-unit pixel UP, a transfer gate TG is disposed on a front surface 1a of a first substrate 1. A portion of the transfer gate TG extends into the first substrate 1. The transfer gate TG is of a vertical type. Alternatively, the transfer gate TG may be of a planar type that does not extend into the first substrate 1 and has a flat shape. A gate oxide film Gox is interposed between the transfer gate TG and the first substrate 1.

[0110] A floating diffusion region FD is disposed in the first substrate 1 on one side of the transmission gate TG. A plurality of floating diffusion regions FD are electrically connected to each other via a floating diffusion region connection part 19. For example, as shown in FIG. 5, eight floating diffusion regions FD are connected to each other via one floating diffusion region connection part 19. For example, each of the eight floating diffusion regions FD collects charges generated from a corresponding photoelectric conversion unit PD, and selectively outputs such charges of the eight floating diffusion regions FD via a source follower transistor DX acting as a source follower buffer amplifier, thereby selectively outputting a potential change in the floating diffusion region FD as an electrical signal corresponding to light incident on the unit pixel UP. The number of floating diffusion regions FD connected to each other via the floating diffusion region connection part 19 is the same as the number of sub-unit pixels UP sharing the source follower transistor DX. The floating diffusion region FD is, for example, a part of the first substrate 1 doped with a second conductive type impurity, or is polysilicon, silicon germanium, or metal doped with a second conductive type impurity. The floating diffusion region connection portion 19 is, for example, polysilicon or silicon germanium doped with impurities of the second conductivity type, or a metal.

[0111] In each unit pixel UP arranged in the first sub-chip CH1, only a transmission gate TG, a photoelectric conversion unit PD, and a floating diffusion region FD are arranged. Some or all of the selection gate SEL, source follower gate SF, reset gate RG, etc. are arranged in the second sub-chip CH2, not in the first sub-chip CH1. That is, some or all of the logic transistors (RX, SX, DX) are arranged in the second sub-chip CH2.

[0112] The image sensor 503 is a rear light receiving image sensor. Light is incident on the inside of the first substrate 1 through a microlens ML located on the rear surface 1b of the first substrate 1. The incident light generates electron-hole pairs at the PN junction. The electrons thus generated move to the photoelectric conversion unit PD. When a voltage is applied to the transfer gate TG, the electrons move to the floating diffusion region FD.

[0113] The first sub-chip CH1 includes a transfer gate TG and a first interlayer insulating film IL1 covering the transfer gate TG on a front surface 1a of a first substrate 1. A first isolation portion STI1 is disposed in the first substrate 1 to define an active region. A floating diffusion region connection portion 19 is embedded in the first isolation portion STI1.

[0114] The first subchip CH1 further includes internal connection contacts 17a. At least one of the internal connection contacts 17a penetrates the embedded insulating pattern 12 of the first pixel isolation unit DTI1 in the peripheral region ER to connect a part of the first wiring 15 to the separated conductive pattern 16 of the first pixel isolation unit DTI1 and applies a negative bias voltage to the separated conductive pattern 16. At least another of the internal connection contacts 17a penetrates the embedded insulating pattern 12 of the second pixel isolation unit DTI2 under the rear conductive pad PAD to connect a part of the first wiring 15 to the separated conductive pattern 16 of the second pixel isolation unit DTI2. A first conductive pad CP1 is disposed in the first interlayer insulating film IL1 at the bottom layer. The first conductive pad CP1 includes copper.

[0115] The second sub-chip CH2 includes a second substrate SB2, a select gate SEL, a source follower gate SF, and a reset gate (not shown) disposed on a front surface 2a of the second substrate SB2, and a second interlayer insulating film IL2 covering them. A second element isolation part STI2 is disposed in the second substrate SB2 to define an active region, and an additional floating diffusion region (not shown) is disposed in the active region. A plurality of through holes are disposed in the second substrate SB2, and a through via 222 is disposed in each through hole. A second conductive pad CP2 is disposed on the through via 222 and exposed through the back surface 2b side of the second substrate SB2. The second conductive pad CP2 contacts the first conductive pad CP1 of the first sub-chip CH1. A through hole insulating film 111 is filled around the through via 222 and the second conductive pad CP2. The through hole insulating film 111 is conformally disposed on the front surface 2a of the second substrate SB2. A second wiring 217 including a via 221 connected to the source follower gate SF and a via 223 connected to an active region of the second substrate SB2 and a third conductive pad CP3 are disposed in the through-hole insulating film 111 and the second interlayer insulating film IL2. The source follower gate SF is connected to the floating diffusion region connector 19 of the first sub-chip CH1 through the through-hole via 222 and the second conductive pad CP2, the first conductive pad CP2, the first wiring 15, and the first contact plug 17. In one embodiment, a portion of the second wiring 217 corresponds to the source follower gate SF.

[0116] 9, a through via 222 is disposed in a through hole penetrating the second substrate SB2, and a second conductive pad CP2 is disposed on the through via 222. A through hole insulating film 111 is filled around the through via 222 and the second conductive pad CP2 to insulate the second substrate SB2 from the through via 222 and the second conductive pad CP2. A lower end of the through via 222 is connected to the second wiring 217. The through via 222 has a cross-sectional width that increases as it gets farther from the second conductive pad CP2, and the second conductive pad CP2 has a cross-sectional width that increases as it gets farther from the through via 222. The second conductive pad CP2 and the second wiring 217 contain copper, and the through via 222 contains tungsten.

[0117] 9, the third sub-chip CH3 includes a third substrate SB3, a peripheral transistor PTR disposed thereon, and a third interlayer insulating film IL3 covering them. A third element isolation part STI3 is disposed in the third substrate SB3 to define an active region. A third wiring 317 and a fourth conductive pad CP3 are disposed in the third interlayer insulating film IL3. The top layer of the third interlayer insulating film IL3 is in contact with the top layer of the second interlayer insulating film IL2. The third sub-chip CH3 includes a circuit for driving the first and / or second sub-chips (CH1, CH2) or storing an electrical signal generated in the first and / or second sub-chips (CH1, CH2).

[0118] 9, an anti-reflection structure AL is disposed on the rear surface 1b of the first substrate 1. The anti-reflection structure AL includes a first insulating film A1, a conductive film A2, a second insulating film A3, and a third insulating film A4, which are stacked in this order. The first insulating film A1, the second insulating film A3, and the third insulating film A4 each include a different material. In one embodiment, the first insulating film A1 includes aluminum oxide, the second insulating film A3 includes silicon oxide, and the third insulating film A4 includes hafnium oxide. The conductive film A2 is an electrically conductive film and includes titanium oxide.

[0119] In this specification, the first insulating film A1 is named the "first antireflective film", the conductive film A2 is named the "second antireflective film", the second insulating film A) is named the "third antireflective film", and the third insulating film A4 is named the "fourth antireflective film".

[0120] The first substrate 1 has a first refractive index n1, the first insulating film A1 has a second refractive index n2, the conductive film A2 has a third refractive index n3, and the second insulating film A3 has a fourth refractive index n4. The average value {(n2+n3) / 2} of the second refractive index n2 and the third refractive index n3 is smaller than the first refractive index n1 and larger than the fourth refractive index n4. The first refractive index n1 is 4.0 to 4.4. The second refractive index n2 is 2.0 to 3.0. The third refractive index n3 is 2.2 to 2.8. The fourth refractive index n4 is 1.0 to 1.9.

[0121] The first insulating film A1 has a first thickness T1, the conductive film A2 has a second thickness T2, the second insulating film A3 has a third thickness T3, and the third insulating film A4 has a fourth thickness T4. Here, the second thickness T2 is greater than each of the first thickness T1 and the fourth thickness T4, and is smaller than the third thickness T3. The first thickness T1 is 10 Å to 100 Å. The second thickness T2 is 100 Å to 600 Å. The third thickness T3 is 600 Å to 900 Å. The fourth thickness T4 is 20 Å to 200 Å.

[0122] Due to the relationship between the refractive indices and / or the relationship between the thicknesses, light incident on the microlenses ML can be refracted and passed through the multi-layer structure of the anti-reflection structure AL to efficiently enter the photoelectric conversion unit PD, thereby increasing the light receiving rate and providing an image sensor 503 with clear image quality.

[0123] In the image sensor 503 according to the present embodiment, the antireflection structure AL is made of titanium oxide (TiO 2 ), but titanium oxide (TiO 2 The conductive film A2 made of ZnO 2 , ZnO 3 , and ZnO 4 , reduces the reflectance of all color lights overall, and further reduces the reflectance of blue light in particular, thereby increasing the quantum efficiency (QE) of the blue pixel.

[0124] The first insulating film A1 also serves as a negative fixed charge film, which can reduce dark current and white spots.

[0125] In addition, a predetermined negative potential (voltage) can be applied to the conductive film A2 to accumulate holes (h+) near the back surface 1b of the first substrate 1. This can further improve the effect of reducing dark current and white spots.

[0126] A first optical black pattern 52p is disposed on the anti-reflection structure AL. The first optical black pattern 52p has a single layer or a multi-layer structure of at least one of a titanium layer, a titanium nitride layer, and a tungsten layer.

[0127] In the pixel array region APS, a light-shielding grid pattern 48a is disposed on the anti-reflection structure AL. A low-refractive grid pattern 50a is disposed on the light-shielding grid pattern 48a. The light-shielding grid pattern 48a and the low-refractive grid pattern 50a overlap the first pixel isolation unit DTI1 and have a grid shape in plan view. The light-shielding grid pattern 48a includes at least one of titanium and titanium nitride. The low-refractive grid patterns 50a all have the same thickness and include the same organic material. The low-refractive grid patterns 50a have a smaller refractive index than the color filters CF1 and CF2. For example, the low-refractive grid patterns 50a have a refractive index of about 1.3 or less. The light-shielding grid pattern 48a and the low-refractive grid pattern 50a prevent crosstalk between adjacent unit pixels UP.

[0128] A protective film 56 is conformally disposed on the first optical black pattern 52p, the light-shielding grid pattern 48a, and the low-refractive grid pattern 50a.

[0129] In the pixel array region APS, the color filters (CF1, CF2) are disposed between the low-refractive grid patterns 50a on the protective film 56. The color filters (CF1, CF2) each have one of blue, green, and red. As another example, the color filters (CF1, CF2) may include other colors such as cyan, magenta, and yellow. In the image sensor according to the present embodiment, the color filters (CF1, CF2) are arranged in a Bayer pattern. As another example, the color filters (CF1, CF2) are arranged in a 2×2 tetra pattern, a 3×3 nona pattern, or a 4×4 hexadeca pattern.

[0130] In the pixel array region APS, microlenses ML are disposed on the color filters (CF1, CF2). The edges of the microlenses ML are in contact with each other and connected. The microlenses ML form an array. The microlenses ML are also called a "microlens array."

[0131] The arrangement of the active region ACT, the transmission gate TG, the floating diffusion region FD, and the photoelectric conversion portion PD, as well as the first element isolation portion STI1 and the floating diffusion region connection portion 19, located in each unit pixel UP, is the same as that described above with reference to Figures 5, 6A, 6B, and 6C.

[0132] The floating diffusion region connection portion of the image sensor according to the embodiment of FIG. 9 may be formed by the method described with reference to FIGS. 7A-7D or the method described with reference to FIGS. 8A-8D.

[0133] As described above, by positioning the floating diffusion region connecting portion 19 within the element isolation portion STI, it is possible to reduce electrostatic coupling formed between the floating diffusion region connecting portion 19 and the wiring located within the interlayer insulating film, thereby increasing the degree of freedom in wiring layout.

[0134] Although the embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the technical spirit of the present invention. [Explanation of symbols]

[0135] 1 First board 12 Buried insulation pattern 14 Isolation insulating film 15, 217, 317 1st to 3rd wiring 16 Separate Conductive Pattern 17 First contact plug 17a Internal connection contact 19 Floating diffusion region connection 19L Spare floating diffusion area connection layer 19P Spare floating diffusion region connection 1a Front side of first board (first surface) 1b Back side of the first board (second side) 22 Trench 2a Front side of second board 2b Back side of second board 46, 60 1st and 2nd rear trenches 48a Shading grid pattern 50a low refraction grid pattern 50b, 50c First and second low-refractive protection patterns 50r Low Refraction Residual Pattern 52a, 52c First and second conductive patterns 52b Rear connection wiring 52p 1st Optical Black Pattern 54a, 54b First and second metal patterns 56 Protective film 111 Through hole insulating film 191 Executives 192, 193 1st and 2nd branches 221, 223 Via 222 Through Via 500, 503 image sensor 1001 Active Pixel Sensor Array 1002 Line Decoder 1003 Line Driver 1004 Column Decoder 1005 Timing Generator 1006 Correlated Double Sampler (CDS) 1007 Analog-to-Digital Converter (ADC) 1008 Input / Output (I / O) Buffer A1 First insulating film (first anti-reflection film) A2 Conductive film (second anti-reflection film) A3 Second insulating film (third anti-reflection film) A4 3rd insulating film (4th anti-reflection film) ACT active region ACT1, ACT2 1st, 2nd active region AL anti-reflection structure APS pixel array area BCA Rear Contact BR1 Contact Area BR2 Via Area BVS(81), BVS(2) 1st and 2nd backside vias CA contact port CF1, CF2 color filters CFB 2nd Optical Black Pattern CFR Capping Pattern CH1, CH2, CH3 1st to 3rd sub chips CI cover insulating film CP1, CP2, CP3, CP4 1st to 4th conductive pads DTI pixel separation section DTI1 1st pixel separation section DTI2 Second pixel separation section (substrate separation section) DX Source Follower Transistor ER Periphery FD Floating diffusion area FD1, FD2 First and second floating diffusion group GI Gate Insulator Gox Gate Oxide GR Groove H1, H2 1st and 2nd halls IL1, IL2, IL3 1st to 3rd interlayer insulating films ML Microlens (Microlens Array) OB Optical Black Area PAD Back conductive pad PD Photoelectric conversion unit PD' Black photoelectric conversion unit PD“ dummy area PR Pad Area PRP photosensitive pattern PTR peripheral transistor RG Reset Gate RX Reset Transistor SB2, SB3 2nd and 3rd boards SEL Select Gate SF Source Follower Gate STI element isolation section STI1, STI2, STI3 1st to 3rd element isolation sections SX selection transistor TG Transmission Gate TX Transistor UP (sub) unit pixel UP1, UP2 1st and 2nd sub-unit pixels UP(1), UP(2) 1st and 2nd unit pixels V DD Power supply voltage V OUT Output Line

Claims

1. a first substrate having a first surface and a second surface opposite to the first surface, the first substrate including a pixel array region having a plurality of active regions on the first surface; an element isolation portion disposed in the first substrate on the first surface side and isolating each of the plurality of active regions on the first surface; a plurality of floating diffusion regions located within the plurality of active regions of the first substrate; a floating diffusion region connector at least a portion of which is embedded in the element isolation region and connects at least two of the plurality of floating diffusion regions.

2. a source follower transistor including a source follower gate electrode located over the first surface of the first substrate; The image sensor of claim 1 , wherein the source follower gate electrode is connected to the floating diffusion region connection portion.

3. The floating diffusion region connection portion is A stem extending in a first direction; a first branch portion extending in a second direction from the trunk portion and connected to the source follower gate electrode; 3. The image sensor of claim 2, further comprising: a second branch portion extending from the trunk in the second direction and connected to a corresponding one of the plurality of floating diffusion regions.

4. the plurality of floating diffusion regions includes a first group of floating diffusion regions and a second group of floating diffusion regions; the first floating diffusion region group is spaced apart from the second floating diffusion region group in the second direction; a part of the element isolation portion is disposed between the first floating diffusion region group and the second floating diffusion region group; 4. The image sensor of claim 3, wherein the stem is disposed in a space between the first and second floating diffusion region groups when viewed from above.

5. The image sensor of claim 2 , wherein one of the floating diffusion region connectors connects eight of the floating diffusion regions to each other.

6. Further including a plurality of transistors in the unit pixel, the plurality of transistors includes a plurality of transfer transistors, a source follower transistor, a reset transistor, and a select transistor; The unit pixel includes a plurality of photoelectric conversion units, and a plurality of first active regions and a plurality of second active regions in the plurality of active regions; At least one of the source follower transistor, the reset transistor, and the selection transistor is located in the first active region; the second active region has the plurality of transfer transistors located therein; 2. The image sensor of claim 1, wherein each of the plurality of transfer transistors selectively couples a corresponding one of the plurality of photoelectric conversion units to a corresponding one of the plurality of floating diffusion regions.

7. 7. The image sensor of claim 6, wherein a source follower gate electrode of the source follower transistor is positioned across two adjacent first active regions among the plurality of first active regions.

8. The image sensor of claim 6 , wherein each of the plurality of floating diffusion regions is located in a corresponding one of the plurality of second active regions.

9. 2. The image sensor of claim 1, wherein the floating diffusion region connection portion comprises polysilicon or silicon germanium doped with N-type impurities.

10. The image sensor of claim 1 , wherein the floating diffusion region connection portion comprises a metal.

11. a cover insulating film formed on an upper surface of the floating diffusion region connection portion; a contact hole penetrating the cover insulating film and exposing an upper surface of the floating diffusion region connection portion, the source follower gate electrode fills the contact hole and contacts an upper surface of the floating diffusion region connection portion; the element isolation portion has a groove on an upper surface of the element isolation portion, the cover insulating film and the floating diffusion region connection portion fill the groove; the floating diffusion region connection portion fills a lower portion of the groove; The image sensor of claim 2 , wherein the cover insulating film fills an upper portion of the groove.

12. 3. The image sensor of claim 2, further comprising a second substrate disposed on the first surface of the first substrate, and a peripheral transistor disposed on the second substrate.

13. 13. The image sensor of claim 12, further comprising a plurality of wirings and a plurality of interlayer insulating films disposed between the first substrate and the second substrate.

14. a second substrate and a third substrate positioned on a first surface of the first substrate; a first wiring and a first interlayer insulating layer located between the first substrate and the second substrate; a second wiring and a second interlayer insulating layer located between the second substrate and the third substrate; 2. The image sensor of claim 1, further comprising a third wiring and a third interlayer insulating layer disposed on the third substrate.

15. the second substrate, the first wiring, and the second wiring form at least one of a source follower transistor, a selection transistor, and a reset transistor; The image sensor of claim 14 , wherein the third substrate and the third wiring form a peripheral transistor.

16. a portion of the second wiring corresponds to a source follower gate electrode of the source follower transistor; 16. The image sensor of claim 15, wherein the source follower gate electrode is connected to the floating diffusion region connector through a through via that penetrates the second substrate.

17. a first substrate having a first surface and a second surface opposite to the first surface, the first substrate including a pixel array region including a plurality of sub-unit pixels and a peripheral region; an anti-reflection structure disposed on the second surface; a pixel separating portion disposed on the first substrate and separating the plurality of sub-unit pixels from each other; a color filter disposed on the anti-reflection structure; a first interlayer insulating film disposed on a first surface of the first substrate; a first wiring disposed in the first interlayer insulating film; a second interlayer insulating film disposed under the first interlayer insulating film; a second wiring disposed in the second interlayer insulating film; a second substrate disposed under the second interlayer insulating film; The first substrate is an isolation portion located in the first substrate and extending from the first surface toward the second surface to isolate each of the active regions of the first surface; a plurality of floating diffusion regions formed within the plurality of active regions of the first substrate; a floating diffusion region connection portion embedded in the element isolation portion and connecting at least two of the plurality of floating diffusion regions; a cover insulating film formed on an upper surface of the floating diffusion region connection part and having a contact hole exposing an upper surface of the floating diffusion region connection part, a portion of the first wiring corresponds to a source follower gate electrode of a source follower transistor; The image sensor according to claim 1, wherein the source follower gate electrode is connected to the floating diffusion region connection portion through the contact hole.

18. The floating diffusion region connection portion is With the executives, a first branch portion extending from the trunk portion and connected to the source follower gate electrode; 20. The image sensor of claim 17, further comprising: a second branch portion extending from the stem and coupled to a corresponding one of the plurality of floating diffusion regions.

19. a first substrate having a first surface and a second surface opposite to the first surface, the first substrate including a plurality of pixel array regions including a plurality of sub-unit pixels and a peripheral region; an anti-reflection structure disposed on the second surface; a pixel separating portion disposed on the first substrate and separating the plurality of sub-unit pixels from each other; a color filter disposed on the anti-reflection structure; a first interlayer insulating film disposed on a first surface of the first substrate; a first wiring disposed in the first interlayer insulating film; A second substrate disposed under the first interlayer insulating film; a second interlayer insulating film disposed under the second substrate; a second wiring disposed in the second interlayer insulating film; a third interlayer insulating film disposed under the second interlayer insulating film; a third wiring disposed in the third interlayer insulating film; a third substrate disposed under the third interlayer insulating film; The first substrate is an isolation portion located in the first substrate and extending from the first surface toward the second surface to isolate each of the active regions of the first surface; a plurality of floating diffusion regions formed within the plurality of active regions of the first substrate; a floating diffusion region connection portion embedded in the element isolation portion and connecting at least two of the plurality of floating diffusion regions, a portion of the second wiring corresponds to a source follower gate electrode of a source follower transistor; The image sensor according to claim 1, wherein the source follower gate electrode is connected to the floating diffusion region connector through a through via that penetrates the second substrate.

20. the second substrate, the first wiring, and the second wiring form the source follower transistor and the selection transistor; 20. The image sensor of claim 19, wherein the third substrate and the third wiring form a peripheral transistor.

Images