Semiconductor device

Abstract

To provide a semiconductor device that has a small occupied area and a high integration degree.SOLUTION: A first conductive layer is formed. A first insulating layer is formed on the first conductive layer. A second conductive layer is formed on the first insulating layer by using the same material as the first conductive layer. A third conductive layer is formed on the second conductive layer. A second insulating layer is formed on the third conductive layer. A resist mask is formed on the second insulating layer. Etching is sequentially performed from a top layer. Formation of an opening on the first conductive layer, and enlargement of a diameter of an opening on the second conductive layer are performed at the same step. By etching the first insulating layer, a contact hole for exposing an upper surface of the first conductive layer is formed.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to a method for manufacturing a semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one aspect relates to an article, a method, or a manufacturing method. One aspect of the present invention is a process, machine, manufacture, or composition. Therefore, the present invention more specifically disclosed herein The technical field of one embodiment of the present invention is a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, device, power storage device, storage device, imaging device, driving method thereof, or manufacturing method thereof One example can be mentioned.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one embodiment of a semiconductor device. A display device, an imaging device, or an electronic device may include a semiconductor device. [Background technology]

[0004] A technology to construct transistors using semiconductor thin films formed on substrates with insulating surfaces The transistor is being used in integrated circuits (ICs) and image display devices (simply called display devices). Semiconductors that can be used in transistors are widely used in electronic devices such as Silicon-based semiconductor materials are widely known as conductive thin films, but other materials include oxides. Semiconductors are attracting attention.

[0005] A transistor including an oxide semiconductor has an extremely small leakage current in a non-conducting state. For example, Patent Document 1 discloses a low-ripple transistor using an oxide semiconductor. Low power consumption CPUs that utilize peak current characteristics have been disclosed. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2012-257187 A Summary of the Invention [Problem to be solved by the invention]

[0007] An object of one embodiment of the present invention is to provide a semiconductor device that occupies a small area. Another object is to provide a semiconductor device with a high degree of integration. Another object of the present invention is to provide a semiconductor device with high speed. One of the objects of the present invention is to provide a semiconductor device having high productivity. Another object of the present invention is to provide a semiconductor device with a high yield. Another object is to provide a novel semiconductor device. It is an object of the present invention to provide a method for fabricating a semiconductor device.

[0008] The description of these problems does not preclude the existence of other problems. It is not necessary for the embodiment to solve all of these problems. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0009] One embodiment of the present invention relates to a method for manufacturing a contact plug electrically connected to a transistor. Regarding.

[0010] One embodiment of the present invention provides a method for manufacturing a semiconductor device comprising the steps of: providing an opening in a stacked body having a first conductive layer and a first insulating layer; A method for manufacturing a semiconductor device in which a contact plug is provided in the opening, comprising: A second conductive layer is provided on the substrate using the same material as the first conductive layer, and a third conductive layer is provided on the second conductive layer. a second insulating layer is provided on the third conductive layer, and a resist mask is provided on the second insulating layer. The second insulating layer is selectively etched using the resist mask as a mask. An opening is provided, and selective etching is performed using the second insulating layer as a mask to form a third insulating layer. An opening is provided in the conductive layer, and the resist mask is removed to form a third conductive layer. By selectively etching the second conductive layer, an opening is provided in the second conductive layer, and a third conductive layer is formed. The first insulating layer and the second conductive layer are selectively etched using the first insulating layer and the second conductive layer as a mask. An opening is provided in the third conductive layer, and the diameter of the opening is enlarged to contact one of the second conductive layers. A portion of the insulating layer is exposed, and selective etching is performed using the first insulating layer and the third conductive layer as a mask. By this, an opening is provided in the first conductive layer and the diameter of the opening in the second conductive layer is enlarged. and selectively etching the third conductive layer and the second conductive layer as a mask. The diameter of the opening of the first insulating layer is enlarged by the above process, and the first conductive layer, filling an opening penetrating the first insulating layer, the second conductive layer and the third conductive layer with a conductive material; The first conductive layer has one surface electrically connected to the side surface of the first conductive layer at the opening. The method for manufacturing a semiconductor device is characterized in that a contact plug is provided.

[0011] Another embodiment of the present invention is a semiconductor device having an oxide semiconductor layer, a first conductive layer, and a first insulating layer. A method for manufacturing a semiconductor device, comprising the steps of: forming a second conductive layer on a first insulating layer using the same material as a first conductive layer; a conductive layer of the second insulating layer, a third conductive layer on the second conductive layer, and a second insulating layer on the third conductive layer. A resist mask is provided on the second insulating layer, and selectively An opening is provided in the second insulating layer by etching the second insulating layer using the second insulating layer as a mask. By selectively etching the third conductive layer, an opening is formed in the third conductive layer and the By eliminating the resist mask and selectively etching using the third conductive layer as a mask, An opening is provided in the second conductive layer, and the third conductive layer and the second conductive layer are used as a mask to select the By selectively etching the first insulating layer, an opening is provided and a third conductive layer is formed. The opening in the second conductive layer is enlarged to expose a portion of the second conductive layer, and the first insulating layer and the third conductive layer are then bonded to each other. By selectively etching the first conductive layer using the second conductive layer as a mask, an opening is formed in the first conductive layer. The diameter of the opening of the second conductive layer is enlarged, and the third conductive layer, the second conductive layer, and The oxide semiconductor layer is then selectively etched using the first conductive layer as a mask. and enlarging the diameter of the opening in the first insulating layer. , through the oxide semiconductor layer, the first conductive layer, the first insulating layer, the second conductive layer and the third conductive layer. A conductive material is filled into the opening through which the first conductive layer passes, and one surface of the first conductive layer and the opening of the first conductive layer are a contact plug electrically connected to a side surface of the semiconductor device A method for making a body device.

[0012] The first conductive layer and the second conductive layer are preferably formed using tungsten.

[0013] The third conductive layer is preferably formed using titanium or titanium nitride.

[0014] The oxide semiconductor layer is made of In, Zn, and M (M is Al, Ti, Sn, Ga, Y, Zr , La, Ce, Nd or Hf).

[0015] The contact plug penetrates the oxide semiconductor layer of the second transistor. It can also be written as: Effect of the Invention

[0016] According to one embodiment of the present invention, a semiconductor device that occupies a small area can be provided. It is possible to provide a semiconductor device with a high degree of integration. Alternatively, a semiconductor device with low power consumption can be provided. Alternatively, a semiconductor device with high productivity can be provided. Alternatively, a novel semiconductor device can be provided. Alternatively, a method for manufacturing the above semiconductor device can be provided.

[0017] Note that the effects of one embodiment of the present invention are not limited to these. In some cases or depending on the situation, the above effects may be different. Alternatively, for example, one aspect of the present invention may be, in some cases, or depending on the situation, In some cases, these effects may not be present. [Brief description of the drawings]

[0018] [Figure 1] 1A and 1B are a cross-sectional view and a circuit diagram illustrating a semiconductor device. [Diagram 2] FIG. [Diagram 3] 1A to 1C are cross-sectional views illustrating a method for manufacturing a contact plug. [Figure 4] 1A to 1C are cross-sectional views illustrating a method for manufacturing a contact plug. [Diagram 5] 1A to 1C are cross-sectional views illustrating a method for manufacturing a contact plug. [Figure 6] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 7] FIG. [Figure 8] 1A to 1C are cross-sectional views illustrating a method for manufacturing a contact plug. [Figure 9] 1A to 1C are cross-sectional views illustrating a method for manufacturing a contact plug. [Figure 10] 1A to 1C are cross-sectional views illustrating a method for manufacturing a contact plug. [Figure 11] FIG. 1 is a top view illustrating a semiconductor device. [Figure 12] 1A and 1B are a cross-sectional view and a circuit diagram illustrating a semiconductor device. [Figure 13] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 14] FIG. 1 is a top view illustrating a semiconductor device. [Figure 15] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 16] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 17] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 18] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 19] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 20] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 21] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel width direction. [Figure 22]1A and 1B are diagrams illustrating a cross section of a transistor in a channel length direction. [Figure 23] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel width direction. [Figure 24] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor layer. [Diagram 25] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor layer. [Figure 26] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 27] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 28] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 29] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Diagram 30] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Diagram 31] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Diagram 32] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel width direction. [Diagram 33] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel length direction. [Diagram 34] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel width direction. [Diagram 35] FIG. 1 is a top view illustrating a transistor. [Diagram 36] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 37] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 38] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 39] 1A to 1C illustrate a method for manufacturing a transistor. [Diagram 40] 1A to 1C illustrate a method for manufacturing a transistor. [Diagram 41] 1A to 1C illustrate a method for manufacturing a transistor. [Diagram 42] FIG. 2 is a diagram for explaining an example of the configuration of a CPU. [Diagram 43] FIG. [Diagram 44]1A to 1C are diagrams illustrating electronic devices. [Diagram 45] FIG. 2 is a diagram illustrating an etching apparatus. [Diagram 46] A cross-sectional SEM photograph of an opening for forming a contact plug. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various ways in form and detail without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be modified in various ways. The present invention is not limited to the above-mentioned embodiments. In the drawings, the same reference numerals are used to designate the same parts or parts having similar functions. In addition, the same elements constituting the figures are used in the same way, and their repeated explanations may be omitted. In some cases, the patterns may be omitted or changed as appropriate between different drawings.

[0020] For example, in the present specification, when it is explicitly stated that X and Y are connected, In this case, X and Y are electrically connected, and X and Y are functionally connected. The case where X and Y are directly connected is also considered to be disclosed in the present specification. Therefore, the present invention is not limited to a specific connection relationship, for example, a connection relationship shown in a drawing or a sentence. Any connections other than those shown in the drawings or text shall be deemed to be included in the drawings or text. do.

[0021] Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). , etc.).

[0022] An example of a direct connection between X and Y is a circuit that allows electrical connection between X and Y. The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, When a resistor (such as an electrode, display element, light-emitting element, or load) is not connected between X and Y, The elements that allow electrical connection between X and Y (e.g., switches, transistors, capacitors, etc.) elements, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc.) , X and Y are connected.

[0023] An example of a case where X and Y are electrically connected is The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more elements (such as an electrode, a display element, a light-emitting element, or a load) can be connected between X and Y. It is possible. The switch has a function that allows it to be turned on and off. A switch can be in a conductive state (on state) or a non-conductive state (off state) and can either pass current or not. The switch has the function of controlling whether or not current flows. When X and Y are electrically connected, This includes the case where Y is directly connected.

[0024] An example of a case where X and Y are functionally connected is a case where a functional connection between X and Y is possible. Circuits that perform the above functions (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits ( power supply circuits (voltage boost circuits, voltage drop circuits, etc.), level shifter circuits that change the potential level of signals, etc.) , voltage sources, current sources, switching circuits, amplifier circuits (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more devices (such as a memory circuit, a control circuit, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X If X is transmitted to Y, then X and Y are considered to be functionally connected. When X and Y are functionally connected, there are cases where X and Y are directly connected and cases where X and Y are functionally connected. and the case where they are electrically connected to each other.

[0025] In addition, if it is explicitly stated that X and Y are electrically connected, are electrically connected (i.e., there is another element or circuit between X and Y) When X and Y are functionally connected (i.e., when X and Y are connected), (When there is a functional connection between X and Y via another circuit in between) and when X and Y are directly connected (i.e., when X and Y are connected without any other element or circuit between them) is deemed to be disclosed in the present specification. If it is explicitly stated that it is connected, The same contents are deemed to be disclosed in the present specification and the like.

[0026] For example, the source (or the first terminal, etc.) of the transistor is connected via Z1 (or The drain (or second terminal, etc.) of the transistor is electrically connected to Z 2 (or not), it may be electrically connected to Y, or the source of the transistor (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. The drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2. and another part of Z2 is directly connected to Y, It is possible to do so.

[0027] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor The terminals of the transistor (or the first terminal, etc.) are electrically connected to each other, and X, the source of the transistor (or the first terminal, etc.) 1 terminal, etc.), the drain (or second terminal, etc.) of the transistor, and Y. "The source (or the third) of the transistor is connected to the The drain (or second terminal, etc.) of the transistor is electrically connected to X. The transistor source (or first terminal, etc.) is electrically connected to Y, and the transistor source (or first terminal, etc.) is electrically connected to X. The drain (or second terminal, etc.) of the transistor, Y, is electrically connected in this order. " Alternatively, "X is the source (or first terminal, etc.) of a transistor. The transistor is electrically connected to Y via a drain (or a second terminal, etc.) and a transistor is electrically connected to X via a drain (or a second terminal, etc.). The source (or first terminal, etc.) of a resistor, the drain (or second terminal, etc.) of a transistor ), Y is provided in this connection order. By using a simple expression method and specifying the order of connections in the circuit configuration, Distinguish between the source (or first terminal, etc.) and the drain (or second terminal, etc.) of a transistor. The technical scope can be determined based on the above.

[0028] Or, as another way of expressing it, for example, "the source (or first terminal, etc.) of a transistor is electrically connected to X through at least a first connection path, and the first connection path is , the second connection path does not have a second connection path, and the second connection path is a transistor The source (or first terminal, etc.) of the transistor and the drain (or second terminal, etc.) of the transistor The first connection path is a path via Z1, and the second connection path is a path between the transistor The drain (or second terminal, etc.) of the capacitor is electrically connected to Y through at least a third connection path. The third connection path does not include the second connection path, and the third connection path The connection path is the path through Z2. The source (or the first terminal, etc.) of the resistor is connected to the resistor via Z1 by at least the first connection path. and X is electrically connected to the first connection path, and the first connection path does not have a second connection path; The second connection path includes a connection path through a transistor, and the second connection path includes a drain of the transistor. (or the second terminal, etc.) is connected to Y via Z2 by at least a third connection path. The third connection path does not have the second connection path. Alternatively, the source (or the first terminal, etc.) of the transistor may be at least The first electrical path is electrically connected to X through Z1, and the first electrical path is The primary path does not have a second electrical path, and the second electrical path is a From the source (or first terminal, etc.) to the drain (or second terminal, etc.) of the transistor The drain (or second terminal, etc.) of the transistor is connected to at least a third The third connection path is electrically connected to Y through Z2 by an electrical path of The fourth electrical path does not include a fourth connection path, and the fourth electrical path is connected to the drain (or 2 terminal) to the source (or first terminal, etc.) of the transistor. Using the same expression as these examples, the circuit configuration By defining the connection path, the source (or first terminal, etc.) of the transistor and , and the drain (or second terminal, etc.) can be distinguished to determine the technical scope. .

[0029] Note that these expression methods are merely examples, and the present invention is not limited to these expression methods. , Y, Z1, and Z2 are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layer, etc.).

[0030] In addition, the circuit diagram shows independent components as if they are electrically connected to each other. Even if the components are the same, one component may have the functions of multiple components. For example, when a part of the wiring also functions as an electrode, one conductive film has the function of the wiring and The electrode functions as both components. The term "electrochemically connected" refers to a case where one conductive film has the functions of multiple components. This also falls within the scope of the above.

[0031] The words "membrane" and "layer" may be interchangeable depending on the situation. For example, the term "conductive layer" can be used interchangeably with the term "conductive film." ". Alternatively, for example, the term "insulating film" may be used. It may be possible to change the term to "insulating layer."

[0032] (Embodiment 1) In this embodiment, a semiconductor device which is one embodiment of the present invention will be described with reference to drawings. .

[0033] FIG. 1A is a cross-sectional view illustrating a structure of a semiconductor device of one embodiment of the present invention. The semiconductor device is a transistor 51 having an active region on a silicon substrate 40, and an oxide semiconductor The transistor 51 is a p-ch type, and the transistor 52 has a semiconductor layer as an active layer. By making the resistor 52 an n-channel type, a CMOS circuit can be formed. The transistors 51 and 52 shown in FIG. 1B form an inverter circuit 90. ).

[0034] Note that the transistor 51 constitutes an inverter circuit 90. This is not a limitation. In some cases or situations, a different circuit may be configured. In addition, elements other than the transistor 51 may be formed on the silicon substrate 40. For example, A capacitance element, a diode, a photodiode, a resistance element, etc. are formed on a silicon substrate 40. When forming a photodiode, it is preferable to form a back-illuminated image sensor. That is, light may be irradiated from the back side of the silicon substrate 40. When configuring an image sensor, the silicon substrate 40 is provided with a photodiode and However, one embodiment of the present invention is not limited thereto. The transistor connected to the photodiode is not formed on the silicon substrate 40. For example, the transistor connected to the photodiode may be the transistor 52. It may be formed above the silicon substrate 40 as shown in FIG.

[0035] The transistor 51 includes an active region in which a channel is formed, a source region, a drain region, a gate The basic structure of the transistor 52 is an insulating film and a gate electrode. The basic structure of the device is an active layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode. As shown in FIG. 1A, each of a transistor 51 and a transistor 52 is By overlapping a portion of the above-mentioned components, the area occupied by the circuit can be reduced.

[0036] In the inverter circuit 90, an n-ch type semiconductor device having an active region in the silicon substrate 40 is used. This eliminates the need for the transistor process, and the process of forming p-wells and n-type impurity regions, etc. This can eliminate the need for additional steps, thereby significantly reducing the number of steps.

[0037] On the transistor 51, an insulating layer 81, an insulating layer 82, an insulating layer 83, an insulating layer 84 and an insulating layer 85 will be established.

[0038] In addition, the transistor 52 is provided on the insulating layer 85, and the insulating layer 8 6, insulating layer 87 and insulating layer 88 are provided.

[0039] Note that the insulating layers provided over the transistors 51 and 52 are the same as those in the above embodiment. In some cases, some of the insulating layers may be omitted, or other insulating layers may be added.

[0040] Either the source or drain region of the transistor 51 is a contact that penetrates the insulating layer 82. The contact plug 61a is electrically connected to the insulating layer 83. The contact plug 61b is electrically connected to the contact plug 61b that penetrates the insulating layer 87. The wire 61 b ​​is electrically connected to the wire 71 on the insulating layer 87 .

[0041] The gate electrode of the transistor 51 is electrically connected to a contact plug 62 a that penetrates the insulating layer 82. The contact plug 62a penetrates the insulating layers 83 to 87. The contact plug 62b is electrically connected to the insulating layer 87. 73 is electrically connected to the wiring 73.

[0042] The other of the source region or the drain region of the transistor 51 is a contact that penetrates the insulating layer 82. The contact plug 63a is electrically connected to the transistor. The insulating layer 83 through the insulating layer 87 are formed on the source electrode or the drain electrode of the capacitor 52. The source of the transistor 51 is electrically connected to the contact plug 63b. The other of the region or drain region and the source electrode or drain electrode of the transistor 52 The other is electrically connected via a contact plug 63a and a contact plug 63b. It will be done.

[0043] The gate electrode of the transistor 52 is formed by a contact plate that penetrates the insulating layer 86 and the insulating layer 87. The contact plug 64 is electrically connected to the wiring 73 on the insulating layer 87. That is, the gate electrode of the transistor 51 and the gate electrode of the transistor 52 are electrically connected to each other. The contact electrodes include the contact plug 62a, the contact plug 62b, the wiring 73, and the contact Electrical connection is made via the tact plug 64 .

[0044] The contact plugs 62a, 62b, and 64 are located at positions in the depth direction that are different from other contacts. Since it differs from the tact plug, it is shown with a dashed line.

[0045] The other of the source electrode and the drain electrode of the transistor 52 is connected to the insulating layer 86 and the insulating The contact plug 65 is electrically connected to the edge layer 87. 65 is electrically connected to the wiring 72 on the insulating layer 87 .

[0046] In the semiconductor device according to one embodiment of the present invention, the source electrode or the drain electrode of the second transistor 52 A characteristic feature is the shape of the contact plug 63b that penetrates one of the drain electrodes.

[0047] In the cross-sectional view shown in FIG. 1A, the contact plug 63b is formed by the insulating layer 86 and the insulating layer The diameter is relatively large in the region penetrating 87, and the source electrode of the second transistor 52 or The diameter of the drain electrode is relatively small in the region where the drain electrode penetrates. By forming the contact plug 63b in such a cross-sectional shape, the second transistor 52 The contact area with either the source electrode or the drain electrode can be increased, and the contact resistance can be reduced. can be made smaller.

[0048] FIG. 2A shows a source electrode or a drain electrode of the second transistor 52 shown in FIG. 1 shows an enlarged view of the vicinity of a region where one of the electrodes contacts a contact plug 63b. The etching conditions are not limited to those shown in FIG. 2(B) to FIG. 2(F). By adjusting the voltage at either the source electrode or the drain electrode of the second transistor 52, The shape of the region where the contact plug 63b contacts the semiconductor substrate 62 and the surrounding area can be changed in various ways. This can be done.

[0049] The inner wall of the contact hole in which the contact plug is formed has a slight taper angle. Therefore, the diameter of the contact plug changes at any point in the depth direction. On the other hand, in one embodiment of the present invention, the contact The plug is characterized by having an area of ​​significant diameter change.

[0050] 3(A) to 5(C) show process diagrams for forming the contact plug 63b. A description of the region below the insulating layer 85 will be omitted.

[0051] The contact plug 63b is connected to the source electrode or the drain electrode of the second transistor 52. A contact hole is formed in the lamination of one or more insulating layers, and It is formed by filling it with a conductor such as a metal.

[0052] The stack includes an insulating layer 85, a source electrode or a drain electrode of the second transistor 52, and a On the other hand, the insulating layer 86 and the insulating layer 87 are stacked in this order from the bottom. It has the following configuration.

[0053] First, the metal layer 32, the metal layer 33, the insulating layer 34, and the organic film 35 are formed on the insulating layer 87 in this order. Then, a resist mask 36 having a desired shape is formed (FIG. 3(A)). The organic film 35 is used to improve the adhesion of the resist mask 36. The resist mask 36 may be formed to a thickness of, for example, 100 nm. It would be sufficient to set it to about m.

[0054] In the following description, all etching steps are performed using a dry etching method. In addition, the etching conditions are appropriately changed to the conditions appropriate for the layer to be etched. shall be replaced.

[0055] The electrode layer 31 is made of, for example, Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, The electrode layer 31 may be formed of a material such as Sc. The thickness of the electrode layer 31 is preferably 10 nm to 40 nm. Preferably, the thickness is 15 nm to 30 nm. Typically, the thickness of the tongue is 20 nm. The insulating film may be a stainless steel film.

[0056] The metal layer 32 can be formed of the same material as the electrode layer 31. The thickness is preferably 0 nm to 50 nm, and more preferably 20 nm to 40 nm. The tungsten film may be 30 nm thick.

[0057] The metal layer 33 is formed by etching the electrode layer 31 under the etching conditions for etching the electrode layer 31. For example, the electrode layer 3 can be formed using a material having a smaller etching rate than that of the electrode layer 3. When a tungsten film is used for the first electrode, a titanium film or a titanium nitride film can be used. The thickness of the metal layer 33 is preferably 20 nm to 100 nm, and more preferably 40 nm to 80 nm. Typically, a titanium film having a thickness of 60 nm can be used.

[0058] The insulating layer 34 is formed under the etching conditions for etching the metal layers 33 and 32. The metal layer 33 and the metal layer 32 are formed using a material having a smaller etching rate than the metal layer 32. For example, a titanium film is used for the metal layer 33 and a tungsten film is used for the metal layer 32. In this case, a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a silicon nitride oxide film is used. The thickness of the insulating layer 34 is preferably 20 nm to 150 nm. More preferably, the thickness is 50 nm to 120 nm. Typically, a silicon nitride film having a thickness of 100 nm is A polysilicon film can be used.

[0059] The metal layer 32, the metal layer 33 and the insulating layer 34 are hard to form an opening of a fine shape. Resist masks made of organic materials can be used as etch masks. Since the shape of the opening changes during the etching process, resist masking is required to form an opening with a high aspect ratio. It is not suitable to use the mask alone as a mask.

[0060] Next, an etching process is performed using the resist mask 36 as a mask, and the organic film 35 and the insulating film 36 are An opening is provided in the layer 34 (see FIG. 3(B)). Here, by setting the film thickness of each layer within the above range, As a result, openings having the same diameter as the openings in the resist mask 36 are formed in the organic film 35 and the insulating layer 34. It can be established.

[0061] Next, an etching process is performed using the resist mask 36, the organic film 35, and the insulating layer 34 as a mask. Then, an opening is formed in the metal layer 33 (see FIG. 3(C)). Although the resist mask 36 is removed and a part of the organic film 35 remains, Alternatively, the organic film 35 may be removed. It is also possible.

[0062] Next, an etching process is performed using the organic film 35 and the insulating layer 34 as a mask, and the metal layer 32 An opening is provided (see FIG. 4(A)). At this time, the organic film 35 and the insulating layer 34 disappear. Good too.

[0063] Next, an etching process is performed using the metal layers 33 and 32 as a mask, and the insulating layers 87 and An opening is provided in the insulating layer 86 (see FIG. 4(B)). The etching is continued so that the diameter of the opening increases, and a part of the metal layer 32 is exposed. .

[0064] Next, an etching process is performed using the metal layer 33 and the metal layer 32 as a mask, and the electrode layer 31 is An opening is provided (see FIG. 4(C)). In this etching process, the electrode layer 31 and the metal layer If 32 is made of the same metal material, etching will proceed on both. Thus, the opening is provided in the electrode layer 31, and at the same time, the metal layer 32 shown in FIG. The exposed area is etched to expose a portion of the top surface of insulating layer 87.

[0065] Next, an etching step is performed using the metal layer 33, the metal layer 32 and the electrode layer 31 as a mask. The diameters of the openings in the insulating layer 87 and the insulating layer 86 are enlarged, and an opening is provided in the insulating layer 85 ( See Figure 5(A).

[0066] Next, chemical vapor deposition (CVD) is applied to the openings formed through the layers in the above steps. A conductor 63B such as a metal is filled in by a vapor deposition method or the like (FIG. 5( See B).

[0067] Then, the unnecessary area of ​​the conductor 63B formed on the insulating layer 87, the metal layer 33 and the metal layer 32 by CMP (Chemical Mechanical Polishing) method, etc. Then, the contact plug 63b is formed.

[0068] Note that the transistor 52 used in the semiconductor device of one embodiment of the present invention has a source layer over an oxide semiconductor layer. A source electrode and a drain electrode are formed, and the source electrode and the drain electrode are covered with an insulating layer. In such a configuration, the oxide contained in the insulating layer 85 may not be in contact with the insulating layer 85. The element is not taken over by the metal layer that constitutes the source electrode and the drain electrode. In this case, the oxygen can be efficiently supplied to the oxide semiconductor layer, and the electrical characteristics of the transistor 52 can be improved. This can improve the performance and reliability.

[0069] In the above structure, the semiconductor device of one embodiment of the present invention is as shown in FIG. 6. The second transistor 52 shown in FIG. 6 is connected to either the source electrode or the drain electrode of the second transistor 52 shown in FIG. 1 is an enlarged view of the vicinity of the region where the base plug 63b comes into contact. 7(B) to 7(F).

[0070] 8A to 10C are diagrams showing steps for forming the contact plug 63b. The stacked structure shown in FIG. 8(A) to FIG. 10(C) is the same as that shown in FIG. 3(A) to FIG. The only difference is that an oxide semiconductor layer 30 is added to the stacked structure. In this case, an opening may be provided by performing an etching process using the electrode layer 31 as a mask. (See FIG. 10(A)). The other steps are the same as those in FIG. 3(A) to FIG. 5(C). Please refer to the explanation of the process.

[0071] 11A and 11B are top views of a semiconductor device of one embodiment of the present invention. 11(A) is a top view of the semiconductor device shown in FIG. 1, and FIG. 11(B) is a top view of the semiconductor device shown in FIG. 1(A) and 6 are side views of the P1-P2 shown in FIGS. In the figure, OS indicates an active layer made of an oxide semiconductor, and Si indicates silicon. The active area of ​​the con is shown.

[0072] Another embodiment of the present invention is shown in FIG. A transistor 53 having an active region on a silicon substrate 40 and an oxide semiconductor layer as an active layer The transistor 53 shown in FIG. In the connection form of the capacitor 55 and the capacitor 54, a circuit 91 shown in the circuit diagram of FIG. The semiconductor device shown in FIG. 12A has a capacitance element 55 and Except for the connection mode, the semiconductor device can have the same structure as that shown in FIG.

[0073] Here, the gate electrode layer of the transistor 53 and the source electrode layer of the transistor 54 A contact is provided to electrically connect one of the drain electrode layers to one of the electrode layers of the capacitance element 55. The contact plug 66a and the contact plug 66b are used. , one of the source electrode layer or the drain electrode layer of the transistor 54 (one of the capacitor 55 The contact plug 66a is electrically connected to the contact hole 66b through an opening provided in the contact hole 66a (common to the electrode). .

[0074] The contact plugs 66a, 66b, and 67 are located at positions in the depth direction that are different from other contacts. Since it differs from the tact plug, it is shown with a dashed line.

[0075] When the structure of the transistor 52 shown in FIG. 6 is applied to the transistor 54, FIG. 14A is a top view of the semiconductor device shown in FIG. FIG. 14B is an example of a top view of the semiconductor device shown in FIG. 12(A) and 13 correspond to the cross section taken along line Q1-Q2 shown in FIGS. 14(A) and 14(B). .

[0076] The circuit 91 shown in FIG. 12B can retain memory contents even when power is not supplied. This is also an example of a semiconductor device (memory device) that has no limit to the number of times it can be written to.

[0077] The transistor 54 including an oxide semiconductor has electrical characteristics of extremely low off-state current. For example, when the voltage between the source and drain is 0.1 V, When the voltage is set to 5 V or 10 V, the off-state current is normalized by the channel width of the transistor. The current density can be reduced from several yA / μm to several zA / μm. Transistors made of other materials, such as crystalline silicon, are easier to operate at high speeds. Therefore, by combining the two, a memory with high data retention capacity and high speed operation can be created. The device can be configured.

[0078] In the semiconductor device shown in FIG. 12B, the potential of the gate electrode of the transistor 54 can be held. By taking advantage of this feature, it is possible to write, retain, and read information as follows.

[0079] The writing and holding of data will be described. First, the potential of the wiring 77 is applied to the transistor 54. is set to an on-state potential, turning on the transistor 54.

[0080] By the above operation, the potential of the wiring 76 is applied to the gate electrode of the transistor 53 and the capacitor 5 5. That is, a predetermined charge is applied to the node FN (write). Here, charges that give two different potential levels (hereinafter, low level charge and high level charge) are Either the charge or the charge itself is given.

[0081] After that, the potential of the wiring 77 is set to a potential at which the transistor 54 is turned off. By turning off 54, the charge applied to the node FN is held (retained). Since the off-state current of the transistor 54 is extremely small, the charge of the node FN remains constant for a long time. Retained.

[0082] Next, reading of information will be described. With a predetermined potential (constant potential) applied to the wiring 75, When an appropriate potential (read potential) is applied to the wiring 78, the charge held in the node FN is In response, the wiring 79 assumes a different potential.

[0083] In general, if the transistor 53 is an n-channel type, the gate electrode ( The apparent threshold voltage V when a high-level charge is applied to the th_ H In this case, a low-level charge is applied to the gate electrode (node ​​FN) of the transistor 53. The apparent threshold voltage V th_L Lower.

[0084] Here, the apparent threshold voltage is the voltage required to turn on the transistor 53. Therefore, the potential of the wiring 78 is V th_H and V th _L By setting the potential V0 between the gate electrode (node ​​FN) of the transistor 53, It can distinguish a given charge.

[0085] For example, when a high level charge is applied in a write operation, the line 78 When the potential is V0 (>V th_H ), transistor 53 is in the "on state." When a level charge is applied, the potential of the wiring 78 becomes V0( <V th_L ) Therefore, the potential of the wiring 79 is not determined. By doing so, the stored information can be read out.

[0086] When memory cells are arranged in an array, only the information in the desired memory cell is read. In this way, in memory cells that do not read information, The transistor 53 is turned "off" regardless of the potential applied to the output electrode. potential, that is, V th_H A smaller potential may be applied to the wiring 78. Regardless of the potential applied to the electrodes, transistor 53 is in the "on" state. Electric potential, i.e., V th_L A larger potential should be applied to the wiring 78 .

[0087] In the semiconductor device shown in FIG. 12B, an off-current By using extremely small transistors, memory contents can be retained for an extremely long period of time. In other words, the refresh operation is unnecessary or the refresh operation is possible. This allows the frequency of operation to be reduced significantly, resulting in a significant reduction in power consumption. In addition, when there is no power supply (however, it is preferable that the potential is fixed), Even if the memory is changed, it is possible to retain the memory contents for a long period of time. An operation of supplying power may be performed during the period.

[0088] In addition, in the above-mentioned driving method, a high voltage is required to write information to the node FN. There is no problem of deterioration of the transistor 53. For example, Electrons are injected into the floating gate by applying a voltage, and electrons are released from the floating gate. Since there is no operation to pull out the transistor, problems such as deterioration of the gate insulating film of the transistor 53 are prevented. In other words, the semiconductor device according to the disclosed invention does not have the problem of the conventional nonvolatile memory. There is no limit to the number of times the memory can be rewritten, which has been a problem, and reliability is improved dramatically. Information is written depending on the on / off state of the transistor, allowing for high-speed operation. can also be easily achieved.

[0089] Components of the semiconductor device according to one embodiment of the present invention will be described below. Although the semiconductor device shown in FIG. 1A will be described, other semiconductor devices shown in this embodiment will be described. The same is true for the body apparatus.

[0090] The silicon substrate 40 is not limited to a bulk silicon substrate, but may be an SOI substrate. Instead of the silicon substrate 40, germanium, silicon germanium, silicon carbide, gallium Materials include aluminum arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, and organic semiconductors. A substrate made of the same material as the material can also be used.

[0091] The transistor 51 is not limited to a planar type transistor, but may be of various types. For example, FIN type, TRI-GATE type, The transistor may be a gate type transistor or the like.

[0092] Similarly, transistor 52, transistor 54, etc. may be of various types. In some cases or depending on the situation, for example, a planar type, FI N (fin) type, TRI-GATE type, etc. transistors This can be done.

[0093] Transistor 52, transistor 54, etc. may be, or may not be, In addition to oxide semiconductors, various semiconductors can be used. Optionally, transistor 52, transistor 54, etc. may be made of, for example, silicon, Germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium It may also include gallium arsenide, indium phosphide, gallium nitride, organic semiconductors, and the like.

[0094] The insulating layer 81 can function as a protective film, and is typically a silicon nitride film or an aluminum oxide film. In addition, the insulating layer 82, the insulating layer 83, the insulating layer 87 and the insulating layer 8 8 can function as a planarizing film, and is typically a silicon oxide film or a silicon oxynitride film. A film or the like can be used.

[0095] The insulating layer 84 can function as a hydrogen blocking film. Hydrogen in the insulating layer provided near the region terminates the dangling bonds of silicon, This has the effect of improving the reliability of the transistor 51. Hydrogen in the insulating layer provided near the oxide semiconductor layer, which is the active layer, is absorbed into the oxide semiconductor. This is one of the factors that generates carriers, which reduces the reliability of the transistor 52. Therefore, the upper layer of a transistor using a silicon-based semiconductor material is not When transistors using nitride semiconductors are stacked, hydrogen diffusion between them is prevented. It is preferable to provide an insulating layer 84 having a function of preventing hydrogen from being trapped in the lower layer. The confinement improves the reliability of the transistor 51 and also prevents hydrogen from penetrating from the lower layer to the upper layer. By suppressing the diffusion of the impurities, the reliability of the transistor 52 can be improved at the same time. can.

[0096] The insulating layer 84 may be made of, for example, silicon nitride, aluminum oxide, or aluminum oxynitride. , gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, halide Use hafnium, hafnium oxide nitride, yttria stabilized zirconia (YSZ), etc. The insulating layer 85 can also be made of these materials.

[0097] The insulating layer 85 serves as an oxygen source for the oxide semiconductor layer of the transistor 52 . Therefore, the insulating layer 85 is an insulating layer containing oxygen, and has a composition with more oxygen than the stoichiometric composition. In addition, the insulating layer 85 is preferably a gate electrode on the back gate side of the transistor 52. Since the oxide semiconductor layer can function as a gate insulating film, the defect-free It is preferable that the film is one that is less likely to generate

[0098] The insulating layer 85 can typically be a silicon oxide film or a silicon oxynitride film. In addition, the insulating layer may be a laminate of a silicon nitride film or a silicon oxynitride film and the insulating layer. The insulating layer 87 may also be made of these materials.

[0099] The contact plugs 61a to 65 are typically made of a metal material. Specifically, tungsten can be used. Alternatively, titanium nitride may be provided on the wall surface of the insulating layer 11 and then tungsten may be filled in. The insulating layer and the upper surfaces of the contact plugs can be planarized by a CMP method. do.

[0100] In this embodiment, one embodiment of the present invention will be described using a configuration of an inverter circuit and a memory circuit as an example. It is possible to apply this to other circuits. This also applies to cases where three or more transistors or other elements are electrically connected. It is possible.

[0101] In this embodiment, a transistor having a silicon active region and a transistor having an oxide semiconductor active region are In the above example, a transistor having a silicon-containing layer is stacked on a semiconductor device. However, the present invention is not limited to this. The present invention can also be applied to a case where a plurality of transistors are stacked. The present invention can also be applied to a case where a plurality of transistors are stacked.

[0102] Further, one embodiment of the present invention can be applied to electrical connection of wirings overlapping with each other through an insulating layer. can.

[0103] FIG. 45 shows an example of an etching apparatus for etching a multilayer film having a plurality of film types. The etching apparatus shown in FIG. C, and to temporarily hold the substrate while it is being moved to each etching chamber. A transfer chamber 820 for transferring etching gas to each etching chamber A gas supply system 830 supplies the gas, etc. It has a supply system, a pump system, and a gas abatement system.

[0104] To form fine openings in a multi-layer film with multiple film types, a parallel plate type etching device is used. In particular, it is preferable to use an etching device having a high-density plasma source. It is preferable to use an appropriate etching gas for etching each layer. It is preferable to have a gas supply system that allows for a selection of gases, especially one that combines multiple gases. It is preferable to have a gas supply system that can

[0105] For example, the formation of a fine opening in a multi-layer film having multiple film types can be achieved in one etching chamber. In this method, the optimum etching gas for each layer can be used. As shown in Figure 45, if the etching equipment has three etching chambers, multiple This allows multiple substrates to be processed simultaneously, improving production efficiency. Cut.

[0106] When etching a multi-layer film having multiple film types in one etching chamber, In the etching chamber, the gas is switched to the optimum gas depending on the type of film to be etched. Various etching products can deposit on the walls of the etching chamber. The particles may peel off from the walls of the chipping chamber and become particles. If it adheres to the surface, it may cause etching defects.

[0107] As a method for preventing the generation of such particles, The following is a method of etching using the etching apparatus shown in Figure 45. Here, an example of etching a multi-layer film having a plurality of film types will be shown. The object of the etching is a first insulating film, a second insulating film, a third insulating film, and an oxide semiconductor film. A conductive film, a fourth insulating film, an organic resin film, and a photoresist are formed on the substrate in this order. The photoresist is a laminated material formed by exposing and developing the photoresist to a desired shape. It has the following shape.

[0108] First, the substrate is placed in the etching chamber 810A, and the organic resin film and the fourth insulating film are Etching is then performed. The substrate is then transferred from the etching chamber 810A to the transfer chamber 810B. The substrate is then moved to an etching chamber 810B via a chamber 820, and the conductive film is etched. The substrate is then transferred from the etching chamber 810B to the transfer chamber 8 20, and then moved to the etching chamber 810A, where the oxide semiconductor film, the third insulating film, The insulating film and the second insulating film are then etched. The substrate is then removed from the etching chamber 810A. Then, the substrate is transferred to the etching chamber 810C via the transfer chamber 820. Then, by ashing, the products of previous etching are removed. The etching chamber 810C is transferred to the transfer chamber 820 via the transfer chamber 820. The substrate is then moved to an etching chamber 810A, where the first insulating film is etched. From the etching chamber 810A, the etching The resist and organic resin film are then removed by ashing. Remove.

[0109] Even if the structure has a multi-layer film, the above steps can be repeated to obtain a multi-layer structure. This makes it possible to form minute openings.

[0110] In the above example, multiple etching steps are used to etch a multilayer film having multiple film types. In this case, the substrate is transferred under vacuum and exposed to the air atmosphere. Since there is no need to use a single etching chamber, etching can be performed with good reproducibility. In this case, the etching gas is not switched for each film type. Therefore, the processing time is shortened. This makes it possible to increase production efficiency.

[0111] The structure shown in this embodiment mode may be appropriately combined with structures shown in other embodiment modes and examples. It can be used.

[0112] (Embodiment 2) In this embodiment, a transistor including an oxide semiconductor that can be used in one embodiment of the present invention will be described. The following description will be given with reference to the drawings. Note that, in the drawings in this embodiment, the For ease of illustration, some elements may be enlarged, reduced, or omitted.

[0113] 15A and 15B are a top view and a cross-sectional view of a transistor 101 of one embodiment of the present invention. FIG. 15(A) is a top view, and FIG. 15(A) is a cross section taken along the dashed line B1-B2 shown in FIG. corresponds to FIG. 15(B). Also, the cross section in the direction of the dashed line B3-B4 shown in FIG. 21(A). The dashed line B1-B2 direction is the channel length direction, and the dashed line B The 3-B4 direction is sometimes called the channel width direction.

[0114] The transistor 101 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; a conductive layer 140 electrically connected to the oxide semiconductor layer 130; layer 150, the oxide semiconductor layer 130, the conductive layer 140, and the insulating layer 1 60, a conductive layer 170 in contact with the insulating layer 160, a conductive layer 140, a conductive layer 150, an insulating layer 1 60, an insulating layer 175 in contact with the conductive layer 170, and an insulating layer 180 in contact with the insulating layer 175. In addition, the insulating layer 180 may have a function as a planarizing film, if necessary. .

[0115] Here, the conductive layer 140 is a source electrode layer, the conductive layer 150 is a drain electrode layer, and the insulating layer 160 is The gate insulating film and the conductive layer 170 can each function as a gate electrode layer.

[0116] In addition, a region 231 shown in FIG. 15B is a source region, a region 232 is a drain region, and a region 2 Region 231 and region 232 are conductive regions. The conductive layers 140 and 150 are in contact with each other. If a conductive material that easily bonds with oxygen is used as the electrode, the resistance of the region 231 and the region 232 can be reduced. It is possible.

[0117] Specifically, the oxide semiconductor layer 130 is in contact with the conductive layer 140 and the conductive layer 150. Oxygen vacancies occur in the oxide semiconductor layer 130, and the oxygen vacancies and the remaining oxygen in the oxide semiconductor layer 130 Due to interaction with hydrogen that is retained or diffuses from the outside, regions 231 and 232 have low resistance. The n-type of the resistor.

[0118] The functions of the "source" and "drain" of a transistor are different for transistors of different polarities. This may be reversed when using a current source or when the direction of the current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" are used interchangeably. In addition, the term "electrode layer" can be replaced with "wiring." can.

[0119] In addition, the conductive layer 170 is illustrated as an example formed of two layers, a conductive layer 171 and a conductive layer 172. However, it may be a single layer or a laminate of three or more layers. The present invention can also be applied to other transistors.

[0120] In addition, although the conductive layer 140 and the conductive layer 150 are illustrated as being formed as a single layer, they may be formed as two or more layers. The above stacked structure may be applied to other transistors described in this embodiment. can.

[0121] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 16A is a top view of the transistor 102. The cross section in the 1-C2 direction corresponds to FIG. 16(B). Also, the dashed line C3 shown in FIG. The cross section in the -C4 direction corresponds to FIG. 21(B). The direction of the dashed dotted line C3-C4 may be referred to as the channel length direction, and the direction of the dashed dotted line C3-C4 may be referred to as the channel width direction.

[0122] The transistor 102 is formed by connecting the end of the insulating layer 160, which acts as a gate insulating film, and the gate electrode layer 101, except that the ends of the conductive layer 170 acting as a gate electrode are not aligned with each other. The transistor 102 has a structure in which the conductive layer 140 and the conductive layer 150 are insulating layers. Since the edge layer 160 is widely covered, the conductive layer 140, the conductive layer 150, and the conductive layer 170 are The resistance between the gate and the gate electrode is high, and the gate leakage current is low.

[0123] The transistor 101 and the transistor 102 are formed by a conductive layer 170, a conductive layer 140, and a conductive The top gate structure has a region where the gate insulating layer 150 overlaps the gate insulating layer 150. The width is preferably 3 nm or more and less than 300 nm in order to reduce parasitic capacitance. On the other hand, since no offset region is formed in the oxide semiconductor layer 130, a transistor with a high on-current is formed. It is easy to form a transistor.

[0124] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 17A is a top view of the transistor 103. The cross section in the 1-D2 direction corresponds to FIG. 17(B). The cross section in the -D4 direction corresponds to FIG. 21(A). The direction of the dashed dotted line D3-D4 may be referred to as the channel length direction, and the direction of the dashed dotted line D3-D4 may be referred to as the channel width direction.

[0125] The transistor 103 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; an insulating layer 160 in contact with the oxide semiconductor layer 130; and an insulating layer covering the oxide semiconductor layer 130, the insulating layer 160, and the conductive layer 170. An edge layer 175, an insulating layer 180 in contact with the insulating layer 175, and a layer including the insulating layer 175 and the insulating layer 180. A conductive layer 140 electrically connected to the oxide semiconductor layer 130 through an opening provided in the and a conductive layer 150. In addition, an insulating layer 180, a conductive layer 140, and a conductive layer An insulating layer (flattening film) or the like may be provided in contact with 150 .

[0126] Here, the conductive layer 140 is a source electrode layer, the conductive layer 150 is a drain electrode layer, and the insulating layer 160 is The gate insulating film and the conductive layer 170 can each function as a gate electrode layer.

[0127] In addition, a region 231 shown in FIG. 17B is a source region, a region 232 is a drain region, and a region 2 Region 231 and region 232 are insulators. For example, if an insulating material containing hydrogen is used as the insulating layer 175, the region The resistance of the region 231 and the region 232 can be reduced.

[0128] Specifically, the process up to the formation of the insulating layer 175 generates a thin film in the region 231 and the region 232. The oxygen vacancies caused by the oxygen vacancies interact with hydrogen diffusing from the insulating layer 175 into the regions 231 and 232. As a result, the regions 231 and 232 become n-type with low resistance. As the material, for example, a silicon nitride film or an aluminum nitride film can be used.

[0129] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 18A is a top view of the transistor 104. The cross section in the 1-E2 direction corresponds to FIG. 18(B). Also, the dashed line E3 shown in FIG. The cross section in the -E4 direction corresponds to FIG. 21(A). The direction of the dashed dotted line E3-E4 may be referred to as the channel length direction, and the direction of the dashed dotted line E3-E4 may be referred to as the channel width direction.

[0130] In the transistor 104, the conductive layer 140 and the conductive layer 150 cover edges of the oxide semiconductor layer. The transistor 103 has a similar structure to the transistor 103, except that the transistor 103 is in contact with the transistor 104.

[0131] In addition, the regions 331 and 334 shown in FIG. 18B are source regions, and the regions 332 and The region 335 can function as a drain region, and the region 333 can function as a channel forming region. Regions 331 and 332 correspond to regions 231 and 232 in transistor 101. The resistance can be reduced in the same manner as in the case of the transistor 2. The resistance can be reduced in the same manner as in the region 231 and the region 232 in the capacitor 103. The length of the region 334 and the region 335 in the channel length direction is preferably 100 nm or less. For a thickness of 50 nm or less, the on-current does not decrease significantly due to the contribution of the gate electric field. Alternatively, the above-mentioned resistance reduction may not be performed.

[0132] The transistor 103 and the transistor 104 are formed by the conductive layer 170 and the conductive layer 140 and the conductive The self-aligned structure does not have an area where the conductive layer 150 overlaps. The parasitic capacitance between the gate electrode layer and the source and drain electrode layers of the transistor is extremely small. This makes it suitable for high-speed operation.

[0133] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 19A is a top view of the transistor 105. The cross section in the 1-F2 direction corresponds to FIG. 19(B). Also, the dashed line F3 shown in FIG. The cross section in the -F4 direction corresponds to FIG. 21(A). The direction of the dashed dotted line F3-F4 may be referred to as the channel length direction, and the direction of the dashed dotted line F3-F4 may be referred to as the channel width direction.

[0134] The transistor 105 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; a conductive layer 141 electrically connected to the oxide semiconductor layer 130; the oxide semiconductor layer 130, the conductive layer 141, and the insulating layer 160 in contact with the conductive layer 151; The conductive layer 170 in contact with the insulating layer 160, the oxide semiconductor layer 130, the conductive layer 141, and the conductive layer 151, insulating layer 160, and conductive layer 170; insulating layer 175 in contact with insulating layer 175; The insulating layer 175 and the insulating layer 180 are electrically conductive through openings provided in the insulating layer 175 and the insulating layer 180. Conductive layer 142 and conductive layer 15 are electrically connected to layer 141 and conductive layer 151, respectively. 2. In addition, if necessary, the insulating layer 180, the conductive layer 142, and the conductive layer 152 are in contact with each other. The insulating layer may be provided.

[0135] Here, the conductive layer 141 and the conductive layer 151 are in contact with the upper surface of the oxide semiconductor layer 130 and The structure is such that it does not come into contact with

[0136] The transistor 105 includes a conductive layer 141 and a conductive layer 151, an insulating layer 175, and a and an opening provided in the insulating layer 180, and the conductive layer 14 is formed through the opening. 1 and the conductive layer 151 are electrically connected to the conductive layer 142 and the conductive layer 152, respectively. The conductive layer 140 (conductive layer 141) has a structure similar to that of the transistor 101. and conductive layer 142) can act as a source electrode layer, and conductive layer 150 (conductive Layer 151 and conductive layer 152) can act as a drain electrode layer.

[0137] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 20A is a top view of the transistor 106. The cross section in the 1-G2 direction corresponds to FIG. 20(B). The cross section in the -G4 direction corresponds to FIG. 21(A). The direction of the dashed dotted line G3-G4 may be referred to as the channel length direction, and the direction of the dashed dotted line G3-G4 may be referred to as the channel width direction.

[0138] The transistor 106 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; a conductive layer 141 electrically connected to the oxide semiconductor layer 130; a conductive layer 151, an insulating layer 160 in contact with the oxide semiconductor layer 130, and a conductive layer 162 in contact with the insulating layer 160; layer 170, an insulating layer 120, an oxide semiconductor layer 130, a conductive layer 141, a conductive layer 151, an insulating layer 160, an insulating layer 175 in contact with the conductive layer 170, and an insulating layer 180 in contact with the insulating layer 175. The conductive layer 141 and the conductive layer 142 are formed through the openings provided in the insulating layer 175 and the insulating layer 180. The conductive layer 142 and the conductive layer 152 are electrically connected to the layer 151, respectively. If necessary, an insulating layer 180, an insulating layer (planarizing film) in contact with the conductive layer 142 and the conductive layer 152, ) and the like.

[0139] Here, the conductive layer 141 and the conductive layer 151 are in contact with the upper surface of the oxide semiconductor layer 130 and The structure is such that it does not come into contact with

[0140] The transistor 106 has the same structure as the transistor 106 except that it has a conductive layer 141 and a conductive layer 151. The conductive layer 140 (conductive layer 141 and conductive layer 142) has a structure similar to that of the capacitor 103. The conductive layer 150 (conductive layer 151 and conductive layer 15 2) can act as a drain electrode layer.

[0141] In the configuration of transistor 105 and transistor 106, conductive layer 140 and conductive layer 1 Since the insulating layer 120 is not in contact with the conductive layer 140, the oxygen in the insulating layer 120 is The oxide semiconductor layer 130 is less likely to be deprived of oxygen by the conductive layer 150. This makes it easier to supply the raw material.

[0142] In addition, the region 231 and the region 232 in the transistor 103, the transistor 104, In the region 334 and the region 335 of the transistor 106, oxygen vacancies are formed and the conductor is formed. Impurities that cause oxygen vacancies in the oxide semiconductor layer may be added. Examples of the elements include phosphorus, arsenic, antimony, boron, aluminum, silicon, and nitrogen. , helium, neon, argon, krypton, xenon, indium, fluorine, chlorine, titanium One or more selected from the group consisting of titanium, zinc, and carbon can be used. Methods for adding impurities include plasma treatment, ion implantation, ion doping, and plasma A Zumai immersion ion implantation method or the like can be used.

[0143] When the above-mentioned element is added to the oxide semiconductor layer as an impurity element, the metal in the oxide semiconductor layer The bond between the element and oxygen is broken, and oxygen vacancies are formed. The interaction between the electron vacancies and hydrogen remaining in the oxide semiconductor layer or added later causes an oxide The conductivity of the semiconductor layer can be increased.

[0144] When hydrogen is added to an oxide semiconductor in which oxygen vacancies are formed by the addition of an impurity element, Hydrogen enters the oxygen vacancy site and a donor level is formed near the conduction band. Note that the oxide semiconductor that has been made a conductor can be called an oxide conductor. It is called an electric body.

[0145] An oxide conductor is a degenerate semiconductor, and the conduction band edge and the Fermi level are coincident or nearly coincident. Therefore, the oxide conductor layer and the source and drain electrode layers are The contact between the oxide conductor layer and the source electrode layer and the conductive layer that functions as a gate electrode is an ohmic contact. In addition, the contact resistance between the conductive layer functioning as the drain electrode layer and the conductive layer can be reduced.

[0146] In addition, the transistor of one embodiment of the present invention can be formed as shown in FIG. 23(A) and (B) are cross-sectional views in the channel length direction shown in FIG. As shown in the cross-sectional view in the width direction of the glass substrate, a conductive layer 173 is formed between the oxide semiconductor layer 130 and the substrate 115. The conductive layer may be used as a second gate electrode layer (back gate). This allows for a further increase in on-current and control of the threshold voltage. In the cross-sectional views shown in A, B, C, D, E, and F, The width of the conductive layer 173 may be shorter than that of the oxide semiconductor layer 130. It may be shorter than the width of 70.

[0147] In order to increase the on-current, for example, the conductive layer 170 and the conductive layer 173 are set to the same potential, and a double In order to control the threshold voltage, the MOSFET is driven as a gate transistor. A constant potential different from that of the conductive layer 170 may be applied to the conductive layer 173. To make the conductive layers 170 and 173 have the same potential, for example, as shown in FIG. 73 may be electrically connected via a contact hole.

[0148] In addition, in the transistors 101 to 106 in FIG. Although the oxide semiconductor layer 130 is illustrated as a single layer, the oxide semiconductor layer 130 may be a multilayer. The oxide semiconductor layer 130 of the transistors 101 to 106 is 25. Alternatively, it can be replaced with the oxide semiconductor layer 130 shown in FIG.

[0149] 24A, 24B, and 24C are top views of an oxide semiconductor layer 130 having a two-layer structure. 24(A) is a top view, and FIG. The cross section in the direction of the dashed line A3-A4 shown in FIG. The cross section corresponds to FIG. 24(C).

[0150] 25A, 25B, and 25C are top views of the oxide semiconductor layer 130 having a three-layer structure. 25(A) is a top view, and the dashed line A1- The cross section in the A2 direction corresponds to FIG. 25(B). Also, the dashed line A3-A shown in FIG. The cross sections in four directions correspond to FIG. 25(C).

[0151] The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are Oxide semiconductor layers having different compositions can be used.

[0152] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 26A is a top view of the transistor 107. The cross section in the 1-H2 direction corresponds to FIG. 26(B). Also, the dashed line H3 shown in FIG. The cross section in the -H4 direction corresponds to FIG. 32(A). The longitudinal direction, the direction of the dashed dotted line H3-H4, may be referred to as the channel width direction.

[0153] The transistor 107 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. a stack of an organic semiconductor layer 130a and an oxide semiconductor layer 130b, and The conductive layer 140 and the conductive layer 150 connected to each other, 0, and an insulating layer 160 in contact with the oxide semiconductor layer 130c. , the conductive layer 170 in contact with the insulating layer 160, the conductive layer 140, the conductive layer 150, the oxide semiconductor layer 130c, an insulating layer 175 in contact with the insulating layer 160 and the conductive layer 170; and an insulating layer 180 that functions as a flattening film, if necessary. A function may be added.

[0154] The transistor 107 has two oxide semiconductor layers 130 in the regions 231 and 232. In the region 233, the oxide semiconductor layer 130a is a first oxide semiconductor layer 130b. The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide The conductive layer 140 and the conductive layer 150 are the insulating layer 160. Except for the fact that a part of the oxide semiconductor layer (oxide semiconductor layer 130c) is interposed between It has a similar configuration to the transistor 101 .

[0155] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 27A is a top view of the transistor 108. The cross section in the 1-I2 direction corresponds to FIG. 27(B). The cross section in the -I4 direction corresponds to FIG. 32(B). The longitudinal direction, the direction of the dashed dotted line I3-I4, may be referred to as the channel width direction.

[0156] In the transistor 108, the insulating layer 160 and the end of the oxide semiconductor layer 130c are connected to the conductive layer 17. It differs from transistor 107 in that it does not coincide with the end of 0.

[0157] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 28A is a top view of the transistor 109. The cross section in the 1-J2 direction corresponds to FIG. 28(B). The cross section in the -J4 direction corresponds to FIG. 32(A). The longitudinal direction, the direction of the dashed dotted line J3-J4, may be referred to as the channel width direction.

[0158] The transistor 109 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. A stack of an organic semiconductor layer 130a and an oxide semiconductor layer 130b, and an oxide semiconductor layer in contact with the stack. a second insulating layer 160 in contact with the oxide semiconductor layer 130c; 0, the stack, the oxide semiconductor layer 130c, the insulating layer 160, and the conductive layer 170 An insulating layer 175 covers the conductive layer 170, an insulating layer 180 contacts the insulating layer 175, and the insulating layer 175 is and a conductive layer 14 electrically connected to the stack through an opening in the insulating layer 180. 0 and conductive layer 150. Also, as required, insulating layer 180, conductive layer 140 and An insulating layer (planarizing film) in contact with the conductive layer 150 may be provided.

[0159] The transistor 109 has two oxide semiconductor layers 130 in the regions 231 and 232. In the region 233, the oxide semiconductor layer 130a is a first oxide semiconductor layer 130b. The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide The transistor 103 has a similar structure to the transistor 103, except that the transistor 103 has a second insulating layer 130c.

[0160] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 29A is a top view of the transistor 110. The cross section in the 1-K2 direction corresponds to FIG. 29(B). Also, the dashed line K3 shown in FIG. The cross section in the -K4 direction corresponds to FIG. 32(A). The longitudinal direction, the direction of the dashed dotted line K3-K4, may be referred to as the channel width direction.

[0161] The transistor 110 has two oxide semiconductor layers 130 in the regions 231 and 232. In the region 233, the oxide semiconductor layer 130a is a first oxide semiconductor layer 130b. The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide The transistor 104 has a similar structure to the transistor 104, except that the transistor 104 has a second insulating layer 130c.

[0162] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 30A is a top view of the transistor 111. The cross section in the 1-L2 direction corresponds to FIG. 30(B). Also, the dashed line L3 shown in FIG. The cross section in the -L4 direction corresponds to FIG. 32(A). The longitudinal direction, the direction of the dashed dotted line L3-L4, may be referred to as the channel width direction.

[0163] The transistor 111 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. a stack of an organic semiconductor layer 130a and an oxide semiconductor layer 130b, and The conductive layer 141 and the conductive layer 151 connected to each other, and the laminate, the conductive layer 141 and the conductive layer 15 1, and an insulating layer 160 in contact with the oxide semiconductor layer 130c. , the conductive layer 170 in contact with the insulating layer 160, the laminate, the conductive layer 141, the conductive layer 151, the oxide an insulating layer 175 in contact with the semiconductor layer 130c, the insulating layer 160, and the conductive layer 170; The insulating layer 180 in contact with the insulating layer 175 and the openings provided in the insulating layer 175 and the insulating layer 180 are Conductive layer 142 and conductive layer 151 are electrically connected to conductive layer 141 and conductive layer 151, respectively. The conductive layer 152 may also include an insulating layer 180, a conductive layer 142, and a conductive layer 153. An insulating layer (flattening film) or the like may be provided in contact with 52 .

[0164] The transistor 111 has two oxide semiconductor layers 130 in the regions 231 and 232. In the region 233, the oxide semiconductor layer 130a is a first oxide semiconductor layer 130b. The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide and the conductive layer 141 and the conductive layer 151 and the insulating layer 160. Except for the fact that a part of the oxide semiconductor layer (oxide semiconductor layer 130c) is interposed between It has a similar configuration to the transistor 105 .

[0165] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 31A is a top view of the transistor 112. The cross section in the 1-M2 direction corresponds to FIG. 31(B). Also, the dashed line M3 shown in FIG. The cross section in the -M4 direction corresponds to FIG. 32(A). The longitudinal direction, the direction of the dashed dotted line M3-M4, may be referred to as the channel width direction.

[0166] The transistor 112 is configured as follows: The oxide semiconductor layer 130 is a two-layer structure (oxide semiconductor layer 130a and oxide semiconductor layer 130b). In the region 333, the oxide semiconductor layer 130 is made up of three layers (the oxide semiconductor layer 130a, the oxide 130a and 130b, and an oxide semiconductor layer 130c). They have a similar configuration.

[0167] In addition, the transistor of one embodiment of the present invention can be formed as shown in FIG. 34(A) and (B) are cross-sectional views in the channel length direction shown in FIG. As shown in the cross-sectional view in the width direction of the glass substrate, a conductive layer 173 is formed between the oxide semiconductor layer 130 and the substrate 115. The conductive layer may be used as a second gate electrode layer (back gate). This allows for a further increase in on-current and control of the threshold voltage. In the cross-sectional views shown in A, B, C, D, E, and F, The width of the conductive layer 173 may be shorter than that of the oxide semiconductor layer 130. It may be shorter than the width of 70.

[0168] In addition, the conductive layer 140 (source electrode layer) and the conductive The layer 150 (drain electrode layer) is a top view (oxide semiconductor layer 1) shown in FIG. 30, conductive layer 140 and conductive layer 150 are shown), O S) of the conductive layer 140 and the conductive layer 150. SD ) may be formed long However, it may be formed short. OS ≧W SD (W SD W OS (below) The gate electric field is easily applied to the entire oxide semiconductor layer 130, and the electrical characteristics of the transistor are improved. It can be improved.

[0169] In the transistors of one embodiment of the present invention (transistors 101 to 112), In either configuration, the conductive layer 170, which is the gate electrode layer, is connected to the insulating layer 170, which is the gate insulating film. The oxide semiconductor layer 130 is electrically surrounded in the channel width direction via the gate insulating film 160, and the on-current Such a transistor structure is called a surrounded channel transistor. This is called the (s-channel) structure.

[0170] In addition, a transistor having an oxide semiconductor layer 130b and an oxide semiconductor layer 130c, etc. In addition, the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c In the transistor having the above structure, the oxide semiconductor layer 130 is made of two or three layers of material. By appropriately selecting the material, a current can be passed through the oxide semiconductor layer 130b. By passing a current through the conductor layer 130b, the device is less susceptible to the effects of interface scattering and a high on-current can be obtained. In addition, by increasing the thickness of the oxide semiconductor layer 130b, the on-current can be improved. For example, the thickness of the oxide semiconductor layer 130b can be set to 100 nm to 200 nm. Good too.

[0171] By using a transistor having the above structure, good electrical characteristics are imparted to a semiconductor device. It is possible.

[0172] Note that in this specification, the channel length refers to, for example, the length of a semiconductor device when viewed from above in a top view of a transistor. The conductor (or the part of the semiconductor through which current flows when the transistor is on) and the gate The source (or source region) in the region where the electrode overlaps or the region where the channel is formed This refers to the distance between the source electrode (or drain region) and the drain (drain electrode). In addition, the channel length of a single transistor does not necessarily have the same value in all regions. That is, the channel length of a transistor may not be fixed to a single value. Therefore, in this specification, the channel length is defined as the length of any one of the regions in which the channel is formed. The value may be a maximum, minimum or average value.

[0173] The channel width is, for example, the width of the semiconductor (or the semiconductor when the transistor is in the on-state). The region where the gate electrode overlaps with the current-carrying part of the gate electrode, or the region where the channel is formed. This refers to the length of the part where the source and drain face each other in the region. In a transistor, the channel width does not necessarily have the same value in all regions. The channel width of each transistor may not be determined to be a single value. In the document, the channel width is defined as any one value, maximum value, or The minimum or average value. Note that depending on the structure of the transistor, the actual shape of the channel may differ. The channel width in the region where the transistor is formed (hereinafter referred to as the effective channel width) The channel width shown in the top view of the capacitor (hereinafter referred to as the apparent channel width) is For example, if the gate electrode covers the side of the semiconductor, the effective channel width However, it may become larger than the apparent channel width, and its effect may become unnegligible. For example, in a fine transistor in which the gate electrode covers the side of the semiconductor, The ratio of the channel region formed on the side of the semiconductor to the ratio of the channel region formed on the surface of the semiconductor In that case, the effective channel width may be larger than the apparent channel width. will be larger.

[0174] In such a case, it may be difficult to estimate the effective channel width through actual measurement. For example, to estimate the effective channel width from the design value, the shape of the semiconductor is known. Therefore, if the shape of the semiconductor is not known precisely, the effective It is difficult to measure channel width accurately.

[0175] Therefore, in this specification, the apparent channel width is defined as the "surrounding channel width (SCW)". In addition, in this specification, So, when we simply write "channel width," it means the enclosed channel width or the apparent channel width. In this specification, when the term "channel width" is used, it refers to the actual In addition, the channel length, channel width, and effective channel The width, apparent channel width, and enclosed channel width were determined by analyzing cross-sectional TEM images. The value can be determined by the following.

[0176] In addition, the field effect mobility of the transistor and the current value per channel width are calculated. In some cases, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0177] The structure shown in this embodiment mode may be appropriately combined with structures shown in other embodiment modes and examples. It can be used.

[0178] (Embodiment 3) In this embodiment, components of the transistor shown in Embodiment 2 will be described in detail. do.

[0179] The substrate 115 is a silicon substrate 40, an insulating layer 81, an insulating layer 82, and an insulating layer 83 in FIG. This corresponds to a configuration including a p-channel transistor 83 and an insulating layer 84. When forming a diaster, n - It is preferable to use a silicon substrate having a conductivity type of 1000 .mu.m. Or, n - The substrate may be an SOI substrate having a silicon layer of type or i-type. If the transistor on the silicon substrate is a p-channel type, the surface on which the transistor is formed It is preferable to use a silicon substrate with a (110) orientation. By forming an h-type transistor, the mobility can be increased.

[0180] The insulating layer 120 corresponds to the insulating layer 85 in FIG. 5, and also serves to supply oxygen to the oxide semiconductor layer 130. Therefore, the insulating layer 120 is an insulating film containing oxygen. It is preferable that the insulating film contains more oxygen than the stoichiometric composition. For example, the surface temperature of the film is 100° C. or higher and 700° C. or lower, preferably 100° C. or higher and 500° C. or lower. In the TDS method used for heat treatment, the amount of oxygen released, calculated as oxygen atoms, is 1.0 x 10 1 9 atoms / cm 3 The film is as described above. Also, the substrate 115 is a substrate on which other devices are formed. In the case of a substrate having such a structure, the insulating layer 120 also functions as an interlayer insulating film, and the surface becomes flat. In this case, planarization may be performed by a CMP method or the like.

[0181] For example, the insulating layer 120 may be made of aluminum oxide, magnesium oxide, silicon oxide, or Silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide , lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, or other oxide insulating films. , silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxynitride, etc. A laminate of the above materials can be used. It is also possible.

[0182] In this embodiment, the oxide semiconductor layer 130 of the transistor is an oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are The details will be mainly explained for the case where the layers are stacked in order.

[0183] In addition, when the oxide semiconductor layer 130 is a single layer, the layer corresponding to the oxide semiconductor layer 130b can be used.

[0184] In addition, when the oxide semiconductor layer 130 has two layers, a layer corresponding to the oxide semiconductor layer 130b and In this case, a layer corresponding to the oxide semiconductor layer 130c is stacked in this order from the insulating layer 120 side. In this configuration, the oxide semiconductor layer 130b and the oxide semiconductor layer 130c are interchanged. It is also possible.

[0185] In addition, when the oxide semiconductor layer 130 has four or more layers, for example, A configuration in which another oxide semiconductor layer is stacked on the oxide semiconductor layer 130 having a three-layer structure, or the three-layer structure Another oxide semiconductor layer may be inserted at any of the interfaces.

[0186] For example, the oxide semiconductor layer 130b may include the oxide semiconductor layer 130a and the oxide semiconductor layer 130b. The oxide layer 130c has a larger electron affinity (energy from the vacuum level to the bottom of the conduction band). The electron affinity is the energy difference between the vacuum level and the top of the valence band (ionic The energy gap between the bottom of the conduction band and the top of the valence band is calculated from the This can be calculated by subtracting the value of

[0187] The oxide semiconductor layer 130a and the oxide semiconductor layer 130c constitute the oxide semiconductor layer 130b. For example, the energy of the conduction band minimum of the oxide semiconductor layer 13 0.05 eV, 0.07 eV, 0.1 eV, or 0.15 eV or more than 0b and is close to the vacuum level within the range of 2 eV, 1 eV, 0.5 eV, or 0.4 eV. It is preferable that the insulating film be made of a thin oxide semiconductor.

[0188] In such a structure, when an electric field is applied to the conductive layer 170, That is, a channel is formed in the oxide semiconductor layer 130b, which has the smallest energy at the bottom of the conduction band. do.

[0189] The oxide semiconductor layer 130a contains at least one metal element constituting the oxide semiconductor layer 130b. Since the oxide semiconductor layer 130b and the insulating layer 120 are in contact with each other, In contrast, an interface state is formed at the interface between the oxide semiconductor layer 130b and the oxide semiconductor layer 130a. The interface state may form a channel, which may cause the transistor to malfunction. Therefore, the provision of the oxide semiconductor layer 130a can reduce the threshold voltage. As a result, variations in electrical characteristics such as the threshold voltage of the transistors can be reduced. In addition, the reliability of the transistor can be improved.

[0190] The oxide semiconductor layer 130c contains at least one metal element constituting the oxide semiconductor layer 130b. Since the oxide semiconductor layer 130b and the gate insulating film (insulating layer 160) are in contact with each other, The interface between the oxide semiconductor layer 130b and the oxide semiconductor layer 130c is Therefore, the oxide semiconductor layer 130c is provided. This makes it possible to increase the field effect mobility of the transistor.

[0191] The oxide semiconductor layer 130a and the oxide semiconductor layer 130c may include, for example, Al, Ti, Ga , Ge, Y, Zr, Sn, La, Ce or Hf is a material having a higher atomic number than the oxide semiconductor layer 130b. Specifically, a material containing the atomic ratio of 1.5 times or more of the atomic ratio can be used. The amount is preferably at least two times, and more preferably at least three times. The above elements bond strongly with oxygen. Therefore, the oxide semiconductor layer has a function of suppressing oxygen vacancies from being generated. The oxide semiconductor layer 130a and the oxide semiconductor layer 130c have a higher oxide content than the oxide semiconductor layer 130b. It can be said that element deficiency is less likely to occur.

[0192] In addition, the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130 The oxide semiconductor that can be used as c contains at least In or Zn. It is preferable that the oxide semiconductor contains both In and Zn. In order to reduce the variation in the electrical characteristics of the transistors, stabilizers were also installed. It is preferred that it includes

[0193] The stabilizer may be Ga, Sn, Hf, Al, or Zr. The stabilizers are the lanthanides La, Ce, Pr, Nd, Sm, Eu, and Gd. , Tb, Dy, Ho, Er, Tm, Yb, Lu, etc.

[0194] For example, oxide semiconductors include indium oxide, tin oxide, gallium oxide, zinc oxide, and I n-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg Oxide, In-Mg oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al- Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide Sn-Al-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In -Ce-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm- Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide In-Dy-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In -Tm-Zn oxide, In-Yb-Zn oxide, In-Lu-Zn ​​oxide, In-Sn- Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, I n-Sn-Al-Zn oxide, In-Sn-Hf-Zn oxide, In-Hf-Al-Zn An oxide can be used.

[0195] In addition, for example, In-Ga-Zn oxide is a material with In, Ga, and Zn as the main components. It means that the oxide contains metal elements other than In, Ga, and Zn. In this specification, a film made of In-Ga-Zn oxide is referred to as an IGZO film. Also called.

[0196] In addition, InMO3(ZnO) m (m>0 and m is not an integer) M may be one selected from Ga, Y, Zr, La, Ce, or Nd. It denotes a metal element or elements. Also, In2SnO5(ZnO) n (n>0, and and n is an integer) may be used.

[0197] The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are At least indium, zinc and M (Al, Ti, Ga, Ge, Y, Zr, Sn, La When the oxide semiconductor layer 1 is an In-M-Zn oxide containing a metal such as Ce or Hf, The oxide semiconductor layer 130a is In:M:Zn=x1:y1:z1 [atomic ratio], and the oxide semiconductor layer 130b is I n:M:Zn=x2:y2:z2 [atomic ratio], and the oxide semiconductor layer 130c is In:M:Z If n=x3:y3:z3 [atomic ratio], then y1 / x1 and y3 / x3 are y2 / x2 It is preferable that y1 / x1 and y3 / x3 are 1.0 times greater than y2 / x2. The thickness is set to 5 times or more, preferably 2 times or more, and more preferably 3 times or more. In the conductor layer 130b, when y2 is equal to or larger than x2, the electrical characteristics of the transistor are stabilized. However, if y2 is three times or more larger than x2, the field effect mobility of the transistor Therefore, it is preferable that y2 is less than three times x2.

[0198] When Zn and O are excluded from the oxide semiconductor layer 130a and the oxide semiconductor layer 130c, In this case, the atomic ratio of In and M is preferably less than 50 atomic %. M is 50 atomic % or more, more preferably In is less than 25 atomic %, and M is 7 In addition, the oxide semiconductor layer 130b contains Zn and O. The atomic ratio of In and M is preferably 25 atomic % or more of In and 75 atomic % or more of M. More preferably, In is 34 atomic % or more and M is 66 atomic % or less. Less than c%.

[0199] The oxide semiconductor layer 130b is a semiconductor layer including the oxide semiconductor layer 130a and the oxide semiconductor layer 130. It is preferable to have a higher indium content than c. In oxide semiconductors, the s orbital of heavy metals is the The s orbitals contribute to carrier conduction, and by increasing the In content, more s orbitals are formed. Because the paths overlap, oxides with more In than M are compared with oxides with the same or less In than M. Therefore, the oxide semiconductor layer 130b has a high indium content. By using an oxide, a transistor with high field effect mobility can be realized.

[0200] The thickness of the oxide semiconductor layer 130a is 3 nm or more and 100 nm or less, preferably 5 nm or more and 5 The thickness of the oxide semiconductor layer 1 is preferably 0 nm or less, and more preferably 5 nm or more and 25 nm or less. The thickness of 30b is 3 nm or more and 200 nm or less, preferably 10 nm or more and 150 nm or less. More preferably, the thickness of the oxide semiconductor layer 130c is set to 15 nm or more and 100 nm or less. The thickness is 1 nm or more and 50 nm or less, preferably 2 nm or more and 30 nm or less, and more preferably The oxide semiconductor layer 130b has a thickness of 3 nm or more and 15 nm or less. It is preferable that the thickness of the oxide semiconductor layer 30a is larger than that of the oxide semiconductor layer 130c.

[0201] In order to provide stable electrical characteristics to a transistor having an oxide semiconductor layer as a channel, In order to achieve this, the impurity concentration in the oxide semiconductor layer is reduced to make the oxide semiconductor layer intrinsic (i-type) or It is effective to make the oxide semiconductor layer substantially intrinsic. Rear density is 1×10 15 / cm 3 Less than 1 × 10 13 / cm 3 Less than And, 8 x 10 11 / cm 3 Less than or equal to 1 × 10 8 / cm 3 Less than or equal to 1×10 -9 / cm 3 This is as above.

[0202] In addition, in the oxide semiconductor layer, hydrogen, nitrogen, carbon, silicon, and a metal other than the main component Elements become impurities. For example, hydrogen and nitrogen contribute to the formation of donor levels and increase the carrier density. In addition, silicon contributes to the formation of impurity levels in the oxide semiconductor layer. The impurity levels can become traps and degrade the electrical characteristics of a transistor. Therefore, the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer It is preferable to reduce the impurity concentration in layer 130c and at each interface.

[0203] In order to make the oxide semiconductor layer intrinsic or substantially intrinsic, a secondary ion beam (SIMS) The silicon concentration estimated by y-Ion Mass Spectrometry (YMS) analysis was 1×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 less than , and more preferably 1×10 18 atoms / cm 3 Controlled to have an area less than In addition, the hydrogen concentration is 2×10 20 atoms / cm 3 Less than or equal to 5×10 1 9 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 The following is further Preferably 5 x 10 18 atoms / cm 3 The control is performed so as to have a region where: The nitrogen concentration may vary depending on the depth of the oxide semiconductor layer or the thickness of the oxide semiconductor layer. In a region of the layer, 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Further details are below. Preferably 5 x 10 17 atoms / cm 3 The following applies.

[0204] When silicon or carbon is contained at a high concentration, the crystallinity of the oxide semiconductor layer may be reduced. In order not to deteriorate the crystallinity of the oxide semiconductor layer, the silicon concentration is set to, for example, 1×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3Less than, even more preferred Or 1×10 18 atoms / cm 3 The control is performed so that the area is less than Carbon concentration 1×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 have an area less than Control it as follows.

[0205] In addition, a transistor using the purified oxide semiconductor film as described above for a channel formation region can be fabricated. The off-state current of the transistor is extremely small. For example, when the voltage between the source and drain is set to 0.1 V, 5 V or 10V, the off-state current per channel width of the transistor is several y It is possible to reduce the intensity to a level ranging from A / μm to several zA / μm.

[0206] In addition, since insulating films containing silicon are often used as gate insulating films for transistors, For the above reasons, the region serving as a channel of the oxide semiconductor layer is It can be said that a structure that does not contact the gate insulating film like a gate insulating film is preferable. When a channel is formed at the interface between the insulating film and the oxide semiconductor layer, carrier scattering occurs at the interface. This leads to a decrease in the field effect mobility of the transistor. It is preferable to separate the region of the conductor layer that becomes the channel from the gate insulating film.

[0207] Therefore, the oxide semiconductor layer 130 is divided into an oxide semiconductor layer 130a and an oxide semiconductor layer 130b. By forming a stacked structure of the oxide semiconductor layer 130b and the oxide semiconductor layer 130c, a channel is formed in the oxide semiconductor layer 130b. Thus, a transistor having high field effect mobility and stable electrical characteristics can be formed. It is possible to form a

[0208] The band structures of the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c In this structure, the energy of the conduction band minimum changes continuously. The oxide semiconductor layer 30a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c have similar compositions. This can also be understood from the fact that oxygen easily diffuses between the oxide semiconductor layer 130a. The oxide semiconductor layer 130b and the oxide semiconductor layer 130c are a stack of layers having different compositions. It can also be said that the layers are physically continuous, and in the drawings, the interfaces of the laminate are is represented by a dashed line.

[0209] The oxide semiconductor layer 130, which is laminated with a common main component, is not simply laminated. Continuous junction (here, a U-shaped junction in which the energy of the conduction band edge changes continuously between layers) The layers are fabricated so that a well structure (U Shape Well) is formed. There are no impurities at the interface that would form defect levels such as trap centers or recombination centers. If impurities are mixed between the stacked oxide semiconductor layers, When the interface is in a non-uniform state, the continuity of the energy band is lost, and carriers are trapped or recombined at the interface. It will disappear when combined.

[0210] For example, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c are formed of In:Ga:Zn= 1:3:2, 1:3:3, 1:3:4, 1:3:6, 1:4:5, 1:6:4 or 1: In-Ga-Zn oxide with an atomic ratio of 9:6 can be used. The compound semiconductor layer 130b has a composition of In:Ga:Zn=1:1:1, 2:1:3, 5:5:6, or Alternatively, an In-Ga-Zn oxide having an atomic ratio of 3:1:2 or the like can be used. The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130 The atomic ratios of c each include a variation of ±20% of the above atomic ratios as an error. nothing.

[0211] The oxide semiconductor layer 130b in the oxide semiconductor layer 130 serves as a well, and The oxide semiconductor layer 130 is formed in the oxide semiconductor layer 130b. Because the energy changes continuously, it can also be called a U-shaped well. A channel formed in this manner can also be called a buried channel.

[0212] In addition, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c are formed by a method of forming a silicon oxide film or the like. In the vicinity of the interface with the insulating layer, trap levels due to impurities or defects may be formed. The presence of the semiconductor layer 130a and the oxide semiconductor layer 130c makes it possible to form the oxide semiconductor layer 13 This makes it possible to keep 0b away from the trap level.

[0213] However, the energy minimum of the conduction band of the oxide semiconductor layer 130a and the oxide semiconductor layer 130c is When the difference between the energy of the conduction band minimum of the oxide semiconductor layer 130b and the energy of the oxide semiconductor layer 130c is small, Electrons in the conductor layer 130b may exceed the energy difference and reach the trap level. When the electrons are captured by the trap levels, negative charges are generated at the interface of the insulating layer, causing the transistor to turn off. The threshold voltage of the transistor is shifted in the positive direction.

[0214] The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c include It is preferable that the crystal portion is included. In particular, by using crystals oriented along the c-axis, the transistor It is possible to give stable electrical properties to the crystals. In addition, the crystals oriented along the c-axis are resistant to distortion, The reliability of a semiconductor device using a flexible substrate can be improved.

[0215] A conductive layer 140 acts as a source electrode layer and a conductive layer 141 acts as a drain electrode layer. 50 includes, for example, Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc and alloys of the metallic materials. Representative examples include Ti, which is particularly susceptible to bonding with oxygen, and the fact that the subsequent process temperature can be relatively high. For these reasons, it is more preferable to use W, which has a high melting point. In addition, Cu and Cu-M, which have low resistance, are also preferable. A laminate of an alloy such as n and the above material may be used. In the transistors 106, 111, and 112, for example, the conductive layer 14 The conductive layers 142 and 152 are laminated films of Ti and Al. etc. can be used.

[0216] The above material has a property of extracting oxygen from the oxide semiconductor layer. In some regions of the oxide semiconductor layer, oxygen is released from the oxide semiconductor layer, and oxygen vacancies are formed. The oxygen vacancies combine with the small amount of hydrogen contained in the layer, turning the region into an n-type region. Therefore, the n-type region is used as the source or drain of a transistor. It can be used.

[0217] The insulating layer 160 acting as a gate insulating film may be made of aluminum oxide, magnesium oxide, Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, oxide Germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, An insulating film containing at least one of hafnium oxide and tantalum oxide can be used. The insulating layer 160 may be a laminate of the above materials. It may contain r and the like as impurities.

[0218] Next, an example of a laminated structure of the insulating layer 160 will be described. The insulating layer 160 is, for example, , nitrogen, silicon, hafnium, etc. Specifically, hafnium oxide and It preferably contains silicon or silicon oxynitride.

[0219] Hafnium oxide and aluminum oxide are comparatively more effective than silicon oxide and silicon oxynitride. Therefore, compared to the case where silicon oxide is used, the thickness of the insulating layer 160 can be reduced. Since the gate insulating film can be made large, the leakage current due to the tunnel current can be reduced. In addition, it is possible to realize a transistor with a small leakage current. Hafnium has a higher dielectric constant than hafnium oxide, which has an amorphous structure. Therefore, in order to obtain a transistor with a small off-state current, hafnium oxide having a crystalline structure is used. Examples of the crystal structure include monoclinic and cubic crystals. However, one aspect of the present invention is not limited to these.

[0220] By the way, the surface on which hafnium oxide having a crystalline structure is formed has interface states due to defects. The interface state may function as a trap center. When silicon is placed close to the channel region of a transistor, the interface states cause the transistor to Therefore, in order to reduce the influence of the interface state, The channel region of the transistor is isolated from the hafnium oxide by placing another film between the transistor and the hafnium oxide. It is preferable to separate the insulating layer from the insulating layer. This film has a buffer function. The film may be a film included in the oxide semiconductor film 160. Examples of films with a buffer function include silicon oxide, silicon oxynitride, and oxide semiconductors. The film having the buffer function may be, for example, a film having a channel region. Use a semiconductor or insulator with a larger energy gap than the semiconductor. The film having the function includes, for example, a semiconductor having a smaller electron affinity than the semiconductor that is to be the channel region. Alternatively, the film having a buffer function may be, for example, a film having a channel region and In this case, a semiconductor or insulator having a larger ionization energy than the semiconductor is used.

[0221] On the other hand, the interface states (trap By trapping charge in the charge center, it may be possible to control the threshold voltage of a transistor. In order to make the charge exist stably, for example, the channel region and hafnium oxide A semiconductor or insulator with a larger energy gap than hafnium oxide is placed between the hafnium and the Alternatively, a semiconductor or insulator with a smaller electron affinity than hafnium oxide may be used. Alternatively, the film with a buffer function may be made of ionized ions rather than hafnium oxide. A semiconductor or insulator with high energy can be placed in the By using this, the charges trapped in the interface state are less likely to be released, and the This allows the charge to be held.

[0222] Examples of such insulators include silicon oxide and silicon oxynitride. In order to trap charges in the interface states in the layer 160, the gate voltage from the oxide semiconductor layer 130 must be The electrons can be moved toward the polar layer (conductive layer 170). temperature (for example, 125°C to 450°C, typically 150°C to 300°C) The potential of the gate electrode layer (conductive layer 170) is set higher than the potential of the source electrode and drain electrode. It is sufficient to maintain the temperature at this temperature for at least one second, typically at least one minute.

[0223] In this way, a transistor in which a desired amount of electrons are trapped in the interface state of the insulating layer 160, etc., The threshold voltage is shifted to the positive side. By adjusting the application time, the amount of electrons captured (the amount of change in threshold voltage) can be controlled. If the charges can be trapped, the charges can be trapped not in the insulating layer 160 but in the A laminated film having a similar structure may be used for other insulating layers.

[0224] In addition, in the insulating layer 120 and the insulating layer 160 in contact with the oxide semiconductor layer 130, nitrogen The semiconductor device may have a region having a low density of states due to oxides. In some cases, potential densities can form within the energy gap of the oxide semiconductor. As the insulating layer, a silicon oxynitride film that emits little nitrogen oxide or a silicon nitride film that emits little nitrogen oxide An aluminum oxynitride film or the like having a small outflow amount can be used.

[0225] In addition, the silicon oxynitride film, which emits a small amount of nitrogen oxide, was analyzed by thermal desorption spectrometry (TDS). (Thermal Desorption Spectroscopy) This is a membrane that releases more ammonia than elemental oxide, and is typically The amount is 1×10 18 pieces / cm 3 5×10 or more 19 pieces / cm 3 The following is ammonia. The amount of release is determined when the surface temperature of the film is 50°C or higher and 650°C or lower, preferably 50°C or higher and 550°C or lower. This is the amount released by the heat treatment below.

[0226] By using the oxide insulating layer as the insulating layer 120 and the insulating layer 160, It is possible to reduce the shift in the threshold voltage of the transistor, and the fluctuation in the electrical characteristics of the transistor can be reduced.

[0227] The conductive layer 170 acting as a gate electrode layer may be, for example, Al, Ti, Cr, Co, or Ni. Conductive films of Cu, Y, Zr, Mo, Ru, Ag, Mn, Nd, Sc, Ta and W In addition, alloys of the above materials and conductive nitrides of the above materials may be used. In addition, a plurality of materials selected from the above materials, alloys of the above materials, and conductive nitrides of the above materials are Typically, the material may be a laminate of tungsten or tungsten and titanium nitride. For example, a laminate of tungsten and tantalum nitride can be used. Alternatively, alloys such as Cu-Mn or laminations of the above materials with Cu or alloys such as Cu-Mn may be used. In this embodiment, tantalum nitride is used for the conductive layer 171 and tungsten is used for the conductive layer 172. This is used to form the conductive layer 170 .

[0228] The insulating layer 175 may be formed using a silicon nitride film or an aluminum nitride film containing hydrogen. The transistor 103, the transistor 104, and the transistor In transistor 106, transistor 109, transistor 110, and transistor 112, By using an insulating film containing hydrogen as the insulating layer 175, part of the oxide semiconductor layer is made n-type. The nitride insulating film also acts as a blocking film against moisture and the like. The reliability of the transistor can be improved.

[0229] Alternatively, an aluminum oxide film may be used as the insulating layer 175. The transistor 101, the transistor 102, the transistor 105, and the transistor In the transistors 107, 108, and 111, the insulating layer 175 is formed of an oxide layer. It is preferable to use an aluminum oxide film. The aluminum oxide film is formed by removing impurities such as hydrogen and moisture. Aluminum oxide has a high barrier effect of preventing the permeation of both water and oxygen. The aluminum film is resistant to impurities such as hydrogen and moisture during and after the transistor manufacturing process. Prevents oxygen from being mixed into the oxide semiconductor layer 130, prevents oxygen from being released from the oxide semiconductor layer, and prevents the insulating layer 1 It is suitable for use as a protective film having the effect of preventing unnecessary release of oxygen from 20. In addition, oxygen contained in the aluminum oxide film can be diffused into the oxide semiconductor layer. do.

[0230] In addition, it is preferable that an insulating layer 180 is formed on the insulating layer 175. are magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride , gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lath oxide The insulating film contains one or more of tantalum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. The insulating layer may also be a laminate of the above materials.

[0231] Here, the insulating layer 180, like the insulating layer 120, has more oxygen than the stoichiometric composition. It is preferable that oxygen released from the insulating layer 180 is transported through the insulating layer 160 to the oxide semiconductor Since the layer 130 can be diffused into the channel forming region, The oxygen vacancies can be filled with oxygen, resulting in a stable transistor. The electrical properties can be obtained.

[0232] In order to increase the integration density of semiconductor devices, it is essential to miniaturize transistors. It is known that the electrical characteristics of transistors deteriorate as the channel width shrinks. When the ON current is reduced, the ON current decreases.

[0233] In the transistors 107 to 112 of one embodiment of the present invention, channels are formed. The oxide semiconductor layer 130c is formed so as to cover the oxide semiconductor layer 130b. The channel formation layer and the gate insulating film are not in contact with each other. This suppresses the scattering of carriers at the interface with the gate insulating film, and the on-state voltage of the transistor is The flow can be increased.

[0234] In the transistor of one embodiment of the present invention, the channel of the oxide semiconductor layer 130 is The gate electrode layer (conductive layer 170) is formed so as to electrically surround the panel in the width direction. Therefore, the oxide semiconductor layer 130 is subjected to a gate electric field from the side in addition to the gate electric field from the direction perpendicular to the top surface. The gate electric field is applied from a direction perpendicular to the channel formation layer. Since the gate electric field is applied to the MOSFET, the effective channel width is enlarged, and the on-current is further increased. Can be enhanced.

[0235] In one embodiment of the present invention, the oxide semiconductor layer 130 is a two-layer or three-layer transistor. First, an oxide semiconductor layer 130b in which a channel is to be formed is formed on an oxide semiconductor layer 130a. In addition, the oxidation of the oxide film according to one embodiment of the present invention has an effect of making it difficult for an interface state to be formed. In a transistor having a three-layer structure of the oxide semiconductor layer 130, the oxide semiconductor layer 130b is disposed in the middle of the three-layer structure. By placing the layer in the position above the object, it is possible to eliminate the influence of impurities from above and below. Therefore, in addition to the improvement of the on-state current of the transistor, the threshold voltage is stabilized. This allows the gate to be more stable and the S value (subthreshold value) to be reduced. The current when the voltage VG is 0V can be reduced, and power consumption can be reduced. Since the threshold voltage of the transistor is stabilized, the long-term reliability of the semiconductor device is improved. In addition, the electrical characteristics of the transistor according to one embodiment of the present invention can be improved with miniaturization. Since deterioration of the semiconductor device can be suppressed, the present invention is suitable for forming a highly integrated semiconductor device.

[0236] The structure shown in this embodiment mode may be appropriately combined with structures shown in other embodiment modes and examples. It can be used.

[0237] (Embodiment 4) In this embodiment, the transistor 102 and the transistor 103 described in the second embodiment are This explains how to make 07.

[0238] First, an example of a method for fabricating a p-ch type silicon transistor included in the substrate 115 will be described. The silicon substrate is n - A single crystal silicon substrate is used, and an insulating layer (film) is applied to the surface. The element formation area is formed by isolating the element with a LO (also called a gate oxide film). COS method (Local Oxidation of Silicon) and STI method (Sh allow Trench Isolation) can be used.

[0239] Here, the substrate is not limited to a single crystal silicon substrate, but may be SOI (Silicon on Insul A substrate such as a photodiode may also be used.

[0240] Next, a gate insulating film is formed so as to cover the element formation region. The surface of the deposition region is oxidized to form a silicon oxide film. After the formation of the silicon oxide film, a nitriding treatment may be performed to nitride the surface of the silicon oxide film.

[0241] Next, a conductive film is formed to cover the gate insulating film. The conductive film may be made of Ta, W, Ti, Elements selected from Mo, Al, Cu, Cr, Nb, etc. or containing these elements as the main components The material can be an alloy or a compound material. It can also be made of a metal nitride film. In addition, it can be made of a polycrystalline film doped with impurity elements such as phosphorus. It can also be formed from a semiconductor material such as silicon.

[0242] Next, the conductive film is selectively etched to form a gate electrode layer on the gate insulating film. Form.

[0243] Next, an insulating film such as a silicon oxide film or a silicon nitride film is formed so as to cover the gate electrode layer. Then, etch-back is performed to form sidewalls on the side surfaces of the gate electrode layer.

[0244] Next, a resist mask is selectively formed so as to cover areas other than the element formation area. By introducing impurity elements using the mask and gate electrode layer, p + Type Impurity Here, to form a p-channel transistor, the impurity element and As the dopant, B, Ga, or the like, which is an impurity element that imparts p-type conductivity, can be used.

[0245] This completes the fabrication of a p-channel transistor with an active region on the silicon substrate. A passivation film such as a silicon nitride film or an aluminum oxide film is formed on the transistor. It is preferable to form

[0246] Next, an interlayer insulating film is formed on the silicon substrate on which the transistors are formed, and various contact plates are Lugs and various wiring are formed. Also, as explained in the first embodiment, the diffusion of hydrogen is prevented. An insulating layer such as aluminum oxide is formed on the substrate 115. The insulating film includes a silicon substrate on which the insulating film is formed, and an interlayer insulating film formed on the silicon substrate.

[0247] Next, a manufacturing method of the transistor 102 will be described with reference to FIGS. The left side of the drawing shows a cross section of the transistor in the channel length direction, and the right side shows a cross section in the channel width direction. The cross section is shown. The drawing in the channel width direction is an enlarged view, so the apparent film thickness of each element is shown on the left. It is different in the drawing on the right.

[0248] The oxide semiconductor layer 130 includes an oxide semiconductor layer 130a, an oxide semiconductor layer 130b, and an oxide semiconductor layer 130c. The oxide semiconductor layer 130 has a three-layer structure. In this case, the oxide semiconductor layer 130a and the oxide semiconductor layer 130b are formed as two layers. When the conductor layer 130 has a single-layer structure, it is sufficient to form the conductor layer 130 into one layer of the oxide semiconductor layer 130b.

[0249] First, an insulating layer 120 is formed on a substrate 115. The type of substrate 115 and the insulating layer 120 The material can be referred to the description of the third embodiment. The insulating layer 120 is formed by sputtering. , CVD method, MBE (Molecular Beam Epitaxy) method, etc. It can be formed.

[0250] In addition, the insulating layer 120 is subjected to ion implantation, ion doping, plasma immersion ion implantation, etc. Oxygen may be added by implantation, plasma treatment, or the like. By adding the oxygen, the supply of oxygen from the insulating layer 120 to the oxide semiconductor layer 130 is further facilitated. It can be made easier.

[0251] Note that the surface of the substrate 115 is an insulator, and impurities are diffused into the oxide semiconductor layer 130 to be provided later. If there is no effect of scattering, the insulating layer 120 may be omitted.

[0252] Next, an oxide semiconductor film 130A that will become the oxide semiconductor layer 130a is formed on the insulating layer 120. The oxide semiconductor film 130B which becomes the semiconductor layer 130b and the oxide semiconductor film 130c which becomes the oxide semiconductor layer 130c are The oxide semiconductor film 130C is formed by sputtering, CVD, MBE, or the like (FIG. 3 6(A)).

[0253] When the oxide semiconductor layer 130 has a stacked structure, the oxide semiconductor film is Using a multi-chamber deposition device (e.g., a sputtering device), each layer is exposed to the atmosphere. It is preferable to laminate the layers continuously without causing any damage to the sputtering device. In order to remove as much water and other impurities as possible from semiconductors, a cryopump is used. High vacuum evacuation (5×10) using a suction type vacuum pump -7 Pa~1×10 -4 Pa level and capable of heating the substrate to 100°C or higher, preferably 500°C or higher. Alternatively, a turbo molecular pump and a cold trap are combined to separate the gas from the exhaust system. Therefore, it is preferable to prevent gas containing carbon components, moisture, etc. from flowing back into the chamber. Also, a pumping system combining a turbo molecular pump and a cryopump may be used.

[0254] In order to obtain a high-purity intrinsic oxide semiconductor, not only is it necessary to evacuate the chamber to a high vacuum, but also to It is preferable to highly purify the sputtering gas. The gas has a dew point of -40°C or less, preferably -80°C or less, more preferably -100°C or less. By purifying the oxide semiconductor film to a high level, it is possible to prevent moisture and other substances from being absorbed into the oxide semiconductor film as much as possible. It is possible.

[0255] The oxide semiconductor film 130A, the oxide semiconductor film 130B, and the oxide semiconductor film 130C are The material described in the third embodiment can be used. In this case, the film can be formed using the material described in the third embodiment as a target. , the oxide semiconductor film 130A, the oxide semiconductor film 130B, and the oxide semiconductor film 130C The atomic ratios each include a variation of ±40% from the above atomic ratios as an error. For example, a target made of In:Ga:Zn=4:2:4.1 is used for sputtering. The atomic ratio of the deposited film can be In:Ga:Zn=4:2:3.

[0256] However, as described in detail in the third embodiment, the oxide semiconductor film 130B contains an oxide semiconductor A material having a larger electron affinity than the oxide semiconductor film 130A and the oxide semiconductor film 130C is used.

[0257] Note that the oxide semiconductor film is preferably formed by a sputtering method. For this purpose, RF sputtering, DC sputtering, AC sputtering, etc. can be used.

[0258] After the oxide semiconductor film 130C is formed, a first heat treatment may be performed. , at a temperature of 250°C or more and 650°C or less, preferably 300°C or more and 500°C or less, The reaction may be carried out in a nitrogen atmosphere, an atmosphere containing 10 ppm or more of an oxidizing gas, or under reduced pressure. The atmosphere of the first heat treatment is an inert gas atmosphere, and then the desorbed oxygen is replenished. In order to prevent this, the first heat treatment may be performed in an atmosphere containing 10 ppm or more of an oxidizing gas. The oxide semiconductor film 130A, the oxide semiconductor film 130B, and the oxide semiconductor film 130C The crystallinity of the insulating layer 120, the oxide semiconductor film 130A, and the oxide semiconductor film 130 are increased. Impurities such as hydrogen and water can be removed from B and the oxide semiconductor film 130C. Note that the first heat treatment is performed on the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, This may also be performed after the etching for forming the oxide semiconductor layer 130c.

[0259] Next, a first conductive layer is formed on the oxide semiconductor film 130A. The first conductive layer may be, for example, It can be formed using the following method.

[0260] First, a first conductive film is formed on the oxide semiconductor film 130A. l, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc, and related metallic materials A single layer or a laminate of materials selected from the alloys above may be used.

[0261] Next, a resist film is formed on the first conductive film, and the resist film is exposed to an electron beam. The first resist is exposed using a method such as immersion exposure or EUV exposure, and then developed. A mask is formed. An organic coating film is placed between the first conductive film and the resist film as an adhesive. It is preferable to form the first resist by using a nanoimprint lithography method. A mask may be formed.

[0262] Next, the first conductive film is selectively etched using the first resist mask to form a first resist. The resist mask is then ashed to form a conductive layer.

[0263] Next, the conductive layer is used as a hard mask to form an oxide semiconductor film 130A. 130B and the oxide semiconductor film 130C are selectively etched to remove the conductive layer. The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c The oxide semiconductor layer 130 is formed by stacking the above-mentioned conductive layers (see FIG. 36B). Alternatively, the oxide semiconductor layer 130 may be formed using a first resist mask without forming a second resist mask. Here, oxygen ions may be implanted into the oxide semiconductor layer 130.

[0264] Next, a second conductive film is formed so as to cover the oxide semiconductor layer 130. The material that can be used for the conductive layer 140 and the conductive layer 150 described in the sixth embodiment The second conductive film can be formed by a method such as sputtering, CVD, or MBE. There can be.

[0265] Next, a second resist mask is formed on the portions that will become the source and drain regions. Then, a part of the second conductive film is etched to form the conductive layer 140 and the conductive layer 150. (See Figure 36(C)).

[0266] Next, an insulating film 160A is formed on the oxide semiconductor layer 130, the conductive layer 140, and the conductive layer 150. The insulating film 160A can be used for the insulating layer 160 described in the third embodiment. The insulating film 160A can be formed by a method such as sputtering, CVD, or MBE. etc. can be used.

[0267] Next, a second heat treatment may be performed under the same conditions as the first heat treatment. By the second heat treatment, the oxygen injected into the oxide semiconductor layer 130 is converted into oxygen. The second heat treatment can be omitted. The above effect may be obtained by a third heat treatment.

[0268] Next, a third conductive film 171A and a fourth conductive film 172A, which will become the conductive layer 170, are formed on the insulating film 160A. The third conductive film 171A and the fourth conductive film 172A are formed as in the embodiment. The conductive layer 171 and the conductive layer 172 may be formed of a material that can be used for the conductive layer 171 and the conductive layer 172 described in 3. The third conductive film 171A and the fourth conductive film 172A may be formed by a sputtering method, a CVD method, or the like. , MBE method, etc. can be used.

[0269] Next, a third resist mask 156 is formed on the fourth conductive film 172A (FIG. 37(A) Then, the third conductive film 171A and the fourth conductive film 171B are formed by using the resist mask. 72A and the insulating film 160A are selectively etched to form the conductive layer 171 and the conductive layer 172. A conductive layer 170 and an insulating layer 160 are formed (see FIG. 37(B)). If the insulating film 160A is not etched, the transistor 102 can be fabricated. Cut.

[0270] Next, the oxide semiconductor layer 130, the conductive layer 140, the conductive layer 150, the insulating layer 160 and the conductive layer An insulating layer 175 is formed on the insulating layer 170. For the material of the insulating layer 175, see the description of the third embodiment. In the case of the transistor 101, an aluminum oxide film is preferably used. The insulating layer 175 can be formed by a sputtering method, a CVD method, an MBE method, or the like. .

[0271] Next, the insulating layer 180 is formed on the insulating layer 175 (see FIG. 37(C)). For the material, the description of the third embodiment can be referred to. In addition, the insulating layer 180 is formed by sputtering. The method may be the CVD method, MBE method, or the like.

[0272] In addition, the insulating layer 175 and / or the insulating layer 180 may be subjected to ion implantation, ion doping, Using plasma immersion ion implantation method, plasma treatment method, etc. By adding oxygen, the insulating layer 175 and / or the insulating layer 1 This makes it easier to supply oxygen from the electrode 80 to the oxide semiconductor layer 130 .

[0273] Next, a third heat treatment may be performed under the same conditions as the first heat treatment. The third heat treatment can be performed by removing the insulating layer 120, the insulating layer 175, and the insulating layer 18. 0, excess oxygen is easily released, and oxygen vacancies in the oxide semiconductor layer 130 are reduced. can be done.

[0274] Next, a method for manufacturing the transistor 107 will be described. Detailed explanation of the steps overlapping with the manufacturing method of 02 will be omitted.

[0275] An insulating layer 120 is formed on a substrate 115, and an oxide semiconductor layer 130a is formed on the insulating layer. The oxide semiconductor film 130A which will become the oxide semiconductor layer 130b is The film is formed by using a method such as sputtering, CVD, or MBE (see FIG. 38(A)).

[0276] Next, a first conductive film is formed on the oxide semiconductor film 130B, and the first A conductive layer is formed using a resist mask, and the conductive layer is then etched with an acid as a hard mask. The conductive semiconductor film 130A and the oxide semiconductor film 130B are selectively etched to form the conductive layer 130A. The layers are removed to form a stack of oxide semiconductor layers 130a and 130b. (See FIG. 38(B)). Note that a hard mask is not formed, and the first resist mask is used. Here, the stack may be formed using the oxide semiconductor layer 130a and the oxide semiconductor Oxygen ions may be implanted into the layer 130b.

[0277] Next, a second conductive film is formed so as to cover the stacked layer. A second resist mask is formed on the portion to be the gate region, and the second resist mask is used to Then, a part of the second conductive film is etched to form the conductive layer 140 and the conductive layer 150 ( See Figure 38(C).

[0278] Next, a conductive layer is formed on the stack of the oxide semiconductor layer 130a and the oxide semiconductor layer 130b. 140 and the conductive layer 150, an oxide semiconductor film 130C which becomes an oxide semiconductor layer 130c is formed. Further, an insulating film 160A and a third conductive film 171A are formed on the oxide semiconductor film 130C. And the fourth conductive film 172A is formed.

[0279] Next, a third resist mask 156 is formed on the fourth conductive film 172A (FIG. 39(A) Then, the third conductive film 171A and the fourth conductive film 171B are formed by using the resist mask. 72A, the insulating film 160A, and the oxide semiconductor film 130C are selectively etched to form a conductive A conductive layer 170 consisting of a layer 171 and a conductive layer 172, an insulating layer 160, and an oxide semiconductor The insulating film 160A and the oxide semiconductor layer 130c are formed (see FIG. 39B). The film 130C is etched using a fourth resist mask to form the transistor 108. can be produced.

[0280] Next, the insulating layer 120, the oxide semiconductor layer 130 (the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, oxide semiconductor layer 130c), conductive layer 140, conductive layer 150, insulating layer 160, and An insulating layer 175 and an insulating layer 180 are formed over the conductive layer 170 (see FIG. 39C).

[0281] Through the above steps, the transistor 107 can be manufactured.

[0282] Next, a method for manufacturing the transistor 111 will be described. Detailed explanation of the steps overlapping with the manufacturing method of 02 will be omitted.

[0283] An insulating layer 120 is formed on a substrate 115, and an oxide semiconductor layer 130a is formed on the insulating layer. The oxide semiconductor film 130A which will become the oxide semiconductor layer 130b is The first conductive film is formed by sputtering, CVD, MBE, or the like. A conductive layer 141a is formed on the semiconductor film 130B using a first resist mask. (See Figure 40(A)).

[0284] Then, the oxide semiconductor film 130A and the oxide semiconductor The oxide semiconductor layer 130a and the oxide semiconductor layer 130b are selectively etched. b and the conductive layer 141a (see FIG. 40B). Oxygen ions may be implanted into the semiconductor layer 130a and the oxide semiconductor layer 130b.

[0285] Next, a second resist mask is formed on the portions that will become the source region and the drain region; Part of the conductive layer 141a is etched using the second resist mask, and the conductive layer 141 Then, a conductive layer 151 is formed (see FIG. 40C).

[0286] Next, a conductive layer is formed on the stack of the oxide semiconductor layer 130a and the oxide semiconductor layer 130b. An oxide semiconductor film 130C that becomes an oxide semiconductor layer 130c is formed on the conductive layer 151. Further, an insulating film 160A and a third conductive film 171A are formed on the oxide semiconductor film 130C. And the fourth conductive film 172A is formed.

[0287] Next, a third resist mask 156 is formed on the fourth conductive film 172A (FIG. 41(A) Then, the third conductive film 171A and the fourth conductive film 171B are formed using the third resist mask. The conductive film 172A, the insulating film 160A, and the oxide semiconductor film 130C are selectively etched. , a conductive layer 170 consisting of a conductive layer 171 and a conductive layer 172, an insulating layer 160, and an oxide The semiconductor layer 130c is formed (see FIG. 41(B)).

[0288] Next, the insulating layer 120, the oxide semiconductor layer 130 (the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, oxide semiconductor layer 130c), conductive layer 141, conductive layer 151, insulating layer 160, and An insulating layer 175 and an insulating layer 180 are formed on the conductive layer 170 .

[0289] Next, openings are formed in the insulating layer 175 and the insulating layer 180 reaching the conductive layer 141 and the conductive layer 151. A fifth conductive film is formed so as to cover the opening. A fourth resist mask is provided, and a fifth conductive film is selected using the fourth resist mask. Then, the conductive layer 142 and the conductive layer 152 are formed by selectively etching (see FIG. 41C).

[0290] Through the above steps, the transistor 111 can be manufactured.

[0291] The various films described in this embodiment, such as a metal film, a semiconductor film, and an inorganic insulating film, are typically The can be formed by sputtering or plasma CVD, but other methods, such as thermal The insulating layer may be formed by a CVD method. An example of a thermal CVD method is MOCVD (Metal O Organic Chemical Vapor Deposition (ALD) method These include the Atomic Layer Deposition (ALD) method.

[0292] Thermal CVD is a film formation method that does not use plasma, so defects can occur due to plasma damage. This has the advantage that the

[0293] In the thermal CVD method, the source gas and the oxidizing agent are fed into the chamber at the same time, and the inside of the chamber is By reacting near or on the substrate under atmospheric or reduced pressure, the material is deposited on the substrate. Film formation may also be performed.

[0294] In the ALD method, the pressure inside the chamber is set to atmospheric pressure or reduced pressure, and the source gas for the reaction is introduced into the chamber. The film is formed by repeatedly introducing and reacting the raw material gas into the inert gas ( For example, two or more kinds of gases (argon, nitrogen, etc.) may be introduced as a carrier gas. The source gases may be supplied to the chamber in sequence. In this case, multiple source gases are not mixed. In this manner, after the reaction of the first source gas, an inert gas is introduced, and then the second source gas is introduced. Alternatively, instead of introducing an inert gas, the first source gas is exhausted by evacuation, and then the second source gas is introduced. The first source gas may be introduced into the substrate so as to adsorb and react with the surface of the substrate to form a first layer. The second source gas is introduced later and adsorbed and reacted with the second layer, which is then formed on the first layer. The gas introduction sequence is controlled to form a thin film of the desired thickness. By repeating this process several times, a thin film with excellent step coverage can be formed. The thickness can be precisely adjusted by changing the number of times the gas is injected. This is suitable for fabricating miniaturized FETs.

[0295] The thermal CVD method such as the MOCVD method or the ALD method may be used in the above-described embodiments. It can form various films such as metal films, semiconductor films, and inorganic insulating films. For example, In-Ga When forming a -Zn-O film, trimethylindium (In(CH3)3), trime Using dimethylgallium (Ga(CH3)3) and dimethylzinc (Zn(CH3)2) The combination is not limited to these, and triethyl gallium may be used instead of trimethyl gallium. Galvanic acid (Ga(C2H5)3) can also be used, and diethyl zinc can be used instead of dimethyl zinc. Zinc (Zn(C2H5)2) can also be used.

[0296] For example, when forming a hafnium oxide film using a deposition system that uses ALD, the solvent and Liquids containing hafnium precursors (hafnium alkoxides and tetrakisdimethylamide hafnium Hf (TDMAH, Hf[N(CH3)2]4) and tetrakis(ethylmethylamide The raw material gas is made by vaporizing hafnium (such as hafnium amide) and ozone ( Two types of gases are used:

[0297] For example, when forming an aluminum oxide film using a film forming apparatus that uses ALD, a solvent and a liquid containing an aluminum precursor (trimethylaluminum (TMA, Al(CH3)3 Two types of gases are used: the raw material gas made by vaporizing ethanol, etc., and H2O as an oxidizing agent. The materials used are tris(dimethylamido)aluminum, triisobutylaluminum, and aluminium. Aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate), etc. There is.

[0298] For example, when forming a silicon oxide film using a deposition system that uses ALD, The silane is adsorbed on the surface to be coated and the radicals of oxidizing gases (O2, nitrous oxide) are provided. is fed to react with the adsorbate.

[0299] For example, when forming a tungsten film using a deposition system that uses ALD, WF6 gas is used. The initial tungsten film is formed by sequentially introducing WF6 gas and H The tungsten film is formed by sequentially introducing the two gases. Note that SiH4 gas is used instead of B2H6 gas. A gas may also be used.

[0300] For example, an oxide semiconductor film, such as In-Ga-Zn-O, can be formed by a film formation apparatus using ALD. When forming a film, In(CH3)3 gas and O3 gas are introduced sequentially to form an In-O layer. Then, Ga(CH3)3 gas and O3 gas are introduced in sequence to form a GaO layer, and Then, Zn(CH3)2 gas and O3 gas are introduced in sequence to form a ZnO layer. The order of these layers is not limited to this example. It is also possible to form a mixed compound layer such as a Ga-Zn-O layer or a Ga-Zn-O layer. Alternatively, H2O gas obtained by bubbling an inert gas such as Ar may be used. It is preferable to use O3 gas, which does not contain O2.

[0301] The structure shown in this embodiment mode may be appropriately combined with structures shown in other embodiment modes and examples. It can be used.

[0302] (Embodiment 5) A structure of an oxide semiconductor film that can be used in one embodiment of the present invention will be described below. .

[0303] In this specification, "parallel" means that the angle between two straight lines is between -10° and 10°. Therefore, it includes the case where the angle is between -5° and 5°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, this also includes cases where the angle is between 85° and 95°.

[0304] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. .

[0305] Oxide semiconductor films are roughly classified into non-single-crystal oxide semiconductor films and single-crystal oxide semiconductor films. The single-crystal oxide semiconductor film is called CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor). Talline Oxide Semiconductor film, polycrystalline oxide semiconductor film The oxide semiconductor film includes a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, and the like.

[0306] First, we will explain the CAAC-OS film.

[0307] The CAAC-OS film is one of oxide semiconductor films having a plurality of crystal parts aligned along the c-axis.

[0308] Transmission Electron Microscope (TEM) A bright-field image and a combined diffraction pattern of the CAAC-OS film were obtained by using a microscope. By observing the TEM image, multiple crystalline regions can be confirmed. On the other hand, the high-resolution TEM image also shows clear boundaries between crystals, i.e., grain boundaries. Therefore, the CAAC-OS film is It can be said that the decrease in electron mobility caused by grain boundaries is unlikely to occur.

[0309] When a high-resolution TEM image of the cross section of the CAAC-OS film was observed from a direction roughly parallel to the sample surface, It can be seen that the metal atoms are arranged in layers in the crystal part. Each layer of metal atoms is The CAAC-OS film is formed on the surface (also called the surface on which the film is formed) or on the upper surface. The CAAC-OS film has a shape similar to that of the crystalline silicon film, and is aligned parallel to the surface on which the CAAC-OS film is formed or the upper surface.

[0310] On the other hand, a high-resolution TEM image of the plane of the CAAC-OS film was observed from a direction roughly perpendicular to the sample surface. They then confirmed that the metal atoms in the crystals were arranged in triangular or hexagonal shapes. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

[0311] X-ray diffraction (XRD) was performed on the CAAC-OS film. For example, a CAAC-OS film with InGaZnO4 crystals was In the out-of-plane analysis, a peak was observed at a diffraction angle (2θ) of approximately 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. This indicates that the crystals in the CAAC-OS film have a c-axis orientation, and the c-axis is generally aligned on the surface on which the film is formed or on the upper surface. It can be seen that it is oriented in a substantially vertical direction.

[0312] In addition, the out-of-plane method of CAAC-OS film with InGaZnO4 crystals In the analysis by , in addition to the peak at 2θ near 31°, a peak also appeared at 2θ near 36°. The peak at 2θ of around 36° may be due to the c-axis orientation in some parts of the CAAC-OS film. The CAAC-OS film contains crystals that do not have a 2θ of around 31°. It is preferred that the spectrum exhibits a peak and does not exhibit a peak at 2θ of around 36°.

[0313] The CAAC-OS film is an oxide semiconductor film with a low concentration of impurities. The impurities include hydrogen, carbon, and The elements are other than the main components of the oxide semiconductor film, such as silicon and transition metal elements. The elements that bond to oxygen more strongly than the metal elements that form the oxide semiconductor film, such as arsenic, are oxidized. By removing oxygen from the oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disrupted, reducing its crystallinity. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide have an atomic radius of Since the molecular radius is large, when the cation is contained in the oxide semiconductor film, the The impurities in the oxide semiconductor film may cause the atomic arrangement to be disturbed, which may result in a decrease in crystallinity. Objects can act as carrier traps or carrier generation sources.

[0314] The CAAC-OS film is an oxide semiconductor film having a low density of defect states. Oxygen vacancies in the semiconductor film can become carrier traps or trap hydrogen, It can be a carrier source.

[0315] A material with a low impurity concentration and a low defect level density (few oxygen vacancies) is called a high-purity intrinsic or The term "substantially high-purity intrinsic" refers to a highly-purified intrinsic oxide semiconductor film. Since there are fewer carrier generation sources, the carrier density can be reduced. The transistor including the oxide semiconductor film has electrical characteristics in which the threshold voltage is negative ( Also called normally-on.) In addition, high purity intrinsic or substantially high purity The highly intrinsic oxide semiconductor film has few carrier traps. The transistors using the thin film have small fluctuations in electrical characteristics and are highly reliable. Note that it takes a certain time for charges trapped in the carrier traps in the oxide semiconductor film to be released. The time when the charge is released is long, and it may behave as if it is a fixed charge. A transistor using an oxide semiconductor film having a high density of defect states has unstable electrical characteristics. This may be the case.

[0316] In addition, the electrical characteristics of transistors using CAAC-OS films were improved by irradiation with visible light or ultraviolet light. The fluctuation is small.

[0317] Next, a microcrystalline oxide semiconductor film will be described.

[0318] The microcrystalline oxide semiconductor film has a region where crystals can be confirmed in a high-resolution TEM image. The microcrystalline oxide semiconductor film has a crystal structure including a region where a crystal part is not clearly observed and a region where a crystal part is not clearly observed. The crystal part contained in the crystal has a size of 1 nm to 100 nm or 1 nm to 10 nm. In particular, the fineness is often between 1 nm and 10 nm, or between 1 nm and 3 nm. The oxide semiconductor film having nanocrystals (nc) is called nc -OS(nanocrystalline oxide semiconductor) In the nc-OS film, for example, the grain boundaries are clearly identified in high-resolution TEM images. It may not be possible to recognize

[0319] The nc-OS film is a microscopic region (e.g., a region of 1 nm to 10 nm, especially a region of 1 nm or more). The atomic arrangement has periodicity in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts. Therefore, no orientation is observed throughout the film. Therefore, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film depending on the analysis method. For example, X-ray diffraction (XR) is used to measure the nc-OS film using X-rays with a diameter larger than that of the crystals. When structural analysis was performed using the D instrument, the crystal plane In addition, the peaks indicating the probe size were not detected in the nc-OS film. Electron diffraction (also called selected area electron diffraction) using an electron beam with a diameter (for example, 50 nm or more) When the diffraction pattern is changed to 0.05μm, a halo-like diffraction pattern is observed. Nanobeam electrons are used, which use an electron beam with a probe diameter close to or smaller than the size of the crystal part. When diffraction is performed, spots are observed. In some cases, spots distributed in a circular pattern may be observed. When performing nanobeam electron diffraction, multiple spots may be observed within a ring-shaped region. do.

[0320] The nc-OS film is an oxide semiconductor film that has higher order than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. In the nc-OS film, there is no regularity in the crystal orientation between different crystal parts. The S film has a higher density of defect states than the CAAC-OS film.

[0321] Next, the amorphous oxide semiconductor film will be described.

[0322] The amorphous oxide semiconductor film is an oxide semiconductor film in which the atomic arrangement in the film is irregular and does not have a crystal part. An example is an oxide semiconductor film that has an amorphous state, such as quartz.

[0323] In the amorphous oxide semiconductor film, no crystalline parts can be confirmed in a high-resolution TEM image.

[0324] When the structure of the amorphous oxide semiconductor film is analyzed using an XRD device, out-of-p In the lane analysis, no peaks indicating crystal planes were detected. When electron diffraction is performed on a conductive film, a halo pattern is observed. When nanobeam electron diffraction is performed on a conductive film, no spots are observed, and a halo pattern is observed. Observed.

[0325] Note that the oxide semiconductor film has a structure that exhibits physical properties between the nc-OS film and the amorphous oxide semiconductor film. An oxide semiconductor film having such a structure may have a structure such as the following. Amorphous-like Oxide Semiconductor (a-like OS) The conductor membrane is called the endothelium.

[0326] In the a-like OS film, voids are observed in the high-resolution TEM image. In addition, crystals may be clearly visible in high-resolution TEM images. The a-like OS film has a region in which a crystal part is not observed and a region in which a crystal part is not observed. Crystallization occurs due to the small amount of electron irradiation, which is the level observed in TEM observations, and the growth of the crystals can be seen. On the other hand, if the nc-OS film is of good quality, the small amount of charge observed by TEM can be observed. Almost no crystallization due to electron irradiation was observed.

[0327] The size of the crystals in the a-like OS film and the nc-OS film was measured using a high-resolution T This can be done using EM images. For example, InGaZnO4 crystals have a layered structure, There are two Ga-Zn-O layers between the In-O layers. Unit cell of the InGaZnO4 crystal The layer has three In-O layers and six Ga-Zn-O layers, for a total of nine layers aligned in the c-axis direction. The spacing between adjacent layers is therefore the (009) plane. This is approximately the same as the lattice spacing (also called the d value), and crystal structure analysis has determined that this value is 0.29 nm Therefore, we focused on the lattice fringes in high-resolution TEM images and In the region where the distance is between 0.28 nm and 0.30 nm, the lattice fringes are InG aIt corresponds to the ab plane of the ZnO4 crystal.

[0328] Note that the oxide semiconductor film may be, for example, an amorphous oxide semiconductor film, an a-like OS film, or a microcrystalline oxide semiconductor film. The semiconductor layer may be a stacked film including two or more of a crystalline oxide semiconductor film and a CAAC-OS film.

[0329] The structure shown in this embodiment mode may be appropriately combined with structures shown in other embodiment modes and examples. It can be used.

[0330] (Embodiment 6) In this embodiment, a CPU including the storage device described in the previous embodiment will be described.

[0331] FIG. 42 shows a CPU using the transistors described in the above embodiments at least in part. FIG. 1 is a block diagram showing a configuration of an example.

[0332] The CPU shown in FIG. 42 includes an ALU 1191 (ALU: Arithmetic Unit) on a board 1190. ic logic unit, arithmetic circuit), ALU controller 1192, instruction A timing decoder 1193, an interrupt controller 1194, and a timing controller 1195, register 1196, register controller 1197, bus interface 1 198 (Bus I / F), rewritable ROM 1199, and ROM interface The substrate 1190 is a semiconductor substrate, a SOI substrate, The ROM 1199 and the ROM interface 1189 are Of course, the CPU shown in FIG. 42 is shown in a simplified form. This is just one example, and actual CPUs have a wide variety of configurations depending on their applications. For example, the configuration including the CPU or arithmetic circuit shown in FIG. 42 is regarded as one core, and a multi-core processor including multiple cores is used. Alternatively, the CPU may be configured to operate each core in parallel. The number of bits that can be handled by a circuit or data bus is, for example, 8 bits, 16 bits, 32 bits, 64 bits, It may be a bit, etc.

[0333] The instructions input to the CPU via the bus interface 1198 are The signal is input to the decoder 1193, decoded, and then passed to the ALU controller 1192, the interface Rupture Controller 1194, Register Controller 1197, Timing Controller Entered into 1195.

[0334] ALU controller 1192, interrupt controller 1194, register controller The controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates a signal for the CPU program. During execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and mask status. The register controller 1197 determines the address of the register 1196 and processes it. It generates a process and reads and writes to register 1196 according to the CPU state.

[0335] The timing controller 1195 also includes the ALU 1191 and the ALU controller 119 2, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal to control the operation timing of the register controller 1197. The timing controller 1195 generates an internal clock signal CLK1 based on the reference clock signal CLK1. The internal clock generating unit generates the internal clock signal CLK2. Supplied to various circuits.

[0336] In the CPU shown in FIG. 42, a register 1196 is provided with a memory cell. The transistors shown in the above embodiment can be used as the memory cells of 1196. do.

[0337] In the CPU shown in FIG. 42, the register controller 1197 receives the According to the instruction, the holding operation is selected in the register 1196. In the memory cell of 96, data is held by a flip-flop or a capacitance Select whether to hold data by the element. When selected, a power supply voltage is applied to the memory cells in the register 1196. If data retention is selected in the capacitive element, rewriting data to the capacitive element This allows the supply of the power supply voltage to the memory cells in the register 1196 to be stopped. .

[0338] FIG. 43 is an example of a circuit diagram of a storage element that can be used as the register 1196. The memory element 1200 includes a circuit 1201 in which stored data is volatilized when the power is cut off, and a circuit 1202 in which stored data is volatilized when the power is cut off. A non-volatile circuit 1202, a switch 1203, a switch 1204, and a logic element The circuit includes a transistor 1206, a capacitor 1207, and a circuit 1220 having a selection function. 1202 includes a capacitor element 1208, a transistor 1209, and a transistor 1210. The memory element 1200 may include a diode, a resistor, an inductor, etc., as necessary. The semiconductor device may further include other elements such as a capacitor.

[0339] Here, the memory device described in the above embodiment can be used for the circuit 1202. When the supply of the power supply voltage to the memory element 1200 is stopped, the transistor 120 The first gate of the transistor 1209 is connected to the ground potential (0V) or to a potential that turns off the transistor 1209. For example, the first gate of the transistor 1209 is connected to a load such as a resistor. The configuration is such that the terminal is grounded via a ground terminal.

[0340] The switch 1203 uses a transistor 1213 of one conductivity type (for example, an n-channel type). The switch 1204 is configured as a transistor of the opposite conductivity type (for example, a p-channel type). An example using a transistor 1214 is shown. Here, the first terminal of the switch 1203 The input corresponds to one of the source and drain of the transistor 1213, and the second input of the switch 1203. The terminal of corresponds to the other of the source and drain of the transistor 1213, and the switch 1203 A control signal RD input to the gate of the transistor 1213 switches the first terminal and the second terminal Conduction or non-conduction between the terminals (i.e., the on or off state of the transistor 1213) The first terminal of the switch 1204 is connected to the source and drain of the transistor 1214. The second terminal of the switch 1204 corresponds to one of the inputs, and the second terminal of the switch 1204 corresponds to the source of the transistor 1214. The other drain of the switch 1204 is connected to the gate of the transistor 1214. The control signal RD determines whether conduction or non-conduction (i.e., truncation) occurs between the first and second terminals. The on or off state of transistor 1214 is selected.

[0341] One of the source and drain of the transistor 1209 is connected to a pair of electrodes of the capacitor 1208. The connection part is electrically connected to one of the gate electrodes of the transistor 1210 and the gate of the transistor 1210. The node M2 ​​is connected to the source or drain of the transistor 1210. The other is electrically connected to a wiring (for example, a GND line) that can supply 1203 (one of the source and drain of the transistor 1213). The second terminal of the switch 1203 (the source and drain of the transistor 1213) is connected to the The other terminal of the switch 1204 (one of the source and drain terminals of the transistor 1214) The second terminal of the switch 1204 (the source terminal of the transistor 1214) is electrically connected to the The other of the source and drain terminals is electrically connected to a wiring that can supply the power supply potential VDD. The second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) ) and a first terminal of the switch 1204 (one of the source and drain of the transistor 1214 ), an input terminal of a logic element 1206, and one of a pair of electrodes of a capacitor 1207; are electrically connected. Here, the connection point is referred to as node M1. The other of the electrodes may be configured to have a constant potential input thereto. It can be configured so that a power supply potential (GND, etc.) or a high power supply potential (VDD, etc.) is input. The other of the pair of electrodes of the capacitor 1207 is connected to a line that can supply a low power supply potential. The other of the pair of electrodes of the capacitor 1208 is electrically connected to a line (for example, a GND line). For example, a low power supply potential (GND, etc.) can be input. ) or a high power supply potential (such as VDD) can be input to the capacitance element 120. The other of the pair of electrodes 8 is connected to a wiring capable of supplying a low power supply potential (for example, GND The power supply is electrically connected to the power supply line.

[0342] The capacitors 1207 and 1208 are used to reduce parasitic capacitance of transistors and wirings. It is possible to omit it by making active use of it.

[0343] A control signal WE is input to a first gate (first gate electrode) of the transistor 1209. The switch 1203 and the switch 1204 are connected to a control signal RD, which is different from the control signal WE. A conductive state or a non-conductive state between the first terminal and the second terminal is selected by When the first terminal and the second terminal of one switch are in a conductive state, the first terminal and the There is no continuity between the two terminals.

[0344] In the transistor 1209 in FIG. 43, the second gate (second gate electrode: back The first gate is connected to a control signal WE, and the second gate is connected to a control signal WE. A control signal WE2 can be input to the output. The control signal WE2 is a signal with a constant potential. The constant potential may be, for example, a ground potential GND or the solenoid potential of the transistor 1209. At this time, the control signal WE2 is set to a potential smaller than the base potential of the transistor. This is a potential signal for controlling the threshold voltage of the transistor 1209. The current when the output voltage is 0 V can be further reduced. The potential signal may be the same as that of WE. It is also possible to use a transistor that does not have

[0345] The other of the source and drain of the transistor 1209 is connected to a data register 1204. In FIG. 43, the signal output from the circuit 1201 corresponds to the The example shown is input to the other of the source and drain of the switch 1203. The signal output from the second terminal (the other of the source and drain of the transistor 1213) is The logic value is inverted by the logic element 1206 to become an inverted signal, and the inverted signal is output via the circuit 1220. The signal is then input to the circuit 1201.

[0346] In FIG. 43, the second terminal of the switch 1203 (the source and drain of the transistor 1213) The signal output from the other of the two trains is routed through logic element 1206 and circuit 1220. The second terminal of the switch 1203 is connected to the first terminal of the switch 1203. The signal output from the other of the source and drain of the transistor 1213 is inverted. For example, the following may be included in the circuit 1201: When there is a node that holds a signal with the inverted logical value of the signal input from the input terminal The second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) A signal output from the input terminal can be input to the node.

[0347] In addition, in FIG. 43, among the transistors used in the memory element 1200, The transistors other than the transistor 1209 are formed of a layer or a substrate 119 made of a semiconductor other than an oxide semiconductor. 0. For example, a silicon layer or The transistor may have a channel formed in a silicon substrate. All the transistors used in 1200 are transistors whose channels are formed in an oxide semiconductor layer. Alternatively, the memory element 1200 may include any other element other than the transistor 1209. The other transistors may include a transistor in which a channel is formed using an oxide semiconductor layer. The transistor has a channel formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. Alternatively, the transistor may be a transistor that is connected to the gate of the transistor.

[0348] For example, a flip-flop circuit can be used for the circuit 1201 in FIG. The logic element 1206 may be, for example, an inverter or a clocked inverter. It is possible.

[0349] In the semiconductor device according to one embodiment of the present invention, while a power supply voltage is not supplied to the memory element 1200, The data stored in the circuit 1201 is transferred to the capacitor 120 provided in the circuit 1202. It can be held by 8.

[0350] Further, a transistor in which a channel is formed in an oxide semiconductor layer has an extremely small off-state current. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor layer is The off-state current is significantly lower than that of a transistor whose channel is formed in silicon. Therefore, by using this transistor as the transistor 1209, the memory element 1 Even when the power supply voltage is not supplied to 200, the signal held in the capacitance element 1208 remains constant for a long period of time. In this way, the memory element 1200 can maintain the stored contents (data) even when the supply of the power supply voltage is stopped. It is possible to hold the data.

[0351] In addition, by providing the switches 1203 and 1204, the precharge operation Since the circuit 1201 is a memory element that performs the above-mentioned operation after the power supply voltage is restarted, This shortens the time it takes to restore the original data.

[0352] In the circuit 1202, the signal held by the capacitor 1208 is The power supply voltage to the memory element 1200 is then restarted. After that, the signal held by the capacitance element 1208 is converted into the state of the transistor 1210 ( The state can be converted to an ON state or an OFF state and read out from the circuit 1202. Therefore, even if the potential corresponding to the signal held in the capacitance element 1208 fluctuates slightly, the original signal can be read out accurately.

[0353] Such a memory element 1200 may be a register or a cache memory of a processor. By using it in a storage device, it is possible to prevent data loss in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped can be restored in a short time. Therefore, the entire processor, or one or more components of the processor, Since the power supply can be stopped for a short period of time in multiple logic circuits, power consumption can be reduced. It can be suppressed.

[0354] In this embodiment, the memory element 1200 is used as a CPU. The 200 is equipped with a DSP (Digital Signal Processor), custom L SI, PLD (Programmable Logic Device) and other LSIs, R Also applied to F-ID (Radio Frequency Identification) It is possible.

[0355] The structure shown in this embodiment mode may be appropriately combined with structures shown in other embodiment modes and examples. It can be used.

[0356] (Embodiment 7) A semiconductor device according to one aspect of the present invention includes a display device, a personal computer, and a recording medium. Image playback devices with advanced functions (typically DVD: Digital Versatile Disc (Devices having a display capable of playing back recording media such as 3D models and displaying the images) In addition, an electronic device in which the semiconductor device according to one embodiment of the present invention can be used Mobile phones, handheld game consoles, portable data terminals, e-book terminals, video cameras , cameras such as digital still cameras, goggle-type displays (head-mounted displays) Ray), navigation systems, audio playback devices (car audio, digital audio players, copiers, fax machines, printers, printer-combiners, automated teller machines Examples of such electronic devices include ATMs and vending machines. vinegar.

[0357] FIG. 44A shows a portable game machine, which includes a housing 901, a housing 902, a display unit 903, and a display unit 904. 904, microphone 905, speaker 906, operation key 907, stylus 908 The portable game machine shown in FIG. However, the number of display units that the portable game machine has is not limited to this. .

[0358] FIG. 44B shows a portable data terminal, which includes a first housing 911, a display unit 912, a camera 919, etc. The display unit 912 has a touch panel function that allows input of information. .

[0359] FIG. 44C shows a notebook personal computer, which includes a housing 921, a display unit 922, and a keyboard. The display device 922 includes a keyboard 923, a pointing device 924, and the like.

[0360] FIG. 44D shows a wristwatch-type information terminal, which includes a housing 931, a display unit 932, and a wristband 9 The display unit 932 may be a touch panel.

[0361] FIG. 44E shows a video camera, which includes a first housing 941, a second housing 942, a display unit 943, The operation key 944, the lens 945, the connection part 946, etc. 945 is provided in the first housing 941, and the display unit 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connection portion 946. The angle between the first housing 941 and the second housing 942 can be changed by the connection part 946. The image on the display unit 943 is transmitted between the first housing 941 and the second housing 94 at the connection unit 946. 2.

[0362] FIG. 44(F) shows an automobile, which includes a body 951, wheels 952, a dashboard 953, and lights. 954 etc.

[0363] The structure shown in this embodiment mode may be appropriately combined with structures shown in other embodiment modes and examples. It can be used. EXAMPLES

[0364] In this embodiment, in order to form the contact plug 63b shown in FIG. 5(A) of the first embodiment, The preparation of a sample having an opening will now be described.

[0365] First, a layered structure as shown in Figure 8(A) was formed on a silicon substrate using the fabrication conditions shown in Table 1. In the following description, the reference symbols shown in the process diagrams of Figs. 8 to 10 will be used.

[0366] [Table 1]

[0367] Incidentally, an opening was provided in the resist mask 36 by photolithography.

[0368] Next, the resist mask 36 is removed by using a CCP (capacitively coupled plasma) etching device. An etching process was then performed using the mask to form openings in the organic film 35 and the insulating layer 34 .

[0369] The etching conditions for the organic film 35 are: electrode distance 40 mm, substrate temperature 20° C., RF power (upper electrode)=1.62W / cm 2 (60MHz), RF power (bottom electrode)=0.32W / cm 2 (2.0 MHz), pressure 6.5 Pa, etching gas CF4 100%.

[0370] The etching conditions for the insulating layer 34 were: electrode distance 40 mm, substrate temperature 20° C., RF power (upper electrode)=0.81W / cm 2 (60MHz), RF power (lower electrode) = 5.73W / cm 2 (2.0MHz), pressure 2.6Pa, etching gas flow ratio Ar:CF4:CHF3 The ratio was 10:1:3.

[0371] Next, a resist mask 36 and a photoresist film 37 are formed on the photoresist film 37 by using an ICP (inductively coupled plasma) etching device. An etching process is performed using the insulating film 35 and the insulating layer 34 as a mask to form an opening in the metal layer 33. Established.

[0372] The etching conditions for the metal layer 33 were: electrode distance 122 mm, substrate temperature 70° C., ICP power= 0.47W / cm 2 (13.56MHz), bias power = 0.29W / cm 2 (13. The operating frequency was 56 MHz, the pressure was 1.9 Pa, and the etching gas was 100% BCl3.

[0373] Next, the organic film 35 and the insulating layer 34 are used as a mask to perform etching using a CCP etching device. A coating step was performed to provide openings in the metal layer 32 .

[0374] The etching conditions for the metal layer 32 were: electrode distance 115 mm, substrate temperature 50° C., RF power (upper part electrode)=1.62W / cm 2(60MHz), RF power (lower electrode) = 0.32W / c m 2 (13.56MHz), pressure 0.6Pa, etching gas flow ratio CF4:O2:C The l2 was set to 2:2:1.

[0375] Next, the metal layer 33 and the metal layer 32 are used as a mask to perform etching using a CCP etching device. A coating step was performed to provide openings in the insulating layer 87 and the insulating layer 86 .

[0376] The etching conditions for the insulating layer 87 are: electrode distance 25 mm, substrate temperature 20° C., RF power (upper electrode)=2.92W / cm 2 (60MHz), RF power (lower electrode) = 6.37W / cm 2 (2.0MHz), pressure 3.3Pa, etching gas flow ratio Ar:O2:C4F6= The ratio was 400:15:11.

[0377] The etching conditions for the insulating layer 86 are: electrode distance 25 mm, substrate temperature 20° C., RF power (upper electrode)=0.49W / cm 2 (60MHz), RF power (bottom electrode) = 2.86W / cm 2 (2.0MHz), pressure 3.3Pa, etching gas flow ratio Ar:CHF3=9:4 It was decided.

[0378] Next, the metal layer 33 and the metal layer 32 are used as a mask to perform etching using a CCP etching device. A bonding process is performed to provide an opening in the electrode layer 31 and expose a part of the upper surface of the insulating layer 87. He made him do so.

[0379] The etching conditions for the electrode layer 31 were: electrode distance 115 mm, substrate temperature 50° C., RF power (upper part electrode)=1.62W / cm 2 (60MHz), RF power (lower electrode) = 0.32W / c m 2 (13.56MHz), pressure 0.6Pa, etching gas flow ratio CF4:O2:C The l2 was set to 2:2:1.

[0380] Next, the metal layer 33, the metal layer 32 and the electrode layer 31 are masked using a CCP etching device. As a result, an etching process is performed to enlarge the diameter of the openings in the insulating layer 87 and the insulating layer 86. An opening was provided in the oxide semiconductor layer 30 and the insulating layer 85 .

[0381] The etching conditions for the insulating layer 87, the insulating layer 86, the oxide semiconductor layer 30, and the insulating layer 85 are as follows: Interelectrode distance 25mm, substrate temperature 20℃, RF power (upper electrode) = 0.49W / cm 2 (60 MHz), RF power (bottom electrode) = 2.86W / cm 2 (2.0MHz), pressure 3.3P a, the etching gas flow ratio was set to Ar:CHF3=9:4.

[0382] By carrying out the above steps, a sample was produced.

[0383] Figure 46 shows a cross-sectional SEM image of the opening of the sample prepared above (corresponding to the cross-sectional view of Figure 5(A)). The diameter of the opening at the top of the insulating layer 87 is 175 nm, and the diameter of the opening at the bottom of the insulating layer 85 is 175 nm. The diameter of the opening was 9.3 nm.

[0384] As shown in FIG. 5A, the openings formed in the insulating layers 86 and 87 on the electrode layer 31 are The diameter of the opening is relatively wide, and the diameter of the opening formed in the region below the electrode layer 31 is relatively narrow. Therefore, it was confirmed that the contact plug was formed by filling the opening with a conductor. When forming a contact plug, the contact area between the electrode layer 31 and the contact plug becomes wider. It can be said that the tact resistance can be reduced.

[0385] The structure shown in this embodiment can be used in appropriate combination with structures shown in other embodiments. do. [Explanation of symbols]

[0386] 30 Oxide semiconductor layer 31 Electrode layer 32 metal layer 33 Metal layer 34 Insulating layer 35 Organic film 36 Resist Mask 40 Silicon Substrate 51 Transistor 52 Transistor 53 Transistor 54 Transistor 55 Capacitive element 61a Contact plug 61b Contact plug 62a Contact plug 62b Contact plug 63a Contact plug 63b Contact plug 63B Conductors 64 Contact plug 65 Contact plug 66a Contact plug 66b Contact plug 71 Wiring 72 Wiring 73 Wiring 75 Wiring 76 Wiring 77 Wiring 78 Wiring 79 Wiring 81 Insulating layer 82 Insulating layer 83 Insulating Layer 84 Insulating Layer 85 Insulating Layer 86 Insulating Layer 87 Insulating Layer 88 Insulating Layer 90 Inverter circuit 91 Circuit 101 Transistor 102 Transistor 103 Transistor 104 Transistor 105 Transistor 106 Transistor 107 Transistor 108 Transistor 109 Transistor 110 Transistor 111 Transistor 112 Transistor 115 Substrate 120 Insulating layer 130 Oxide semiconductor layer 130a Oxide semiconductor layer 130A Oxide semiconductor film 130b Oxide semiconductor layer 130B Oxide semiconductor film 130c Oxide semiconductor layer 130C Oxide semiconductor film 140 Conductive layer 141 Conductive layer 141a Conductive layer 142 Conductive Layer 150 Conductive layer 151 Conductive layer 152 Conductive layer 156 Resist Mask 160 Insulating layer 160A Insulating film 170 Conductive Layer 171 Conductive Layer 171A Conductive film 172 Conductive Layer 172A Conductive film 173 Conductive Layer 175 Insulating Layer 180 Insulating layer 231 areas 232 areas 233 areas 331 areas 332 areas 333 areas 334 areas 335 areas 810A Etching Chamber 810B Etching Chamber 810C Etching Chamber 820 Transfer Chamber 830 Gas Supply System 901 Case 902 Case 903 Display section 904 Display section 905 Microphone 906 Speaker 907 Operation Key 908 Stylus 911 Case 912 Display section 919 Camera 921 Case 922 Display section 923 Keyboard 924 Pointing Device 931 Case 932 Display section 933 Wristband 941 Case 942 Case 943 Display section 944 Operation Key 945 Lens 946 Connection 951 Body 952 wheels 953 Dashboard 954 Light 1189 ROM Interface 1190 Board 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Registers 1197 Register Controller 1198 Bus Interface 1199 ROM 1200 memory elements 1201 Circuit 1202 Circuit 1203 Switch 1204 Switch 1206 Logic elements 1207 Capacitive element 1208 Capacitive element 1209 Transistor 1210 Transistor 1213 Transistor 1214 Transistor 1220 Circuit

Claims

[Claim 1] A first transistor and a second transistor are included. the first transistor has a silicon active region; the second transistor has an oxide semiconductor layer as an active layer; A method for manufacturing a semiconductor device, comprising forming a contact plug as a source electrode or a drain electrode of the second transistor, forming a first insulating layer; forming a first conductive film on the first insulating layer; forming a second insulating layer on the first conductive film; forming a second conductive film on the second insulating layer; forming a third conductive film on the second conductive film; forming a third insulating layer on the third conductive film; forming a resist mask on the third insulating layer; forming an opening in the third insulating layer using the resist mask; forming openings in the second conductive film and the third conductive film by using the resist mask and the third insulating film; forming an opening in the second insulating layer using the second conductive film and the third conductive film, the opening in the third conductive film having a larger diameter than the opening in the second conductive film; an opening is formed in the first conductive film by using the second conductive film and the third conductive film, and a diameter of the opening in the second conductive film is enlarged; forming an opening in the first insulating layer using the first conductive film, the second conductive film, and the third conductive film, thereby forming a first opening in the first conductive film and a second opening in the second insulating layer, the second opening having a diameter larger than that of the first opening; the first opening and the second opening are filled with a conductor to form a contact plug.

Images