Structure with through-substrate vias and method of forming same - Patents.com

Abstract

A microelectronic structure having through-substrate vias (TSVs) and methods of forming the same are disclosed. The microelectronic structure can include a bulk semiconductor having a via structure. The via structure can have first and second conductive portions. The via structure can also have a barrier layer between the first conductive portion and the bulk semiconductor. The structure can have a second barrier layer between the first and second conductive portions. The second conductive portion can extend from the second barrier layer to a top surface of the bulk semiconductor. The microelectronic structure containing the TSVs is configured such that the microelectronic structure can be coupled to a second element or structure.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Provisional Patent Application No. 63 / 216,389, entitled "STRUCTURE HAVING THROUGH-SUBSTRATE VIA AND METHOD OF FORMING SAME," filed June 29, 2021, and U.S. Provisional Patent Application No. 63 / 131,263, entitled "STRUCTURE HAVING THROUGH-SUBSTRATE VIA AND METHOD OF FORMING SAME," filed December 28, 2022, the contents of each of which are hereby incorporated by reference in their entirety into this specification.

[0002] TECHNICAL FIELD The present invention relates to structures having through-substrate vias and methods of forming the same. [Background technology]

[0003] Semiconductor elements, such as integrated device dies or chips, may be mounted or stacked on other elements. For example, a semiconductor element may be mounted on a carrier, such as a package substrate, an interposer, a reconfiguration wafer or element, or another semiconductor element. As another example, a semiconductor element may be stacked on top of another semiconductor element, e.g., a first integrated device die may be stacked on top of a second integrated device die. In some arrangements, through-substrate vias (TSVs) may extend vertically through the thickness of the semiconductor element to convey electrical signals through the semiconductor element, e.g., from a first side of the semiconductor element to a second, opposing side of the semiconductor element. Summary of the Invention [Problem to be solved by the invention]

[0004] There is a continuing need for improved methods of forming TSVs.

[0005] Particular implementations will now be described with reference to the following drawings, which are provided by way of example and not limitation. [Brief description of the drawings]

[0006] [Figure 1A] 1A-1D illustrate conventional processing steps for forming TSVs in an element. [Figure 1B] 1A-1D illustrate conventional processing steps for forming TSVs in an element. [Figure 1C] 1A-1D illustrate conventional processing steps for forming TSVs in an element. [Figure 1D] 1A-1D illustrate conventional processing steps for forming TSVs in an element. [Figure 1E] 1A-1D illustrate conventional processing steps for forming TSVs in an element. [Figure 1F] 1A-1D illustrate conventional processing steps for forming TSVs in an element. [Diagram 2] FIG. 1 shows an etch depth map of a processed wafer. [Figure 3A] 1 is an example wafer map of an etched wafer. [Figure 3B] 1 is an example wafer map of an etched wafer. [Figure 4A] 1 illustrates a method of forming a microelectronic structure in accordance with various embodiments. [Figure 4B] 1 illustrates a method of forming a microelectronic structure in accordance with various embodiments. [Figure 4C] 1 illustrates a method of forming a microelectronic structure in accordance with various embodiments. [Figure 4D] 1 illustrates a method of forming a microelectronic structure in accordance with various embodiments. [Figure 4F] 1 illustrates a method of forming a microelectronic structure in accordance with various embodiments. [Figure 4G] 1 illustrates a method of forming a microelectronic structure in accordance with various embodiments. [Figure 4H] 1 illustrates a method of forming a microelectronic structure in accordance with various embodiments. [Figure 4I] 1 illustrates a method of forming a microelectronic structure in accordance with various embodiments. [Figure 5A]1 illustrates a method of forming a microelectronic structure in accordance with various embodiments. [Figure 5B] 1 illustrates a method of forming a microelectronic structure in accordance with various embodiments. [Figure 5C] 1 illustrates a method of forming a microelectronic structure in accordance with various embodiments. [Figure 5D] 1 illustrates a method of forming a microelectronic structure in accordance with various embodiments. [Figure 5E] 1 illustrates a method of forming a microelectronic structure in accordance with various embodiments. [Figure 5F] 1 illustrates a method of forming a microelectronic structure in accordance with various embodiments. [Figure 5G] 1 illustrates a method of forming a microelectronic structure in accordance with various embodiments. [Figure 5H] 1 illustrates a method of forming a microelectronic structure in accordance with various embodiments. [Figure 5I] 1 illustrates a method of forming a microelectronic structure in accordance with various embodiments. [Figure 6A] 1 illustrates a method of forming a microelectronic structure in accordance with various embodiments. [Figure 6B] 1 illustrates a method of forming a microelectronic structure in accordance with various embodiments. [Figure 6C] 1 illustrates a method of forming a microelectronic structure in accordance with various embodiments. [Figure 6D] 1 illustrates a method of forming a microelectronic structure in accordance with various embodiments. [Figure 6E] 1 illustrates a method of forming a microelectronic structure in accordance with various embodiments. [Figure 6F] 1 illustrates a method of forming a microelectronic structure in accordance with various embodiments. [Figure 6G] 1 illustrates a method of forming a microelectronic structure in accordance with various embodiments. [Figure 6H]1 illustrates a method of forming a microelectronic structure in accordance with various embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] 1A-F illustrate various conventional processing steps for forming TSVs in microelectronic structures. Traditionally, the formation of TSVs can be performed using via-middle or front-side via-last processing methods. Both of these methods are high volume manufacturing processes for different dies, including, for example, 40 μm thick dies. Both of these processes involve etching through the TSVs into the bulk silicon after integrated circuit fabrication. The technical challenges of these processes increase with shrinking die thickness. These challenges can include TSV etch uniformity, die thickness uniformity, and the overall quality of the backside dielectric layer formed.

[0008] In Figure 1A, the microelectronic structure comprises a portion 102 of a semiconductor wafer. The via structure shown comprises a via-middle structure in which active circuitry 106, e.g., transistors or other active circuit elements, can be formed on or within an active surface of the bulk semiconductor portion 102, one or more insulating layers 112 and 113 can be formed over the active circuitry 106, and an opening 104 for a TSV can be formed through the one or more insulating layers 112 and 113 and through the portion of the bulk semiconductor portion 102. In some arrangements, a metallization layer 110, e.g., back-end-of-line (BEOL) or redistribution layer (RDL), can be provided on or within the one or more insulating layers.

[0009] In FIG. 1B, a via structure 108 can be provided. The via structure 108 can extend into the opening and across the insulating layers 112 and 113. In FIG. 1C, a conductive pad 114 can be provided on the one or more insulating layers and electrically connected to the metallization layer 110. The conductive overburden from electroplating the via structure 108 in FIG. 1B can be removed (e.g., polished off) in FIG. 1C. As shown in FIG. 1D, a conductive pad 117 can be provided on the one or more insulating layers 112 and 113 and electrically connected to the via structure 108. The conductive pad 117 can be configured to electrically connect to another element. In some arrangements, the conductive pad 117 can be part of the BEOL or RDL.

[0010] As shown in FIG. 1E, the front side of the microelectronic structure 114 can be attached to the carrier 120 with an adhesive 118. The carrier 120 can include a temporary handle wafer used to support the microelectronic structure 114 during processing. In some embodiments, the adhesive 118 can comprise an organic adhesive and can be sensitive to high temperatures. Thus, using the adhesive 118 to attach the carrier 120 to the microelectronic structure 114 can limit the temperatures that can be applied during processing. However, in another embodiment, the carrier 120 can be bonded directly to the front side of the microelectronic structure 114 without the adhesive 118. While the front side 114 is attached to the carrier 120, the back side of the semiconductor portion 124 can be ground or worn away to expose the vias 108. As shown in FIG. 1F, a dielectric layer 122 can be deposited on the back side of the semiconductor 124. A backside metallization layer 116, for example, a back-end-of-line (BEOL) or redistribution layer (RDL), can be provided on the dielectric layer 122 and can be configured to electrically connect to the via structures 108.

[0011] Conventional via formation processes have several issues that result in non-uniform via lengths. For example, the etching process used to form the openings for the vias may be non-uniform throughout a substrate such as a wafer, especially for the high aspect ratio openings used for the vias, which results in different via opening depths. The non-uniformity of the fabricated vias results in yield losses during the TSV exposure process. Furthermore, the dielectric deposition that is part of the TSV exposure process may be limited by the temporary bonding material used to bond the die to the carrier. The adhesive may limit the deposition temperature of the backside dielectric and cause various processing issues. Furthermore, the non-uniformity of the temporary bonding layer thickness may add to the thinned silicon wafer thickness uniformity. Indeed, as shown in FIG. 2, for a 12-inch wafer, the etching process used to form the via openings may have a non-uniformity of approximately 7 microns. In some areas of the wafer, the etch depth will be high (202), while in some areas of the wafer, the etch depth will be low (206), and other areas of the wafer will have an etch depth (204) between the low etch depth (206) and the high etch depth (202). The varying depth of the via opening leads to different via structure lengths, with the opening filled with a conductive material, e.g., copper.

[0012] As shown in FIG. 3A, different via lengths can result in significant yield loss. This thickness loss can further reduce TSV yield when coupled with wafer thickness variations, for example, due to process transients. For example, dies with TSVs that are too short (304) to be useful and dies with TSVs that are too long (302) to be useful may not be used. For example, some dies in a wafer may have TSVs that are too long (302) to be useful and break off during grinding or polishing. Other vias are too short (304) to be useful and become buried in the semiconductor portion of the device. Furthermore, in some processes, non-uniform TSVs can result from incomplete or non-uniform plating procedures. For example, such processes may be able to uniformly etch via openings, but plating processes through high aspect ratio openings may not be able to fill the via openings uniformly. This process variation reduces the number of useful (306) dies. Thus, non-uniform TSV lengths can result from a variety of different processing methods.

[0013] FIG. 3B illustrates thickness variations for an 8 inch wafer that can be measured after TSV planarization. As can be seen, the thickness of the wafer can vary by 4 microns. Some areas of the wafer can have a thickness up to 58.09 microns, while other areas of the wafer can have a thickness of 56.09 microns, while other areas of the wafer can have a lower thickness of about 54.67 microns. Wafer thickness variations can also cause some TSVs to be invalid, resulting in a reduced level of process control.

[0014] As discussed above, the length of the TSVs may vary considerably across the wafer after grinding the backside of the semiconductor portion to expose the TSVs, for example, due to non-uniformities in die thickness and etch non-uniformities in the TSV openings. Thus, when the backside of the bulk semiconductor portion is ground or otherwise thinned, the exposed vias may protrude from the backside of the thinned semiconductor portion by various lengths, and some vias may remain unexposed and buried in the semiconductor portion as discussed above. To reduce the non-uniform length of the TSVs while preventing breakage of the protruding TSVs, one or more backside dielectric layers may be provided on the backside of the semiconductor portion and on the TSVs. Although it is possible to use solder bumps with some variation in the height of the TSVs, this variation results in a lack of planarity, making stacking difficult. Some stacking techniques, such as direct hybrid bonding, are particularly sensitive to "local" variations.

[0015] For example, in some processes, after an initial backside silicon grind and selective removal of silicon to the liner of the TSVs by wet or dry etching methods, approximately 6-7 microns of the TSVs protrude from the backside of the semiconductor portion. A barrier layer, e.g., a dielectric barrier layer such as silicon nitride, silicon oxynitride, silicon carbonitride, diamond-like carbon, or any other suitable dielectric barrier material layer, can be deposited on the backside of the semiconductor portion, on the sidewalls of the exposed TSVs, and on the exposed edge surfaces of the exposed TSVs. A second dielectric layer, such as silicon oxide or any other suitable dielectric, can be deposited on the dielectric barrier layer, including the top surface of the barrier layer, the portion of the barrier layer extending along the sidewalls of the exposed TSVs, and the portion of the barrier layer disposed along the edge surfaces of the exposed TSVs. After depositing the backside dielectric layer, the vias and portions of the dielectric layer can be polished or otherwise removed to planarize the vias and reduce non-uniformities.

[0016] In other processes, thinner layers of the first and / or second dielectric barrier layers can be deposited over the thinned semiconductor portions and vias. For example, in other processes, the dielectric layer may be only 1 or 2 microns, e.g., significantly thinner than the length of the protruding portion of the via. Polishing the via and dielectric layer may cause portions of the via to break off, causing the ends of the via to become embedded in the semiconductor portion and recessed relative to the backside of the semiconductor portion. Broken TSVs may reduce device yields.

[0017] In some of these processes, the metal selected in the TSVs can result in significant changes in the performance of the TSVs. For example, in some processes, copper (Cu) can be an effective deposition metal. When used in TSVs, copper is a possible alloy metal that can change the expansion and polishing properties of the TSVs. Copper at the bottom of an etch via is generally trapped and may not be able to anneal at the same rate or at the same temperature as free copper. These different properties can result in Cu TSVs that do not have a stable crystallographic structure during the deposition process prior to the exposure of the TSVs. Furthermore, the TSV metallization may contain metallic or organic impurities that are unsuitable for reliable direct bonding, for example, via a Direct Bond Interconnect® process. Additionally, shrinkage of TSVs during storage or thermal processing has been shown to cause topographical problems, such as the formation of rims or trenches, in the insulating oxide surrounding the TSVs.

[0018] Some of the major issues that reduce the yield of conventional TSV formation processes include non-uniformity of TSV etch depth and TSV breakage during polishing. TSVs can have a typical depth variation of 2-4um out of a total depth of 55um throughout a 300mm wafer. This depth variation can create challenges in achieving uniform surface bonding. Furthermore, non-uniform TSVs can result in breakage during processing, leading to reduced yield. Silicon wafers can be planarized using chemical mechanical processing (CMP) planarization. During CMP planarization, some TSVs can tear. This breakage can be caused, in part, by excessive TSV exposure, which is often due to TSV depth variation.

[0019] Traditionally, backside TSV processing has not been used for direct bonding in high volume manufacturing. Traditional procedures to planarize the TSVs on the backside of the wafer may also rely on patterning copper pads and adding solder bumps to the wafer. Also, traditional backside processing does not prevent TSV folds and cannot achieve planarity suitable for direct bonding. These processes may not be suitable for high volume manufacturing due to the length of polishing time, the number of polishing cycles which can range from 4-6 cycles and take up to 2 hours of machining time, the amount of material deposited (5um), the amount of material removed (2-4um depending on the oxide deposited), and the total annealing time used between polishes (3-5 1 hour annealing cycles).

[0020] Various embodiments disclosed herein can improve device yields by ensuring uniform TSV lengths throughout the thinned wafer. In some embodiments, using a copper wet etch, the copper TSV surface can be lowered to less than a few microns below the silicon surface. In some embodiments, the surrounding silicon bulk will help contain and stabilize the copper in the TSVs. In some embodiments, a barrier layer is deposited prior to deposition of the copper seed layer. In some embodiments, electroplating techniques are used to fill the vias. In some embodiments, some TSVs may be deeper than others, and an electroplating process can be used to accommodate the additional depth of the damaged TSVs.

[0021] In some embodiments, the annealing process stabilizes the copper plug material to provide similar chemical and structural properties to the device side copper used for bonding. In some embodiments, the annealing process stabilizes the copper plug material to have the same impurity and texture characteristics as the device side bonding copper. In some embodiments, the copper plating can be annealed as a direct bonding interface. This annealing stabilizes the copper plug material and makes the plug material chemically and physically similar to the device side direct bonding interface copper pad.

[0022] In some embodiments, the CMP used for the copper layer may include slurries and processes for standard direct bond interface CMP. In some embodiments, the CMP for the TSVs may be the same as the device side CMP in terms of slurry usage and machining time. In some embodiments, the CMP parameters may be the same or similar to the device side CMP parameters. In some embodiments, this CMP uniformity may be achieved with or without the use of additional photolithography steps. In some embodiments, the only photolithography step used during the CMP process may be full backside processing.

[0023] 4A-4I illustrate a method of forming a microelectronic structure according to an embodiment. As shown in FIG. 4A and as described above, a TSV structure 410 may be provided at least partially through the thickness of a substrate including a bulk semiconductor portion 404. In some embodiments, the bulk semiconductor portion 404 may include silicon, germanium, silicon carbide, or any other suitable semiconductor material. One or more liner layers 412 may be provided from the front side 406 of the substrate to the opening. The one or more liner layers 412 may include a dielectric liner 415 in some embodiments. The dielectric liner 415 of the one or more liner layers 412 may include silicon nitride, silicon oxynitride, silicon carbonitride, diamond-like carbon, and any other suitable dielectric. In some embodiments, the one or more liner layers 412 may additionally or alternatively include a first liner barrier layer 413. While FIG. 4A illustrates the layer 412 diagrammatically as a single layer, it should be appreciated that the layer 412 may comprise multiple layers or sublayers, including, for example, a dielectric liner 415 and a liner barrier layer 413. The first conductive via 402 may be provided in an opening through the liner layer 412. In some embodiments, the first conductive via 402 may comprise copper, although other suitable metals may be used. The first conductive via portion 402 may be provided from the front side of the substrate 406. The first liner barrier layer 413 may comprise a conductive barrier to reduce diffusion of the conductive via material. The first liner barrier layer 413 may be a different material than the conductive materials of the first conductive via portion 402 and the second conductive via portion 424. The first liner barrier layer 413 may be configured to reduce diffusion of the conductive materials of the first conductive via portion 402 and / or the second conductive via portion 424 into the surrounding dielectric and / or semiconductor materials. Examples of materials used for the first liner barrier layer 413 include metal and metal nitride materials, such as titanium nitride, tantalum nitride, and any other suitable metal and metal nitride materials. The first conductive via portion 402 can be electroplated in the opening and over the seed layer.The front or front side, e.g., first side 406, of the wafer can include the active side of the semiconductor portion in which or on which active integrated circuits, such as transistors, are formed. The front or first side 406 of the wafer can be attached to a carrier 414. The carrier 414 can function as a temporary handle wafer in some embodiments. In some embodiments, the microelectronic structures can be attached to the carrier 414 using an adhesive. In other embodiments, the microelectronic structures can be bonded directly to the carrier 414 without an intervening adhesive using direct bonding techniques, which are described in more detail below. As shown in FIGS. 4A-C, the TSVs 410 can have varying heights throughout the substrate due to variable etching through significant depths in the bulk semiconductor.

[0024] In FIG. 4B, the backside or second side 408 of the semiconductor portion, which at this stage is also the backside of the substrate, may be thinned by dry etching or otherwise removing to expose the TSVs 410. As shown, the TSVs 410 may protrude beyond the backside of the semiconductor portion 408. As described above, the length of the TSVs 410 may be non-uniform across the wafer, so that the TSVs 410 protrude by varying lengths above the semiconductor portion 416. The etching process may leave the via structure 410 intact, so that the one or more liner layers 412, including the dielectric liner 415 and the first liner barrier layer 413, remain disposed on and along the sidewalls 411 of the conductive via portion. In FIG. 4C, one or more dielectric layers 418 may be provided, e.g., deposited, over the top surface 408 of the bulk semiconductor portion 416, along the sidewalls 411 of the via structure 410, and over an edge of the via structure 410 that defines the backside 408 of the substrate. While FIG. 4C illustrates the layer 418 diagrammatically as a single layer, it should be appreciated that the layer 418 may comprise multiple layers or sublayers. In various embodiments, the dielectric layer 418 may be a first dielectric barrier layer 419 disposed over the bulk semiconductor portion 416 and over the via structure 410. The dielectric layer 418 may further include a second dielectric layer 421 overlying the first dielectric barrier layer 419. In various embodiments, the first dielectric barrier layer 419 may include a material that reduces copper migration, such as, for example, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, diamond-like carbon (DLC), or any other suitable dielectric barrier layer material. The second dielectric layer 421 may include a low-k dielectric and may be an inorganic dielectric, such as silicon oxide. As shown in FIG. 4C, the TSVs 410 may protrude beyond the semiconductor portion 408 by a distance in a range of approximately 0 to 10 microns, 1 to 7 microns, or 5 to 6 microns. As further described herein, TSV 410 may break, as seen in TSV 420, and recess into semiconductor portion 416 and / or dielectric layer 418 a distance in the range of 0 to 10 microns, 1 to 7 microns, or 2 to 6 microns.The thickness of the dielectric layer 418 may be in the range of about 2-7 microns, in the range of about 3-7 microns, or in the range of about 4-6 microns, or in one embodiment, about 5 microns.

[0025] In FIG. 4D, the via structure 410 and the dielectric layer 418 can be planarized using, for example, a chemical mechanical polishing (CMP) process applied to the backside 408 of the substrate. As discussed herein above, the planarization process can break off one or more of the TSVs 410, such as the central TSV 420. For example, in FIG. 4D, the central TSV 420 is shown as broken off such that the TSV 420 is embedded in the dielectric layer 418 and / or the semiconductor portion 416 and recessed below the surface. As discussed above, broken TSVs such as the central TSV 420 can reduce wafer device yield. Depending on the chemistry selected for the CMP slurry, some or all of the other TSVs 410 may also be recessed below the dielectric layer and / or the semiconductor portion.

[0026] In FIG. 4E, the first conductive via portion 402 may be selectively etched to recess below the backside of the substrate 408, e.g., below the dielectric layer 418 and / or the semiconductor portion 408. Because the central TSV 420 is broken off, the etch depth of the central via structure 420 is deeper than the etch depth of the other via structures 410. In various embodiments, a selective copper wet etch may be performed to etch only a portion of the first conductive via portion 402. Advantageously, in the illustrated embodiment, all of the TSVs 410 throughout the substrate 416 are recessed at least to some extent below the top surface of the applied dielectric layer 418. In other embodiments, recessing of the TSVs 410 may be accomplished during CMP as described above with respect to FIG. 4D. In still other embodiments, only a portion of the TSVs 410 are recessed, with or without a separate recessing step. For example, in some embodiments, a conventional CMP process is used in which some TSVs 410 are substantially recessed below surface 408, for example by bending.

[0027] As shown in FIG. 4F, a second barrier layer 422 can be provided on the exposed end surface of the first conductive via portion 402 and along the liner barrier layer 412 to improve yield and provide a planarized high quality bonding surface. A seed layer (not shown) can be provided on the second barrier layer 422, and a second conductive via portion 424 can be provided on the second barrier layer 422 from the backside of the substrate 416, for example, by electroplating. The microelectronic structure can be annealed, which can advantageously facilitate grain growth to improve the direct bond. Advantageously, a deposition process, such as electroplating, and an annealing process can be selected together to prepare the direct hybrid bond, as opposed to a plating process used to initially fill the TSV via 410, which is selected to improve filling of the high aspect ratio deep via.

[0028] In various embodiments, alloying additives can be added to the conductive material of the TSV 410. The alloying additives can be provided to control thermal expansion and / or improve the corrosion resistance of the conductor. In some embodiments, the conductor is copper, silver, gold, or any other suitable conductive material. The alloying additive material can include metallic elements, such as beryllium, indium, gallium, nickel, manganese, and typically corresponds to less than 5 atomic %, more specifically less than 2 atomic %, of the TSV 410. The alloying additives can be applied as part of the seed layer or second barrier layer 422 and diffused therefrom. Such alloying elements can be present in different amounts to improve the hardness, corrosion resistance, and / or suppress grain formation during subsequent annealing of the TSV 410. The first conductive portion 402 can contain a smaller percentage of alloying elements compared to the second conductive portion 424, since larger grains are desired in the second conductive portion to facilitate interdiffusion in the metal-metal direct bonding process. For example, in some embodiments, the second conductive via portion 424 can have at least 5% less, at least 10% less, at least 15% less, or at least 20% less alloying elements than the first conductive via portion.

[0029] Additionally, one or more organic additives, such as levelers, suppressors, and accelerators, may be provided to the plating bath during formation of the TSVs 410 to improve filling. In various embodiments, a different additive and / or a different ratio of additive, e.g., less additive, may be added when plating the second conductive via portion 424 compared to the type or amount of additive used when plating the first conductive via portion 402 that fills the opening. For example, in some embodiments, additives may be used when plating both the first conductive via portion 402 and the second conductive via portion 424, but the amount of additive used in the first conductive via portion 402 may be substantially different than the amount used in the second conductive via portion 424. In some embodiments, more additive may be used when plating the first conductive via portion 402 than when plating the second conductive via portion 424. In some embodiments, additives such as organic additives can be added during electroplating of the first conductive via portion 402, for example to improve filling, while a different ratio or type of organic additive can be added during electroplating of the second conductive via portion 424. In various embodiments, the plating bath for the first conductive via portion 402 can include a greater percentage of organic additives than the plating bath for forming the second conductive via portion 424. Thus, the first conductive via portion 402 can have a greater percentage of impurities such as sulfur, oxygen, nitrogen, and / or carbon than the second conductive via portion 424. In various embodiments, the first conductive via portion 402 can be formed in a plating bath having a higher concentration of a leveler, e.g., Janus Green, that introduces more impurities such as nitrogen, carbon, and / or oxygen than the second conductive via portion 422. In both portions 402 and 424, the impurities from the additives can be measured in parts per million (ppm).

[0030] After electroplating, impurities from the plating additives, such as carbon, nitrogen, sulfur, oxygen, among other impurities, may be incorporated into the first conductive via portion 402 and / or the second conductive via portion 424. In some embodiments, the amount of impurities present in the first conductive via portion 402 may be greater than the amount of impurities present in the second conductive via portion 424. In some embodiments, only trace amounts of impurities may be present in the second conductive via portion 424. Furthermore, the impurities present in the second conductive via portion 424 may have a different composition and / or concentration compared to the first conductive via portion 402. These compositions may be selected to affect the grain size, orientation, or thermal stability of the interconnect that can be formed by the second conductive portion. The impurities may include other material elements present in the conductive via at a concentration of less than 2 atomic %, e.g., less than 100 ppm or less than 50 ppm. In one embodiment, the impurities in the second conductive via portion 424 may be less than the impurities in the first conductive via portion 402. For example, in some embodiments, the second conductive via portion 424 can have at least 5% less, at least 10% less, or at least 20% less non-copper elements (e.g., metal alloy elements or impurities from plating bath additives) than the first conductive via portion 402.

[0031] In FIG. 4G, the overlying portions of the dielectric layer 418 relative to the second conductive via portion 424 and the second barrier layer 422 can be removed, for example, using a CMP process applied to the backside of the substrate. The polishing process can expose and planarize the dielectric layer 418 and serve as a preparatory step for direct bonding, i.e., a very high degree of polishing achieves sufficient planarity for direct bonding. Advantageously, the central broken TSV 420 has been repaired and the metal recess is provided to an appropriate depth so that the polished dielectric layer 418 and the second conductive via portion 424 can be used for the direct bonding process. For example, the plating and annealing process can form grains such as copper, gold, or silver grains oriented along 111 crystal planes that are primarily perpendicular to the bonding surface, or a metal texture such as copper, which can enhance the diffusion and bonding of the metal during direct bonding. In various embodiments, the metal texture can be oriented to have a geometric component that is approximately perpendicular to the bonding surface. In some embodiments, the second conductive via portion 424 can have a first ratio 111 plane oriented within 30° of the vertical, e.g., within 30° of a vertical axis extending along the longitudinal dimension of the via structure, within 20° of the vertical, or within 10° of the vertical. The second conductive via portion 424 can have a second ratio 111 plane oriented within 30° of the vertical, e.g., within 30° of a vertical axis extending along the longitudinal dimension of the via structure, within 20° of the vertical, or within 10° of the vertical. In some embodiments, the second ratio can be greater than the first ratio. In the illustrated embodiment, a CMP selection, see FIG. 4D and corresponding discussion, and subsequent indentation, see FIG. 4E and corresponding discussion, are selected to ensure indentation to the extent that it penetrates the entire substrate, and each TSV 410 can include both the first conductive via portion 402 and the second conductive via portion 424. In other embodiments, not all TSVs 410 are recessed through the entire substrate at the stage of Figure 4E, but only some TSVs 410 include second conductive via portions 424. In either case, the CMP process selected to achieve the structure of Figure 4G can be selected to facilitate subsequent direct hybrid bonding.Thus, each of the TSVs 410 can be recessed below the top surface of the dielectric layer 418 by, for example, less than 40 nm, less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, but greater than or equal to about 5 nm, for example, greater than or equal to about 2 nm.

[0032] As shown in FIG. 4H, the microelectronic elements described above can be utilized in a multi-die or multi-element stack. For example, a first stacked die 434 can be bonded directly to the base wafer 432 without adhesive. In some embodiments, the front active surface can be bonded to the base wafer. As described below, the contact pads 426 of the first die can be bonded directly to the contact pads 426 of the wafer without adhesive, and the non-conductive regions can be bonded directly to corresponding non-conductive regions of the wafer without adhesive 430. Additional devices can be stacked and directly bonded to the backside of the microelectronic structure. For example, as shown, the contact pads 426 of the second element or die 436 can be bonded directly to the exposed TSV structures 410 of the first element 434 without adhesive. The non-conductive regions of the second element or die 436 can be bonded directly to the dielectric layer 418 without adhesive. Additional elements can be bonded directly to the second element or die to form several elements in a stacked directly bonded structure. In some other applications, wafers processed by the methods described herein can be assembled or stacked and bonded directly to one another without an intervening adhesive layer.

[0033] FIG. 4I illustrates a via structure 410 formed using various disclosed embodiments. As illustrated, the microelectronic structure can include a bulk semiconductor portion 404 having a first / front side 406 and a second / back side 408 opposite the first side. In some embodiments, the second side 408 can include an active side having active circuitry formed in or on the second side. Additionally or alternatively, in some embodiments, the first side 406 can include an active side having active circuitry formed in or on the second side. In other embodiments, the first side 406 can include an inactive side without active circuitry. The via structure 410 can be disposed in an opening that extends at least partially, such as completely, through the bulk semiconductor portion 404 along a direction non-parallel to the first side. The via structure can include a first conductive via portion 402, a second conductive via portion 424, and a second barrier layer 422. The second barrier layer 422 includes a first portion 440 disposed between the first conductive via portion 402 and the second conductive via portion 424. The second barrier layer 422 can also include a second portion 442 disposed along a sidewall 411 of the second conductive via portion 402. The second conductive via portion 424 can extend from the second barrier layer 440 to at least the surface 408 of the substrate. As described above, the second conductive via portion 424 can have a different composition than the first conductive via portion 402.

[0034] Both the first conductive via portion 402 and the second conductive via portion 424 can be formed of, for example, copper, but can have different types and / or concentrations of alloying elements and impurities due to, for example, levelers, suppressors, accelerators, plating current density, and / or grain size and / or orientation used in the electroplating process. For example, the first conductive via portion 402 and / or the second conductive via portion 424 can have different ratios to non-copper elements such as metal alloying elements or impurities from plating bath additives. The first via portion 402 can have more non-copper elements than the second via portion 424. In some embodiments, the first via portion 402 can have alloying elements such as Be, Mn, Ni introduced through diffusion from the barrier layer 412 or through a seed layer. The second via portion 424 can be free of such non-copper elements or can have only trace levels of such impurities. The second via portion 424 has such non-copper elements, but in smaller amounts compared to the first via portion. In some configurations, alloying material may be provided that is captured through the barrier layer 412 and / or seed layer during plating to immobilize particles in the first via portion 402. Additionally, one or more organic additives may be provided during plating to improve filling during plating of the first via portion 402, and the additives may not be used in the second conductive via portion 424. In other embodiments, organic or other additives may be added to both the first via portion 402 and the second via portion 424, but the first via portion 402 may have a higher concentration of impurities left by the additives after plating. As described herein, impurities such as sulfur, oxygen, carbon, or nitrogen may be present in the TSV 410 at a higher concentration in the first via portion 402 compared to the second via portion 424. In some embodiments, non-copper elemental components, including impurities from alloying elements and additives, are higher in the first conductive via portion 402 than in the second conductive via portion 424. For example, in some embodiments, the second conductive via portion 424 can have at least 5% less, at least 10% less, at least 15% less, or at least 20% less non-copper elements than the first conductive via portion.The composition and grain structure of the first conductive portion 402 can be the result of processing selected to optimize filling of deep, high aspect ratio vias, and the composition and grain structure of the second conductive portion 424 can be selected to optimize subsequent direct hybrid bonding.

[0035] As shown in FIG. 4I, the dielectric layer 418 can be disposed on the bulk semiconductor portion 404, and the second conductive via portion 424 extends through the dielectric layer 418 such that its end is flush with the top surface of the dielectric layer 418 or is slightly recessed relative to the top surface of the dielectric layer 418, e.g., by less than about 40 nm, less than about 30 nm, less than about 20 nm, less than about 10 nm, or less than about 5 nm. The dielectric layer 418 can include a planarized dielectric bonding layer configured to bond directly to another element. The dielectric layer 418 can further include a dielectric barrier layer over the bulk semiconductor portion 404, and the planarized dielectric bonding layer is disposed over the dielectric barrier layer. The first liner barrier layer 412 can extend along the sidewalls 411 of the first conductive portion 402 and the second conductive portion 424. As shown, the second barrier layer 440 can include a second portion 442 that extends along the first barrier layer 412 between the first barrier layer 412 and the second conductive via portion 424. Thus, the overall barrier thickness is greater between the second conductive portion 424 and the bulk substrate 404 compared to the barrier thickness between the first conductor portion 402 and the bulk substrate 404, and can comprise two distinct barrier layers, which may or may not be of different composition.

[0036] 5A-5I illustrate a method of forming a microelectronic structure according to another embodiment. Unless otherwise noted, the embodiment of FIG. 5A-5I may be the same or substantially similar to the like components of FIG. 4A-4I. For example, the steps of FIG. 5A-5E may be the same as those described above in connection with FIG. 4A-4E. However, in FIG. 5F, a barrier layer may not be provided on the first conductive via portion 410. Rather, the second conductive via portion 424 may be plated directly on the first conductive via portion 410 without an intervening barrier layer or on only the intervening seed layer and on the bulk semiconductor portion 416. As described above, the structure of FIG. 5F may be annealed to facilitate copper grain growth that contributes to direct bonding.

[0037] In various embodiments, the embedded conductive material of the first conductive via portion 402 may be more constrained than the upper portion of the conductive material of the second conductive via portion 424. During annealing, the first conductive via portion 402 and the second conductive via portion 424 may form different metal textures and / or have different concentrations of non-copper elements, such as alloying elements and / or impurities from plating additives. For example, the first metal texture of the first conductive via portion 402 may be different from the second metal texture of the second conductive via portion 424. In various embodiments, including those disclosed in FIGS. 4A-4I and 5A-5I, the crystal structure of the second conductive via portion 424 may have grains oriented vertically along 111 crystal planes non-parallel, e.g., substantially perpendicular, to the bonding interface to enhance metal diffusion, e.g., copper diffusion, during direct bonding. The grains may have a geometric component that is substantially perpendicular to the bonding interface. In some embodiments, the first conductive via portion 402 and the second conductive via portion 424 can comprise different metals or different alloys. For example, in some embodiments, the first conductive via portion 402 can include a copper alloy and the second conductive via portion 424 can include substantially pure copper.

[0038] Figures 5G and 5H may be substantially similar to the steps described in Figures 4G and 4H. Figure 5I illustrates the microelectronic structure without the intervening barrier layer of Figure 4I. As shown in Figure 5I, the second conductive via portion 424 may be formed separately after the first conductive via portion 402. Unlike Figure 4I, there is no intervening barrier layer 440 between the first conductive via portion 402 and the second conductive via portion 424.

[0039] 6A-6H illustrate other embodiments that enable the formation of conductive vias 606 having a substantially uniform length while avoiding degradation of the vias 606, e.g., copper vias or other suitable conductive metal, and / or contamination of the semiconductor portion 604, e.g., silicon or other suitable semiconductor. Unless otherwise noted, the embodiments of FIGS. 6A-6H may be substantially similar to the components of FIGS. 4A-5I. For example, as described above and illustrated in FIG. 6A, a semiconductor element 604, e.g., a semiconductor wafer, may have a plurality of conductive vias 606 formed in the semiconductor portion 604, e.g., a silicon bulk or device portion. A front side of the bulk semiconductor is illustrated above and an opposing back side 612 of the bulk semiconductor is illustrated below. In various embodiments, the front side 610 may include an active side of the semiconductor element such that active circuitry may be formed on or near the front side 610. A dielectric liner and / or barrier layer 608 may line the opening in which the vias 606 are located. One or more front side dielectric layers 602 may be provided on the front side of the semiconductor portion 610. Although Figure 6A illustrates layer 602 diagrammatically as a single layer, it should be appreciated that layer 602 may comprise multiple layers or sublayers. The front side dielectric layer 602 may comprise any suitable type of dielectric including, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, diamond-like carbon (DLC), and any other suitable dielectric.

[0040] As discussed above, the depth of the opening at which the conductive via 606 material is deposited, e.g., electroplated, may vary, resulting in the formation of vias with non-uniform lengths. The lack of uniformity may result in difficulties in exposing the vias from the backside of the semiconductor element 612. In fact, the etching variation of the via opening 606 may be about 2-3 microns or more, so that there may be a 50% or more variation in the height of the TSV. In the process of Figures 4B and 5B, the semiconductor portion 604 is dry etched to expose the via 606, which may protrude at different heights above the semiconductor material 604. However, dry etching the semiconductor material 604, such as silicon, using an etchant such as SF6 may cause severe erosion of the copper via material, especially if the dielectric liner and / or liner barrier layer 608 are etched before the via 606 is properly exposed. Additionally, processing of conductive vias 606, for example by CMP, grinding, and other processing methods, can cause some of the conductive material of the vias, for example copper material, to contaminate semiconductor portion 604, for example silicon.

[0041] Thus, unlike the processes of Figures 4B and 5B, in Figure 6B the backside of the semiconductor portion 612 can be ground and polished, for example by CMP, to expose the via 606. The grinding and polishing process can uniformly expose the conductive via 606 and can accommodate the non-uniform length of the via 606 prior to grinding and polishing. For example, the backside of the semiconductor element 612 can be ground and polished until all of the via 606 is exposed on the backside of the planarized, ground and polished semiconductor element 614. Thus, in the illustrated embodiment, a grinding and polishing process can be used to expose the via 606 having a substantially uniform length. In other embodiments, such as those described above in connection with Figures 4A-5I, it may not be desirable to expose the via 606 using CMP since exposing the via 606, which includes copper, among other materials, to CMP can contaminate the semiconductor portion, e.g., silicon. In such embodiments, an etching process, e.g., an SF6 etch, can be used to initially expose the via 606, as described above.

[0042] Moving to FIG. 6C, the conductive via 606 can be etched from the backside 614 to form an etch recess in the conductive material, which may include copper. For example, the conductive material can be etched to a depth in the range of 0.25 microns to 3 microns, 0.5 microns to 3 microns, e.g., about 1 micron in one embodiment. In FIG. 6D, a first backside dielectric layer 616 can be provided, e.g., deposited, on the ground and polished backside 618 of the semiconductor portion and in the etch recess 620 formed in the via. As shown, the first backside dielectric layer 616 can extend into the recess against a dielectric liner and / or barrier layer disposed over the copper via and in the opening 620. In some embodiments, the first backside dielectric layer 616 can comprise multiple layers. For example, in the illustrated embodiment, the first backside dielectric layer 616 can include a first dielectric layer 617, e.g., a low temperature silicon nitride dielectric layer, disposed over the backside of the semiconductor portion and the via 606, and a second dielectric layer 619, e.g., a low temperature silicon oxide dielectric layer, covering the first dielectric layer 617. For example, in various embodiments, the first dielectric layer 617 and / or the second dielectric layer 619 can be formed using a low temperature chemical vapor deposition (CVD) process. However, in other embodiments, the first backside dielectric layer 616 can comprise only a single dielectric layer or more than two dielectric layers.

[0043] Moving to FIG. 6E, the backside 614 of the semiconductor element can be polished (e.g., by CMP) to remove a first portion of the first backside dielectric layer 616 overlying the semiconductor portion 604 to expose the semiconductor portion 604. A second portion of the first backside dielectric layer 620 can remain disposed in a recess over the conductive via 606, as shown in FIG. 6E. The remaining second portion of the first backside dielectric layer 620 can serve to protect the conductive via material during a subsequent dry etch of the semiconductor portion 604, as shown in FIG. 6F. Thus, the dry etch of FIG. 6F can uniformly expose the via 606, and the second portion of the first backside dielectric layer 620 can serve to protect the copper of the via during a dry etch using, for example, SF6. Additionally, at the stage of FIG. 6F, an etchant highly selective to silicon, for example, SF6, can be used over the first backside dielectric layer 620, which can include silicon oxide on the exposed surface. Thus, as shown after dry etching in Figure 6F, the via 606, the first portion of the first backside dielectric layer 620, and the dielectric liner / barrier layer 608 may protrude relative to the etched surface on the backside of the semiconductor portion 604. In various embodiments, the via may protrude by an amount in the range of 3 microns to 4 microns.

[0044] Turning to FIG. 6G, a second backside dielectric layer 624 can be provided, e.g., deposited, on the etched surface 622 of the semiconductor portion 604, along the exposed liner layer sidewalls of the via 606, on the ends of the liner layer 608, and on the second portion of the first backside dielectric layer 620. In some embodiments, the second backside dielectric layer 624 can comprise multiple layers. For example, in the illustrated embodiment, the second backside dielectric layer can include a first dielectric layer 625, e.g., a low-temperature silicon nitride dielectric layer, disposed on the etched surface 622 of the semiconductor portion 622 and the second portion of the first backside dielectric layer 620, and a second dielectric layer 627, e.g., a low-temperature silicon oxide dielectric layer, covering the first dielectric layer 625. However, in other embodiments, the second backside dielectric layer 624 can comprise only a single dielectric layer or more than two dielectric layers. The thickness of the second backside dielectric layer 624 can be any suitable thickness, e.g., in the range of 4 microns to 5 microns in various embodiments. Beneficially, the thickness of one or both of the first backside dielectric layer 625 and the second backside dielectric layer 627 can be selected to provide adequate support or stress compensation, particularly for a thinned die.

[0045] As shown in FIG. 6H, the backside of the semiconductor element can be polished (e.g., with CMP) to expose the via 606. In particular, polishing can remove the portion of the second backside dielectric layer 624 disposed over the first backside dielectric layer 616, the remaining second portion of the first backside dielectric layer 620, and can thin the portion of the second backside dielectric layer overlying the semiconductor portion. Thus, in the structure of FIG. 6H, the second backside dielectric layer 624 can be disposed over the etched surface 622 of the semiconductor portion 604 and around the via liner layer 608, e.g., a liner dielectric layer and / or a liner barrier layer. In various embodiments, polishing can also serve to recess the conductive material in the via 606 relative to the second backside dielectric layer 624 to prepare the backside of the semiconductor element for direct bonding. In various embodiments, polishing can recess the conductive material by an amount in the range of 1 nm to 20 nm, or in the range of 1 nm to 10 nm. As discussed above, the semiconductor element can be directly bonded and / or stacked to another element. Similarly, the front side dielectric layer 602 may be removed to expose the vias 606 on the front side, allowing one or more additional elements to be stacked and bonded directly to the front side of the semiconductor element.

[0046] Examples of direct bonding methods and direct bonding structures Various embodiments disclosed herein relate to direct bonded structures in which two elements can be directly bonded to one another without the aid of an adhesive. Two or more semiconductor elements, such as integrated device dies, wafers, and other semiconductor elements, can be stacked or bonded together to form a bonded structure. The conductive contact pads of one element can be electrically connected to corresponding conductive contact pads of another element. Any suitable number of elements can be stacked in a bonded structure.

[0047] In some embodiments, the elements are directly bonded to each other without adhesive. In various embodiments, the non-conductive or dielectric of the first element can be directly bonded to the corresponding non-conductive or dielectric field region of the second element without adhesive. The non-conductive material can be referred to as the non-conductive bonding region or bonding layer of the first element. In some embodiments, the non-conductive material of the first element can be directly bonded to the corresponding non-conductive material of the second element using dielectric-dielectric bonding techniques. For example, the dielectric-dielectric bond can be formed without adhesive using direct bonding techniques disclosed in at least U.S. Patent Nos. 9,564,414, 9,391,143, and 10,434,749, the entire contents of each of which are incorporated herein by reference in their entirety for all purposes.

[0048] In various embodiments, a hybrid direct bond can be formed without the aid of an adhesive. For example, the dielectric bonding surfaces can be polished to a high degree of smoothness. The bonding surfaces can be cleaned and exposed to a plasma and / or etchant to activate the surfaces. In some embodiments, the surfaces can be terminated with a chemical species after or during activation, e.g., during a plasma and / or etch step. Without being limited by theory, in some embodiments, an activation step can be performed to break chemical bonds at the bonding surfaces, and a termination step can provide additional chemical species at the bonding surfaces that improve the bond energy during direct bonding. In some embodiments, activation and termination treatments are provided in the same step, e.g., with a plasma or wet etchant to activate and terminate the surfaces. In other embodiments, the bonding surfaces can be terminated in a separate process to provide additional chemical species for direct bonding. In various embodiments, the termination chemical species can include nitrogen. Additionally, in some embodiments, the bonding surfaces can be exposed to fluorine. For example, there may be one or more fluorine peaks near the layers and / or bonding interface. That is, in some embodiments, in a direct bond structure, the bonding interface between the two dielectrics can include a much smoother interface with higher nitrogen content and / or fluorine peaks for the bonding interface. Additional examples of activation and / or termination processes can be found throughout U.S. Pat. Nos. 9,564,414, 9,391,143, and 10,434,749, the entire contents of each of which are incorporated herein in their entirety for any purpose.

[0049] In various embodiments, the conductive contact pads of a first component can be directly bonded to corresponding conductive contact pads of a second component. For example, hybrid bonding techniques can be used to provide conductor-conductor direct bonds along a bonding interface that includes the covalently directly bonded dielectric-dielectric surfaces prepared as described above. In various embodiments, conductor-conductor, e.g., contact pad-contact pad direct bonds and dielectric-dielectric hybrid bonds can be formed using direct bonding techniques disclosed at least in U.S. Patent Nos. 9,716,033 and 9,852,988, the entire contents of each of which are incorporated herein by reference in their entirety for all purposes.

[0050] For example, the dielectric bonding surfaces can be prepared and bonded directly to each other without the aid of an adhesive as described above. Conductive contact pads, which may be surrounded by non-conductive dielectric field regions, can also be bonded directly to each other without the aid of an adhesive. In some embodiments, each contact pad can be recessed below an outer surface (e.g., top surface) of the dielectric region or non-conductive bonding region, e.g., recessed by less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, e.g., recessed in the range of 2 nm to 20 nm or in the range of 4 nm to 10 nm. The non-conductive bonding regions can be bonded directly to each other without an adhesive at room temperature in some embodiments, after which the bonded structure can be annealed. In the annealed state, the contact pads can expand to contact each other and form a direct metal-metal bond. Advantageously, the use of hybrid bonding technology, such as direct bond interconnect, or DBI®, available from Xperi, Inc. of San Jose, Calif., can allow for high density pads connected throughout the direct bond interface, e.g., small or fine pitch for a regular array. In some embodiments, the pitch of the bond pads or conductive traces embedded in the bonding surface of one of the bonding elements can be less than 40 microns, or less than 10 microns, or even less than 2 microns. In some applications, it is desirable for the ratio of the bond pad pitch to one of the bond pad dimensions to be less than 5, or less than 3, and in some cases less than 2. In other applications, the width of the conductive traces embedded in the bonding surface of one of the bonding elements can range from 0.3 microns to 3 microns. In various embodiments, the contact pads and / or traces can include copper, although other metals may be suitable.

[0051] Thus, in a direct bonding process, a first element can be bonded directly to a second element without the aid of an adhesive. In some configurations, the first element can include a singulated element, such as a singulated integrated device die. In other configurations, the first element can include a carrier or substrate (e.g., a wafer) that includes a plurality, e.g., tens, hundreds, or more, of device regions that, when singulated, form a plurality of integrated device dies. Similarly, the second element can include a singulated element, such as a singulated integrated device die. In other configurations, the second element can include a carrier or substrate (e.g., a wafer).

[0052] As described herein, the first and second elements can be directly bonded to each other without an adhesive, which is distinct from a deposition process. In one application, the width of the first element in the bonded structure can be similar to the width of the second element. In some other embodiments, the width of the first element in the bonded structure can be distinct from the width of the second element. The width or area of ​​the larger element in the bonded structure can be at least 10% greater than the width or area of ​​the smaller element. Thus, the first and second elements can include non-deposited elements. Furthermore, directly bonded structures, unlike deposited layers, can include defective regions along the bond interface where nanovoids exist. The nanovoids can form due to activation of the bonded surfaces, e.g., exposure to a plasma. As discussed above, the bond interface can involve a concentration of material from the activation and / or final chemical treatment steps. For example, in embodiments utilizing nitrogen plasma for activation, a nitrogen peak can form at the bond interface. In embodiments utilizing oxygen plasma for activation, an oxygen peak can form at the bond interface. In some embodiments, the bond interface can include silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. As described herein, the direct bond can include a covalent bond that is stronger than a van der Waals bond. The tie layer can include a polished surface that has been planarized to a high degree of smoothness.

[0053] In some embodiments, a metal-metal bond is formed between the contact pads. In some embodiments, the contact pads include copper or a copper alloy. In various embodiments, the metal-metal bond between the contact pads can be bonded such that the copper grains grow into each other across the bond interface. In some embodiments, the copper can have grains oriented along 111 crystal planes to improve diffusion of the copper across the bond interface. The bond interface can extend substantially completely to at least a portion of the bonded contact pads, such that there are substantially no gaps between the non-conductive bond regions at or near the bonded contact pads. In some embodiments, a barrier layer can be provided under the contact pads, which can include, for example, copper. However, in other embodiments, there may be no barrier layer under the contact pads, for example, as described in U.S. Patent Application Publication No. 2019 / 0096741, which is incorporated by reference herein in its entirety for any purpose.

[0054] In one embodiment, a microelectronic structure is disclosed that may include a bulk semiconductor portion having a first side and a second side opposite the first side, and a via structure disposed in an opening extending at least partially through the bulk semiconductor portion along a direction non-parallel to the first side, the via structure comprising a first conductive via portion, a second conductive via portion, a first barrier layer extending along a sidewall of the first via conductive portion, and a second barrier layer including a first portion disposed between the first conductive via portion and the second conductive via portion, the second conductive via portion extending from the second barrier layer to at least the first side.

[0055] In some embodiments, the microelectronic structure includes a dielectric layer over the bulk semiconductor portion, the second conductive via portion extending through the dielectric layer such that an end of the second conductive via portion is flush with or recessed from an upper surface of the dielectric layer. In some embodiments, the dielectric layer comprises a planarized dielectric bonding layer configured to bond directly with another element. In some embodiments, the dielectric layer further comprises a dielectric barrier layer over the bulk semiconductor portion, the planarized dielectric bonding layer disposed on the dielectric barrier layer. In some embodiments, the second barrier layer includes a second portion extending along the first barrier layer between the first barrier layer and the second conductive via portion. In some embodiments, the first metallic texture of the first conductive via portion is different from the second metallic texture of the second conductive via portion. In some embodiments, the second metallic texture has grains oriented along 111 crystallographic planes that are non-parallel to the bonding interface. In some embodiments, the first and second conductive via portions comprise copper, the copper of the first conductive via portion having impurity material therein. In some embodiments, the first conductive via portion has a higher impurity concentration than the second conductive via portion. In some embodiments, the first conductive via portion further comprises one or more alloying elements including one or more of beryllium (Be), indium (In), gallium (Ga), manganese (Mn), and nickel (Ni). In some embodiments, the impurity material comprises one or more of sulfur, oxygen, carbon, or nitrogen. In some embodiments, the first and second conductive via portions comprise different metals or different alloys. In some embodiments, the second surface comprises an active surface including active integrated circuits formed in or on the second surface. In some embodiments, the microelectronic structure is directly bonded to another element without an intervening adhesive. In some embodiments, an end face of the second conductive via portion is directly bonded to a contact pad of the other element without an intervening adhesive. In some embodiments, the microelectronic element and the non-conductive bonding region of the other element are directly bonded to each other without an intervening adhesive.In some embodiments, the microelectronic structure can include a second via structure having a first conductive via portion, a second conductive via portion, a first barrier layer extending along a sidewall of the first conductive via portion, and a second barrier layer including a first portion disposed between the first conductive via portion and the second conductive via portion, wherein the second conductive via portion of the via structure extends along a length different from a length of the second conductive via portion of the second via structure.

[0056] In another embodiment, a microelectronic structure is disclosed that may include a bulk semiconductor portion having a first side and a second side opposite the first side, and a via structure disposed in an opening passing through the first side along a direction non-parallel to the first side and extending at least partially through the bulk semiconductor portion, the via structure comprising a first conductive via portion and a second conductive via portion disposed directly above and in contact with the first conductive via portion without an intervening barrier layer, the second conductive via portion being disposed between the first side and the first conductive via portion, the first conductive via portion having a different material composition than the second conductive via portion.

[0057] In some embodiments, the microelectronic structure comprises a barrier layer extending along sidewalls of the first and second conductive portions. In some embodiments, the microelectronic structure includes a dielectric layer over the bulk semiconductor portion, the second conductive via portion extending through the dielectric layer such that an end of the second conductive via portion is flush with or recessed from an upper surface of the dielectric layer. In some embodiments, the dielectric layer comprises a planarized dielectric bonding layer configured to bond directly to another element. In some embodiments, the dielectric layer further comprises a dielectric barrier layer over the bulk semiconductor portion, the planarized dielectric bonding layer disposed over the dielectric barrier layer. In some embodiments, the first metallic texture of the first conductive via portion is different from the second metallic texture of the second conductive via portion. In some embodiments, the second metallic texture has grains oriented along 111 crystal planes. In some embodiments, the first and second conductive via portions comprise copper, the copper of the first conductive via portion having impurity material therein. In some embodiments, the first conductive via portion further comprises one or more alloying elements including one or more of beryllium (Be), indium (In), gallium (Ga), manganese (Mn), and nickel (Ni). In some embodiments, the impurity material comprises one or more of sulfur, oxygen, carbon, or nitrogen. In some embodiments, the first and second conductive via portions comprise different metals or different alloys. In some embodiments, the microelectronic structure is directly bonded to another element without an adhesive. In some embodiments, an end face of the second conductive via portion is directly bonded to a contact pad of the other element without an adhesive. In some embodiments, the microelectronic element and the non-conductive bonding region of the other element are directly bonded to each other without an adhesive.

[0058] In another embodiment, a microelectronic structure is disclosed that may include a bulk semiconductor portion having a first side and a second side opposite the first side, and a via structure disposed in an opening passing through the first side along a direction non-parallel to the first side and extending at least partially through the bulk semiconductor portion, the via structure comprising a first conductive via portion and a second conductive via portion disposed directly above and in contact with the first conductive via portion without an intervening barrier layer, the second conductive via portion being disposed between the first side and the first conductive via portion, the first conductive via portion being formed prior to and separately from the second conductive via portion.

[0059] In some embodiments, the microelectronic structure comprises a barrier layer extending along sidewalls of the first and second conductive portions. In some embodiments, a first metallic texture of the first conductive via portion is different from a second metallic texture of the second conductive via portion. In some embodiments, the second metallic texture has grains oriented along 111 crystallographic planes. In some embodiments, the first metallic texture has a first proportion of 111 planes oriented within 30° of the vertical, and the second metallic texture has a second proportion of 111 planes oriented within 30° of the vertical, the second proportion being greater than the first portion. In some embodiments, the first and second conductive via portions comprise copper, and the copper of the first conductive via portion has an impurity material therein. In some embodiments, the first conductive via portion has a higher percentage of alloying elements compared to the second conductive via portion. In some embodiments, the microelectronic structure is directly bonded to another element without an intervening adhesive. In some embodiments, an end face of the second conductive via portion is directly bonded to a contact pad of another element without an intervening adhesive. In some embodiments, the non-conductive bonding region of the microelectronic element and another element are bonded directly without an intervening adhesive.

[0060] In another embodiment, a method of forming a microelectronic structure is disclosed that includes forming an opening at least partially through a substrate having a front surface and a back surface opposite the front surface, the opening extending through the front surface along a direction non-parallel to a second surface, providing a first conductive via portion from the front surface in the opening, removing material from the back surface to expose the first conductive via portion, and providing a fill structure in the opening from the back surface to the first conductive via portion after exposure.

[0061] In some embodiments, providing a fill structure includes providing a second conductive via portion in the opening from the back surface across the first conductive via portion. In some embodiments, the method includes recessing the first conductive via portion from the back surface after exposing. In some embodiments, the method includes providing a second barrier layer over the first conductive via portion after providing the first conductive via portion but before providing the second conductive via portion. In some embodiments, the method includes providing a first barrier layer along a sidewall of the first conductive via portion. In some embodiments, the method includes providing a first barrier layer before providing the first conductive via portion. In some embodiments, providing a second barrier layer includes providing a second barrier layer along the first barrier layer between the first barrier layer and the second conductive via portion. In some embodiments, the method includes providing a dielectric layer over the bulk semiconductor portion, the dielectric layer at least partially defining a back surface of the substrate, and the second conductive via portion extending through the dielectric layer such that an end of the second conductive via portion is flush with or recessed from the back surface of the substrate. In some embodiments, the method includes preparing the dielectric layer for direct bonding to another element. In some embodiments, the method includes providing a dielectric barrier layer over the bulk semiconductor portion, the dielectric bonding layer being disposed on the dielectric barrier layer. In some embodiments, the method includes directly bonding the dielectric layer to another element without an intervening adhesive. In some embodiments, the method includes directly bonding an end face of the second conductive via portion to a contact pad of the other element without an intervening adhesive. In some embodiments, providing the fill structure includes providing a dielectric layer in a recess over the first conductive via portion. In some embodiments, the method includes removing a portion of the substrate from the back surface such that the first conductive via portion protrudes from the back surface of the substrate, and removing the dielectric layer to expose the conductive via. In some embodiments, removing the portion of the substrate comprises etching a backside of the substrate. In some embodiments, the method can include providing a second backside dielectric layer over at least the etched backside of the substrate and the portion of the dielectric layer disposed in the recess.In some embodiments, the method can include removing at least a portion of the second backside dielectric layer overlying the portion of the dielectric layer disposed in the recess. In some embodiments, the method can include planarizing the second backside dielectric layer and recessing the first conductive via portion relative to the second backside dielectric layer.

[0062] In another embodiment, a method of forming a microelectronic structure is disclosed that includes forming an opening at least partially through a substrate having a front surface and a back surface opposite the front surface, the opening extending through the front surface along a direction non-parallel to the front surface, filling the opening with a first conductive via portion, removing material from the back surface to expose the first conductive via portion, and refilling a portion of the opening with a fill structure after exposing the first conductive portion.

[0063] In some embodiments, refilling a portion of the opening with a fill structure includes providing a second conductive via portion in the opening from the back surface over the first conductive via portion. In some embodiments, the method includes recessing the first conductive portion after exposing to define a portion of the opening. In some embodiments, the method includes depositing a second barrier layer over the first conductive via portion after the recessing and before refilling. In some embodiments, the method includes depositing the first barrier layer to line the opening before filling. In some embodiments, depositing the second barrier layer includes depositing the second barrier layer over the first barrier layer within the portion of the opening. In some embodiments, refilling a portion of the opening with a fill structure includes providing a dielectric layer in the recess over the first conductive via portion. In some embodiments, the method includes removing a portion of the substrate from the back surface such that the first conductive via portion protrudes from the back surface of the substrate, and removing the dielectric layer to expose the conductive via. In some embodiments, removing a portion of the substrate includes etching the back surface of the substrate. In some embodiments, the method can include providing a second backside dielectric layer over at least the etched backside of the substrate and the portion of the dielectric layer disposed in the recess. In some embodiments, the method can include removing at least the portion of the second backside dielectric layer overlying the dielectric layer disposed in the recess. In some embodiments, the method can include planarizing the second backside dielectric layer and recessing the first conductive via portion relative to the second backside dielectric layer.

[0064] In another embodiment, a bonded structure is disclosed. The bonded structure includes a first element having a first bonding surface, the first element having a third surface opposite the first bonding surface, a second element having a second bonding surface, and a via structure disposed in an opening extending at least partially through the first element from the first bonding surface along a direction non-parallel to the first bonding surface, the via structure including a first conductive via portion and a second conductive via portion in contact with each other, the second conductive via portion being at least partially embedded in a bonding material at the bonding surface of the first element, and the bonding material and the second conductive via portion being directly bonded to the bonding surface of the second element without an intervening adhesive. In some embodiments, the non-conductive bonding regions of the first and second elements are directly bonded without an intervening adhesive.

[0065] In another embodiment, a method of forming a microelectronic structure is disclosed that includes providing a substrate having an opening and a conductive via disposed in the opening, the conductive via extending partially through the substrate from a first side to a second side of the substrate, removing a portion of the substrate from the second side to expose the conductive via, removing a portion of the conductive via from the second side of the substrate to form a recess, providing a dielectric layer over the conductive via and in the recess, further removing a portion of the substrate from the second side such that the conductive via protrudes from the second side of the substrate, and removing the dielectric layer to expose the conductive via.

[0066] In some embodiments, removing the portion of the substrate includes at least one of grinding and polishing the second side. In some embodiments, at least one of grinding and polishing includes planarizing the substrate and the conductive via. In some embodiments, removing the portion of the conductive via includes etching the conductive via. In some embodiments, providing a dielectric layer includes providing a first backside dielectric layer over the backside of the substrate and in the recess. In some embodiments, providing the first backside dielectric layer includes providing a plurality of dielectric layers. In some embodiments, providing a plurality of dielectric layers includes providing a first silicon nitride layer over the backside of the substrate and over the conductive via, and providing a second silicon oxide layer over the first silicon nitride layer. In some embodiments, the method may include removing a portion of the first backside dielectric layer disposed over the backside of the substrate before further removing the portion of the substrate. In some embodiments, further removing the portion of the substrate includes etching the backside of the substrate. In some embodiments, the method can include providing a second backside dielectric layer over at least the etched backside of the substrate and the portion of the first backside dielectric layer disposed in the recess. In some embodiments, the method can include removing at least a portion of the second backside dielectric layer overlying the portion of the first backside dielectric layer disposed in the recess. In some embodiments, the method can include planarizing the second backside dielectric layer and recessing the conductive via relative to the second backside dielectric layer.

[0067] Unless the context clearly indicates otherwise, the words "comprises," "comprising," "including," "including," and the like, throughout this specification and claims, shall be construed in an inclusive sense, i.e., "including but not limited to," as opposed to a restrictive or inclusive sense. As used generally herein, the word "coupled" refers to two or more elements that are either directly connected or connected through one or more intermediate elements. As used generally herein, the word "connected" refers to two or more elements that are either directly connected or connected through one or more intermediate elements. Additionally, the words "herein," "above," "below," and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of this application. Furthermore, as used herein, when a first element is described as "on" or "on" a second element, the first element can be directly on or on the second element such that the first and second elements are in direct contact, or the first element can be indirectly on or on the second element such that there are one or more intervening elements between the first and second elements. Where relevant, words using the singular or plural in the above Detailed Description can also include the plural or singular, respectively. The word "or" in connection with a list of two or more items covers the following interpretations for that word: any of the items in the list, all of the items in the list, and all of any combinations of the items in the list.

[0068] Moreover, among other things, conditional language used herein, such as "can," "could," "might," "may," "eg," "for example," and "such as," are generally intended to convey that particular embodiments include certain features, elements, and / or conditions while other embodiments do not, unless specifically stated otherwise or understood otherwise within the context of use. Thus, such conditional language is generally not intended to imply that features, elements, and / or conditions are in any way required for one or more embodiments.

[0069] Although certain embodiments have been described, these embodiments are presented as examples only and are not intended to limit the scope of the disclosure. Indeed, the novel apparatus, method, and system described herein may be embodied in a variety of other forms, and various omissions, substitutions, and modifications may be made to the forms of the methods and systems described herein without departing from the spirit of the present disclosure. For example, although blocks are presented in a given arrangement, alternative embodiments may perform similar functions using different components and / or circuit topologies, and some blocks may be deleted, moved, added, subdivided, combined, and / or modified. Each of these may be implemented in a variety of different ways. Any suitable combination of the elements and operations of the various embodiments described above may be made to provide yet other embodiments. The claims and their equivalents are intended to cover such forms or modifications as fall within the scope and spirit of the present disclosure.

Claims

1. a bulk semiconductor portion having a first surface and a second surface opposite the first surface; a via structure disposed in an opening extending at least partially through the bulk semiconductor portion along a direction non-parallel to the first surface; the via structure comprises a first conductive via portion, a second conductive via portion, a first barrier layer extending along a sidewall of the first conductive via portion, and a second barrier layer including a first portion disposed between the first conductive via portion and the second conductive via portion, the second conductive via portion extending from the second barrier layer to at least the first surface; Microelectronic devices.

2. a dielectric layer on the bulk semiconductor portion; the second conductive via portion extends through the dielectric layer such that an end of the second conductive via portion is flush with or recessed from a top surface of the dielectric layer. The microelectronic device of claim 1 .

3. The microelectronic device of claim 2 , wherein the dielectric layer comprises a planarized dielectric bonding layer configured for direct bonding with another element.

4. The microelectronic device of claim 3 , wherein the dielectric layer further comprises a dielectric barrier layer over the bulk semiconductor portion, and the planarized dielectric bonding layer is disposed over the dielectric barrier layer.

5. 10. The microelectronic device of claim 1, wherein the second barrier layer includes a second portion that extends along the first barrier layer between the first barrier layer and the second conductive via portion.

6. 10. The microelectronic device of claim 1, wherein a first metal texture of the first conductive via portion is different from a second metal texture of the second conductive via portion.

7. The microelectronic device of claim 6 , wherein the second metal texture has grains oriented along 111 crystallographic planes non-parallel to the bond interface.

8. 10. The microelectronic device of claim 1, wherein the first conductive via portion and the second conductive via portion comprise copper, the copper of the first conductive via portion having an impurity material therein.

9. 9. The microelectronic device of claim 8, wherein the first conductive via portion has a higher impurity concentration than the second conductive via portion.

10. 9. The microelectronic device of claim 8, wherein the first conductive via portion further comprises one or more alloying elements including one or more of beryllium (Be), indium (In), gallium (Ga), manganese (Mn), and nickel (Ni).

11. The microelectronic device of claim 8 , wherein the impurity material comprises one or more of sulfur, oxygen, carbon, or nitrogen.

12. The microelectronic device of claim 1 , wherein the first conductive via portion and the second conductive via portion comprise different metals or different alloys.

13. The microelectronic device of claim 1 , wherein the second surface comprises an active surface including active integrated circuits formed in or on the second surface.

14. A bonded structure comprising: The microelectronic device of claim 1 , The microelectronic device is directly bonded to another element without an adhesive. Binding structure.

15. The bonded structure of claim 14 , wherein the non-conductive bonding regions of the microelectronic element and the other element are bonded directly without an intervening adhesive.

16. a bulk semiconductor portion having a first surface and a second surface opposite the first surface; a via structure disposed in an opening that extends through the first surface along a direction non-parallel to the first surface and at least partially through the bulk semiconductor portion; the via structure comprises a first conductive via portion and a second conductive via portion disposed directly above and in contact with the first conductive via portion without an intervening barrier layer, the second conductive via portion being disposed between the first surface and the first conductive via portion, the first conductive via portion having a different material composition than the second conductive via portion; Microelectronic devices.

17. 17. The microelectronic device of claim 16, further comprising a barrier layer extending along sidewalls of the first conductive portion and the second conductive portion.

18. a dielectric layer on the bulk semiconductor portion; the second conductive via portion extends through the dielectric layer such that an end of the second conductive via portion is flush with or recessed below a top surface of the dielectric layer.

17. The microelectronic device of claim 16.

19. 17. The microelectronic device of claim 16, wherein the first conductive via portion and the second conductive via portion comprise copper, the copper of the first conductive via portion having an impurity material therein.

20. 20. The microelectronic device of claim 19, wherein the first conductive via portion comprises one or more alloying elements including one or more of beryllium (Be), indium (In), gallium (Ga), manganese (Mn), and nickel (Ni).

21. 20. The microelectronic device of claim 19, wherein the impurity material comprises one or more of sulfur, oxygen, carbon, or nitrogen.

22. 17. The microelectronic device of claim 16, wherein the first conductive via portion and the second conductive via portion comprise different metals or different alloys.

23. A bonded structure comprising: The microelectronic device of claim 16, The microelectronic device is directly bonded to another element without an adhesive. Binding structure.

24. a bulk semiconductor portion having a first surface and a second surface opposite the first surface; a via structure disposed in an opening that extends through the first surface along a direction non-parallel to the first surface and at least partially through the bulk semiconductor portion; the via structure comprises a first conductive via portion and a second conductive via portion disposed directly above and in contact with the first conductive via portion without an intervening barrier layer, the second conductive via portion being disposed between the first surface and the first conductive via portion, the first conductive via portion being formed prior to and separately from the second conductive via portion; Microelectronic devices.

25. 25. The microelectronic device of claim 24, further comprising a barrier layer extending along sidewalls of the first conductive portion and the second conductive portion.

26. 25. The microelectronic device of claim 24, wherein a first metal texture of the first conductive via portion is different from a second metal texture of the second conductive via portion.

27. 27. The microelectronic device of claim 26, wherein the second metal texture has grains oriented along 111 crystallographic planes.

28. the first metal texture has a first ratio of 111 planes oriented within 30° of normal; the second metal texture has a second ratio of 111 planes oriented within 30° of normal, the second ratio being greater than the first ratio; 28. The microelectronic device of claim 27.

29. 25. The microelectronic device of claim 24, wherein the first conductive via portion and the second conductive via portion comprise copper, the copper of the first conductive via portion having an impurity material therein.

30. 25. The microelectronic device of claim 24, wherein the first conductive via portion has a higher percentage of alloying elements than the second conductive via portion.

31. A bonded structure comprising:

25. The microelectronic device of claim 24, The microelectronic device is directly bonded to another element without an adhesive. Binding structure.

32. 32. The bonded structure of claim 31, wherein an end face of the second conductive via portion is bonded directly to a contact pad of the other element without an intervening adhesive.

33. 32. The bonded structure of claim 31, wherein the non-conductive bonding regions of the microelectronic element and the other element are bonded directly without an intervening adhesive.

34. a first element having a first bonding surface and a third surface opposite the first bonding surface; a second element having a second bonding surface; a via structure disposed in an opening extending from the first bonding surface at least partially through the first element along a direction non-parallel to the first bonding surface; the via structure comprises a first conductive via portion and a second conductive via portion in contact with each other, the second conductive via portion being at least partially embedded in a bonding material at the bonding surface of the first component, and the bonding material and the second conductive via portion being directly bonded to the bonding surface of the second component without an intervening adhesive; Binding structure.

35. 35. The bonded structure of claim 34, wherein the non-conductive bond regions of the first and second elements are bonded directly without an intervening adhesive.

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