Structure with through-substrate vias and method of forming same - Patents.com

Abstract

A microelectronic structure is disclosed. The microelectronic structure can include a bulk semiconductor portion having a first side and a second side opposite the first side. The microelectronic structure can include a via structure extending at least partially through the bulk semiconductor portion along a direction non-parallel to the first side. The microelectronic structure can include a first dielectric barrier layer disposed on the first side of the bulk semiconductor portion and extending to the via structure. The microelectronic structure can include a second dielectric layer disposed on the first dielectric barrier layer and extending to the via structure.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Provisional Patent Application No. 63 / 131,226, entitled “STRUCTURE HAVING THROUGH-SUBSTRATE VIA AND METHOD OF FORMING SAME,” filed December 28, 2020, the entire contents of each of which are hereby incorporated by reference into this specification.

[0002] TECHNICAL FIELD The present invention relates to structures having through-substrate vias and methods of forming the same. [Background technology]

[0003] A semiconductor element, such as an integrated device die or chip, may be mounted or stacked on other elements. For example, a semiconductor element may be mounted on a carrier, such as a package substrate, an interposer, a reconfiguration wafer or element, or the like. As another example, a semiconductor element may be stacked on top of another semiconductor element, e.g., a first integrated device die may be stacked on top of a second integrated device die. In some arrangements, through-substrate vias (TSVs) may extend vertically through the thickness of the semiconductor element to convey electrical signals through the semiconductor element, e.g., from a first side of the semiconductor element to a second, opposing side of the semiconductor element. Summary of the Invention [Problem to be solved by the invention]

[0004] There is a continuing need for improved methods of forming TSVs.

[0005] Particular implementations will now be described with reference to the following drawings, which are provided by way of example and not limitation. [Brief description of the drawings]

[0006] [Figure 1A] 1A-1D illustrate steps in a process for forming through-substrate vias in a microelectronic structure. [Figure 1B] 1A-1C illustrate different stages of a process for forming through-substrate vias in a microelectronic structure. [Figure 1C] 1A-1C illustrate different stages of a process for forming through-substrate vias in a microelectronic structure. [Figure 1D] 1A-1C illustrate different stages of a process for forming through-substrate vias in a microelectronic structure. [Figure 1E] 1A-1C illustrate different stages of a process for forming through-substrate vias in a microelectronic structure. [Figure 1F] 1A-1C illustrate different stages of a process for forming through-substrate vias in a microelectronic structure. [Diagram 2] FIG. 1 shows the height of vias formed at different locations on a 12-inch wafer. [Diagram 3] 13 is a post-TSV exposure wafer distribution map for an 8-inch wafer showing vias that are too long and vias that are too short. [Figure 4] 1 is a distribution map showing thickness variation on an 8-inch wafer after TSV planarization. [Diagram 5] 1 is a schematic cross-sectional side view of a structure having surface non-uniformities. [Figure 6] 1 is a schematic cross-sectional side view of a microelectronic structure according to an embodiment. [Figure 7A] 1A-1D illustrate steps in a method of forming a microelectronic structure according to an embodiment. [Figure 7B] 1A-1C illustrate different stages in a method of forming a microelectronic structure. [Figure 7C] 1A-1C illustrate different stages in a method of forming a microelectronic structure. [Figure 7D] 1A-1C illustrate different stages in a method of forming a microelectronic structure. [Figure 7E] 1A-1C illustrate different stages in a method of forming a microelectronic structure. [Figure 7F] 1A-1C illustrate different stages in a method of forming a microelectronic structure. [Figure 7G]FIG. 1 illustrates a microelectronic structure bonded to a carrier. [Figure 7H] FIG. 13 shows a microelectronic structure bonded to a carrier after a removal process. [Figure 7I] FIG. 13 shows a microelectronic structure bonded to a carrier after another removal step. [Figure 7J] FIG. 1 illustrates a microelectronic structure bonded to a wafer. [Figure 7K] FIG. 1 shows a microelectronic structure bonded to a wafer after removal of the carrier. [Figure 7L] FIG. 13 shows a singulation element attached to another element. [Figure 8A] FIG. 2 is a cross-sectional view of a via structure. [Figure 8B] 1 is a cross-sectional view of a via structure according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] 1A-1F illustrate various conventional processing steps for forming TSVs in a microelectronic structure 1. In FIGS. 1A-1F, the microelectronic structure comprises a portion of a semiconductor wafer (bulk semiconductor portion 12). The via structure shown comprises a via-middle structure, where active circuitry 10 (e.g., transistors or other active circuit elements) can be formed on or within an active surface 12a of the bulk semiconductor portion 12, one or more insulating layers 14 can be formed on the active circuitry 10, and an opening 16 for a through-substrate via (TSV) can be formed through the one or more insulating layers 14 and the portion of the bulk semiconductor portion 12 (see FIG. 1A). A via structure 18 can be provided in the opening 16, as shown in FIGS. 1B and 1C. A conductive overburden resulting from electroplating of the via structure 18 in FIG. 1B can be removed (e.g., polished off) in FIG. 1C. A conductive pad 20 can be provided on the one or more insulating layers 14 and electrically connected to the via structure 18, as shown in FIG. 1D. The conductive pads 20 can be configured to electrically connect to another element. For example, the conductive pads 20 can be front-side interconnect contacts (FIC) or front-side redistribution layers (FRDL). The contact pads 20 of the microelectronic structure 1 (first element) can be directly bonded to the contact pads of the second element. In some arrangements, a metallization layer 110, e.g., back-end-of-line (BEOL) or redistribution layer (RDL), can be provided on or within one or more insulating layers 14. The metallization layers 22 can be connected by conductive interconnects 24. As described herein, in various embodiments, the microelectronic structure 1 (e.g., first element) can be directly bonded to the second element without an intervening adhesive. The insulating bonding layer of the first element can be directly bonded to the insulating bonding layer of the second element. Any suitable number of elements can be stacked and directly bonded to each other.

[0008] As shown in FIGS. 1E and 1F, the front side of the microelectronic structure 1 can be attached to a carrier 26 with an adhesive 28. The carrier 26 can include a temporary handle wafer used to support the microelectronic structure 1 during processing such as backgrinding. In some embodiments, the adhesive 28 can include an organic adhesive and can be sensitive to high temperatures. Thus, using an adhesive 28 to attach the carrier 26 to the microelectronic structure 1 can limit the temperatures that can be applied during processing. However, in other embodiments, the carrier 26 can be directly bonded to the front side of the microelectronic structure 1 without the adhesive 28. The back side (e.g., first side) of the semiconductor portion 12 can be ground or worn away to expose the via structure 18 while the front side (e.g., second side) is attached to the carrier 26. As shown in FIG. 1F, a dielectric layer 29 can be deposited on the backside of the semiconductor portion 12. A backside metallization layer 31, e.g., a redistribution layer (RDL), can be provided on the dielectric layer 29 and can be configured to electrically connect to the via structure 18.

[0009] Conventional via formation processes have several problems that lead to non-uniform via lengths. For example, the etching process used to form the openings for the vias is non-uniform throughout the substrate (e.g., wafer), especially for the high aspect ratio openings used for the vias, which results in different via opening depths. In fact, as shown in FIG. 2, for a 12-inch wafer, the etching process used to form the via openings may have a non-uniformity of about 7 microns. Some areas of the wafer will have a high etch depth, while some areas of the wafer will have a low etch depth, and other areas of the wafer will have an etch depth between the low and high etch depths. Thus, with the conductive material (e.g., copper) filling the openings, the varying depths of the etched via openings lead to different via structure lengths. The selectively etched TSV cavities can be lined with a dielectric layer, and the surface of the dielectric liner can be coated with a suitable barrier or adhesion layer before filling the cavity with a conductive layer, e.g., copper.

[0010] FIG. 3 is a wafer distribution map after TSV exposure for an 8-inch wafer showing vias that are too long and vias that are too short. Vias that are too long are vias with lengths that exceed a desired or predetermined length range, and vias that are too short are vias that have lengths that are shorter than an optimized desired or predetermined length range. FIG. 4 is a distribution map showing thickness variation (4 μm variation) on an 8-inch wafer after TSV planarization. As shown in FIGS. 3 and 4, different via lengths can result in significant loss of yield. For example, dies with TSVs that are too short to be fully exposed or useful, and dies with TSVs that are too long to be fractured during TSV planarization cannot be used. For example, some dies in a wafer may have TSVs that are too short to be practically usable within the die. Other vias may be too long or break during grinding or polishing, leaving the vias buried in the semiconductor portion of the device and making it relatively difficult to form backside interconnects to pads or RDLs. Additionally, in some processes, non-uniform TSVs can result from incomplete or non-uniform plating procedures. For example, such processes may be able to etch via openings uniformly, but may not be able to fill the via openings uniformly with plating processes through high aspect ratio openings. This process variation reduces the number of usable dies. Thus, non-uniform TSV lengths may result from a variety of different processing methods.

[0011] FIG. 4 illustrates thickness variations for an 8 inch wafer that can be measured after TSV planarization. As can be seen, the thickness of the wafer can vary by 4 microns. Some areas of the wafer can have a thickness up to 58.09 microns, while other areas of the wafer can have a thickness of 56.09 microns, while other areas of the wafer can have a lower thickness of about 54.67 microns. Wafer thickness variations can also cause some TSVs to be invalid, resulting in a reduced level of process control.

[0012] As discussed above, the length of the TSVs may vary considerably across the wafer after grinding the backside of the semiconductor portion to expose the TSVs, for example, due to non-uniformities in die thickness and etch non-uniformities in the TSV openings. Thus, when the backside of the bulk semiconductor portion is ground or otherwise thinned, the exposed vias may protrude from the backside of the thinned semiconductor portion by various lengths, and some vias may remain unexposed and buried in the semiconductor portion as discussed above. To reduce the non-uniform length of the TSVs while preventing damage to the protruding TSVs, one or more backside dielectric layers may be provided on the backside of the semiconductor portion and on the TSVs. Although it is possible to use solder bumps with some variation in the height (protrusion from the backside) of the TSVs, this variation results in a lack of planarity, making stacking difficult. Some stacking techniques (such as direct hybrid bonding) are particularly sensitive to local variations.

[0013] In conventional TSV processing of the type shown in Figures 1A-1F, one or more backside dielectric layers 29 may be provided on the backside of semiconductor portion 12 and on the exposed TSVs. For example, in some processes, a barrier layer (e.g., silicon nitride, silicon oxynitride, silicon carbonitride, diamond-like carbon, etc.) may be deposited on the backside of semiconductor portion 12, on the sidewalls of the exposed TSVs, and on the exposed edge surfaces of the exposed TSVs. A second dielectric layer (such as silicon oxide or any other suitable dielectric) may be deposited on the dielectric barrier layer, including an upper surface of the barrier layer, the portions of the barrier layer extending along the sidewalls of the exposed TSVs, and the portions of the barrier layer disposed along the edge surfaces of the exposed TSVs. After depositing the backside dielectric layer, the vias and portions of the dielectric layer may be polished (or otherwise removed) to planarize the vias and reduce non-uniformities.

[0014] As an example, FIG. 8A shows a via structure 18 formed using a conventional via-middle or via-last process after grinding or polishing the via structure 18, a portion of the dielectric layer 30 (e.g., a low-temperature oxide (LTO) layer), and a portion of the dielectric barrier layer 32 (e.g., a copper (Cu) diffusion barrier layer). For example, an LTO deposition process may involve depositing the dielectric layer using a silane, such as tetraethoxysilane (TEOS), at a temperature of 200° C. or lower. In contrast to LTO, a high-temperature oxide (HTO) layer can be subjected to a higher and more stable temperature. The HTO layer may be deposited at a temperature higher than 200° C. In some embodiments, the HTO layer may be deposited at a temperature of 250° C. or higher. In some embodiments, the HTO layer may be deposited at a temperature of 300° C. or higher, or 350° C. or higher. For example, the HTO may include TEOS at 400° C. In Figure 8A, the dielectric barrier layer 32 extends over the thinned backside of the bulk semiconductor portion and along the sidewall 34 of the conductive via structure 18 (e.g., along the sidewall of the dielectric liner 36). The dielectric layer 30 is disposed over the dielectric barrier layer 32 (e.g., a SixOyNz layer) and terminates at the portion of the dielectric barrier layer 32 that extends along the sidewall 34 of the via structure 18. In the structure shown in Figure 8A, the dielectric layer 30 does not contact the dielectric liner 36 of the via structure 18.

[0015] In conventional processes, the dielectric layer 30 (and the dielectric barrier layer 32) can be deposited using a suitable deposition process (e.g., a plasma enhanced chemical vapor deposition (PE-CVD) process). However, as mentioned above, the adhesive used to attach the temporary carrier to the microelectronic device is typically still in place during the dielectric deposition and is typically sensitive to high temperature processing. Thus, in conventional processes, the backside dielectric layer (which in some arrangements may comprise a barrier material such as silicon nitride and a low-k material such as silicon oxide) is generally deposited at low temperatures, e.g., below 200° C. or below 300° C. Deposition of the dielectric layer 30 at low temperatures can result in the formation of a low-quality low-temperature silicon oxide layer. Indeed, subsequent annealing of the device, such as at 200° C. or higher, can cause voids to grow rapidly in the low-temperature oxide (LTO) layer. A low-quality dielectric layer can be problematic in some applications, such as direct bonding processes. The presence of voids can render the dielectric surface unsuitable for subsequent processing, such as direct bonding. Additionally, wafer or die thickness non-uniformities can accumulate at the bonding surface and can be exacerbated by depositing additional layers on the elements, as shown in Figure 5. When multiple elements are stacked (e.g., directly bonded), thickness non-uniformities can adversely affect planarity and reduce bonding effectiveness in wafer-to-wafer (W2W) and die-to-wafer (D2W) applications, as well as adversely affect the transfer or stacking of additional device layers.

[0016] Various embodiments disclosed herein address challenges in via formation and direct bonding due to etch non-uniformity of via openings, thickness non-uniformity of the die or wafer, and quality of the backside dielectric layer. FIG. 6 is a schematic cross-sectional side view of a microelectronic structure 2 according to an embodiment. As shown in FIG. 6, the backside dielectric layer can be formed before the TSVs are exposed as a buried layer 50 between two elements 44, 48 (e.g., two semiconductor elements). The disclosed embodiments can provide better TSV depth uniformity and better wafer or die thickness uniformity. Furthermore, rather than depositing a lower quality LTO as the backside dielectric layer, the disclosed embodiments allow for the use of a high quality high temperature oxide (HTO) layer as the backside dielectric layer because the backside dielectric layer is formed well before the low temperature adhesive is used for carrier attachment. The use of HTO as the dielectric layer can be beneficially used in applications where an LTO layer would be undesirable, such as direct bonding applications.

[0017] 7A-7L illustrate a method of forming a microelectronic structure 3 (see FIGS. 7I-7K) according to various embodiments. FIG. 7A is a schematic cross-sectional side view of a first element 40 and a second element 42 coupled to the first element 40. A first dielectric barrier layer 46 and a second dielectric layer 50 may be interposed between the bulk semiconductor portion 44 of the first element 40 and the bulk semiconductor portion 48 of the second element 42. As shown in FIG. 7A, a semiconductor substrate (the bulk semiconductor portion 44 of the first element 40 or the bulk semiconductor portion 48 of the second element 42) is provided with a buried dielectric layer (the second dielectric layer 50). For example, any of a number of silicon-on-insulator (SOI) processes may be used to provide the buried dielectric layer (the second dielectric layer 50). In one example, the first element 40 (e.g., a first semiconductor element) can be directly bonded to the second element 42 (e.g., a second semiconductor element) along a bonding interface 52 without an intervening adhesive. In some embodiments, the bonding interface 52 can be within the second dielectric layer 50. As described in more detail below, the non-conductive bonding surfaces of the first and second elements 40, 42 can be prepared for direct bonding. For example, the non-conductive or dielectric bonding surfaces can be polished to a high degree of smoothness and activated and / or terminated with an appropriate chemical species. The first and second elements can be brought into direct contact and the non-conductive bonding surfaces of the first and second elements can form a direct covalent bond without an intervening adhesive.

[0018] One or more buried dielectric layers may be provided along the bonding interface between the first and second elements. As shown in FIG. 7A, a first dielectric barrier layer 46 may be provided (e.g., deposited) on the bulk semiconductor portion 48 of the second element 42. The first dielectric barrier layer 46 may comprise any suitable barrier layer that prevents or reduces the diffusion of a conductive material (e.g., copper), such as silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, diamond-like carbon, etc. A second dielectric layer 50 may be provided on the bulk semiconductor portion 48 of the second element 42 between the first dielectric barrier layer 46 and the bulk semiconductor portion 48 of the second element 42. The second dielectric layer 50 may comprise a high temperature silicon oxide (HTO) material in some embodiments. In some embodiments, the second dielectric layer 50 may comprise silicon oxynitride (SiON) or silicon oxycarbonitride (SiOCN). For example, the second dielectric layer 50 may comprise SiO2, SiNx, or SiCNO.

[0019] In some embodiments, the second dielectric layer 50 may be provided over the second element 42, and the second dielectric layer 50 of the second element 42 may be directly bonded to the bulk semiconductor portion 44 of the first element 40. In such embodiments, the bonding interface 52 may be located along the interface between the buried dielectric layer (the second dielectric layer 50) and the first element 40. In other embodiments, the second dielectric layer 50 may be provided over the first element 40, and the second dielectric layer 50 of the first element 40 may be directly bonded to the bulk semiconductor portion 48 of the second element 42. In such embodiments, the bonding interface may be located along the interface between the buried dielectric layer (the second dielectric layer 50) and the second element 42. In yet another embodiment, a first portion of the buried dielectric layer (second dielectric layer 50) can be provided on the first element 40, a second portion of the buried dielectric layer (second dielectric layer 50) can be provided on the second element 42, and the first and second portions of the buried dielectric layer (second dielectric layer 50) can be directly bonded to each other. In such an embodiment, the bond interface can extend between the first and second portions within the buried dielectric layer (second dielectric layer 50). The buried dielectric layer (second dielectric layer 50) can have a thickness in the range of 0.5 microns to 3 microns or in the range of 1 micron to 2 microns. The thickness of the buried dielectric layer can be selected to balance stress with the back-end-of-line (BEOL) designed to be formed on the opposite side of the first element.

[0020] Since the buried dielectric layer (second dielectric layer 50) is formed prior to attachment to the carrier, a high temperature deposition process can be used to deposit the dielectric layer on the first and / or second elements 40, 42. For example, in some embodiments, the buried dielectric layer (second dielectric layer 50) can comprise a high temperature oxide (HTO) dielectric layer, which has superior quality compared to LTO layers used in the prior art. The HTO layer can have fewer defects when heated to temperatures above 300° C. or above 350° C. In some embodiments, the HTO layer can have a relatively low level of hydrogen in the form of SiH bonds or OH bonds compared to the LTO layer. For example, the LTO layer can have a hydrogen content of at least 5% or at least 10%. Additionally, the LTO layer is porous and can absorb moisture. The presence of hydrogen and / or moisture can diffuse to the bond interface 52 during annealing, causing voids to form in the LTO layer. Additionally, the density of LTO films is generally low, so polishing and etching rates can be about 10% to 20% higher than HTO layers. Advantageously, the HTO layer used in the disclosed embodiments can have a higher density than the LTO layer, and therefore can accommodate faster polishing and etching rates. Additionally, the HTO layer can have a hydrogen content of less than 5%, less than 3%, or less than 1% in various embodiments. In various embodiments, HTO can be chemically stable at temperatures, for example, greater than 200° C., greater than 300° C., or greater than 400° C. In other embodiments, the dielectric film (e.g., second dielectric layer 50) can be formed at low temperatures and / or with a unique deposition process to obtain high quality dielectrics, for example, with Si, O, N, C. The flexibility of depositing the dielectric layer first allows the composition of the film to be engineered to improve performance for various factors, including diffusion resistance to metals, etch selectivity, and thermal conductivity. This dielectric layer (second dielectric layer 50) can be engineered to optimize properties for a particular application. In some embodiments, the second dielectric layer 50 can be deposited or grown. The second dielectric layer 50 can include, for example, a thermal oxide produced by annealing.In some embodiments, the second dielectric layer 50 may include a relatively thin native oxide, such as a native oxide having a thickness of about 1 nm. The surface may be treated to grow a thicker oxide, for example, to form a thermal oxide having a thickness in the range of 300 nm to 500 nm. For example, the surface may be annealed in the presence of oxygen and / or moisture.

[0021] 7B, the bulk semiconductor portion 44 of the first element 40 may be thinned (e.g., ground and / or polished) to form a thinned bulk semiconductor portion 44'. A surface of the thinned bulk semiconductor portion 44' may function as the active front surface 54 of the device (first element 40) in some embodiments. Active integrated circuits (not shown), such as transistors, may be formed in or on the active surface 54, and BEOL metallization layers may be formed thereon, either before or after the TSV formation shown in Figures 7C-7E.

[0022] In FIG. 7C, a multi-step etch recipe can be used to controllably form an opening 56 for a via structure 57 (see FIGS. 7E-7L). In a first step, a first plasma etch chemistry can be used to etch the bulk semiconductor portion 44' of the first element 40 (which in some embodiments can include silicon). The first etch chemistry can have a high etch selectivity (e.g., about 60:1) between the bulk semiconductor portion 44' (e.g., silicon) and the buried dielectric layer (e.g., the first dielectric barrier 46 layer, which can comprise silicon oxide). For example, in some embodiments, a Bosch etch procedure (e.g., SF6 can be used as an etchant) can be used to selectively and controllably form the opening 56 through the silicon bulk semiconductor portion 44'. Due to the Bosch etch step, a first sidewall of the bulk semiconductor portion adjacent to the via structure 57 in the first element can have a first artifact indicative of the first etch step. For example, the first etching step (e.g., a Bosch etch) may leave a first artifact having a ridge 58 that leaves a surface roughness profile along a first sidewall of the bulk semiconductor portion. Due to the high etch selectivity, the buried dielectric layer (e.g., the first dielectric barrier layer 46) may act as an etch stop layer that prevents over-etching into the second dielectric layer 50 and / or the underlying bulk semiconductor portion 48 of the second element 42.

[0023] The second etching step may include a second etching chemistry (e.g., a dielectric etch chemistry) that etches through the first dielectric barrier layer 46, the second dielectric layer 50 (e.g., silicon oxide) and into a portion of the bulk semiconductor portion 48 (e.g., silicon) of the second semiconductor element 42. Thus, the second etching chemistry may etch a controllable amount through the first and second dielectric layers 46, 50 and into the bulk semiconductor portion 48 of the second element 42. The second etching may form a second artifact along the sidewalls of the first dielectric layer 46, the second dielectric barrier layer 50, and the bulk semiconductor portion 48 of the second element 42. The second artifact may be visually different from the first artifact upon inspection using optical imaging techniques. For example, the surface roughness of the second artifact may be different from the surface roughness of the first artifact. In an embodiment, the surface roughness of the second artifact may be less (eg, smoother) than the surface roughness of the first artifact.

[0024] The second etch may etch to a depth of less than 5 microns, less than 3 microns, or less than 1 micron, e.g., in the range of 0.05 microns to 5 microns, 0.05 microns to 3 microns, 0.05 microns to 1 micron, 0.05 microns to 0.5 microns, 0.25 microns to 5 microns, 0.25 microns to 3 microns, 0.25 microns to 1 micron, or 0.5 microns to 1 micron. Because the via etch proceeds only through the reduced (thinned) thickness of the first element 40, the etch uniformity may be controlled to less than about 1 micron because the selective etch is performed through the remaining semiconductor bulk thickness and stops on the buried dielectric (first dielectric layer 46 and second dielectric barrier) and because the etch depth into the bulk semiconductor portion 48 of the second element 42 is very small compared to the total thickness of the die.

[0025] 7D, a dielectric liner layer 54 of a via structure 57 may be provided in an opening 56 along the sidewalls of the bulk semiconductor portion 44' of the first element 40, along the sidewalls of the first dielectric barrier layer 46, and along the sidewalls of the bulk semiconductor portion 48 of the second element 42. The dielectric liner layer 54 may include any suitable dielectric, such as silicon oxide, silicon nitride. A barrier layer (not shown) may be provided on the dielectric liner layer 54 in the opening 56. The barrier layer may comprise a conductive barrier layer in some embodiments to prevent or reduce migration of conductive materials (such as copper). The conductive barrier layer of the via structure 57 may comprise, for example, a metal or metal nitride, such as titanium nitride, tantalum nitride, or any other suitable barrier layer.

[0026] 7E, a seed layer (not shown) may be provided in the opening 56 over the semiconductor portion of the first element 40 and over the barrier layer in the opening 56. A conductive via 62 (e.g., copper) may be provided (e.g., electroplated) in the opening 56 over the seed layer (not shown). The seed layer and / or adhesion layer may be removed from the top surface of the silicon bulk semiconductor portion 44' of the first element 40 by polishing (e.g., chemical mechanical polishing, or CMP) and / or wet etching techniques. The via formation process may also have low thickness variations, e.g., thickness variations of less than 1 micron.

[0027] In FIG. 7F, one or more dielectric and metallization layers, such as back-end-of-line (BEOL) layers 64, may be provided on the top (front) surface of the bulk semiconductor portion 44' of the first element 40 to connect to the conductive vias 62. The BEOL layers 64 may include traces for routing electrical signals from the TSVs 62 to other portions of the microelectronic structure. In other embodiments, the BEOL layers 64 may be provided prior to the TSV etch of FIG. 7C. In FIG. 7G, a temporary carrier 66 may be attached to the BEOL structure with a temporary adhesive 68. As discussed above, the temporary adhesive 68 may be sensitive to high temperature processing. Since the buried dielectric layers (first dielectric layer 46 and second dielectric barrier layer 50) are already provided, there is no need for a subsequent high temperature backside dielectric deposition, and therefore the temporary adhesive 68 may be used to attach the carrier 66. In other embodiments, the carrier 66 may be directly bonded to the BEOL 64 without an adhesive.

[0028] Moving to FIG. 7H, the second element 42 (including its bulk semiconductor portion 48) on the backside of the structure can be removed to expose the via structure 57. In some embodiments, the second element 42 can be back-ground and / or polished to expose the TSV structure 57. With the semiconductor portion 48 of the second element 42 removed, the TSV structure 57 protrudes from the second dielectric layer 50. Because the via opening 56 is formed with a highly uniform depth (e.g., the etching depth into the bulk semiconductor portion 48 of the second element 42 can be highly controlled due to the selectivity of most of the depth stopping on the buried dielectric 50 and due to its low aspect ratio), the length of the via structure 57 extending across the second dielectric layer 50 can have a high uniformity. As shown in FIG. 7H, compared to the conventional process, the disclosed embodiment is much simpler and less expensive than the typical backside TSV exposure process because it does not require the use of additional dry etching and does not require the use of a low temperature nitride (LTN) barrier layer and an LTO dielectric layer.

[0029] In FIG. 7I, the backside of the microelectronic structure 3 can be polished planar to remove the protruding portions of the TSV structures 57. For example, the backside can be polished to a high smoothness using a CMP process. In some embodiments, the CMP chemistry can be selected to recess the TSV structures 57 below the HTO dielectric surface to facilitate subsequent direct hybrid bonding. A higher quality HTO dielectric layer may be suitable for direct bonding to another element or structure. For example, as shown in FIG. 7J and described below, the microelectronic structure 3 can be directly bonded to another device wafer 4 or a stack of multiple wafers in a wafer-to-wafer (W2W) process. In FIG. 7K, the temporary carrier 66 and adhesive 68 can be removed. The microelectronic structure 3 can be integrated into a larger electronic system, or additional layers of elements can be integrally formed or stacked (e.g., bonded) on the microelectronic structure 3. The bonded wafers can be singulated into multiple bonded elements 5 or dies.

[0030] FIG. 7L illustrates an alternative die-to-wafer (D2W) process in which microelectronic structures in wafer form can be prepared on a dicing frame 70 for dicing or singulation. Diced elements 6 can be prepared for direct bonding and picked and placed onto another element, such as a wafer 4, an integrated device die, or a stack of multiple wafers. Diced elements 6 (e.g., diced microelectronic structures) can be directly bonded to other elements without adhesives, as described in more detail below. In some embodiments, diced elements 6 can comprise one of elements 5.

[0031] As discussed above, FIG. 8A illustrates a via structure 18 formed using conventional backside TSV exposure, barrier deposition, and LTO deposition processes. FIG. 8B illustrates a via structure 57 formed in accordance with embodiments disclosed herein. As shown in FIG. 8B, the bulk semiconductor portion 44' of the first element 40 can have a first side 72 and a second side 74 opposite the first side 72. The via structure 57 can extend at least partially through (e.g., through) the bulk semiconductor portion 44' along a direction non-parallel to the first side 72. The first dielectric barrier layer 46 can be disposed on the first side 72 of the bulk semiconductor portion 44' and extend to the via structure 57. In the illustrated embodiment, the first dielectric barrier layer 46 is disposed directly over and in contact with the bulk semiconductor portion 44', although in other embodiments, additional layers can be interposed between the first dielectric barrier layer 46 and the bulk semiconductor portion 44'. The second dielectric layer 50 may be disposed on the first dielectric barrier layer 46 and may extend to the via structure 57. In the illustrated embodiment, the second dielectric layer 50 is disposed directly on and in contact with the first dielectric barrier layer 46, although in other embodiments, additional layers may be interposed between the first dielectric barrier layer 46 and the second dielectric layer 50.

[0032] The via structure 57 may include a conductive via 62 and a dielectric liner 54 disposed about the conductive via 62. The second dielectric layer 50 may extend to (e.g., contact) the dielectric liner 54 without an intervening barrier. The via structure 57 may include a second barrier layer 78 extending along the conductive via between the metal (e.g., copper) of the conductive via 62 and the dielectric liner 54. As discussed above, the second dielectric layer 50 may include a high temperature silicon oxide (HTO) layer. Additionally, as discussed above, a first sidewall 80 of the bulk semiconductor portion 44' adjacent the via structure 57 may have a first artifact indicative of a first etching step, and a second sidewall 82 of the dielectric layer 50 adjacent the via structure 57 may have a second artifact indicative of a second etching step different from the first etching step. The first and second artifacts have different surface roughness profiles along the first and second sidewalls 80, 82. For example, the first artifact includes ridges indicative of a Bosch etch process. In some embodiments, the first artifact includes ridges and the second artifact does not include ridges. In some other embodiments, the first artifact includes ridges having a first surface roughness and the second artifact includes ridges having a second surface roughness that is different (e.g., smoother) than the first surface roughness. Such artifacts are visible via a scanning electron microscope (SEM) image of the final product.

[0033] As mentioned above, the first dielectric barrier layer 46 may comprise silicon nitride, although other types of dielectrics may be used as mentioned above. The via structure 57 may extend through the bulk semiconductor portion 44', the first dielectric barrier layer 46, and the second dielectric layer 50. The via structure 57 may have an end face 84 that is flush with or slightly recessed relative to a surface 86 of the second dielectric layer 50 opposite the bulk semiconductor portion 44'. In various embodiments, it may be advantageous to slightly recess the end face 84 of the conductive via structure 57 relative to the surface 86 of the dielectric layer 50 to accommodate thermal expansion during annealing and to form a direct metallurgical bond. Alternatively, the via structure 57, and in particular the conductive via 62 (e.g., copper) of the via structure 57, may be recessed by less than 30 nm, less than 20 nm, and in particular less than 15 nm or less than 10 nm from the second dielectric (HTO) surface to facilitate subsequent direct hybrid bonding. An end surface 84 of the via structure 57 and a surface 86 of the dielectric layer 50 may include planarized surfaces.

[0034] Examples of direct bonding methods and direct bonding structures Various embodiments disclosed herein relate to direct bonded structures in which two elements can be directly bonded to one another without the aid of an adhesive. Two or more semiconductor elements (such as integrated device dies, wafers, etc.) can be stacked or bonded together to form a bonded structure. The conductive contact pads of one element can be electrically connected to corresponding conductive contact pads of another element. Any suitable number of elements can be stacked in a bonded structure.

[0035] In some embodiments, the elements are directly bonded to each other without adhesive. In various embodiments, the non-conductive or dielectric of the first element can be directly bonded to the corresponding non-conductive or dielectric field region of the second element without adhesive. The non-conductive material can be referred to as the non-conductive bonding region or bonding layer of the first element. In some embodiments, the non-conductive material of the first element can be directly bonded to the corresponding non-conductive material of the second element using dielectric-dielectric bonding techniques. For example, the dielectric-dielectric bond can be formed without adhesive using direct bonding techniques disclosed at least in U.S. Pat. Nos. 9,564,414, 9,391,143, and 10,434,749, the entire contents of each of which are incorporated herein by reference in their entirety for all purposes.

[0036] In various embodiments, a direct hybrid bond can be formed without the aid of an adhesive. For example, the dielectric bonding surfaces can be polished to a high degree of smoothness. The bonding surfaces can be cleaned and exposed to a plasma and / or an etchant to activate the surfaces. In some embodiments, the surfaces can be terminated with chemical species after or during activation (e.g., during a plasma and / or etch step). Without being limited by theory, in some embodiments, an activation step can be performed to break chemical bonds at the bonding surfaces, and a termination step can provide additional chemical species at the bonding surfaces that improve the bond energy during direct bonding. In some embodiments, activation and termination treatments are provided in the same step, e.g., with a plasma or wet etchant to activate and terminate the surfaces. In other embodiments, the bonding surfaces can be terminated in a separate process to provide additional chemical species for direct bonding. In various embodiments, the termination chemical species can include nitrogen. Additionally, in some embodiments, the bonding surfaces can be exposed to fluorine. For example, there may be one or more fluorine peaks near the layers and / or bonding interface. That is, in a direct bond structure, the bonding interface between the two dielectrics can include a very smooth interface with higher nitrogen content and / or fluorine peaks for the bonding interface. Additional examples of activation and / or termination processes can be found throughout U.S. Pat. Nos. 9,564,414, 9,391,143, and 10,434,749, the entire contents of each of which are incorporated herein in their entirety for any purpose.

[0037] In various embodiments, the conductive contact pads of a first component can be directly bonded to corresponding conductive contact pads of a second component. For example, hybrid bonding techniques can be used to provide conductor-conductor direct bonds along a bonding interface that includes a covalently directly bonded dielectric-dielectric surface prepared as described above. In various embodiments, conductor-conductor (e.g., contact pad-contact pad) direct bonds and dielectric-dielectric hybrid bonds can be formed using direct bonding techniques disclosed at least in U.S. Patent Nos. 9,716,033 and 9,852,988, the entire contents of each of which are incorporated herein by reference in their entirety for all purposes.

[0038] For example, the dielectric bonding surfaces can be prepared and bonded directly to each other without an adhesive as described above. The conductive contact pads (which may be surrounded by non-conductive dielectric field regions) can also be bonded directly to each other without an adhesive. In some embodiments, each contact pad can be recessed below the outer surface (e.g., top surface) of the dielectric field or non-conductive bonding region, for example, recessed by less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, for example, recessed in the range of 2 nm to 20 nm or in the range of 4 nm to 10 nm. The non-conductive bonding regions can be bonded directly to each other without an adhesive at room temperature in some embodiments, after which the bonded structure can be annealed. In the annealed state, the contact pads can expand and contact each other to form a metal-metal direct bond. Advantageously, the use of direct bond interconnect, or DBI®, a technology commercially available from Xperi, Inc. of San Jose, Calif., can allow for high density pads (e.g., small or fine pitch for a regular array) connected throughout the direct bond interface. In some embodiments, the pitch of the bond pads or conductive traces embedded in the bonding surface of one of the bonding elements may be less than 40 microns, or less than 10 microns, or even less than 2 microns. In some applications, it is desirable for the ratio of the bond pad pitch to one of the bond pad dimensions to be less than 5, or less than 3, and in some cases less than 2. In other applications, the width of the conductive traces embedded in the bonding surface of one of the bonding elements may range from 0.3 microns to 3 microns. In various embodiments, the contact pads and / or traces may comprise copper, although other metals may be suitable.

[0039] That is, in a direct bonding process, a first element can be bonded directly to a second element without an intervening adhesive. In some configurations, the first element can include a singulated element, such as a singulated integrated device die. In other arrangements, the first element can comprise a carrier or substrate (e.g., a wafer) that includes a plurality (e.g., tens, hundreds, or more) of device regions that, when singulated, form a plurality of integrated device dies. Similarly, the second element can include a singulated element, such as a singulated integrated device die. In another configuration, the second element can include a carrier or substrate (e.g., a wafer).

[0040] As described herein, the first and second elements can be directly bonded to each other without adhesive, which is distinct from a deposition process. In one application, the width of the first element in the bonded structure is similar to the width of the second element. In some other embodiments, the width of the first element in the bonded structure is distinct from the width of the second element. Similarly, the width or area of ​​the larger element in the bonded structure can be at least 10% greater than the width or area of ​​the smaller element. Thus, the first and second elements can include non-deposited elements. Furthermore, directly bonded structures, unlike deposited layers, can include defective regions along the bonded interface where nanovoids exist. The nanovoids can form due to activation (e.g., exposure to plasma) of the bonded surfaces. As discussed above, the bonded interface can involve a concentration of material from the activation and / or final chemical treatment steps. For example, in embodiments utilizing nitrogen plasma for activation, a nitrogen peak can form at the bonded interface. In embodiments utilizing oxygen plasma for activation, an oxygen peak can form at the bonded interface. In some embodiments, the bonded interface can comprise silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. As described herein, the direct bond can include a covalent bond that is stronger than a van der Waals bond. The tie layer can include a polished surface that has been planarized to a high degree of smoothness.

[0041] In some embodiments, a metal-metal bond is formed between the contact pads. In some embodiments, the contact pads include copper or a copper alloy. In various embodiments, the metal-metal bond between the contact pads can be bonded such that the copper grains grow into one another across the bond interface. In some embodiments, the copper can have grains oriented along 111 crystal planes to improve diffusion of the copper across the bond interface. The bond interface can extend substantially completely to at least a portion of the bonded contact pads, such that there are substantially no gaps between the non-conductive bond regions at or near the bonded contact pads. In some embodiments, a barrier layer can be provided under the contact pads (which may include, for example, copper). However, in other embodiments, there may be no barrier layer under the contact pads, for example, as described in U.S. Patent Application Publication No. 2019 / 0096741, which is incorporated by reference herein in its entirety for any purpose.

[0042] In one embodiment, a microelectronic structure is disclosed. The microelectronic structure can include a bulk semiconductor portion having a first side and a second side opposite the first side. The microelectronic structure can include a via structure extending at least partially through the bulk semiconductor portion along a direction non-parallel to the first side. The microelectronic structure can include a first dielectric barrier layer disposed on the first side of the bulk semiconductor portion and extending to the via structure. The microelectronic structure can include a second dielectric layer disposed on the first dielectric barrier layer and extending to the via structure.

[0043] In some embodiments, the via structure comprises a conductive via and a dielectric liner disposed about the conductive via, with the second dielectric layer extending to the dielectric liner. In some embodiments, the via structure comprises a second barrier layer extending along the conductive via between the conductive via and the dielectric liner. In some embodiments, the second dielectric layer comprises a dielectric layer comprising silicon oxynitride. In some embodiments, the second dielectric layer comprises a high temperature silicon oxide layer. In some embodiments, the second dielectric layer comprises a dielectric layer including silicon oxycarbonitride. In some embodiments, a first sidewall of the bulk semiconductor portion adjacent the via structure has a first artifact indicative of a first etching step, and a second sidewall of the dielectric layer adjacent the via structure has a second artifact indicative of a second etching step different from the first etching step. In some embodiments, the first and second artifacts have different surface roughness profiles along the first and second sidewalls. In some embodiments, the first artifact includes a ridge indicative of a Bosch etching step. In some embodiments, the first dielectric barrier layer comprises silicon nitride. In some embodiments, the via structure extends through the bulk semiconductor portion, the first dielectric barrier layer, and the second dielectric layer. In some embodiments, the via structure has an end face that is recessed relative to a face of the second dielectric layer opposite the bulk semiconductor portion. In some embodiments, the end face of the via structure and the face of the dielectric layer include planarized surfaces. In some embodiments, the second dielectric layer and the via structure are directly bonded to another element without an intervening adhesive along a bonding interface. In some embodiments, the second face of the bulk semiconductor portion comprises an active face including active circuitry, one or more insulating layers over the active face, and a back-end-of-line layer over the one or more insulating layers.

[0044] In another embodiment, a microelectronic structure is disclosed that may include a bulk semiconductor portion having a first side and a second side opposite the first side, a dielectric layer disposed on the first side of the bulk semiconductor portion, and a via structure extending at least partially through the bulk semiconductor portion and through the dielectric layer along a direction non-parallel to the first side, wherein a first sidewall of the bulk semiconductor portion adjacent the via structure has a first artifact indicative of a first etching step and a second sidewall of the dielectric layer adjacent the via structure has a second artifact indicative of a second etching step different from the first etching step.

[0045] In some embodiments, a barrier dielectric layer is interposed between the dielectric layer and the bulk semiconductor portion, but not between the dielectric layer and the via structure. In some embodiments, the via structure comprises a conductive via and a dielectric liner disposed about the conductive via, with the second dielectric layer extending to the dielectric liner. In some embodiments, the via structure comprises a second barrier layer extending along the conductive via between the conductive via and the dielectric liner. In some embodiments, the second dielectric layer comprises a high temperature silicon oxide layer. In some embodiments, the first and second artifacts have different surface roughness profiles along the first and second sidewalls. In some embodiments, the first artifact includes a ridge indicative of a Bosch etch process. In some embodiments, the second dielectric layer and the via structure are directly bonded to another element without an adhesive along the bonding interface.

[0046] In another embodiment, a microelectronic structure is disclosed. The microelectronic structure can include a bulk semiconductor portion having a first side and a second side opposite the first side, a via structure extending at least partially through the bulk semiconductor portion along a direction non-parallel to the first side, and a dielectric layer disposed on the bulk semiconductor portion and extending to the via structure, the dielectric layer comprising a high temperature silicon oxide layer. In some embodiments, a barrier dielectric layer is interposed between the dielectric layer and the bulk semiconductor portion, but not between the dielectric layer and the via structure.

[0047] In another embodiment, a microelectronic structure is disclosed. The microelectronic structure can include a bulk semiconductor portion having a first side and a second side opposite the first side, a via structure extending at least partially through the bulk semiconductor portion along a direction non-parallel to the first side, and a dielectric layer disposed on the bulk semiconductor portion and extending to the via structure, the dielectric layer comprising a silicon oxynitride layer. In some embodiments, a barrier dielectric layer is interposed between the dielectric layer and the bulk semiconductor portion, but not between the dielectric layer and the via structure.

[0048] In another embodiment, a method of forming a microelectronic structure is disclosed that can include preparing a semiconductor structure with a buried dielectric layer, etching an opening through a front side of the semiconductor structure stopping on the buried dielectric layer, continuing to etch the opening through the buried dielectric layer, depositing a conductive material in the opening to form a conductive via, and exposing the conductive via from a back side of the semiconductor structure.

[0049] In some embodiments, preparing the semiconductor structure includes preparing a bulk semiconductor portion and a base substrate, with a buried dielectric layer disposed between the bulk semiconductor portion and the base substrate. In some embodiments, continuing to etch the opening includes etching partially into the base substrate. In some embodiments, exposing the conductive via includes removing the base substrate. In some embodiments, the method includes forming at least a portion of a buried dielectric layer on one of the bulk semiconductor portion and the base substrate. In some embodiments, forming at least a portion of the buried dielectric layer includes forming a first barrier dielectric layer and a second dielectric layer on the first barrier dielectric layer. In some embodiments, the method includes forming a first portion of the buried layer on the bulk semiconductor portion and a second portion of the buried dielectric layer on the base substrate. In some embodiments, the method includes annealing the microelectronic structure after depositing the conductive material. In some embodiments, the exposing includes polishing a backside of the semiconductor structure. In some embodiments, the method includes directly bonding the polished backside of the semiconductor structure to another element without an intervening adhesive. In some embodiments, directly bonding comprises directly bonding the polished surface of the buried dielectric layer and the conductive vias to another element without an intervening adhesive along the bonding interface.

[0050] Unless the context clearly indicates otherwise, the words "comprises," "comprising," "including," "including," and the like, throughout this specification and claims, shall be construed in an inclusive sense, i.e., "including but not limited to," as opposed to a restrictive or inclusive sense. As used generally herein, the word "coupled" refers to two or more elements that are either directly connected or connected through one or more intermediate elements. As used generally herein, the word "connected" refers to two or more elements that are either directly connected or connected through one or more intermediate elements. Additionally, the words "herein," "above," "below," and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of this application. Furthermore, as used herein, when a first element is described as "on" or "on" a second element, the first element can be directly on or on the second element such that the first and second elements are in direct contact, or the first element can be indirectly on or on the second element such that there are one or more intervening elements between the first and second elements. Where relevant, words using the singular or plural in the above Detailed Description can also include the plural or singular, respectively. The word "or" in connection with a list of two or more items covers the following interpretations for that word: any of the items in the list, all of the items in the list, and all of any combinations of the items in the list.

[0051] In one aspect, a microelectronic structure is disclosed. The microelectronic structure can include a bulk semiconductor portion having a first side and a second side opposite the first side. The microelectronic structure can include a via structure extending at least partially through the bulk semiconductor portion along a direction non-parallel to the first side. The microelectronic structure can include a first dielectric barrier layer disposed on the first side of the bulk semiconductor portion and extending to the via structure. The microelectronic structure can include a second dielectric layer disposed on the first dielectric barrier layer and extending to the via structure.

[0052] In one embodiment, the via structure includes a conductive via and a dielectric liner disposed about the conductive via. The second dielectric layer can extend to the dielectric liner.

[0053] The via structure can include a second barrier layer extending along the conductive via between the conductive via and the dielectric liner.

[0054] In one embodiment, the second dielectric layer comprises a dielectric layer including silicon oxynitride.

[0055] In one embodiment, the second dielectric layer comprises a high temperature silicon oxide layer.

[0056] In one embodiment, the second dielectric layer comprises a dielectric layer including silicon oxycarbonitride.

[0057] In one embodiment, a first sidewall of the bulk semiconductor portion adjacent the via structure has a first artifact indicative of a first etching step, and a second sidewall of the dielectric layer adjacent the via structure has a second artifact indicative of a second etching step different from the first etching step.

[0058] The first and second artifacts may have different surface roughness profiles along the first and second sidewalls.

[0059] The first artifacts include ridges indicative of the Bosch etch process.

[0060] In one embodiment, the first dielectric barrier layer comprises silicon nitride.

[0061] In one embodiment, the via structure extends through the bulk semiconductor portion, the first dielectric barrier layer, and the second dielectric layer.

[0062] In one embodiment, the via structure has an end face that is recessed relative to a surface of the second dielectric layer opposite the bulk semiconductor portion.

[0063] The end surface of the via structure and the surface of the dielectric layer may include planarized surfaces.

[0064] In one embodiment, the second dielectric layer and the via structure are directly bonded to another element without an intervening adhesive along the bonding interface.

[0065] In one embodiment, the second side of the bulk semiconductor portion includes an active side including active circuitry, one or more insulating layers on the active side, and one or more back-end-of-line layers on the one or more insulating layers.

[0066] In one aspect, a microelectronic structure is disclosed. The microelectronic structure may include a bulk semiconductor portion having a first side and a second side opposite the first side, a dielectric layer disposed on the first side of the bulk semiconductor portion, and a via structure extending at least partially through the bulk semiconductor portion and through the dielectric layer along a direction non-parallel to the first side. A first sidewall of the bulk semiconductor portion adjacent to the via structure has a first artifact indicative of a first etching step. A second sidewall of the dielectric layer adjacent to the via structure has a second artifact indicative of a second etching step different from the first etching step.

[0067] In one embodiment, the barrier dielectric layer is interposed between the dielectric layer and the bulk semiconductor portion, but not between the dielectric layer and the via structure.

[0068] The via structure can include a conductive via and a dielectric liner disposed about the conductive via. The second dielectric layer can extend to the dielectric liner.

[0069] The via structure can include a second barrier layer extending along the conductive via between the conductive via and the dielectric liner.

[0070] In one embodiment, the second dielectric layer comprises a high temperature silicon oxide layer.

[0071] In one embodiment, the first and second artifacts have different surface roughness profiles along the first and second sidewalls.

[0072] The first artifacts may include ridges indicative of a Bosch etch process.

[0073] In one embodiment, the second dielectric layer and the via structure are directly bonded to another element without an intervening adhesive along the bonding interface.

[0074] In one aspect, a microelectronic structure is disclosed. The microelectronic structure can include a bulk semiconductor portion having a first side and a second side opposite the first side, a via structure extending at least partially through the bulk semiconductor portion along a direction non-parallel to the first side, and a dielectric layer disposed on the bulk semiconductor portion and extending to the via structure. The dielectric layer comprises a high temperature silicon oxide layer.

[0075] In one embodiment, the barrier dielectric layer is interposed between the dielectric layer and the bulk semiconductor portion, but not between the dielectric layer and the via structure.

[0076] In one aspect, a microelectronic structure is disclosed. The microelectronic structure can include a bulk semiconductor portion having a first side and a second side opposite the first side, a via structure extending at least partially through the bulk semiconductor portion along a direction non-parallel to the first side, and a dielectric layer disposed on the bulk semiconductor portion and extending to the via structure. The dielectric layer includes a silicon oxynitride layer.

[0077] In one embodiment, the barrier dielectric layer is interposed between the dielectric layer and the bulk semiconductor portion, but not between the dielectric layer and the via structure.

[0078] In one aspect, a method of forming a microelectronic structure is disclosed. The method can include preparing a semiconductor structure with a buried dielectric layer. The method can include etching an opening through a front side of the semiconductor structure stopping on the buried dielectric layer. The method can include continuing to etch the opening through the buried dielectric layer. The method can include depositing a conductive material into the opening to form a conductive via. The method can include exposing the conductive via from a back side of the semiconductor structure.

[0079] In one embodiment, the semiconductor structure includes multiple buried dielectric layers including the buried dielectric layer.

[0080] In one embodiment, preparing the semiconductor structure includes preparing a bulk semiconductor portion and a base substrate, the buried dielectric layer may be disposed between the bulk semiconductor portion and the base substrate.

[0081] Continuing to etch the opening can include etching partially into the base substrate.

[0082] Exposing the conductive vias can include removing the base substrate.

[0083] The method may further include forming at least a portion of a buried dielectric layer over one of the bulk semiconductor portion and the base substrate.

[0084] Forming at least a portion of the buried dielectric layer may include forming a first barrier dielectric layer and a second dielectric layer on the first barrier dielectric layer.

[0085] The method may further include forming a first portion of the buried layer over the bulk semiconductor portion and a second portion of the buried dielectric layer over the base substrate.

[0086] In one embodiment, the method further comprises annealing the microelectronic structure after depositing the conductive material.

[0087] In one embodiment, the exposing step includes polishing the backside of the semiconductor structure.

[0088] The method may further include directly bonding the polished backside of the semiconductor structure to another element without an intervening adhesive.

[0089] Directly bonding can include directly bonding the polished surface of the buried dielectric layer and the conductive vias to another element without an intervening adhesive along the bonding interface.

[0090] Moreover, among other things, conditional language used herein, such as "can," "could," "might," "may," "eg," "for example," and "such as," are generally intended to convey that a particular embodiment includes certain features, elements, and / or conditions while another embodiment does not, unless specifically stated otherwise or understood otherwise within the context of use. Thus, such conditional language is generally not intended to imply that the features, elements, and / or conditions are in any way required for one or more embodiments.

[0091] Although certain embodiments have been described, these embodiments are presented as examples only and are not intended to limit the scope of the disclosure. Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms, and various omissions, substitutions, and modifications may be made to the forms of the methods and systems described herein without departing from the spirit of the present disclosure. For example, although blocks are presented in a given arrangement, alternative embodiments may perform similar functions using different components and / or circuit topologies, and some blocks may be deleted, moved, added, subdivided, combined, and / or modified. Each of these may be implemented in a variety of different ways. Any suitable combination of the elements and operations of the various embodiments described above may be made to provide further embodiments. The claims and their equivalents are intended to cover such forms or modifications as fall within the scope and spirit of the present disclosure.

Claims

1. a bulk semiconductor portion having a first surface and a second surface opposite the first surface; a via structure extending at least partially through the bulk semiconductor portion along a direction non-parallel to the first surface; a first dielectric barrier layer disposed on the first surface of the bulk semiconductor portion and extending to the via structure; a second dielectric layer disposed on the first dielectric barrier layer and extending to the via structure; A microelectronic structure comprising:

2. The microelectronic structure of claim 1 , wherein the via structure comprises a conductive via and a dielectric liner disposed about the conductive via, the second dielectric layer extending to the dielectric liner.

3. The microelectronic structure of claim 2 , wherein the via structure comprises a second barrier layer extending along the conductive via between the conductive via and the dielectric liner.

4. The microelectronic structure of claim 1 , wherein the second dielectric layer comprises a dielectric layer comprising silicon oxynitride.

5. The microelectronic structure of claim 1 , wherein the second dielectric layer comprises a high temperature silicon oxide layer.

6. The microelectronic structure of claim 1 , wherein the second dielectric layer comprises a dielectric layer comprising silicon oxycarbonitride.

7. 2. The microelectronic structure of claim 1, wherein a first sidewall of the bulk semiconductor portion adjacent the via structure has a first artifact indicative of a first etching step, and a second sidewall of the dielectric layer adjacent the via structure has a second artifact indicative of a second etching step different from the first etching step.

8. The microelectronic structure of claim 7 , wherein the first artifact and the second artifact have different surface roughness profiles along the first sidewall and the second sidewall.

9. The microelectronic structure of claim 8 , wherein the first artifact comprises a ridge indicative of a Bosch etch process.

10. The microelectronic structure of claim 1 , wherein the first dielectric barrier layer comprises silicon nitride.

11. 2. The microelectronic structure of claim 1 , wherein the via structure has an end face that is recessed relative to a surface of the second dielectric layer opposite the bulk semiconductor portion, and the end face of the via structure and the surface of the dielectric layer comprise planarized surfaces.

12. The microelectronic structure of claim 1 , wherein the second dielectric layer and the via structure are directly bonded to another element without an intervening adhesive along a bonding interface.

13. 2. The microelectronic structure of claim 1, wherein the second surface of the bulk semiconductor portion comprises an active surface including active circuitry, one or more insulating layers on the active surface, and one or more back-end-of-the-line layers on the one or more insulating layers.

14. a bulk semiconductor portion having a first surface and a second surface opposite the first surface; a dielectric layer disposed on the first surface of the bulk semiconductor portion; a via structure extending at least partially through the bulk semiconductor portion along a direction non-parallel to the first surface and through the dielectric layer, a first sidewall of the bulk semiconductor portion adjacent the via structure having a first artifact indicative of a first etching step and a second sidewall of the dielectric layer adjacent the via structure having a second artifact indicative of a second etching step different from the first etching step; A microelectronic structure comprising:

15. 15. The microelectronic structure of claim 14, wherein a barrier dielectric layer is interposed between the dielectric layer and the bulk semiconductor portion but not between the dielectric layer and the via structure, the via structure comprising a conductive via and a dielectric liner disposed about the conductive via, the dielectric layer extending to the dielectric liner.

16. The microelectronic structure of claim 14 , wherein the second dielectric layer comprises a high temperature silicon oxide layer.

17. The microelectronic structure of claim 14 , wherein the first artifact and the second artifact have different surface roughness profiles along the first sidewall and the second sidewall.

18. 15. The microelectronic structure of claim 14, wherein the dielectric layer and the via structure are bonded directly to another element without an intervening adhesive along a bonding interface.

19. a bulk semiconductor portion having a first surface and a second surface opposite the first surface; a via structure extending at least partially through the bulk semiconductor portion along a direction non-parallel to the first surface; a dielectric layer disposed over the bulk semiconductor portion and extending to the via structure, the dielectric layer comprising a high temperature silicon oxide layer; A microelectronic structure comprising:

20. 20. The microelectronic structure of claim 19, wherein a barrier dielectric layer is interposed between said dielectric layer and said bulk semiconductor portion, but not between said dielectric layer and said via structure.

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