Thermally Conductive Wafer Layer

Abstract

In the described example, a semiconductor wafer (502) with a thermally conductive surface layer includes a bulk semiconductor layer having a first surface and a second surface, circuitry on the first surface, a metal layer (510) attached to the first surface or the second surface, and a graphene layer (512) attached to the metal layer (510). The first surface faces the second surface. The metal layer (510) includes a transition metal.

Description

[Technical field]

[0001] This application relates generally to semiconductor device manufacturing, and more particularly to thermally conductive coatings for substrates.

[0002] FIG. 1 (PRIOR ART) illustrates an exemplary side view of a drop-on-demand inkjet printer 100 used to deposit material onto a surface 102. As shown in FIG. 1, the drop-on-demand inkjet printer 100 includes a nozzle 104 that emits material provided by a reservoir 106. An actuator (not shown) causes the material to be emitted from the nozzle 104 as droplets 108 at specific times (on demand). The droplets 108 impact the surface 102 and are attracted by the surface 102 to form liquid beads 110 held together by surface tension. The timing of the droplets 108 ejected from the nozzle 104 as the inkjet printer 100 moves over the surface 102 determines the resulting pattern.

[0003] Other inkjet printer configurations are available. A continuous inkjet printer (not shown) can also be used to selectively deposit material on a surface. A continuous inkjet printer uses a catcher located between the inkjet nozzle and the substrate surface. The catcher captures the droplet material and returns it to a reservoir when the catcher is not deflected, allowing the inkjet printer to continuously form and emit droplets. Deposition occurs when the catcher is deflected away from an intermediate position between the inkjet nozzle and the substrate surface, allowing the droplets to reach the substrate surface. Various types of droplet deposition actuation can be used, including thermal actuation, piezoelectric actuation, electromechanical actuation, and acoustic actuation inkjet printers.

[0004] Inkjet printers used for the deposition of semiconductor device related materials, and the noun "inkjet printer" as used herein, are not inkjet printers used in business offices to print legible documents and images. Instead, "inkjet printer" as used herein refers to a mechanism for depositing a volume of liquid ("ink"), usually on the picoliter or femtoliter scale, onto a semiconductor wafer surface, where the so-called "ink" contains semiconductor processing related nanoparticles and / or precursors in a suspension. The ink is then dried and the suspended material can be annealed to form permanent structures on the surface on which the ink was deposited. Unwanted components of the liquid and other delivery medium used to deliver the nanoparticles from the inkjet printer 100 to the surface 102 are volatilized from the wafer surface by an annealing or sintering process, leaving the desired deposited material on the surface 102. The business office inkjet printer and the inkjet printer as described herein have some similar features, hence the term "inkjet printer."

[0005] Inkjet printing, as described herein, is a non-contact, additive manufacturing and patterning process. ("Non-contact" refers to the absence of contact between the deposition device, i.e., the inkjet printer, and the substrate surface.) Materials are directly deposited layer by layer in a specific pattern, generally without the use of a mask or stencil, which may correspond to a conventional patterned deposition on a portion of a surface, or a blanket deposition over the entire surface. Once the ink is deposited, it is dried and annealed or sintered to form the desired layer. Inkjet printing is useful for patterning a variety of materials on a surface by including a variety of materials in the respective inks, including conductors, dielectrics, ceramics, oxides, and semiconductors.

[0006] 2 (PRIOR ART) shows an example diagram 200 of a wafer 202. Generally, semiconductor devices are fabricated on one surface of the wafer 202, referred to herein as the "front" surface 204. The surface opposite the "front" surface is referred to herein as the "back" surface 206 or the "backside" 206. A backside metal layer 208 is fabricated on the backside surface 206 to enhance thermal conduction. The metal layer 208 typically comprises copper, although other highly thermally conductive metals can be used.

[0007] High localized power dissipation in the device can generate significant localized heat that can warp the substrate on which the device is built or can cause destructive chemical reactions in the device components. The conductive metal layer 208 spreads the heat across the wafer 202, delocalizing high temperatures and facilitating heat dissipation via attached heat sinks or the like.

[0008] FIG. 3 (PRIOR ART) illustrates an exemplary process 300 for fabricating a backside metal layer 208 on the backside surface 206 of the wafer 202 (or other substrate) of FIG. 2. In step 302, the front surface 204 of the wafer 202 is patterned such that a pattern material 304, such as a conductive metal or polysilicon, fills trenches 306 created using an etching process. The etching process may include, for example, spinning on a photoresist, optically exposing the photoresist, developing the photoresist to remove exposed or unexposed portions of the photoresist (depending on whether a positive or negative photoresist is used), and etching to create the trenches 306. In step 308, an adhesive 310 is applied over the front surface 204 of the wafer 202. In step 312, a glass carrier 314, useful as a secure handle for gripping and manipulating the wafer 202, is attached to the adhesive 310. In step 316, a double-sided grinding tape 318 is attached to the glass carrier 314. In step 320, the wafer 202 is flipped over with the glass carrier 314, and the grinding tape 318 is applied onto a stable surface (not shown). A grinder 322 is prepared to reduce the thickness of the wafer 202, for example, from a thickness of 680-700 microns to a thickness of 50 microns. In step 324, the thickness of the wafer 202 is reduced by the grinder 322. In step 326, the wafer 202, adhesive 310, and glass carrier 314 are removed from the grinding tape 318 and the stable surface.

[0009] In step 327, a TiW (titanium-tungsten alloy) layer 328 is deposited on the backside surface 204 of the wafer 202, and a copper layer 330 is deposited on the TiW layer 328. In step 332, a layer of photoresist 334 is spun onto the wafer 202 on the copper layer 330. The layer of photoresist 334 is then patterned (e.g., using optical exposure and development) such that regions 336 of the photoresist 334 corresponding to the scribe lines are free of photoresist 334. The scribe line regions 336 are locations between the dies where it is acceptable to cut the wafer 202 into individual dies without damaging the circuitry. In step 338, the backside 204 of the wafer 202 is etched to remove portions of the TiW layer 328 and copper layer 330 corresponding to the regions 336. In steps 340 and 342, the backside 204 of the wafer 202 is further etched to facilitate subsequent dicing (die separation).

[0010] In step 344, a double-sided dicing tape 346 is adhered to the layer of photoresist 334 and used to hold the wafer 202 in place on a stable surface. In step 348, the glass carrier 314 is removed using, for example, laser debonding. In step 350, dicing is performed along the scribe lines to cut the wafer 202 into individual dies. Summary of the Invention

[0011] In a described example, a semiconductor wafer with a thermally conductive surface layer includes a bulk semiconductor layer having a first surface and a second surface, circuitry on the first surface, a metal layer attached to the first surface or the second surface, and a graphene layer attached to the metal layer. The first surface faces the second surface. The metal layer includes a transition metal. [Brief description of the drawings]

[0012] [Figure 1]FIG. 1 (Prior Art) shows an example side view of a drop-on-demand inkjet printer used to deposit material onto a surface.

[0013] [Diagram 2] FIG. 2 (Prior Art) shows a diagram of a backside metal layer fabricated on the backside surface of a wafer to improve thermal conduction.

[0014] [Diagram 3] FIG. 3 (Prior Art) illustrates the process of fabricating backside metal on the backside surface of the wafer of FIG.

[0015] [Figure 4A] 1 shows a diagram of an exemplary process for making metal nanoparticles.

[0016] [Figure 4B] 1 shows an exemplary diagram of metal nanoparticles.

[0017] [Figure 5A] 1 shows an example diagram of a wafer having a layer of metal nanoparticles deposited in droplets on the backside of the wafer, including metal nanoparticles with embedded particles of various carbon species.

[0018] [Figure 5B] 1 shows an example diagram of a wafer after sintering a layer of metal nanoparticles to form a thermally conductive backside layer.

[0019] [Figure 6] 1 illustrates an exemplary process for creating a thermally conductive layer on the backside surface of a wafer.

[0020] [Figure 7] An alternative embodiment of step 630 of FIG. 6 is shown in which a layer of TiW and one or more metal layers, such as a layer of Cu, are added to the backside of the wafer. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] FIG. 4A shows a diagram of an exemplary process 400 for making metallic nanoparticles 402. By incorporation, some metallic nanoparticles 402 are embedded with carbon seed particles. Such metal-carbon nanoparticles are useful for making a thermally conductive layer on the backside 504 of a semiconductor wafer 502, as will be further described with respect to FIGS. 5A and 5B. Graphene can also provide a favorable high thermal conductivity, which is usually measured in W / mK (Watts per meter-Kelvin). Amorphous carbon has a thermal conductivity of about 1.7 W / mK, pure copper has a thermal conductivity of about 401 W / mK, while graphene has a thermal conductivity of 2000-2500 W / mK.

[0022] FIG. 4A shows that a transition metal 404 and solid carbon 406 (e.g., amorphous or graphitic carbon rods) are vaporized by applying a high power current 408 in an arc reactor 410 to form metallic nanoparticles 402. In particular, transition metals such as silver, nickel, ruthenium, cobalt, molybdenum, and iridium generally have a hexahedral surface structure in solid form. (Metal components are selected for their reactivity. Metals that are too reactive may lead to structural instability in the final product related to microstructural changes due to phase transformation.) Also, carbon that nucleates on the hexahedral transition metal is more likely to grow in a hexahedral structure to form graphene. Thus, when the metal and carbon cool, metallic nanoparticles 402 are formed, including metallic nanoparticles 402 with embedded carbon particles. The metallic nanoparticles 402 produced by the process 400 of FIG. 4A are generally 4-150 nm in diameter. Generally, smaller particle size corresponds to increased thermal conductivity due to higher surface area compared to larger particle size. Experimental design is useful to calibrate the arc tool to optimize the particle generation process by optimizing parameters such as vaporization energy, chamber size and shape, reactant shape and content, and cooling rate. Some metallic nanoparticles 402 form without embedded carbon particles, while some metallic nanoparticles 402 form with multiple carbon particles. Various carbon species may be embedded in the metallic nanoparticles 402 at this stage. However, after the calcination step (which is part of the process for depositing the backside 504 thermally conductive layer on the wafer 502, described with reference to Figures 5A and 5B), regardless of the initial species of carbon, carbon originates from the metal and reconstructs to form graphene carbon.

[0023] 4B shows an example diagram 412 of a metallic nanoparticle 402. The nanoparticle 402 includes a metal 416 and a graphene platelet 414. A graphene platelet is a single or multi-layer portion of a two-dimensional graphite sheet and has a hexagonal lattice structure.

[0024] FIG. 5A shows an example diagram 500 of a wafer 502 having a layer of metallic nanoparticles 402 deposited in droplets on the backside 504 of the wafer 502, including metallic nanoparticles 402 embedded with particulates of various carbon species. The deposition occurs after circuitry (pattern material 608, see FIG. 6) has been formed on the frontside 506 (front surface) of the wafer 502. The circuitry may include electrical functional structures attached to (fabricated in or on) the frontside 506 of the wafer 502. The deposition of the metallic nanoparticles 402 occurs on the backside 504 of the wafer 502, and thus on the opposite side of the bulk of the wafer 502 from the front of the wafer 502 and the circuitry. As used herein, deposition on the surface of the wafer means either deposition directly on the surface of the wafer or deposition on the surface of a material attached to and adjacent to the surface of the wafer.

[0025] Deposition is advantageously performed with the nanoparticles 402 dissolved or suspended in the ink, for example by an inkjet printer 100 as described with respect to FIG. 1, such that the metallic nanoparticles 402 do not clump. The nanoparticles 402 may be deposited non-uniformly. The droplets used for deposition may have an upper diameter of, for example, 200 nm to 1 micron. For example, droplets with a diameter of 200 nm or less may be used, with a viscosity of 8 to 20 cubic Pascals, a surface tension of 28 to 32 mN / m (millinewtons per meter), and a pH of 4 to 9. Multiple layers of droplets are typically used, with the number of layers of droplets deposited depending on the designed effective thermal conductance. The substrate surface may be prepared prior to printing to allow uniform adhesion of the nanoparticle-laden ink to the substrate surface.

[0026] Inkjet printers that deposit larger droplets allow for larger metallic nanoparticles 402 to be used. With small (4-150 nm) metallic nanoparticles 402, the metallic nanoparticles 402 may overlap or clump together. Larger metallic nanoparticles 402 reduce overlap and clumping, which allows for the creation of graphene sheets 512 (FIG. 5B) with fewer grain boundaries in the sintered graphene sheets 512. (Graphene sheets 512 are also referred to herein as graphene layers.) Grain boundaries cause electron scattering. Fewer grain boundaries improve thermal conductivity. Generally, sintering results in a certain amount of inclusions, such as voids and carbon that does not come out of the formed metallic layer, to form the graphene sheets 512 (as described further below). Fewer inclusions correlate with higher thermal conductivity. Thus, the sintering process can be designed to reduce inclusions.

[0027] 5B shows an example view 508 of the wafer 502 after sintering the layer of metallic nanoparticles 402 to form a thermally conductive backside layer 504. After the metallic nanoparticles 402 are deposited (FIG. 5A), they are sintered at a temperature below 400° C. (centigrade), typically between 250° C. and 300° C. The temperature limitation is related to the circuitry prefabricated on the front side 506 of the wafer 502. Temperatures above 400° C. may damage the circuitry.

[0028] A heating device, such as an oven (not shown), sinters (heats) and melts the metallic nanoparticles 402. As the molten metal cools, carbon from the carbon-containing nanoparticles 402 rises from the flowing metal to the surface of the metal. The carbon rearranges and seeds onto the hexagonally structured cooled surface of the metal to form graphene sheets 512. Thus, the carbon emerging from the metal rearranges to match the hexagonal surface structure of the solidifying metal, meaning that the carbon forms graphene. The graphene sheets 512 may be, for example, a few monolayers (atomic molecular layers) thick. FIG. 5B also shows the molten metallic nanoparticles 510. Although the molten metallic nanoparticles 510 are shown as uniform sheets, the top and bottom surfaces may be somewhat rough, reflecting the sintered nanoparticle origin of the layer corresponding to the molten metallic nanoparticles 510. As discussed above with respect to FIG. 4A, the graphene sheets 512 are highly conductive, allowing for a thinner thermally conductive backside layer 504, which tends to reduce warping of the wafer 502. Thus, a thinner thermally conductive backside layer 504 reduces stress and associated warpage in the wafer 502. For example, a backside layer 504 having a thickness of a few microns or less may avoid excessive stress on the wafer 502. As a result of sintering, the fused metallic nanoparticles 510 are attached to and proximate to the backside surface 504 of the wafer 502. Thus, the fused metallic nanoparticles 510 are attached directly to the backside surface 504 of the wafer 502 or to a layer overlying and directly or indirectly attached to the backside surface 504 of the wafer 502. The graphene sheet 512 is formed such that it is fixedly bonded (attached) to the layer of fused metallic nanoparticles 510.

[0029] FIG. 6 illustrates an exemplary process for fabricating a thermally conductive layer on the backside surface 601 of a wafer 606. In step 602, the front surface 604 of the wafer 606 is patterned such that a pattern material 608, such as a conductive metal or polysilicon, fills pre-made trenches 610 using an etching process (similar to that described with respect to FIG. 3). In some examples, the pattern material 608 is arranged (designed) to form a circuit. In step 612, an adhesive 614 is applied to cover the front surface 604 of the wafer 606. In step 616, a glass carrier 618, useful as a secure handle for gripping and manipulating the wafer 606, is attached to the adhesive 614. In step 620, a double-sided grinding tape 622 is bonded to the glass carrier 618. In step 624, the wafer 606 is flipped over using the glass carrier 618 and the grinding tape 622 is bonded to a stable surface (not shown), thereby holding the wafer 606 in place. A grinder 626 is provided to reduce the thickness of the wafer 606 from a first thickness (e.g., 680-700 microns) to a second thickness (e.g., 50 microns). In step 628, the thickness of the wafer is reduced by the grinder 626.

[0030] At step 630, the wafer 606, adhesive 614, and glass carrier 618 are removed from the grinding tape 622 and the stable surface. Also at step 630, the SiO 2 A layer 632 is added to the backside 601 of the wafer 606. SiO 2 Layer 632 is usefully added to provide a dielectric layer, but is thin, e.g., a few tenths of a nanometer thick, to allow for effective functioning of the subsequently added thermally conductive layer (graphene layer 636). In step 634, an inkjet printer prints a SiO 2Metal nanoparticles including carbon particles are deposited (on layer 632) which are sintered to form a metal layer (shown in FIG. 5B as molten metal nanoparticles 510) and then cooled to form a graphene layer 636 on the surface of the metal layer. In step 638, the glass carrier 618 is removed. In step 640, the wafer 606 is cut (642) into individual dies.

[0031] As is evident from a comparison of Figures 3 and 6, selective inkjet deposition of the graphene sheet backside layer allows for a reduction in the number of steps in the die fabrication process, including the fabrication of the thermally conductive backside layer. For example, the number of steps can be reduced by depositing the graphene sheet and metallic backside layer so as not to cover the dicing locations.

[0032] FIG. 7 shows an alternative embodiment of step 630 of FIG. 6 in which one or more metal layers 732 , such as a layer of TiW and a layer of Cu, are added to the backside 601 of the wafer 606 .

[0033] In some embodiments, spin coating is used to apply the nanoparticles to the substrate surface.

[0034] In some embodiments, different portions of the backside of the wafer are covered by the metal layer and the graphene layer, in some embodiments, substantially all of the backside of the wafer is covered by the metal layer and the graphene layer, where substantially all means depends on the portion of the backside of the wafer that needs to be covered to meet the design requirements for heat spreading of the thermally conductive backside layer.

[0035] In some embodiments, a graphene sheet layer is fabricated on a front surface of a substrate. For example, the graphene sheet layer on the front surface of the substrate is useful for heat spreading. Such a graphene sheet layer may be fabricated, for example, near an integrated circuit or other functional device or other heat source.

[0036] In some embodiments, the graphene sheet layer is fabricated on only a portion of the front or back surface of the substrate, hi some embodiments, the graphene sheet layer is fabricated on the front surface of the substrate except for a portion of the front surface that is covered by a functional device, such as an integrated circuit.

[0037] In some embodiments, a filter is used in the arc process to generate particles for deposition.

[0038] In some embodiments, the metallic portion of the nanoparticles is formed from an alloy of multiple transition metals.

[0039] Modifications may be made to the exemplary embodiments described, and other embodiments are possible, within the scope of the invention.

Claims

1. An integrated circuit comprising: a semiconductor substrate having opposing first and second surfaces, the first surface having a patterned region; circuit elements in the patterned area; a metal layer on the second surface; and a carbon layer on the metal layer; 4. An integrated circuit comprising:

2. 2. The integrated circuit of claim 1, The integrated circuit, wherein the metal layer comprises a transition metal, the transition metal comprising at least one of silver, nickel, ruthenium, cobalt, molybdenum, and iridium.

3. 2. The integrated circuit of claim 1, The carbon layer includes internal grain boundaries.

4. The integrated circuit of claim 1, The integrated circuit wherein the metal layer comprises a layer of metal nanoparticles and carbon particles.

5. The integrated circuit of claim 4, The integrated circuit wherein said metal nanoparticles are between 4 nm and 150 nm in diameter.

6. The integrated circuit of claim 1, The carbon layer comprises a graphene layer.

7. The integrated circuit of claim 1, The carbon layer is smaller than 10 atomic layers.

8. The integrated circuit of claim 1, The integrated circuit further comprising a dielectric layer between the second surface and the metal layer.

9. The integrated circuit of claim 8, The integrated circuit wherein the thickness of the dielectric layer is less than 1 nanometer.

10. An integrated circuit comprising: a semiconductor substrate having opposing first and second surfaces, the first surface having a patterned region; circuit elements in the patterned area; a layer of metal nanoparticles and carbon particles on the second surface; 4. An integrated circuit comprising:

11. 11. An integrated circuit according to claim 10, The integrated circuit, wherein the metal nanoparticles comprise a transition metal, the transition metal comprising at least one of silver, nickel, ruthenium, cobalt, molybdenum, and iridium.

12. 11. An integrated circuit according to claim 10, The integrated circuit, wherein said metal nanoparticles are between 4 nm and 150 nm in diameter.

13. The integrated circuit of claim 10, The integrated circuit further comprising a carbon layer over said layer of metal nanoparticles and carbon particles.

14. The integrated circuit of claim 13, The carbon layer comprises a graphene layer.

15. The integrated circuit of claim 13, The carbon layer is smaller than 10 atomic layers.

16. The integrated circuit of claim 10, The integrated circuit further comprising a dielectric layer between the second surface and the layer of metal nanoparticles and carbon particles.

17. The integrated circuit of claim 16, The integrated circuit wherein the dielectric layer has a thickness of less than 1 nanometer.

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