Printed package and manufacturing method thereof

Abstract

A method (500) for interconnecting bond pads of a semiconductor die or device with corresponding leads in a lead frame with conductive interconnects printed instead of bond wires, and a device resulting from said method. More specifically, some examples include printing (510) insulating base paths from bond pads on the semiconductor die to the leads of the lead frame to which the semiconductor die is attached. Base conductive traces are printed (512) on top of the insulating base paths from each bond pad on the die to the corresponding lead of the lead frame. Optionally, on top of the conductive traces, a cover insulating cover layer is applied (514) on the exposed portions of the conductive interconnects and base insulating layer. Preferably, this is not a separate layer, but can be the same material as the base layer in order to fully adhere and fuse into a single structure. Optionally, a protective layer is then applied (516) on the resulting device.

Description

[Technical field]

[0001] Wire bonding is the process of providing electrical connections between a silicon chip and the external leads of a semiconductor device using very fine bonding wire. Typically, gold (Au), aluminum (Al), or copper (Cu) wire is used. During ball wire bonding, a ball is first formed by melting the end of the wire (which is held by a bonding tool known as a capillary) with an electronic flame-off (EFO). This free air ball has a diameter ranging from 1.5 to 2.5 times the wire diameter. Consistency of the free air ball size, controlled by the EFO and tail length, is important for a good bond. The free air ball is then brought into contact with a bond pad. The appropriate amount of pressure, heat, and ultrasonic force are then applied to the ball for a specific amount of time to form an initial metallurgical weld between the ball and the bond pad, as well as to deform the ball bond itself into its final shape. The wire is then threaded through the corresponding fingers of the lead frame, forming a gradual arc or "loop" between the bond pad and the lead finger. Pressure and ultrasonic forces are applied to the wire to form a second bond (known as a wedge bond, stitch bond, or fishtail bond), this time with the lead finger. The wire bonding machine, or wire bonder, clamps the wire and breaks it by lifting the capillary, in preparation for the next wire bonding cycle.

[0002] One of the benefits of Moore's Law is the continued reduction in die size and cost. However, while die sizes have decreased significantly, printed circuit board (PCB) geometries have not shrunk at the same rate. This requires packages to reroute connections on the small die to the larger PCB area. This different rate of evolution in the die and PCB has limited how much package sizes can shrink. The size, location, and pitch of the pins on the package are defined in part by the constraints of the PCB and SMT (SMT) process. Wire bonding has been the most traditional method of achieving these interconnections between the die and the lead frame that is attached into the packaged semiconductor that can be formed from it being attached to the PCB. Innovations in wire bonding over the past few decades have been significant. Summary of the Invention

[0003] This Summary is provided to introduce a selection of concepts described in a simplified form that are further described below in the Detailed Description, including the drawings provided. This Summary does not limit the scope of the claimed subject matter.

[0004] The embodiments provide a method for interconnecting bond pads of a semiconductor die or device with corresponding leads in a lead frame with printed conductive interconnects instead of the bond wires of the prior art, and an apparatus resulting from said method. More specifically, some examples include printing an insulating base path (PI, epoxy, silicone, etc.) from the bond pads on the semiconductor die to the leads of the lead frame to which the semiconductor die is attached. On top of the insulating base path from each bond pad on the die to the corresponding lead of the lead frame, a base conductive trace is printed (conductive ink, conductive polymer, sintered Cu sintered Ag, Ag epoxy, etc.). Optionally, on top of the conductive trace, a covering insulating cover layer is applied on the exposed portions of the conductive interconnects and the base insulating layer. Preferably, this can be the same material as the base layer in order to fully adhere and fuse into a single structure, rather than being a separate layer. Optionally, a protective layer is applied onto the resulting device using methods such as lamination, spray coating, injection molding, casting, AB multi-part casting (epoxy + hardener), glazing, roller coating, brush coating, dipping, screen printing, and the like.

[0005] [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a perspective view of the bottom surface of a 28-pin single row QFN device.

[0007] [Diagram 2] FIG. 2 is a perspective view of the top surface of the QFN device of FIG. 1 with a portion of the device encapsulant removed.

[0008] [Diagram 3] FIG. 2 is a partial perspective view of a leadframe strip showing four QFN leadframes.

[0009] [Figure 4] 3 is a side cross-sectional view of the QFN device 10 taken along reference line AA in FIG. 2.

[0010] [Diagram 5] 1 is a flow chart of a method for manufacturing a packaged electronic device.

[0011] [Figure 6] 6 is a flow chart of one exemplary method for manufacturing a packaged electronic device 600 that modifies the method of FIG. 5 between steps 502 and 504.

[0012] [Figure 7] 7 is a flow chart of another exemplary method for manufacturing a packaged electronic device 700 that modifies the method of FIG. 5 between steps 510 and 512.

[0013] [Figure 8] 8 is a flow chart of yet another exemplary method for manufacturing a packaged electronic device 800 that modifies the method of FIG. 5 between steps 508 and 512.

[0014] [Figure 9] 6 is a flow chart of yet another exemplary method for manufacturing a packaged electronic device 900 that modifies the method of FIG. 5 between steps 512 and 514.

[0015] [Figure 10] 6 is a flow chart of another exemplary method for manufacturing a packaged electronic device 1000 that modifies the method of FIG. 5 between steps 510 and 514.

[0016] [Figure 11] 5 is a flow chart of yet another exemplary method for manufacturing a packaged electronic device 1100 that modifies the method of FIG. 5 between steps 510 and 514.

[0017] [Figure 12]5 is a flowchart of yet another exemplary method for manufacturing a packaged electronic device 1200 that modifies the method of FIG. 5 between steps 510 and 514.

[0018] [Figure 13] 5 is a flowchart of yet another exemplary method for manufacturing a packaged electronic device 1300 that modifies the method of FIG. 5 between steps 512 and 516.

[0019] [Figure 14] 5 is a flowchart of another example method for manufacturing a packaged electronic device 1400 that modifies the method of FIG. 5 between steps 512 and 516.

[0020] [Figure 15] 5 between steps 512 and 516 is a flowchart of yet another exemplary method for manufacturing a packaged electronic device 1500.

[0021] [Figure 16] 5 is a flowchart of yet another exemplary method for manufacturing a packaged electronic device 1600 that modifies the method of FIG. 5 between steps 514 and 518.

[0022] [Figure 17A] 1 is a top view of a QFN leadframe strip 36 including several individual six-lead or pin leadframe units 37.

[0023] [Figure 17B] 17B is a cross-sectional view of the QFN leadframe strip 36 taken along reference line BB in FIG. 17A.

[0024] [Figure 18A] 1 is a top view of an individual lead frame unit 38. FIG.

[0025] [Figure 18B]18B is a side view of an individual lead frame unit 38 taken along reference line CC in FIG. 18A.

[0026] [Figure 19A] FIG. 4 is a top view of an alternative Chip-on-Lead (COL) leadframe unit 40 for directly attaching the bottom surface of a die to a portion of the leads 12.

[0027] [Figure 19B] 19B is a side view of an individual lead frame unit 38 along the reference line DD in FIG. 19A.

[0028] [Figure 20A] 1 is a top view of a pre-molded QFN leadframe strip 44. FIG.

[0029] [Figure 20B] 20B is a cross-sectional view of the pre-molded QFN leadframe strip 44 taken along reference line EE of FIG. 20A.

[0030] [Figure 21A] A top view of a pre-molded leadframe unit 46 on a QFN leadframe strip 46.

[0031] [Figure 21B] 21B is a cross-sectional view of the pre-molded lead frame unit 46 shown in FIG. 21A taken along the reference line FF.

[0032] [Figure 22A] FIG. 1 is a top view of a COL leadframe unit having a pre-mold 48.

[0033] [Figure 22B] 22B is a cross-sectional view of the pre-molded lead frame unit 46 shown in FIG. 22A taken along reference line GG.

[0034] [Figure 23A]22 is a top view of the leadframe 46 of FIG. 21 having a layer of die attach on the die attach pad 14. FIG.

[0035] [Figure 23B] 23B is a side view of lead frame 46 of FIG. 23A taken along reference line HH.

[0036] [Figure 23C] 23 is a top view of the leadframe 48 of FIG. 22 having a layer of die attach on the leads 12. FIG. [Figure 23D] 23D is a side view of the lead frame 48 of FIG. 23C taken along the reference line H1-H1.

[0037] [Figure 24A] 1 is a top view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded leadframe unit 46.

[0038] [Figure 24B] 24B is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line II in FIG. 24A.

[0039] [Figure 24C] 1 is a top view of an optional example of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of a lead 12 of a chip-on-lead (COL) pre-molded leadframe unit 48.

[0040] [Figure 24D] 24C is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a lead 12 of a pre-molded leadframe unit 48 taken along reference line I1-I1 of FIG. 24C.

[0041] [Figure 25A]FIG. 24A is a top view of an alternative COL embodiment in which there is no die support pad and the integrated circuit (IC) die 18 is attached directly to the leads 12 of the leadframe unit (a non-premolded leadframe is shown in the example of FIG. 24A with no molding material between the leads 12).

[0042] [Figure 25B] FIG. 25B is a side view of an alternative COL implementation along reference line JJ of FIG. 25A in which there is no die support pad and an integrated circuit (IC) die 18 is attached directly to leads 12 of the leadframe unit.

[0043] [Figure 26A] 5 is a top view of an electronic assembly manufactured according to the exemplary method 500 of FIG. 5 with implementation at 510, in which a blanket insulating layer 52 is printed, deposited, formed, or otherwise applied as a base layer spanning portions of the top surfaces of the lead fingers 12 in the premolded lead frame 46, across the premolded lead frame 42, over one side of the die 18, across the top of the die 18, under the opposite side of the die 18, across the premolded lead frame 42 on the opposite side of the premolded lead frame 46, and up to portions of the top surfaces of the lead fingers 12 on the opposite side of the premolded lead frame 46 (e.g., at 510 in FIG. 5 ).

[0044] [Figure 26B] 26B is a cross-sectional view of the electronic assembly of FIG. 26A taken along various reference lines. [Figure 26C] 26B is a cross-sectional view of the electronic assembly of FIG. 26A taken along various reference lines. [Figure 26D] 26B is a cross-sectional view of the electronic assembly of FIG. 26A taken along various reference lines. [Figure 26E] 26B is a cross-sectional view of the electronic assembly of FIG. 26A taken along various reference lines. [Figure 26F] 26B is a cross-sectional view of the electronic assembly of FIG. 26A taken along various reference lines. [Figure 26G] 26B is a cross-sectional view of the electronic assembly of FIG. 26A taken along various reference lines. [Fig. 26H] 26B is a cross-sectional view of the electronic assembly of FIG. 26A taken along various reference lines. [Figure 26I] 26B is a cross-sectional view of the electronic assembly of FIG. 26A taken along various reference lines. [Figure 26J] 26B is a cross-sectional view of the electronic assembly of FIG. 26A taken along various reference lines.

[0045] [Figure 27A] FIG. 5 is a top view of an electronic assembly that has been manufactured according to the exemplary method 500 of FIG. 5 using the implementation at 510. Instead of using a single blanket insulating layer as shown in FIGS. 26A-26J, two spaced-apart half blanket insulating layers 64 are applied as a base layer, each extending across the pre-mold 42, onto one side on the die 18, across a portion of the top of the die 18 just beyond the bond pads 50 of the die 18 (e.g., at 510 in FIG. 5), and onto the top surface of a portion of the lead fingers 12 in the pre-mold lead frame 46.

[0046] [Figure 27B] 27B is a cross-sectional view of the electronic assembly of FIG. 27A taken along various reference lines. [Figure 27C] 27B is a cross-sectional view of the electronic assembly of FIG. 27A taken along various reference lines. [Figure 27D] 27B is a cross-sectional view of the electronic assembly of FIG. 27A taken along various reference lines. [Figure 27E] 27B is a cross-sectional view of the electronic assembly of FIG. 27A taken along various reference lines. [Figure 27F] 27B is a cross-sectional view of the electronic assembly of FIG. 27A taken along various reference lines. [Figure 27G] 27B is a cross-sectional view of the electronic assembly of FIG. 27A taken along various reference lines. [Fig. 27H] 27B is a cross-sectional view of the electronic assembly of FIG. 27A taken along various reference lines. [Figure 27I] 27B is a cross-sectional view of the electronic assembly of FIG. 27A taken along various reference lines. [Figure 27J]27B is a cross-sectional view of the electronic assembly of FIG. 27A taken along various reference lines.

[0047] [Figure 28A] FIG. 5 is a top view of an electronic assembly fabricated according to example method 500 of FIG. 5 using implementation 510, in which individual insulating layers 66 are used instead of blanket insulating layer 52 of FIGS. 26A-J or half blanket insulating layer 64 of FIGS. 27A-J.

[0048] [Figure 28B] 28B is a cross-sectional view of the electronic assembly of FIG. 28A taken along various reference lines. [Figure 28C] 28B is a cross-sectional view of the electronic assembly of FIG. 28A taken along various reference lines. [Figure 28D] 28B is a cross-sectional view of the electronic assembly of FIG. 28A taken along various reference lines. [Figure 28E] 28B is a cross-sectional view of the electronic assembly of FIG. 28A taken along various reference lines. [Figure 28F] 28B is a cross-sectional view of the electronic assembly of FIG. 28A taken along various reference lines. [Figure 28G] 28B is a cross-sectional view of the electronic assembly of FIG. 28A taken along various reference lines. [Fig. 28H] 28B is a cross-sectional view of the electronic assembly of FIG. 28A taken along various reference lines. [Figure 28I] 28B is a cross-sectional view of the electronic assembly of FIG. 28A taken along various reference lines. [Figure 28J] 28B is a cross-sectional view of the electronic assembly of FIG. 28A taken along various reference lines.

[0049] [Figure 29A] The die 18 is shown attached to a pre-molded lead frame 46 prior to application of the insulating material.

[0050] [Figure 29B] The results of multiple successive passes of printing of insulating material by printhead 68 are shown. [Figure 29C]The results of multiple successive passes of printing of insulating material by printhead 68 are shown. [Figure 29D] The results of multiple successive passes of printing of insulating material by printhead 68 are shown. [Figure 29E] The results of multiple successive passes of printing of insulating material by printhead 68 are shown. [Figure 29F] The results of multiple successive passes of printing of insulating material by printhead 68 are shown. [Figure 29G] The results of multiple successive passes of printing of insulating material by printhead 68 are shown. [Figure 29H] The results of multiple successive passes of printing of insulating material by printhead 68 are shown. [Figure 29I] The results of multiple successive passes of printing of insulating material by printhead 68 are shown. [Figure 29J] The results of multiple successive passes of printing of insulating material by printhead 68 are shown.

[0051] [Diagram 30] 1 is a partial cross-sectional side view of a die attached to a lead frame in accordance with various examples. [Diagram 31] 1 is a partial cross-sectional side view of a die attached to a lead frame in accordance with various examples. [Diagram 32] 1 is a partial cross-sectional side view of a die attached to a lead frame in accordance with various examples. [Diagram 33] 1 is a partial cross-sectional side view of a die attached to a lead frame in accordance with various examples.

[0052] [Diagram 34] FIG. 1 illustrates that the shrinkage of insulating materials, particularly polymers, is proportional to the distance from the nearest contact surface.

[0053] [Diagram 35]FIG. 2 is a partial cross-sectional side view of a die attached to a leadframe with a convex shape to the insulating layer resulting from a significant amount of insulating material deposited on the die and leadframe.

[0054] [Diagram 36] FIG. 36 is a partial cross-sectional side view of a die attached to a lead frame similar to FIG. 35, illustrating the results of CTE shrinkage of an insulating layer having a convex outer surface.

[0055] [Figure 37A] 5 is a top view of an electronic assembly manufactured according to the exemplary method 500 of FIG. 5 with implementation at 510, in which a blanket insulating layer 52 is printed, deposited, formed, or otherwise applied as a base layer spanning portions of the top surfaces of the lead fingers 12 in the premolded lead frame 48, across the premolded lead frame 48, across the premolded lead frame 42, on one side of the die 18, across the top of the die 18, under the opposite side of the die 18, across the premolded lead frame 42 on the opposite side of the premolded lead frame 48, and on portions of the top surfaces of the lead fingers 12 on the opposite side of the premolded lead frame 48 (e.g., at 510 in FIG. 5 ).

[0056] [Figure 37B] FIG. 37B is a cross-sectional view of the electronic assembly of FIG. 37A taken along reference line K1-K1.

[0057] [Figure 38A] FIG. 5 is a top view of an electronic assembly that has been manufactured according to the exemplary method 500 of FIG. 5 using implementation at 510. Instead of using a single blanket insulating layer as shown in FIGS. 37A and 37B, two spaced apart half blanket insulating layers 64 are applied as a base layer, each across the top surface of a portion of the lead fingers 12 in the pre-molded lead frame 48, across the pre-molded lead frame 42, on one side of the die 18, and across a portion of the top of the die 18 just beyond the bond pads 50 on the die 18 (e.g., at 510 in FIG. 5).

[0058] [Figure 38B] 38B is a cross-sectional view of the electronic assembly of FIG. 38A taken along reference line N1-N1.

[0059] [Figure 39A] FIG. 5 is a top view of an electronic assembly manufactured according to the exemplary method 500 of FIG. 5 using the implementation at 510, in which individual insulating layers 66 are used instead of the blanket insulating layer 52 of FIG. 37B or the half blanket insulating layer 64 of FIGS. 38A and 38B.

[0060] [Figure 39B] FIG. 39B is a cross-sectional view of the electronic assembly of FIG. 39A along reference line R1-R1.

[0061] [Figure 40A] FIG. 5 is a top view of an electronic assembly manufactured according to the exemplary method 500 of FIG. 5 using implementation at 512, in which a plurality of conductive traces or interconnects 74 are printed or formed on a blanket insulating layer 52 (e.g., FIGS. 26A-26J), each conductive trace or interconnect between a respective bond pad 50 of the die 18 and a corresponding top surface of a respective lead 12 of the pre-molded lead frame 46.

[0062] [Figure 40B] 40B is a cross-sectional view of the electronic assembly of FIG. 40A taken along various reference lines. [Figure 40C] 40B is a cross-sectional view of the electronic assembly of FIG. 40A taken along various reference lines. [Figure 40D] 40B is a cross-sectional view of the electronic assembly of FIG. 40A taken along various reference lines. [Figure 40E] 40B is a cross-sectional view of the electronic assembly of FIG. 40A taken along various reference lines. [Diagram 40F] 40B is a cross-sectional view of the electronic assembly of FIG. 40A taken along various reference lines. [Figure 40G] 40B is a cross-sectional view of the electronic assembly of FIG. 40A taken along various reference lines. [Figure 40H]40B is a cross-sectional view of the electronic assembly of FIG. 40A taken along various reference lines. [Fig. 40I] 40B is a cross-sectional view of the electronic assembly of FIG. 40A taken along various reference lines. [Figure 40J] 40B is a cross-sectional view of the electronic assembly of FIG. 40A taken along various reference lines.

[0063] [Figure 41A] FIG. 5 is a top view of an electronic assembly that has been manufactured according to the exemplary method 500 of FIG. 5 using implementation at 512, in which a plurality of conductive traces or interconnects 74 are printed or formed on two spaced apart half blanket insulating layers 64 (e.g., FIGS. 27A-27J) applied as a base layer, each spanning over the top of a portion of a lead finger 12 in pre-molded lead frame 46, across pre-molded lead frame 42, on one side of die 18, and over a portion of the top of die 18 just beyond bond pad 50 on die 18.

[0064] [Figure 41B] 41B is a cross-sectional view of the electronic assembly of FIG. 41A taken along various reference lines. [Figure 41C] 41B is a cross-sectional view of the electronic assembly of FIG. 41A taken along various reference lines. [Figure 41D] 41B is a cross-sectional view of the electronic assembly of FIG. 41A taken along various reference lines. [Figure 41E] 41B is a cross-sectional view of the electronic assembly of FIG. 41A taken along various reference lines. [Fig.41F] 41B is a cross-sectional view of the electronic assembly of FIG. 41A taken along various reference lines. [Figure 41G] 41B is a cross-sectional view of the electronic assembly of FIG. 41A taken along various reference lines. [Fig. 41H] 41B is a cross-sectional view of the electronic assembly of FIG. 41A taken along various reference lines. [Fig.41I] 41B is a cross-sectional view of the electronic assembly of FIG. 41A taken along various reference lines. [Figure 41J] 41B is a cross-sectional view of the electronic assembly of FIG. 41A taken along various reference lines.

[0065] [Figure 42A] FIG. 5 is a top view of an electronic assembly that has been manufactured according to the exemplary method 500 of FIG. 5 using implementation at 512, in which conductive layers 74 are printed or formed on individual insulating layers 66 (e.g., FIGS. 28A-28J) that are applied as a base layer, each across the top surface of a portion of a lead finger 12 in the pre-molded lead frame 46, across the pre-molded lead frame 42, on one side of the die 18, and across a portion of the top of the die 18 just beyond the bond pads 50 on the die 18.

[0066] [Figure 42B] 42B is a cross-sectional view of the electronic assembly of FIG. 42A taken along various reference lines. [Figure 42C] 42B is a cross-sectional view of the electronic assembly of FIG. 42A taken along various reference lines. [Fig.42D] 42B is a cross-sectional view of the electronic assembly of FIG. 42A taken along various reference lines. [Figure 42E] 42B is a cross-sectional view of the electronic assembly of FIG. 42A taken along various reference lines. [Fig.42F] 42B is a cross-sectional view of the electronic assembly of FIG. 42A taken along various reference lines. [Figure 42G] 42B is a cross-sectional view of the electronic assembly of FIG. 42A taken along various reference lines. [Fig. 42H] 42B is a cross-sectional view of the electronic assembly of FIG. 42A taken along various reference lines. [Fig.42I] 42B is a cross-sectional view of the electronic assembly of FIG. 42A taken along various reference lines. [Fig.42J] 42B is a cross-sectional view of the electronic assembly of FIG. 42A taken along various reference lines.

[0067] [Figure 43A] The die 18 is shown attached to a pre-molded lead frame 46 prior to application of the insulating material for the second insulating layer.

[0068] [Figure 43B]3 shows the result of multiple successive passes of printing of conductive material by printhead 68 onto a base insulating layer. [Figure 43C] 3 shows the result of multiple successive passes of printing of conductive material by printhead 68 onto a base insulating layer. [Fig. 43D] 3 shows the result of multiple successive passes of printing of conductive material by printhead 68 onto a base insulating layer. [Figure 43E] 3 shows the result of multiple successive passes of printing of conductive material by printhead 68 onto a base insulating layer. [Figure 43F] 3 shows the result of multiple successive passes of printing of conductive material by printhead 68 onto a base insulating layer. [Figure 43G] 3 shows the result of multiple successive passes of printing of conductive material by printhead 68 onto a base insulating layer. [Fig. 43H] 3 shows the result of multiple successive passes of printing of conductive material by printhead 68 onto a base insulating layer. [Figure 43I] 3 shows the result of multiple successive passes of printing of conductive material by printhead 68 onto a base insulating layer. [Figure 43J] 3 shows the result of multiple successive passes of printing of conductive material by printhead 68 onto a base insulating layer. [Figure 43K] 3 shows the result of multiple successive passes of printing of conductive material by printhead 68 onto a base insulating layer. [Figure 43L] 3 shows the result of multiple successive passes of printing of conductive material by printhead 68 onto a base insulating layer.

[0069] [Figure 44A]FIG. 5 is a top view of an electronic assembly manufactured according to the exemplary method 500 of FIG. 5 using mounting at 512, in which a plurality of conductive traces or interconnects 74 are printed or formed on a blanket insulating layer 52 (e.g., FIGS. 36A-36J), each conductive trace or interconnect between a respective bond pad 50 of the die 18 and a corresponding top surface of a respective lead 12 of the pre-molded lead frame 48.

[0070] [Figure 44B] FIG. 44B is a cross-sectional view of the electronic assembly of FIG. 44A taken along reference line K3-K3.

[0071] [Figure 45A] FIG. 5 is a top view of an electronic assembly manufactured according to the exemplary method 500 of FIG. 5 using implementation at 512, in which a plurality of conductive traces or interconnects 74 are printed or formed on two spaced half blanket insulating layers 64 (e.g., FIGS. 38A and 38B) applied as a base layer, each spanning the top surface of a portion of a lead finger 12 in the pre-molded lead frame 48, across the pre-molded lead frame 42, on one side of the die 18, and across a portion of the top of the die 18 just beyond the bond pad 50 on the die 18.

[0072] [Figure 45B] FIG. 45B is a cross-sectional view of the electronic assembly of FIG. 45A taken along reference line N3-N3.

[0073] [Figure 46A] A top view of an electronic assembly manufactured according to the exemplary method 500 of FIG. 5 with mounting at 512, in which conductive layers 74 are printed or formed on individual insulating layers 66 (e.g., FIGS. 46A and 46B) applied as a base layer, each across the top surface of a portion of a lead finger 12 in the pre-molded lead frame 48, across the pre-molded lead frame 42, on one side of the die 18, and across a portion of the top of the die 18 just beyond the bond pads 50 on the die 18.

[0074] [Figure 46B] FIG. 46B is a cross-sectional view of the electronic assembly of FIG. 46A taken along reference line R3-R3.

[0075] [Figure 47A] 5A and 5B, a top view of an electronic assembly that has been manufactured according to the exemplary method 500 of FIG. 5 with mounting at 514, in which a second insulating layer, e.g., a blanket overlay insulating layer 76, has been printed, deposited, formed, or otherwise applied over the exposed portions of the blanket base or basic insulating layer 52 and the exposed portions of the conductive traces or interconnects 74 on the base or basic insulating layer 52 (see FIGS. 40A and 40B), over a portion of the top surface of the lead fingers 12 in the pre-molded lead frame 46, across the pre-molded lead frame 42, across the top of the die 18, under the opposite side of the die 18, across the pre-molded lead frame 42 on the opposite side of the pre-molded lead frame 46, and over a portion of the top surface of the lead fingers 12 on the opposite side of the pre-molded lead frame 46.

[0076] [Figure 47B] 56B is a cross-sectional view of the electronic assembly of FIG. 56A taken along various reference lines. [Figure 47C] 56B is a cross-sectional view of the electronic assembly of FIG. 56A taken along various reference lines. [Figure 47D] 56B is a cross-sectional view of the electronic assembly of FIG. 56A taken along various reference lines. [Figure 47E] 56B is a cross-sectional view of the electronic assembly of FIG. 56A taken along various reference lines. [Fig.47F] 56B is a cross-sectional view of the electronic assembly of FIG. 56A taken along various reference lines. [Figure 47G] 56B is a cross-sectional view of the electronic assembly of FIG. 56A taken along various reference lines. [Fig. 47H] 56B is a cross-sectional view of the electronic assembly of FIG. 56A taken along various reference lines. [Fig.47I] 56B is a cross-sectional view of the electronic assembly of FIG. 56A taken along various reference lines. [Figure 47J] 56B is a cross-sectional view of the electronic assembly of FIG. 56A taken along various reference lines. [Figure 47K] 56B is a cross-sectional view of the electronic assembly of FIG. 56A taken along various reference lines. [Figure 47L] 56B is a cross-sectional view of the electronic assembly of FIG. 56A taken along various reference lines. [Figure 47M] 56B is a cross-sectional view of the electronic assembly of FIG. 56A taken along various reference lines. [Figure 47N] 56B is a cross-sectional view of the electronic assembly of FIG. 56A taken along various reference lines. [Fig.47O] 56B is a cross-sectional view of the electronic assembly of FIG. 56A taken along various reference lines. [Figure 47P] 56B is a cross-sectional view of the electronic assembly of FIG. 56A taken along various reference lines. [Figure 47Q] 56B is a cross-sectional view of the electronic assembly of FIG. 56A taken along various reference lines. [Figure 47R] 56B is a cross-sectional view of the electronic assembly of FIG. 56A taken along various reference lines.

[0077] [Figure 48A] 5 is a top view of an electronic assembly that has been manufactured according to the exemplary method 500 of FIG. 5 with implementation at 514, in which a second insulating layer, e.g., a blanket over insulating layer 76, has been printed, deposited, formed, or otherwise applied over the exposed portions of the half blanket base or basic insulating layer 64 and the exposed portions of the conductive traces or interconnects 74 on the half blanket base or basic insulating layer 66 (see FIGS. 41A and 41B), each over a portion of the top surface of the lead fingers 12 in the pre-molded lead frame 46, across the pre-molded lead frame 42, over one side of the die 18, and across a portion of the top of the die 18 just beyond the top of the bond pad 50 closest to the side of the die 18 that the respective half blanket base or basic insulating layer 64 is adjacent to.

[0078] [Figure 48B] 48B are cross-sectional views of the electronic assembly of FIG. 48A taken along various reference lines. [Figure 48C]48B are cross-sectional views of the electronic assembly of FIG. 48A taken along various reference lines. [Figure 48D] 48B are cross-sectional views of the electronic assembly of FIG. 48A taken along various reference lines. [Figure 48E] 48B are cross-sectional views of the electronic assembly of FIG. 48A taken along various reference lines. [Fig.48F] 48B are cross-sectional views of the electronic assembly of FIG. 48A taken along various reference lines. [Figure 48G] 48B are cross-sectional views of the electronic assembly of FIG. 48A taken along various reference lines. [Fig. 48H] 48B are cross-sectional views of the electronic assembly of FIG. 48A taken along various reference lines. [Fig.48I] 48B are cross-sectional views of the electronic assembly of FIG. 48A taken along various reference lines. [Fig.48J] 48B are cross-sectional views of the electronic assembly of FIG. 48A taken along various reference lines. [Figure 48K] 48B are cross-sectional views of the electronic assembly of FIG. 48A taken along various reference lines. [Figure 48L] 48B are cross-sectional views of the electronic assembly of FIG. 48A taken along various reference lines. [Figure 48M] 48B are cross-sectional views of the electronic assembly of FIG. 48A taken along various reference lines. [Figure 48N] 48B are cross-sectional views of the electronic assembly of FIG. 48A taken along various reference lines. [Fig.48O] 48B are cross-sectional views of the electronic assembly of FIG. 48A taken along various reference lines. [Figure 48P] 48B are cross-sectional views of the electronic assembly of FIG. 48A taken along various reference lines. [Figure 48Q] 48B are cross-sectional views of the electronic assembly of FIG. 48A taken along various reference lines. [Figure 48R] 48B are cross-sectional views of the electronic assembly of FIG. 48A taken along various reference lines.

[0079] [Figure 49A]5A is a top view of an electronic assembly that has been manufactured according to method 500 of FIG. 5 with implementation at 514, in which a second insulating layer, e.g., a blanket coated insulating layer 76, is printed, deposited, formed, or otherwise applied over the exposed portions of the individual base or base insulating layers 66 and the exposed portions of each conductive trace or interconnect 74 on the individual blanket base or base insulating layer 66 (see FIGS. 42A and 42B), each over a portion of the top surface of the lead fingers 12 in the pre-molded lead frame 46, across the pre-molded frame 42, on one side of the die 18, and across a portion of the top of the die 18 just beyond the bond pad 50 closest to the side of the die 18 to which each individual base or base insulating layer 66 is adjacent.

[0080] [Figure 49B] 49B is a cross-sectional view of the electronic assembly of FIG. 49A taken along various reference lines. [Figure 49C] 49B is a cross-sectional view of the electronic assembly of FIG. 49A taken along various reference lines. [Figure 49D] 49B is a cross-sectional view of the electronic assembly of FIG. 49A taken along various reference lines. [Figure 49E] 49B is a cross-sectional view of the electronic assembly of FIG. 49A taken along various reference lines. [Fig.49F] 49B is a cross-sectional view of the electronic assembly of FIG. 49A taken along various reference lines. [Figure 49G] 49B is a cross-sectional view of the electronic assembly of FIG. 49A taken along various reference lines. [Fig. 49H] 49B is a cross-sectional view of the electronic assembly of FIG. 49A taken along various reference lines. [Fig.49I] 49B is a cross-sectional view of the electronic assembly of FIG. 49A taken along various reference lines. [Figure 49J] 49B is a cross-sectional view of the electronic assembly of FIG. 49A taken along various reference lines. [Figure 49K] 49B is a cross-sectional view of the electronic assembly of FIG. 49A taken along various reference lines. [Figure 49L] 49B is a cross-sectional view of the electronic assembly of FIG. 49A taken along various reference lines. [Figure 49M] 49B is a cross-sectional view of the electronic assembly of FIG. 49A taken along various reference lines. [Figure 49N] 49B is a cross-sectional view of the electronic assembly of FIG. 49A taken along various reference lines. [Fig.49O] 49B is a cross-sectional view of the electronic assembly of FIG. 49A taken along various reference lines. [Figure 49P] 49B is a cross-sectional view of the electronic assembly of FIG. 49A taken along various reference lines. [Figure 49Q] 49B is a cross-sectional view of the electronic assembly of FIG. 49A taken along various reference lines. [Figure 49R] 49B is a cross-sectional view of the electronic assembly of FIG. 49A taken along various reference lines.

[0081] [Figure 50A] 5A and 5B, and a top view of an electronic assembly that has undergone fabrication in accordance with 500 of FIG. 5 with implementation at 514, in which two half blanket coated insulating layers 78 have been printed, deposited, formed, or otherwise applied, respectively, over the exposed portions of the blanket base or basic insulating layer 52 and the exposed portions of the conductive traces or interconnects 74 on the base or basic insulating layer 52 (see FIGS. 40A and 40B), extending over a portion of the top surface of the lead fingers 12 in the premolded lead frame 46, across the premolded lead frame 42, over one side of the die 18, across the top of the die 18, down on the opposite side of the die 18, across the premolded lead frame 42 on the opposite side of the premolded lead frame 46, and to a portion of the top surface of the lead fingers 12 on the opposite side of the premolded lead frame 46.

[0082] [Figure 50B] 50B is a cross-sectional view of the electronic assembly of FIG. 50A taken along various reference lines. [Figure 50C] 50B is a cross-sectional view of the electronic assembly of FIG. 50A taken along various reference lines. [Figure 50D] 50B is a cross-sectional view of the electronic assembly of FIG. 50A taken along various reference lines. [Figure 50E] 50B is a cross-sectional view of the electronic assembly of FIG. 50A taken along various reference lines. [Figure 50F] 50B is a cross-sectional view of the electronic assembly of FIG. 50A taken along various reference lines. [Figure 50G] 50B is a cross-sectional view of the electronic assembly of FIG. 50A taken along various reference lines. [Figure 50H] 50B is a cross-sectional view of the electronic assembly of FIG. 50A taken along various reference lines. [Fig. 50I] 50B is a cross-sectional view of the electronic assembly of FIG. 50A taken along various reference lines. [Fig. 50J] 50B is a cross-sectional view of the electronic assembly of FIG. 50A taken along various reference lines. [Figure 50K] 50B is a cross-sectional view of the electronic assembly of FIG. 50A taken along various reference lines. [Figure 50L] 50B is a cross-sectional view of the electronic assembly of FIG. 50A taken along various reference lines. [Figure 50M] 50B is a cross-sectional view of the electronic assembly of FIG. 50A taken along various reference lines. [Figure 50N] 50B is a cross-sectional view of the electronic assembly of FIG. 50A taken along various reference lines. [Fig. 50O] 50B is a cross-sectional view of the electronic assembly of FIG. 50A taken along various reference lines. [Figure 50P] 50B is a cross-sectional view of the electronic assembly of FIG. 50A taken along various reference lines. [Figure 50Q] 50B is a cross-sectional view of the electronic assembly of FIG. 50A taken along various reference lines. [Figure 50R] 50B is a cross-sectional view of the electronic assembly of FIG. 50A taken along various reference lines.

[0083] [Figure 51A]5 is a top view of an electronic assembly that has undergone fabrication in accordance with 500 of FIG. 5 with implementation at 514, in which two half blanket coated insulating layers 78 have been printed, deposited, formed, or otherwise applied (see FIGS. 41A and 41B) over the exposed portions of the half blanket base or basic insulating layer 64 and the exposed portions of the conductive traces or interconnects 74 on the half blanket base or basic insulating layer 66, respectively, over a portion of the top surface of the lead fingers 12 in the pre-molded lead frame 46, across the pre-molded lead frame 42, over one side of the die 18, just beyond the bond pad 50 closest to the side of the die 18 to which each half blanket base or basic insulating layer 64 is adjacent, and over a portion of the top of the die 18.

[0084] [Figure 51B] 51B is a cross-sectional view of the electronic assembly of FIG. 51A taken along various reference lines. [Figure 51C] 51B is a cross-sectional view of the electronic assembly of FIG. 51A taken along various reference lines. [Fig. 51D] 51B is a cross-sectional view of the electronic assembly of FIG. 51A taken along various reference lines. [Figure 51E] 51B is a cross-sectional view of the electronic assembly of FIG. 51A taken along various reference lines. [Fig. 51F] 51B is a cross-sectional view of the electronic assembly of FIG. 51A taken along various reference lines. [Figure 51G] 51B is a cross-sectional view of the electronic assembly of FIG. 51A taken along various reference lines. [Fig. 51H] 51B is a cross-sectional view of the electronic assembly of FIG. 51A taken along various reference lines. [Fig. 51I] 51B is a cross-sectional view of the electronic assembly of FIG. 51A taken along various reference lines. [Fig. 51J] 51B is a cross-sectional view of the electronic assembly of FIG. 51A taken along various reference lines. [Figure 51K] 51B is a cross-sectional view of the electronic assembly of FIG. 51A taken along various reference lines. [Figure 51L] 51B is a cross-sectional view of the electronic assembly of FIG. 51A taken along various reference lines. [Figure 51M] 51B is a cross-sectional view of the electronic assembly of FIG. 51A taken along various reference lines. [Figure 51N] 51B is a cross-sectional view of the electronic assembly of FIG. 51A taken along various reference lines. [Fig. 51O] 51B is a cross-sectional view of the electronic assembly of FIG. 51A taken along various reference lines. [Figure 51P] 51B is a cross-sectional view of the electronic assembly of FIG. 51A taken along various reference lines. [Fig. 51Q] 51B is a cross-sectional view of the electronic assembly of FIG. 51A taken along various reference lines. [Figure 51R] 51B is a cross-sectional view of the electronic assembly of FIG. 51A taken along various reference lines.

[0085] [Figure 52A] 5 is a top view of an electronic assembly that has undergone manufacture in accordance with 500 of FIG. 5 with implementation at 514, in which two half blanket coated insulating layers 76 have been printed, deposited, formed, or otherwise applied (see FIGS. 42A and 42B) over the exposed portions of the base or basic insulating layer 66 and the exposed portions of each conductive trace or interconnect 74 on the individual blanket base or basic insulating layers 66, each spanning a portion of the top surface of the lead fingers 12 in the pre-molded lead frame 46, across the pre-molded lead frame 42, over one side of the die 18, just beyond the bond pad 50 closest to the side of the die 18 to which each individual base or basic insulating layer 66 is adjacent, and across a portion of the top of the die 18.

[0086] [Figure 52B] 52B is a cross-sectional view of the electronic assembly of FIG. 52A taken along various reference lines. [Figure 52C] 52B is a cross-sectional view of the electronic assembly of FIG. 52A taken along various reference lines. [Fig. 52D] 52B is a cross-sectional view of the electronic assembly of FIG. 52A taken along various reference lines. [Figure 52E] 52B is a cross-sectional view of the electronic assembly of FIG. 52A taken along various reference lines. [Fig. 52F]52B is a cross-sectional view of the electronic assembly of FIG. 52A taken along various reference lines. [Fig. 52G] 52B is a cross-sectional view of the electronic assembly of FIG. 52A taken along various reference lines. [Fig. 52H] 52B is a cross-sectional view of the electronic assembly of FIG. 52A taken along various reference lines. [Fig. 52I] 52B is a cross-sectional view of the electronic assembly of FIG. 52A taken along various reference lines. [Fig. 52J] 52B is a cross-sectional view of the electronic assembly of FIG. 52A taken along various reference lines. [Figure 52K] 52B is a cross-sectional view of the electronic assembly of FIG. 52A taken along various reference lines. [Figure 52L] 52B is a cross-sectional view of the electronic assembly of FIG. 52A taken along various reference lines. [Figure 52M] 52B is a cross-sectional view of the electronic assembly of FIG. 52A taken along various reference lines. [Fig. 52N] 52B is a cross-sectional view of the electronic assembly of FIG. 52A taken along various reference lines. [Fig. 52O] 52B is a cross-sectional view of the electronic assembly of FIG. 52A taken along various reference lines. [Figure 52P] 52B is a cross-sectional view of the electronic assembly of FIG. 52A taken along various reference lines. [Fig. 52Q] 52B is a cross-sectional view of the electronic assembly of FIG. 52A taken along various reference lines. [Fig. 52R] 52B is a cross-sectional view of the electronic assembly of FIG. 52A taken along various reference lines.

[0087] [Figure 53A]5 is a top view of a manufactured electronic assembly according to 500 of FIG. 5 with implementation at 514, in which an individual overlying insulating layer 80 has been printed, deposited, formed, or otherwise applied over the exposed portions of the blanket base or basic insulating layer 52 and the exposed portions of the conductive traces or interconnects 74 on the base or basic insulating layer 52 (see FIGS. 40A and 40B ), covering portions of the top surfaces of the lead fingers 12 in the premolded lead frame 46, across the premolded lead frame 42, over one side of the die 18, across the top of the die 18, under the opposite side of the die 18, across the premolded lead frame 42 on the opposite side of the premolded lead frame 46, and covering portions of the top surfaces of the lead fingers 12 on the opposite side of the premolded lead frame 46.

[0088] [Figure 53B] 53B is a cross-sectional view of the electronic assembly of FIG. 53A taken along various reference lines. [Figure 53C] 53B is a cross-sectional view of the electronic assembly of FIG. 53A taken along various reference lines. [Fig. 53D] 53B is a cross-sectional view of the electronic assembly of FIG. 53A taken along various reference lines. [Figure 53E] 53B is a cross-sectional view of the electronic assembly of FIG. 53A taken along various reference lines. [Fig. 53F] 53B is a cross-sectional view of the electronic assembly of FIG. 53A taken along various reference lines. [Figure 53G] 53B is a cross-sectional view of the electronic assembly of FIG. 53A taken along various reference lines. [Fig. 53H] 53B is a cross-sectional view of the electronic assembly of FIG. 53A taken along various reference lines. [Fig. 53I] 53B is a cross-sectional view of the electronic assembly of FIG. 53A taken along various reference lines. [Fig. 53J] 53B is a cross-sectional view of the electronic assembly of FIG. 53A taken along various reference lines. [Figure 53K] 53B is a cross-sectional view of the electronic assembly of FIG. 53A taken along various reference lines. [Figure 53L] 53B is a cross-sectional view of the electronic assembly of FIG. 53A taken along various reference lines. [Figure 53M] 53B is a cross-sectional view of the electronic assembly of FIG. 53A taken along various reference lines. [Figure 53N] 53B is a cross-sectional view of the electronic assembly of FIG. 53A taken along various reference lines. [Fig. 53O] 53B is a cross-sectional view of the electronic assembly of FIG. 53A taken along various reference lines. [Figure 53P] 53B is a cross-sectional view of the electronic assembly of FIG. 53A taken along various reference lines. [Figure 53Q] 53B is a cross-sectional view of the electronic assembly of FIG. 53A taken along various reference lines. [Figure 53R] 53B is a cross-sectional view of the electronic assembly of FIG. 53A taken along various reference lines.

[0089] [Figure 54A] 5 is a top view of an electronic assembly that has undergone fabrication in accordance with 500 of FIG. 5 using the implementation at 514, in which individual overlying insulating layers 80 have been printed, deposited, formed, or otherwise applied over the exposed portions of the half blanket base or basic insulating layer 64 and the exposed portions of the conductive traces or interconnects 74 on the half blanket base or basic insulating layer 66 (see FIGS. 41A and 41B), each over a portion of the top surface of the lead fingers 12 in the pre-molded lead frame 46, across the pre-molded lead frame 42, over one side of the die 18, and across the top of the die 18 just beyond the top of the bond pad 50 closest to the side of the die 18 to which the respective half blanket base or basic insulating layer 64 is adjacent.

[0090] [Figure 54B] 54B is a cross-sectional view of the electronic assembly of FIG. 54A taken along various reference lines. [Fig. 54C] 54B is a cross-sectional view of the electronic assembly of FIG. 54A taken along various reference lines. [Fig. 54D] 54B is a cross-sectional view of the electronic assembly of FIG. 54A taken along various reference lines. [Figure 54E] 54B is a cross-sectional view of the electronic assembly of FIG. 54A taken along various reference lines. [Fig. 54F] 54B is a cross-sectional view of the electronic assembly of FIG. 54A taken along various reference lines. [Figure 54G] 54B is a cross-sectional view of the electronic assembly of FIG. 54A taken along various reference lines. [Fig. 54H] 54B is a cross-sectional view of the electronic assembly of FIG. 54A taken along various reference lines. [Fig. 54I] 54B is a cross-sectional view of the electronic assembly of FIG. 54A taken along various reference lines. [Fig. 54J] 54B is a cross-sectional view of the electronic assembly of FIG. 54A taken along various reference lines. [Figure 54K] 54B is a cross-sectional view of the electronic assembly of FIG. 54A taken along various reference lines. [Figure 54L] 54B is a cross-sectional view of the electronic assembly of FIG. 54A taken along various reference lines. [Figure 54M] 54B is a cross-sectional view of the electronic assembly of FIG. 54A taken along various reference lines. [Fig. 54N] 54B is a cross-sectional view of the electronic assembly of FIG. 54A taken along various reference lines. [Fig. 54O] 54B is a cross-sectional view of the electronic assembly of FIG. 54A taken along various reference lines. [Figure 54P] 54B is a cross-sectional view of the electronic assembly of FIG. 54A taken along various reference lines. [Fig. 54Q] 54B is a cross-sectional view of the electronic assembly of FIG. 54A taken along various reference lines. [Fig.54R] 54B is a cross-sectional view of the electronic assembly of FIG. 54A taken along various reference lines.

[0091] [Figure 55A]5A is a top view of an electronic assembly that has been manufactured according to the exemplary method 500 of FIG. 5 with implementation at 514, in which individual covering insulating layers 80 are printed, deposited, formed, or otherwise applied (see FIGS. 42A and 42B) over the exposed portions of each individual base or base insulating layer 66 and the exposed portions of each conductive trace or interconnect 74 on each individual blanket base or base insulating layer 66, each across a portion of the top surface of a lead finger 12 in the pre-molded lead frame 46, across the pre-molded lead frame 42, on one side of the die 18, just beyond the bond pad 50 closest to the side of the die 18 to which each individual base or base insulating layer 66 is adjacent, and across a portion of the top of the die 18.

[0092] [Figure 55B] 55B is a cross-sectional view of the electronic assembly of FIG. 55A taken along various reference lines. [Figure 55C] 55B is a cross-sectional view of the electronic assembly of FIG. 55A taken along various reference lines. [Fig. 55D] 55B is a cross-sectional view of the electronic assembly of FIG. 55A taken along various reference lines. [Figure 55E] 55B is a cross-sectional view of the electronic assembly of FIG. 55A taken along various reference lines. [Fig. 55F] 55B is a cross-sectional view of the electronic assembly of FIG. 55A taken along various reference lines. [Figure 55G] 55B is a cross-sectional view of the electronic assembly of FIG. 55A taken along various reference lines. [Fig. 55H] 55B is a cross-sectional view of the electronic assembly of FIG. 55A taken along various reference lines. [Fig. 55I] 55B is a cross-sectional view of the electronic assembly of FIG. 55A taken along various reference lines. [Fig. 55J] 55B is a cross-sectional view of the electronic assembly of FIG. 55A taken along various reference lines. [Figure 55K] 55B is a cross-sectional view of the electronic assembly of FIG. 55A taken along various reference lines. [Figure 55L] 55B is a cross-sectional view of the electronic assembly of FIG. 55A taken along various reference lines. [Figure 55M]55B is a cross-sectional view of the electronic assembly of FIG. 55A taken along various reference lines. [Fig. 55N] 55B is a cross-sectional view of the electronic assembly of FIG. 55A taken along various reference lines. [Fig. 55O] 55B is a cross-sectional view of the electronic assembly of FIG. 55A taken along various reference lines. [Figure 55P] 55B is a cross-sectional view of the electronic assembly of FIG. 55A taken along various reference lines. [Fig. 55Q] 55B is a cross-sectional view of the electronic assembly of FIG. 55A taken along various reference lines. [Fig. 55R] 55B is a cross-sectional view of the electronic assembly of FIG. 55A taken along various reference lines.

[0093] [Figure 56A] The die 18 is shown attached to a pre-molded lead frame 46 prior to application of the insulating material for the second insulating layer.

[0094] [Figure 56B] The results of multiple successive passes of printing of cover layer insulating material by printhead 68 are shown. [Figure 56C] The results of multiple successive passes of printing of cover layer insulating material by printhead 68 are shown. [Figure 56D] The results of multiple successive passes of printing of cover layer insulating material by printhead 68 are shown. [Figure 56E] The results of multiple successive passes of printing of cover layer insulating material by printhead 68 are shown. [Fig. 56F] The results of multiple successive passes of printing of cover layer insulating material by printhead 68 are shown. [Figure 56G] The results of multiple successive passes of printing of cover layer insulating material by printhead 68 are shown. [Fig. 56H] The results of multiple successive passes of printing of cover layer insulating material by printhead 68 are shown. [Fig. 56I] The results of multiple successive passes of printing of cover layer insulating material by printhead 68 are shown. [Fig. 56J] The results of multiple successive passes of printing of cover layer insulating material by printhead 68 are shown. [Figure 56K] The results of multiple successive passes of printing of cover layer insulating material by printhead 68 are shown. [Figure 56L] The results of multiple successive passes of printing of cover layer insulating material by printhead 68 are shown.

[0095] [Figure 57A] 5A and 5B, with mounting at 514, in which a second insulating layer, e.g., a blanket coated insulating layer 76, is printed, deposited, formed, or otherwise applied over the exposed portions of the blanket base or basic insulating layer 52 and the exposed portions of the conductive traces or interconnects 74 on the base or basic insulating layer 52 (see FIGS. 44A and 44), extending over a portion of the top surfaces of the lead fingers 12 in the premolded lead frame 48, across the premolded lead frame 42, over one side of the die 18, across the top of the die 18, down on the opposite side of the die 18, across the premolded mold 42 on the opposite side of the premolded lead frame 48, and to a portion of the top surfaces of the lead fingers 12 on the opposite side of the premolded lead frame 48.

[0096] [Figure 57B] FIG. 57B is a cross-sectional view of the electronic assembly of FIG. 57A taken along reference line K7-K7.

[0097] [Figure 58A]5 is a top view of an electronic assembly that has been manufactured according to the exemplary method 500 of FIG. 5 with implementation at 514, where a second insulating layer, e.g., a blanket over insulating layer 76, has been printed, deposited, formed, or otherwise applied over the exposed portions of the half blanket base or basic insulating layer 64 and the exposed portions of the conductive traces or interconnects 74 on the half blanket base or basic insulating layer 66 (see FIGS. 44A and 44B), each extending over a portion of the top surface of the lead fingers 12 in the pre-molded lead frame 48, across the pre-molded lead frame 42, over one side of the die 18, and just beyond the top of the bond pad 50 closest to the side of the die 18 to which the respective half blanket base or basic insulating layer 64 is adjacent.

[0098] [Figure 58B] FIG. 58B is a cross-sectional view of the electronic assembly of FIG. 58A taken along reference line K8-K8.

[0099] [Figure 59A] 5 is a top view of an electronic assembly that has been manufactured according to the exemplary method 500 of FIG. 5 with implementation at 514, in which a second insulating layer, e.g., a blanket over insulating layer 76, is printed, deposited, formed, or otherwise applied over the exposed portions of the half blanket base or basic insulating layer 64 and the exposed portions of the conductive traces or interconnects 74 on the half blanket base or basic insulating layer 66 (see FIGS. 44A and 44B), each over a portion of the top surface of the lead fingers 12 in the pre-molded lead frame 48, across the pre-molded lead frame 42, over one side of the die 18, and across a portion of the top of the die 18 just beyond the top of the bond pad 50 closest to the side of the die 18 that the respective half blanket base or basic insulating layer 64 is adjacent to.

[0100] [Figure 59B] 59B is a cross-sectional view of the electronic assembly of FIG. 59A taken along various reference lines.

[0101] [Figure 60A]5 with mounting at 514, includes two half blanket coated insulating layers 78, each printed, deposited, formed, or otherwise applied over the exposed portions of the blanket base or basic insulating layer 52 and the exposed portions of the conductive traces or interconnects 74 on the base or basic insulating layer 52 (see FIGS. 40A and 40B), over a portion of the top surface of the lead fingers 12 in the pre-molded lead frame 46, across the pre-molded lead frame 42, over one side of the die 18, across the top of the die 18, down on the opposite side of the die 18, across the pre-molded lead frame 42 on the opposite side of the pre-molded lead frame 46, and over a portion of the top surface of the lead fingers 12 on the opposite side of the pre-molded lead frame 46.

[0102] [Figure 60B] A cross-sectional view of the electronic assembly of Figure 60A along reference line N7-N7.

[0103] [Figure 61A] 5A and 5B, each of which is printed, deposited, formed, or otherwise applied over the exposed portions of the half blanket base or basic insulating layer 64 and the exposed portions of the conductive traces or interconnects 74 on the half blanket base or basic insulating layer 66 (see FIGS. 41A and 41B), each of which extends over a portion of the top surface of the lead fingers 12 in the pre-molded lead frame 46, across the pre-molded lead frame 42, and over one side of the die 18, with each half blanket base or basic insulating layer 64 extending over a portion of the top of the die 18 just beyond a portion of the top of the bond pad 50 closest to the side of the die 18 adjacent to the die 18.

[0104] [Figure 61B] 61B is a cross-sectional view of the electronic assembly of FIG. 61A taken along various reference lines.

[0105] [Figure 62A] 5A and 5B, each printed, deposited, formed, or otherwise applied over the exposed portions of the respective base or base insulating layers 66 and the exposed portions of each conductive trace or interconnect 74 on the respective blanket base or base insulating layers 66 (see FIGS. 42A and 42B), each extending over a portion of the top surface of the lead fingers 12 in the pre-molded lead frame 46, across the pre-molded lead frame 42, over one side of the die 18, just beyond the bond pad 50 closest to the side of the die 18 to which each respective base or base insulating layer 66 is adjacent, and across a portion of the top of the die 18.

[0106] [Figure 62B] A cross-sectional view of the electronic assembly of Figure 62A along reference line N9-N9.

[0107] [Figure 63A] 5 with mounting at 514, which includes individual overlying insulating layers 80, each printed, deposited, formed, or otherwise applied over an exposed portion of a blanket base or basic insulating layer 52 and an exposed portion of a conductive trace or interconnect 74 on the base or basic insulating layer 52 (see FIGS. 40A and 40B), across a portion of the top surface of a lead finger 12 in a premolded lead frame 46, across the premolded lead frame 42, over one side of a die 18, across the top of the die 18, down on the opposite side of the die 18, across the premolded lead frame 42 on the opposite side of the premolded lead frame 46, and across a portion of the top surface of a lead finger 12 on the opposite side of the premolded lead frame 46.

[0108] [Figure 63B] 63B is a cross-sectional view of the electronic assembly of FIG. 63A taken along various reference lines.

[0109] [Fig. 64A] 5, using implementation 514, which includes individual overlying insulating layers 80, each printed, deposited, formed, or otherwise applied over the exposed portions of the half blanket base or basic insulating layer 64 and the exposed portions of the conductive traces or interconnects 74 on the half blanket base or basic insulating layer 66 (see FIGS. 41A and 41B), each spanning a portion of the top surface of the lead fingers 12 in the pre-molded lead frame 46, across the pre-molded lead frame 42, and across a portion of the top of the die 18 just beyond the bond pad 50 closest to the side of the die 18 adjacent to each half blanket base or basic insulating layer 64.

[0110] [Fig. 64B] FIG. 64B is a cross-sectional view of the electronic assembly of FIG. 64A taken along reference line R8-R8.

[0111] [Figure 65A] 5 is a top view of an electronic assembly that has been manufactured according to the exemplary method 500 of FIG. 5 using implementation 514, which includes individual blanket insulating layers 80, each printed, deposited, formed, or otherwise applied over the exposed portions of each individual base or base insulating layer 66 and the exposed portions of each conductive trace or interconnect 74 on each individual blanket base or base insulating layer 66 (see FIGS. 42A and 42B), each spanning a portion of the top surface of a lead finger 12 in the pre-molded lead frame 46, across the pre-molded lead frame 42, and onto one side of the die 18, and across a portion of the top of the die 18 just beyond the bond pad 50 closest to the side of the die 18 to which each individual base or base insulating layer 66 is adjacent.

[0112] [Figure 65B] A cross-sectional view of the electronic assembly of Figure 65A along reference line R9-R9.

[0113] [Figure 66A] FIG. 1 is a top view of a packaged semiconductor device using plastic encapsulation.

[0114] [Figure 66B] FIG. 66B is a side view of the packaged device of FIG. 66A.

[0115] [Figure 67A] FIG. 1 is a top view of a (COL) packaged semiconductor device using plastic encapsulation.

[0116] [Figure 67B] FIG. 67B is a side view of the (COL) packaged device of FIG.

[0117] [Figure 68] Demonstrating multiple encapsulation options including lamination, transfer molding, injection molding, casting, potting, 3D printing, scribe dispensing, screen printing, spray coating, spin coating, dipping, and dam and fill.

[0118] [Figure 69A] 1 shows a schematic diagram of the package assembly process described above from manufacturing or selecting a leadframe through molding and device singulation. [Figure 69B] 1 shows a schematic diagram of the package assembly process described above from manufacturing or selecting a leadframe through molding and device singulation.

[0119] [Figure 70] A side view of a packaged semiconductor device 84 is shown soldered or otherwise electrically connected to a printed wiring board (PWB) that is used to perform its designed function.

[0120] [Figure 71] 1 is a schematic diagram of an exemplary inkjet printing apparatus.

[0121] [Figure 72] 1 is a schematic diagram of an example aerosol jet printing device.

[0122] [Figure 73] 1 is a schematic diagram of an exemplary ultrasonic spray printing apparatus.

[0123] [Figure 74] FIG. 1 is a schematic diagram of a micro-dispensing printing apparatus.

[0124] [Figure 75] FIG. 1 is a schematic diagram of an EHD / electrospray printing apparatus.

[0125] [Figure 76] FIG. 1 is a schematic diagram of a laser-induced forward transfer (LIFT) printing device.

[0126] [Figure 77A] FIG. 11 is a top view of an electronic assembly manufactured according to example method 500 of FIG. 5 using the implementation at 1102 of FIG. 11, which allows multiple interconnect shapes, sizes, materials, and contacts to be formed on a single die.

[0127] [Fig. 77B] 77B is a cross-sectional view of the electronic assembly of FIG. 77A taken along various reference lines;

[0128] [Fig. 78A] It shows a step gradient where there is a discrete step boundary between the conductive interconnect and the insulating layer such that different printing inks are used, one for the conductive and the other for the insulating.

[0129] [Fig. 78B] An alternative example to the discrete step boundaries shown in FIG. 78A is shown, where there is a proposed gradient transition between the conductive interconnect layer and the insulating layer, where the printer contains a mixture of the two contact materials with a gradually changing mixture ratio.

[0130] [Figure 79A] 1 shows an alternative implementation for a print package. [Figure 79B] 1 shows an alternative implementation for a print package. [Figure 79C] 1 shows an alternative implementation for a print package. [Fig. 79D] 1 shows an alternative implementation for a print package. [Figure 79E] 1 shows an alternative implementation for a print package. [Fig. 79F] 1 shows an alternative implementation for a print package. [Fig. 79G] 1 shows an alternative implementation for a print package. [Fig. 79H] 1 shows an alternative implementation for a print package.

[0131] [Figure 80A] A commercially available inkjet printer is shown.

[0132] [Figure 80B] Individual printing nozzles for providing individually controlled flows of specific materials are shown, which can be moved along the X, Y, and Z axes shown in FIG. 80C.

[0133] [Fig. 80C] The X, Y and Z axes are shown.

[0134] [Figure 81A] A nozzle row is shown for replacing the individual print nozzles of FIG. 80B.

[0135] [Fig. 81B] A nozzle bank is shown for replacing the individual printing nozzles of FIG. 80B.

[0136] [Fig. 81C] FIG. 80C shows a nozzle system for replacing the individual printing nozzles of FIG.

[0137] [Figure 82] Exemplary printing systems for printing base insulating layers, conductive interconnects, capping insulating layers, and protective layers according to the above-mentioned embodiments are shown, which have sequentially arranged banks of printing nozzles and an integrated curing system that allows for manufacturability and material flexibility. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0138] In the drawings, like reference numerals refer to like elements throughout, and various features are not necessarily drawn to scale. In the following description and claims, the terms "including," "includes," "having," "has," "with," or variations thereof, are inclusive, similar to the term "comprising," and therefore mean "including, but not limited to." Also, the term "couple" refers to, for example, when a first device couples to or is coupled to a second device, the connection may be through a direct electrical connection or through an indirect electrical connection via one or more intervening devices and connections.

[0139] The terms "semiconductor die" and "semiconductor device" are used herein and are synonymous. As used herein, "semiconductor die" refers to a die formed using semiconductor materials. Examples include dies containing integrated circuits, in which hundreds or thousands of transistors are formed and coupled together using patterned conductors to perform a desired function. Further examples include dies containing passive devices such as resistors, capacitors, inductors, and diodes formed on a semiconductor substrate. Discrete devices such as one or a few power field effect transistors (FETs), bipolar junction transistors (BJTs), rectifiers, and amplifiers formed on a semiconductor substrate are also examples of semiconductor dies. Analog-to-digital converters, RF filters, transceivers, photocells, photodiodes, digital micromirror devices (DMDs), and transformers are further examples of semiconductor dies. As used herein, a "packaged semiconductor device" or a "packaged electronic device" is a semiconductor die mounted on a substrate having leads or terminals and covered, in whole or in part, with a mold compound or other protective material.

[0140] The term "lead frame" or "leadframe" is used herein. As used herein, "lead frame" or "leadframe" is a metal structure in a semiconductor chip / die package that carries signals or power from the chip / die to the outside of the package or vice versa. Leadframes can be made from Cu or alloys of Cu. Laminates (substrates, PCBs, etc.), brass, steel, aluminum, etc. can be formed from alternative choices. Metal leadframes can be pre-plated with NiPdAu, NuPd, NuPdAgAu, Ag spots, Cu, NiSn, Sn, etc. Bare Cu leadframes are also an option. The finish of the leadframe can be further roughened to improve adhesion.

[0141] The term "inkjet deposition" is used herein for an exemplary process of depositing material. As used herein, "inkjet deposition" means depositing material from a liquid in a reservoir that feeds a nozzle by forming droplets in response to an electrical signal as the nozzle moves relative to a surface. An inkjet deposition tool may have tens, hundreds, or even more nozzles. In printing, the material is ink, and the inkjet deposition process is referred to as "inkjet printing." In the deposition of materials in manufacturing, the liquid being deposited may be referred to as "ink," and as used herein, the term "ink" may include solders, dielectrics, conductive materials, adhesives, and polymers as used in such arrangements. Inkjet deposition allows for precise placement of material by using "drop-on-demand" (DOD) technology, in which a reservoir of liquid has a nozzle and a small amount of liquid is extruded from the nozzle in response to an electrical signal. The liquid forms droplets as it falls vertically onto a surface. The precision of an inkjet deposition tool allows the deposition of liquid material in some areas and not in others as the tool moves across the surface (or as the surface moves under the tool if the tool is fixed). The reservoir can contain a piezoelectric actuator that responds to an electrical signal or, in a thermal inkjet deposition tool, expels a known volume of ink through a nozzle, where the liquid is rapidly heated by a resistive element in the reservoir, expanding and forcing a known volume of liquid through the nozzle. The liquid forms droplets that move vertically to land on the surface where the material is to be deposited. Because the material can be placed very precisely, even if small, no etching or material removal steps are required to remove the material after inkjet deposition. Also, the material is used very efficiently with little waste when compared to spin-coating, screen-print deposition, or slit-print deposition processes. Multiple inkjet deposition passes can be used to build up thicker layers of material.

[0142] The terms "screen print deposition" and "slit print deposition" are used herein. As used herein, screen print deposition refers to using a stencil to cover areas excluded from deposition and drag liquid ink across the stencil while openings in the stencil allow deposition in those areas. As used herein, slit print deposition means using a slit in a tool that is moved across the substrate as ink flows through the slit to deposit material onto the substrate.

[0143] Quad Flat No Leads packages (QFN) are devices that are widely used in the consumer electronics market. QFN devices have been around for about 20 years. Unlike leaded devices, in QFN packages, the electrical contacts or terminals are inserted into the mold cap. See Figure 1, nothing extends from the Q-FN device for surface mounting. This feature of leadless packages (QFN and SON) allows them to be small, on the order of chip scale.

[0144] A QFN device 10 begins with a leadframe having a die attach pad 14, which can also function as a thermal pad, and leads 12, see FIG. 2. In at least one example, the leadframe is constructed of 200 um (or 8 mils) thick copper material, with the leads being 200 mm wide. An integrated circuit (IC) die 18 is then attached to the top side of the die attach pad via die attach material 22. Wire bonds 20 are then formed between the leadframe leads 12 and the electrical contacts or terminals of the IC die 18. Finally, the resulting combination of IC die, die support pad, leadframe, and bond wires is encapsulated with a mold compound 16. Plastic is often used as the mold compound, although other materials, including ceramic, can be used. In an exemplary QFN manufacturing process 34, there are multiple QFN devices 10 on a leadframe strip 36 that are block molded / encapsulated together (see FIG. 3). The QFN device 10 is then singulated to produce individual QFN devices or units (see FIGS. 1 and 2). The bottom flat surface of the QFN device is the only contact surface for attachment to a printed wiring board (PWB). The leads 12 and die attach / thermal pad 14 are not covered by a plastic molding / encapsulant 16. The exposed surface of the die attach / thermal pad 14 can be soldered to corresponding pads on the PWB or attached with other thermally conductive die attach material. The leads 12 of the QFN device 10 can be soldered to corresponding electrical contacts or terminals on the PWB. FIG. 4 is a side cross-sectional view of the QFN device 10 taken along reference line AA in FIG. 2.

[0145] Wire bonding, as shown above in device 10, is essentially a unit process that uses standard wire sizes (and materials) to make one bond at a time. Packages such as Wireless Chip Scale Packages (WCSPs) limit the ability to utilize very small die. Due to the geometry of the wire bond loops, the subsequent step of encapsulation may be done with transfer molding, which is also a complex process. The wire bonding and molding processes also severely limit the size of the strip (lead frame) that can be processed through each process. This limits the ability to reduce productivity and costs associated with manufacturing. Also, in addition to the manufacturing and cost issues associated with wire bonded devices, dies designed for higher operating frequencies, such as those encountered in mmWave devices (20-300 GHz), make wire bonded interconnects lossy, causing input signals to reflect away from the signal's intended destination. As a result of all of these issues, as die sizes continue to shrink and / or die operating frequencies continue to increase, alternative interconnect technologies for wire bonding are needed.

[0146] FIG. 5 illustrates a method for manufacturing a packaged electronic device that overcomes many of the above-mentioned problems and limitations of wire bond interconnects between leadframe leads and bond pads on a die attached to the leadframe. The method includes, among other things, printing conductive interconnects between bond pads on an integrated circuit die to corresponding leads of a leadframe to which the integrated circuit is attached. Illustrated examples of printing include inkjet printers, scribe dispense, aerosol jet, μTP, laser transfer, spray, EHD, microdispense, etc., to print or deposit conductive inks, conductive polymers, metal-filled epoxies, sintered metal powders, liquid-assisted sintered particles, or solder pastes to form conductive traces and / or contacts. In one example, the method 500 includes manufacturing a leadframe at 502, which may include manufacturing a leadframe strip having a plurality of leadframes or leadframe units. Alternatively, the leadframe strip may instead be obtained from a company that manufactures the desired leadframe strip. Wafer processing at 504 is used to manufacture a plurality of desired integrated circuit devices or dies on the wafer. Die singulation is performed at 506 to separate the multiple die wafer into individual integrated circuit dies. Alternatively, individual integrated circuit dies can be obtained instead from a company that manufactures the desired integrated circuit dies. The integrated circuit dies are then attached to the leadframe unit at 508 using epoxy, silicone, solder, sintered metal, hybrid polymer, or other adhesive. After the integrated circuit die is attached to the leadframe unit, a base or basic insulating layer is applied at 510 that spans from the bond pads on the die to the respective lead fingers of the leadframe unit. The insulating layer can be a polymer, epoxy, silicone, mold, or other insulating material.At 512, conductive traces are formed between bond pads on the die to respective lead fingers on the leadframe unit by depositing or otherwise forming a conductive ink, conductive polymer, metal-filled epoxy, sintered metal powder, liquid assisted sintered particles, or solder paste on a base insulative layer from the bond pads on the die to the respective lead fingers on the leadframe unit. At 514, a coating or second insulating layer is applied over the exposed portions of the conductive traces. At 516, a protective coating is applied over the uncoated or exposed portions of the die, base insulative layer, second insulating layer, and leadframe leads. The coated die / leadframe is then singulated and removed from the leadframe strip at 518.

[0147] 6-16 show various exemplary variations on the method for manufacturing a packaged electronic device shown in FIG. 5, each of which results in a different embodiment or example. FIG. 6 shows one exemplary method for manufacturing a packaged electronic device 600 that modifies the method of FIG. 5 between steps 502 and 504. This example includes pre-molding the leadframe at step 602 prior to wafer processing at step 504. Alternatively, pre-molding the leadframe can occur at any time after manufacturing the leadframe at step 502 and immediately prior to applying the insulating layer at step 510. FIG. 7 shows another exemplary method for manufacturing a packaged electronic device 700 that modifies the method of FIG. 5 between steps 510 and 512. This example includes curing the insulating layer at step 702 prior to applying conductive traces on the insulating layer from bond pads on the die to the leadframe leads. FIG. 8 shows yet another exemplary method for manufacturing a packaged electronic device 800 that modifies the method of FIG. 5 between steps 508 and 512. This example includes replacing the step of applying an insulating layer on a basis from the bond pads on the die to the leadframe leads in step 510 of Figure 5 with applying an insulating layer in multiple thin passes on a basis from the bond pads on the die to the leadframe leads in step 802. This step essentially replaces the single pass application of a base insulating layer in step 510 of Figure 5 with a multi-pass base layer in step 802. Figure 9 illustrates yet another exemplary method for manufacturing a packaged electronic device 900 that modifies the method of Figure 5 between steps 512 and 514. This example includes curing the conductive traces in step 902 before applying a second insulating layer over the contact traces in step 514.

[0148] FIG. 10 illustrates another exemplary method for manufacturing a packaged electronic device 1000 that modifies the method of FIG. 5 between steps 510 and 514. This example includes replacing the single pass application of conductive traces on the insulating layer from the bond pads on the die to the lead frame leads in step 512 of FIG. 5 with multi-pass conductive traces applied on the insulating layer from the bond pads on the die to the lead frame leads in step 1002. This step essentially replaces the single pass conductive traces in step 512 of FIG. 5 with multi-pass conductive traces in step 1002. FIG. 11 illustrates yet another exemplary method for manufacturing a packaged electronic device 1100 that modifies the method of FIG. 5 between steps 510 and 514. This example includes replacing the conductive traces applied on the insulating layer from the bond pads on the die to the lead frame leads in step 512 of FIG. 5 with conductive traces having multiple shapes, sizes, and / or different materials on the insulating layer from the bond pads on the die to the lead frame leads in step 1102. This step essentially replaces the single shape, size, and / or material trace in step 512 of Figure 5 with a conductive trace having a different shape, size, and / or material in step 1102. Figure 12 illustrates yet another example method for manufacturing a packaged electronic device 1200 that modifies the method of Figure 5 between steps 510 and 514. This example includes replacing the single pass applied conductive trace applied on the insulating layer from the bond pads on the die to the lead frame leads in step 512 of Figure 5 with a conductive trace applied in multiple thin passes having different shapes, sizes, and / or materials in step 1202. This step essentially replaces the single pass conductive trace in step 512 of Figure 5 with a conductive trace applied in multiple thin passes having different shapes, sizes, and / or materials in step 1202.

[0149] FIG. 13 illustrates yet another exemplary method for manufacturing a packaged electronic device 1300 that modifies the method of FIG. 5 between steps 512 and 516. This example includes replacing the single pass second insulating layer over the conductive traces at step 514 of FIG. 5 with a second insulating layer applied in multiple thin passes over the conductive traces at step 1302. FIG. 14 illustrates another exemplary method for manufacturing a packaged electronic device 1400 that modifies the method of FIG. 5 between steps 512 and 516. This example includes replacing the second insulating layer over the conductive traces at step 514 of FIG. 5 with individual second insulating layers over each conductive trace at step 1402. FIG. 15 illustrates another exemplary method for manufacturing a packaged electronic device 1500 that modifies FIG. 5 between steps 512 and 516. This example includes replacing the second insulating layer over the conductive traces in step 514 of Figure 5 with individual second insulating layers in multiple thin passes over each conductive trace in step 1502. Figure 16 illustrates yet another exemplary method for manufacturing a packaged electronic device 1600 that modifies the method of Figure 5 between steps 514 and 518. This example includes replacing step 516 of Figure 5 with applying a protective coating in multiple passes over the exposed portions of the die, lead frame, foundation, and second insulating layer in step 1602. Each of the methods illustrated in Figures 6-16 can be used alone or in combination with one or more other methods to modify the method in Figure 5.

[0150] To overcome the above-mentioned shortcomings of wire bonds, in various implementations, the wire bonds 20 in Figure 4 are replaced with printed conductive traces or interconnects enclosed within first and second insulating layers. Figures 17-92 show packaged electronic devices (e.g., QFN devices in this example) that have undergone fabrication according to the exemplary method of Figure 5, including those modified by various ones of Figures 6-16, or combinations thereof.

[0151] According to one embodiment or example, a process for making a QFN device with printed conductive traces or interconnects begins with the selection or creation of a leadframe strip (e.g., created at 502 in FIG. 5). FIG. 17A is a top view of a QFN leadframe strip 36 including several individual 6-lead or pin leadframe units 37. FIG. 17B is a cross-sectional view of the QFN leadframe strip 36 along reference line BB in FIG. 17A. Multiple leadframe units may comprise a single leadframe strip or a panel. In at least one embodiment of the present invention, the leadframe may be much larger in size than a conventional leadframe since this embodiment does not use conventional wire bonding or conventional molding limited by current manufacturing equipment. An exemplary leadframe is 4-8 mils thick. The leadframe (panel) size is 50×100 mm to 300×200 mm. FIG. 18A is a top view of an individual leadframe unit 38. FIG. 18B is a side view of an individual leadframe unit 38 along reference line CC in FIG. 18A. Figure 19A is a top view of an alternative chip-on-lead (COL) leadframe unit 40 for directly attaching the bottom surface of the die to some of the leads 12, thus eliminating the die attach pad 14 seen in leadframe unit 38 of Figures 18A and 18B. Figure 19B is a side view of an individual leadframe unit 38 along reference line DD of Figure 19A.

[0152] The leadframe may be pre-molded 42 with insulating material such as mold compound, epoxy, polymer, or ceramic (e.g., as fabricated in 602 of FIG. 6) to fill the gaps between the metal sections. Alternatively, a pre-taped leadframe may be used instead of a pre-molded. In such a case, the tape may be sacrificed. The thickness of the pre-molded may be the same as the thickness of the leadframe. For a COL configuration, this step may be skipped. FIG. 20A is a top view of a pre-molded QFN leadframe strip 44. FIG. 20B is a cross-sectional view of the pre-molded QFN leadframe strip 44 along reference line EE of FIG. 20A. FIG. 21A is a top view of a pre-molded leadframe unit 46 on a QFN leadframe strip 46. FIG. 21B is a cross-sectional view of the pre-molded leadframe unit 46 shown in FIG. 21A along reference line FF. FIG. 22A is a top view of a COL leadframe unit with a pre-molded 48. Figure 22B is a cross-sectional view of the pre-molded leadframe unit 46 shown in Figure 22A taken along reference line GG. Alternatively, instead of manufacturing the leadframe strips (e.g., at 502 in Figure 5), the leadframe strips can be obtained from a company that manufactures the desired leadframe strips.

[0153] A semiconductor wafer is processed (e.g., at 504 in FIG. 5 ) to produce a plurality of integrated circuits (ICs) or dies on the wafer according to a well technique to produce dies (not shown) of a desired size, shape, and functionality. Each die portion 18 includes a semiconductor portion (e.g., silicon) and a conductive feature 50 (e.g., copper pad or post). Alternatively, instead of processing a wafer to produce a desired integrated circuit (IC) or die, the desired integrated circuit (IC) or die can be obtained from a company that produces the desired integrated circuit (IC) or die, such as Texas Instruments. The plurality of processed die portions 18 on the wafer are then singulated from the wafer (e.g., at 506 in FIG. 5 ) using a dicing technique such as mechanical sawing, laser, water jet, or other technique sufficient to separate the plurality of die portions into individual singulated dies 18. Alternatively, instead of singulating individual dies 18 on a wafer, the desired singulated dies 18 can be obtained from a company that manufactures the desired integrated circuits (ICs) or dies and singulates the dies 18 into individual dies, such as Texas Instruments, Inc. Although Figure 5 illustrates leadframe fabrication at (502), wafer processing at (504), and die singulation at (506), the order and timing of these steps can be rearranged so long as both the leadframe strip 36 and the leadframe with singulated IC dies are completed and ready for the next processing step.

[0154] To overcome the limitations and drawbacks of wire bonding as an interconnect between a die and a corresponding lead frame and / or lead in a packaged semiconductor device, this specification describes multiple implementations for forming printed and / or deposited conductive traces or interconnects between a die 18 and a corresponding lead frame and / or lead frame components such as lead frame lead 12 instead of forming wire bonds such as wire bond 20. Unlike traditional wire bonding, the proposed implementations deposit or print conductive traces or interconnects between bond pads on the die and conductors on the lead frame. Printed electronics refers to the use of ink-based organic / inorganic materials with electronic properties (metallic, conductive, semiconducting, dielectric) that can be printed on both rigid and flexible substrates to achieve one or several functions in logic / memory based active devices, as well as sensors, batteries, antennas, and / or passive devices such as resistors, inductors, and capacitors. Printing techniques considered for printing electronics include inkjet printers, aerosol jet, μTP, laser transfer, spray, EHD / electrospray, and microdispensing, the advantages and disadvantages of each of which are described below.

[0155] Deposition or printing of conductive traces or interconnects involves multiple steps. Adhesive die attach 22 can be dispensed (or printed) on the top side of die attach pad 14 in pre-molded leadframe unit 46 (see FIGS. 23A and 23B). FIG. 23A is a top view of leadframe 46 of FIG. 21 with a layer of die attach on die attach pad 14. FIG. 23B is a side view of leadframe 46 of FIG. 23A along reference line HH. Die attach 22 can be a die attach tape applied using techniques known in the art, or a liquid or viscous material deposited using other known techniques such as screen printing, photolithography and etching, or CVD, PVD, or vacuum deposition. Alternatively, adhesive die attach 22 can be printed or deposited using inkjet printing, spray coating, microdispensing, aerosol jet, ElectroHydroDynamic (EHD) techniques with suitable adhesive and insulating or conductive properties. Optionally, adhesive die attach 22 can be applied, dispensed (or printed) on the top side of the leads 12 that support the die 18 in a chip-on-lead (COL) pre-molded leadframe unit 48 (see FIGS. 23C and 23D). FIG. 23C is a top view of the leadframe 48 of FIG. 22 with a layer of die attach on the leads 12. FIG. 23D is a side view of the leadframe 48 of FIG. 23C along reference line H1-H1. Alternatively, adhesive die attach 22 can be dispensed instead on the bottom surface of the die 18 instead of the leads 12 of FIGS. 23C and 23D, or instead of the leads 12 of FIGS. 23C and 23D. The die attach 22 can be formed from an epoxy, silicone, solder sintered metal, hybrid polymer, or other adhesive. The die attach 22 can be conductive or insulating depending on the design requirements, including whether heat and / or current is conducted through the die attach pad 14 for a COL configuration or through the leads 12 under the die. The COL configuration requires an insulated die attach to avoid pin shorting.Next, an integrated circuit (IC) die 18 is placed on the leadframe unit and die attach 22 bonds the integrated circuit (IC) die 18 to the pre-molded leadframe unit 46 or, optionally, to the pre-molded leadframe unit 48 (e.g., at 508 in FIG. 5).

[0156] FIG. 24A is a top view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of a premolded leadframe unit 46. FIG. 24B is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of a premolded leadframe unit 46 along reference line II of FIG. 24A. FIG. 24C is a top view of an optional example of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of a lead 12 of a chip-on-lead (COL) premolded leadframe unit 48. FIG. 24D is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a lead 12 of a premolded leadframe unit 48 along reference line I1-I1 of FIG. 24D.

[0157] Figure 25A is a top view of an alternative COL embodiment where there is no die support pad and the integrated circuit (IC) die 18 is attached directly to the leads 12 of the leadframe unit (a non-premolded leadframe is shown in the example of Figure 24A where there is no molding material between the leads 12). Figure 25B is a side view of the alternative COL implementation along reference line JJ of Figure 25A where there is no die support pad and the integrated circuit (IC) die 18 is attached directly to the leads 12 of the leadframe unit.

[0158] Base or Basic Insulation Layer

[0159] 26A-36 illustrate an electronic assembly that has undergone fabrication according to the example method 500 of FIG. 5 with implementation at 510. In one example, in FIG. 26A, a blanket insulating layer 52 is printed, deposited, formed, or otherwise applied (e.g., at 510 in FIG. 5) as a base layer over a portion of the top surfaces of the lead fingers 12 in the premolded lead frame 46, across the premolded 42, on one side of the die 18, across the top of the die 18, across the opposite side of the die 18, across the premolded 42 on the opposite side of the premolded lead frame 46, and over a portion of the top surfaces of the lead fingers 12 on the opposite side of the premolded lead frame 46. Optionally, the blanket insulating layer 52 can be cured at this point (e.g., at 702 in FIG. 7) or later with additional layers. The blanket insulating layer 52 can be a polymer, epoxy, silicone, mold, or other insulator. The insulating layer 52 follows the contours of the topology on the lead frame 46 and the die 18 while smoothing out turns in the Z-axis. The insulating layer 52 is applied to form paths and access for subsequent layers of conductive ink or other conductive material that form conductive interconnects between the bond pads 54 on the die 18 and the leads 12. As seen in FIG. 26A, a blanket insulating layer 52 covers the top surface of the die 18 and the sides of the die 18 adjacent the bond pads 50. The blanket insulating layer 52 can be formed or deposited using one of several techniques, such as screen printing, photolithography and etching, CVD, PVD, vacuum deposition, inkjet printing, spray coating, microdispensing, aerosol jet, ElectroHydroDynamic (EHD) techniques, having suitable insulating properties.

[0160] If inkjet printing is used, the insulating layer 52 can be formed from inkjet deposition compatible polymers such as polyimide inks, thermosetting epoxy-based polymer inks, and UV-curable acrylate inks. To avoid excessive stress on the assembly, it is preferable to use polymers with an elastic modulus of less than 3.4 GPa, more preferably less than 2 GPa. The thickness of the insulating layer 52 can be on the order of 2 μm to 35 μm. A more preferred range is about 2 μm to 20 μm or less, and even more preferably in the range of about 2 μm to about 10 μm. Since the inkjet solvent deposited material has a solvent, i.e., initial thickness, after the solvent dissipates, the remaining material forms an insulating layer with a reduced thickness. Multiple inkjet depositions can be performed (e.g., at 802 in FIG. 8) to achieve the desired thickness. Inkjet deposition allows for precise placement of material by using a "drop-on-demand" (DOD) technique, in which a container of liquid has a nozzle and a small amount of liquid is extruded from the nozzle in response to an electrical signal. The liquid forms droplets as it falls vertically onto a surface.

[0161] The precision of the inkjet deposition tool allows deposition of liquid material in some areas and not in other areas as the tool moves across the surface (or as the surface moves under the tool if the tool is fixed). Because the insulating material can be placed very precisely, even in small areas, no etching or material removal steps are required to remove the material after inkjet deposition. Referring to FIG. 26A, the insulating layer 52 does not cover the through holes or voids 54 over the bond pads 50 on the die 18 or the through holes or voids 56 in the insulating layer 52 over the top surface of each lead 12 on the lead frame 46. With inkjet printing, no etching or material removal steps are required for the through holes or voids 54 or 56 to remove the material after inkjet deposition, reducing material waste and avoiding later etching or ablation steps. The through holes or voids 54 and 56 facilitate later connection of conductive material between the leads 12 on the lead frame 46 and the bond pads 50 on the die 18. To achieve a desired thickness of insulating layer 52, multiple inkjet depositions can be performed (e.g., at 802 in FIG. 8). A single pass deposition increases manufacturing throughput and reduces costs, but may not provide the more accurate and / or desired results of multi-pass deposition. As additional inkjet materials are developed, a reduction in the amount of solvent can reduce the initial thickness required, thereby reducing the need for multi-pass deposition. FIG. 26B is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 along reference line KK in FIG. 26A.

[0162] According to one example, insulating layer 52 is a blanket layer upon which conductive material is deposited from bond pads 50 on die 18 to leads 12. Figure 26C is a cross-sectional view of integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line MM in Figure 26A. Figure 26D is a cross-sectional view of integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line WW in Figure 26A, showing insulating layer 52 extending down from the vertical sides of die 18 to die pad 46.

[0163] According to another example, insulating layer 52 is a blanket layer having rectangular channels or grooves 58 for subsequent conductive material deposited from bond pads 50 on die 18 to leads 12. Figure 26E is a cross-sectional view of integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line MM in Figure 26A. Figure 26F is a cross-sectional view of integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line WW in Figure 26A, showing insulating layer 52 extending down from the vertical sides of die 18 to die pad 46.

[0164] According to yet another example, insulating layer 52 is a blanket layer having semicircular channels 60 formed in blanket layer 52 from bond pads 50 on die 18 to leads 12. FIG. 26G is a cross-sectional view of integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line MM in FIG. 26A. FIG. 26H is a cross-sectional view of integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line WW in FIG. 26A, showing insulating layer 52 extending down from a vertical side of die 18 to die pad 46. According to yet another example, insulating layer 52 is a blanket layer having v-shaped channels 62 formed in blanket layer 52 from bond pads 50 on die 18 to leads 12. Figure 26I is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line MM in Figure 26A. Figure 26J is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line WW in Figure 26A, showing insulating layer 52 extending down from the vertical sides of die 18 to die pad 46. While the above examples of rectangular 58, semicircular 60, and v-shaped 62 channels in blanket layer 52 have been described, other channel configurations are possible and contemplated by this description.

[0165] In another example, in FIG. 27A, instead of using a single blanket insulating layer, two spaced apart half blanket insulating layers 64 are applied as a base layer, each spanning the top surface of a portion of the lead fingers 12 in the pre-molded lead frame 46, across the pre-molded lead frame 42, onto one side of the die 18, and across a portion of the top of the die 18 just beyond the bond pads 50 on the die 18 (e.g., at 510 in FIG. 5). Optionally, the half blanket insulating layer 64 can be cured at this point (e.g., at 702 in FIG. 7) or later with additional layers. The half blanket insulating layers 64 can be polymers, epoxies, silicones, molds, or other insulators. The insulating layers 64 each follow the contours of the topology on the lead frame 46 and the die 18 while smoothing out turns in the Z-axis. The insulating layers 64 are applied to form paths and accesses for subsequent layers of conductive ink or other conductive material. 27A, each half blanket insulating layer 64 covers a portion of the top surface of die 18 just beyond bond pads 50 and the side surface of die 18. Half blanket insulating layers 64 can be formed or deposited using one of several techniques, such as screen printing, photolithography and etching, CVD, PVD, vacuum deposition, inkjet printing, spray coating, microdispensing, aerosol jet, ElectroHydroDynamic (EHD) techniques, having suitable insulating properties.

[0166] If inkjet printing is used, the half blanket insulating layer 64 can be formed from inkjet deposition compatible polymers such as polyimide inks, thermosetting epoxy-based polymer inks, and UV-curable acrylate inks. To avoid excessive stress on the assembly, it is preferable to use polymers with an elastic modulus of less than 3.4 GPa, more preferably less than 2 GPa. The thickness of the insulating layer 64 can be on the order of 2 μm to 35 μm. A more preferred range is about 2 μm to 20 μm or less, and even more preferably in the range of about 2 μm to about 10 μm. Inkjet printer solvent deposited material has a solvent, i.e., initial thickness, and after the solvent dissipates, the remaining material forms an insulating layer with a reduced thickness. Multiple inkjet depositions can be performed (e.g., at 802 in FIG. 8) to achieve the desired thickness. Inkjet deposition allows for precise placement of material by using a "drop-on-demand" (DOD) technique, in which a container of liquid has a nozzle and a small amount of liquid is extruded from the nozzle in response to an electrical signal. The liquid forms droplets as it falls vertically onto a surface.

[0167] The precision of the inkjet deposition tool allows deposition of liquid material in some areas and not in other areas as the tool moves across the surface (or as the surface moves under the tool if the tool is fixed). Because the insulating material can be placed very precisely, even in small areas, no etching or material removal steps are required to remove the material after inkjet deposition. With reference to Figures 27A and 27B, the insulating layer 64 does not cover the through holes or voids 54 over the bond pads 50 on the die 18 or the through holes or voids 56 in the insulating layer 64 over the top surface of each lead 12 on the lead frame 46. With inkjet printing, no etching or material removal steps are required for the through holes or voids 54 or 56 to remove the material after inkjet deposition, reducing material waste and avoiding later etching or ablation steps. The through holes or voids 54 and 56 facilitate later connection of conductive material between the leads 12 on the lead frame 46 and the bond pads 50 on the die 18. To achieve a desired thickness of half blanket insulating layer 64, multiple inkjet depositions can be performed (e.g., at 802 in FIG. 8). A single pass deposition increases manufacturing throughput and reduces costs, but may not provide the most accurate and / or desired results possible with multi-pass deposition. As additional inkjet materials are developed, a reduction in the amount of solvent can reduce the initial thickness required, thereby reducing the need for multi-pass deposition. FIG. 27B is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 along reference line NN in FIG. 27A.

[0168] According to one example, each half blanket insulating layer 64 of FIG. 27A is a blanket layer that does not have channels or grooves in which conductive material is deposited from bond pads 50 on die 18 to corresponding leads 12. FIG. 27C is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line PP of FIG. 27A. FIG. 27D is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line QQ of FIG. 27A, showing insulating layer 64 extending down from a vertical side of die 18 to die pad 46. According to another example, each half blanket insulating layer 64 of FIG. 27E is a blanket layer having rectangular channels 58 formed in blanket layer 52 from bond pads 50 on die 18 to corresponding leads 12, where conductive material is deposited from bond pads 50 on die 18 to corresponding leads 12. FIG. 27E is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line PP of FIG. 27A. FIG. 27F is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line QQ of FIG. 27A, showing insulating layer 64 extending down from a vertical side of die 18 to die pad 46.

[0169] According to yet another example, each half blanket insulating layer 64 is a blanket layer having semicircular channels 60 formed in blanket layer 64 from bond pads 50 on die 18 to leads 12, where conductive material is deposited from bond pads 50 on die 18 to corresponding leads 12. FIG. 27G is a cross-sectional view of integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line PP in FIG. 27A. FIG. 27H is a cross-sectional view of integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line QQ in FIG. 27A, showing insulating layer 64 extending down from a vertical side of die 18 to die pad 46. According to yet another example, each half blanket insulating layer 64 is a blanket layer having a v-shaped channel 62 formed in the blanket layer 64 from a bond pad 50 on the die 18 to a lead 12, in which a conductive material is deposited from the bond pad 50 on the die 18 to the corresponding lead 12. FIG. 27I is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of a die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line PP in FIG. 27A. FIG. 27J is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of a die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line QQ in FIG. 27A, showing the insulating layer 64 extending down from a vertical side of the die 18 to the die pad 46. Although the above examples of rectangular 58, semicircular 60, and v-shaped 62 channels in the blanket layer 64 have been described, other channel configurations are possible and contemplated by this description.

[0170] In another example, in FIG. 28A, an individual insulating layer 66 is used in place of the blanket insulating layer 52 of FIGS. 26A-J or the half blanket insulating layer 64 of FIGS. 27A-J. Each individual insulating layer 66 is a base layer for a conductive layer that is subsequently applied or deposited. Each individual insulating layer 66 extends over a portion of the top surface of an individual lead finger 12 in the pre-molded lead frame 46, across the pre-molded lead frame 42, onto one side of the die 18, and across the top of the die 18 just beyond the single bond pad 50 on one side of the die 18 (e.g., at 510 in FIG. 5). Each insulating layer 66 can be a polymer, epoxy, silicone, mold, or other insulator. Each insulating layer 66 follows the contours of the topology on the lead frame 46 and the die 18 while smoothing out turns in the Z-axis. Each insulating layer 66 forms a path or base and access for a subsequent layer of conductive ink or other conductive material to be applied thereover. As seen in FIG. 28A, each insulating layer 66 surrounds a bond pad 50 on the die 18 and has a hole, void, or opening 56 in the insulating layer 66 over the bond pad 50. Each insulating layer 64 extends from the respective bond pad 50 over the top surface of the die 18, down the side of the die 18 closest to the bond pad 50 and lead frame 46, across the pre-mold 42, to the leads 12 on the other side of the pre-mold 42. A hole, void, or opening 54 is formed in the insulating layer 64 over the top of each lead 12. The insulating layer 66 can be formed or deposited using one of several techniques, such as screen printing, photolithography and etching, CVD, PVD, vacuum deposition, inkjet printing, spray coating, microdispensing, aerosol jet, ElectroEly Dynamic (EHD) techniques, having suitable insulating properties.

[0171] If inkjet printing is used, the insulating layer 66 can be formed from inkjet deposition compatible polymers such as polyimide inks, heat cured epoxy-based polymer inks, and UV cured acrylate inks. To avoid excessive stress on the assembly, it is preferable to use polymers with a modulus of elasticity less than 3.4 GPa, more preferably less than 2 GPa. The thickness of the insulating layer 66 can range from about 2 μm to 35 μm. A more preferred range is about 2 μm to 20 μm or less, and even more preferably from about 2 μm to about 10 μm. Inkjet printer solvent deposited materials have a solvent, i.e., initial thickness, and after the solvent dissipates, the remaining material forms an insulating layer with a reduced thickness. Optionally, individual insulating layers 66 can be cured at this point (e.g., at 702 in FIG. 7) or later with additional layers. Multiple inkjet depositions can be performed (e.g., at 802 in FIG. 8) to achieve the desired thickness. Inkjet deposition allows for precise placement of materials by using "drop-on-demand" (DOD) technology, in which a container of liquid has a nozzle and small amounts of liquid are forced out of the nozzle in response to an electrical signal. The liquid forms droplets as it falls vertically onto a surface.

[0172] The precision of the inkjet deposition tool allows deposition of liquid material in some areas as it traverses across the surface (or as the surface moves under the tool if the tool is fixed) and precludes deposition of liquid material in other areas (such as holes, voids, or openings 54 and 56). Because the insulating material can be placed very precisely even in small areas, no etching or material removal steps are required to remove material (e.g., to form holes, voids, or openings 54 and 56) after inkjet deposition. With reference to FIG. 28A, the individual insulating layer 66 does not cover the through-holes, voids, or openings 54 over the bond pads 50 on the die 18, or the through-holes, voids, or openings 56 in the insulating layer 66 over the top surface of each lead 12 on the lead frame 46. With inkjet printing, no etching or material removal steps are required for the through-holes or voids 54 or 56 to remove material after inkjet deposition, which reduces material waste and avoids a later etching or ablation step. The through holes, voids, or openings 54 and 56 facilitate subsequent connection of conductive material between the leads 12 on the lead frame 46 and the corresponding bond pads 50 on the die 18. To achieve the desired thickness of the half blanket insulating layer 66, multiple inkjet depositions can be performed (e.g., at 802 in FIG. 8). A single pass deposition increases manufacturing throughput and reduces costs, but may not produce the same precisely defined features as a multi-pass deposition. As additional inkjet materials are developed, a reduction in the amount of solvent can reduce the initial thickness required, thereby reducing the need for multi-pass depositions. FIG. 28B is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of the die attach pad 14 of the pre-molded lead frame unit 46 along reference line RR in FIG. 28A.

[0173] According to one example, each insulating layer 66 is an individual insulating layer that does not have channels or grooves for subsequent conductive material deposited up from bond pads 50 on die 18 to leads 12. Figure 28C is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line TT in Figure 28A. Figure 28D is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line UU in Figure 28A, showing the insulating layer extending down from the vertical side of die 18 to die pad 46.

[0174] According to another example, each insulating layer 66 is an individual insulating layer with a rectangular shaped channel or groove for subsequent conductive material deposited from bond pad 50 on die 18 to leads 12. Fig. 28E is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line TT in Fig. 28A, showing each insulating layer 66 having a rectangular channel or groove 58 in the top surface of die 18. Fig. 28F is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line UU in Fig. 28A, showing the insulating layer extending down from the vertical side of die 18 to die pad 46. According to yet another example, each insulating layer 66 is an individual insulating layer with a semicircular channel or groove for subsequent conductive material deposited in from bond pad 50 on die 18 to leads 12. FIGURE 28G is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line TT in FIGURE 28A, showing each insulating layer 66 having a semicircular channel or groove 60 on the top surface of die 18. FIGURE 28H is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line UU in FIGURE 28A, showing the insulating layer extending down from the vertical side of die 18 to die pad 46.

[0175] According to yet another example, each insulating layer 66 in FIG. 28E is an individual insulating layer formed with a v-shaped channel or groove 62 for subsequent conductive material deposited in from bond pad 50 on die 18 to lead 12. FIG. 28I is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line TT in FIG. 28A. FIG. 28J is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line UU in FIG. 28A, showing that each insulating layer 66 extends from the top surface of die 18 down the side of die 18 to the top surface of leadframe 46. While the above examples of rectangular 58, semicircular 60, and v-shaped 62 channels in blanket layer 64 have been described, other channel configurations are possible and contemplated hereby.

[0176] The individual insulating layers 66 can be formed or deposited using one of several techniques. The insulating layers 66 can be formed from inkjet deposition compatible polymers such as polyimide inks, heat curable epoxy-based polymer inks, and UV curable acrylate inks. To avoid excessive stress on the assembly, it is preferable to use polymers with an elastic modulus of less than 3.4 GPa, more preferably less than 2 GPa. The thickness of the insulating layer 52 can be on the order of 2 μm to 35 μm. A more preferred range is about 2 μm to 20 μm or less, and even more preferably in the range of about 2 μm to about 10 μm. Inkjet printer solvent deposited material has a solvent, i.e., initial thickness, and after the solvent dissipates, the remaining material forms an insulating layer with a reduced thickness. To achieve the desired thickness, multiple inkjet depositions can be performed (e.g., at 802 in FIG. 8). Inkjet deposition allows for precise placement of material by using a "drop-on-demand" (DOD) technique, in which a reservoir of liquid has a nozzle and a small amount of liquid is extruded from the nozzle in response to an electrical signal. Liquids form droplets when dropped vertically onto a surface.

[0177] 29A-29L show an example where a non-screen printing process 800 is performed with a printhead 68 controlled to translate along a controlled lateral direction or path 70 while directing insulating material along a vertical direction 72 to obtain a desired profile of a blanket insulating layer 52 (e.g., FIGS. 26A-26J), a half blanket insulating layer 64 (e.g., FIGS. 27A-27J), or an individual insulating layer 66 (e.g., FIGS. 28A-28J). In one example, the process is performed with an inkjet printhead 68 having a position controller, such as a servo controller, configured to translate and control the position of the printhead 68 in three dimensions (e.g., the X and Y directions shown in the figures, and the orthogonal Z direction off-page in FIGS. 29A-29L). In one implementation, the printing system translates the printhead 68 in the XZ plane while controlling the Y-direction spacing between the top side of the leadframe 46, the die 18, and the printhead 68. The printing system in one example also controls the supply of insulating material from the nozzles of the print head to print on and off, for example, to facilitate precise, high-resolution control over where insulating material is printed and not printed. The non-screen printing process 800 also provides control over the thickness (e.g., in the Y direction) of the deposited insulating material via one or more of the deposition rate and controlling the time that the print head 68 is positioned over a particular area of ​​the lead frame 46 and / or die 18. This facilitates printing different thicknesses of insulating material in different locations in a particular implementation.

[0178] To obtain the desired contours of the insulating layers 52, 64, and 66 along the non-horizontal surfaces, the insulating material may be formed or applied in multiple passes, with each pass dispensing viscous material on the Z dimension only at the desired XY location. The viscosity of the material, as well as exposure to temperature, light, or gas, can hold the partially cured material in place. FIG. 29A shows the die 18 attached to the pre-mold lead frame 46 prior to applying the insulating material. FIG. 29B shows the results of a first pass of printing the insulating material with the print head 68. FIG. 29C shows the results of a second pass of printing the insulating material with the print head 68. FIG. 29D shows the results of a third pass of printing the insulating material with the print head 68. FIG. 29E shows the results of a fourth pass of printing the insulating material with the print head 68. FIG. 29F shows the results of a fifth pass of printing the insulating material with the print head 68. FIG. 29G shows the results of a sixth pass of printing the insulating material with the print head 68. FIG. 29H shows the result of a seventh pass of printing insulating material by print head 68. FIG. 29I shows the result of an eighth pass of printing insulating material by print head 68. FIG. 29J shows the result of a ninth pass of printing insulating material by print head 68. FIG. 29K shows the result of a tenth pass of printing insulating material by print head 68. FIG. 29L shows the result of a final pass of printing insulating material by print head 68. Although FIGS. 29B-29L show a total of eleven passes of insulating material by print head 68, a greater or lesser number of passes of insulating material may actually be used depending on many factors including the type of insulating material used, the viscosity of the insulating material, the desired thickness of the insulating material, the desired resolution of control of the deposition of the insulating material, etc. Also, in the example of depositing a blanket layer 52, a portion of blanket layer 52 may extend across the top surface of die 18 between bond pads 50 on opposite sides of die 18 (not shown in FIGS. 29K and 29L).

[0179] Different orientations of the insulating material can be created depending on the type, viscosity, and amount of insulating material printed or otherwise deposited. Figure 30 shows an example with a larger amount of insulating material in the insulating layer (52, 64, 66), especially around the sidewall surface of the die 18, where it is attached to the die support pad 14 of the pre-molded lead frame 46, and where the top surface of the insulating layer (52, 64, 66) is in an approximately diagonal layer from the top surface of the die 18 to the top surface of the leads 12. Figure 31 shows another example with a thinner insulating layer (52, 64, 66), especially around the sidewall surface of the die 18, where it is attached to the die support pad 14 of the pre-molded lead frame 46, and where the insulating layer (52, 64, 66) is in an approximately vertical layer from the top surface of the die 18 to the die attach pad. Figure 32 shows yet another example where the overall height of the insulating layer (52, 64, 66) can be reduced by using a thinner die 18. 33 shows yet another example in which a thicker die attach 22 is used, allowing the use of a thinner insulating layer (52, 64, 66) where a portion of it extends outwardly along the die pad 14 away from the die 18, thus depositing a smaller amount of insulating material, particularly around the sidewall surfaces of the die 18, where it is attached to the die support pad 14 of the pre-molded lead frame 46, and where the insulating layer (52, 64, 66) is in a generally vertical layer from the top surface of the die 18 towards the die attach pad 14. However, the shrinkage of insulating materials, particularly polymers, is proportional to their distance from the nearest contact surface (see FIG. 34).

[0180] FIG. 35 illustrates an example in which a significant insulating layer is formed on the corresponding die and leadframe. The convex shape results from the significant amount of insulating material deposited on the die and leadframe. A thick or non-uniform layer of insulating material creates increased stresses in the packaged semiconductor device due to the expansion and contraction characteristics of the different materials that comprise the packaged device due to the coefficient of thermal expansion (CTE). FIG. 36 illustrates the result of CTE contraction of an insulating layer with a convex outer surface, where the contraction is greatest toward the nearest solid surface, which may result in separation between the insulating layer and any other surface to which it is attached. On the other hand, a thinner insulating layer that contours to the horizontal surfaces of the pre-molded leadframe 46 and the vertical side surfaces of the die 18 provides more uniformity and reduces the stress associated with the CTE. Also, reducing the vertical thickness of the die 18 helps reduce the stress associated with the CTE by reducing the vertical height of the insulating layer.

[0181] In the example shown in Figures 29B-29L, the non-screen printing process 800 is an inkjet printing process. An inkjet printer implementation of the non-screen printing process 800 is advantageous for efficiently printing feature sizes from about 100 microns down to 10-50 microns. In another example, the non-screen printing process 800 is an electrostatic jet printing process. An electrostatic jet printing implementation of the non-screen printing process 800 provides finer resolution, for example, for printing feature sizes down to 10-50 μm. The material for the insulating layer includes solvent, and therefore the insulating layer is initially deposited in a layer that is thicker than the desired finished layer. In one example, the material deposited for the insulating layer is 60% solvent, so that only 40% of the initially deposited material remains after rapid drying. Alternative materials may have a reduced solvent-to-material ratio, resulting in less solvent being dissipated and therefore a smaller initial thickness being required for the same thickness of final layer. The non-mold materials for the insulating layers have a light filler loading, for example 20-30% filler mass, which provides control over viscosity, conformality, wettability, modulus, and coefficient of thermal expansion (CTE). In contrast, when a mold compound is used as the insulating layer, the mold compound used in some arrangements may be 90% filler weight, while liquid resins for packaging may have 50-60% filler weight. In alternative arrangements, the insulating layers (52, 64, 66) may be deposited by spraying, spin coating, dispensing by other methods, and vapor deposition.

[0182] Figures 37A, 37B, 38A, 38B, 39A and 39B show an alternative chip-on-lead (COL) packaged electronic device. The major difference between the alternative chip-on-lead (COL) packaged electronic device and the previously described devices is the lead frame 46 in the COL device, which has a die attach pad 14 and leads 12 spaced from the die attach pad, which is replaced with a lead frame that includes leads but does not include a die attach pad. In the case of a COL device, the semiconductor die is attached directly to and supported by the leads rather than to a die attach pad such as die attach pad 14. The actual steps for manufacturing a COL device are otherwise substantially similar to the fabrication previously described for devices having a die attach pad with leads spaced from the die attach pad (see Figures 27A-29L) and will not be repeated here. Conductive Traces or Interconnects

[0183] 40A-43L show an electronic assembly that has undergone fabrication according to the exemplary method 500 of FIG. 5 with implementation in step 512. Step 512 includes applying conductive traces on an insulating layer from bond pads on the die to lead frame leads. The conductive traces and any contacts can be made using low resistance materials. Conductive inks, conductive polymers, metal-filled epoxies, sintered metal powders, liquid-assisted sintered particles, solder pastes, and the like can be used to form the traces and contacts. The material can be applied using at least one of a number of techniques, including inkjet printing, EHD / electrospray printing, spray coating printing, aerosol jet printing, microdispensing printing, laser-induced forward transfer printing, microtransfer printing, scribe dispensing, and screen printing. The conductive material that forms the conductive traces is constrained within the contours created by the aforementioned blanket 52, half blanket 64, and individual insulating layers 66 that form the basic insulating layer. This avoids unexpected shorts and opens. The conductive material conforms to the contours of the base layer and adheres well to the previous and subsequent overcoat layers.

[0184] 40A illustrates an example where a plurality of conductive traces or interconnects 74 are printed or formed on blanket insulating layer 52 (e.g., FIGS. 26A-26J), with each conductive trace or interconnect between a respective bond pad 50 of die 18 and a corresponding top surface of a respective lead 12 of pre-molded lead frame 46 (e.g., at 512 in FIG. 5). In one example, one end of each conductive trace or interconnect 74 extends down through a through hole or void 54 in blanket insulating layer 52 and to a respective bond pad 50 of die 18, and another opposite end of each conductive trace or interconnect 74 extends down through a through hole or void 56 to the top surface of a corresponding lead 12 on lead frame 46. In another example, solder balls, solder paste, or other conductive material is printed or deposited in through holes or voids 54 and 56 before the conductive traces or interconnects are printed or deposited (not shown). In this example, one end of each conductive trace or interconnect 74 extends to a respective solder ball, solder paste, or other conductive material in the through-hole or void 54, and the other end of the conductive trace or interconnect 74 extends to a solder ball, solder paste, or other conductive material in the through-hole or void 54. The above process is repeated to connect each of the remaining bond pads 50 on the die 18 to the top surface of a corresponding respective lead 12 of the lead frame 46. Optionally, the conductive traces or interconnects 74 may be cured after each layer of conductive material is applied (e.g., at 902 in FIG. 9 ), or after multiple layers of conductive material are applied.

[0185] Each conductive trace or interconnect 74 follows the topology of the insulating layer 52 which follows the contours of the topology on the lead frame 46 and the die 18 while smoothing out turns in the Z-axis. As seen in FIG. 40A, each of the interconnects 74 couples a bond pad 50 on the die 18 to a corresponding lead 12 on the pre-molded lead frame 46. In the example of FIG. 40A, a conductive trace or interconnect 74 couples each of the six bond pads 50 on the die 18 to a corresponding one of the six leads on the pre-molded lead frame 46. Each conductive trace or interconnect 74 can be formed or deposited using one of the printing techniques previously mentioned. Each conductive trace or interconnect 74 can be formed from conductive ink, conductive polymer, metal-filled epoxy, sintered metal powder, liquid-assisted sintered particles, solder paste, and the like. The selected conductive material preferably has a modulus of elasticity less than 3.4 GPa, more preferably less than 2 GPa, to avoid excessive stress on the assembly. The thickness of the conductive layer 74 can range from about 2 μm to 35 μm. A more preferred range is about 2 μm to 20 μm or less, and even more preferred is about 2 μm to about 10 μm. When inkjet printing is used, the inkjet solvent deposited material has a solvent, i.e., initial thickness, and after the solvent dissipates, the remaining material forms the conductive traces or interconnects 74 at a reduced thickness. To achieve the desired thickness, multiple inkjet depositions can be performed (e.g., at 1002 in FIG. 10). Inkjet deposition allows for precise placement of material by using a "drop-on-demand" (DOD) technique, in which a reservoir of liquid has a nozzle and a small amount of liquid is extruded from the nozzle in response to an electrical signal. The liquid forms droplets as it falls vertically onto a surface.

[0186] The precision of the inkjet deposition tool allows deposition of liquid material in some areas and not in other areas as the tool moves across the surface (or as the surface moves under the tool if the tool is fixed). The conductive material can be placed very precisely, even in small areas, so no etching or material removal step is required to remove the material after inkjet deposition. To achieve the desired thickness of the conductive trace or interconnect 74, a single deposition can be performed or multiple inkjet depositions can be performed (e.g., at 1002 in FIG. 10). Single pass deposition is more preferable for increasing manufacturing throughput and reducing costs, but may not produce the precise and / or desirable results as produced by multi-pass deposition. As additional inkjet materials are developed, a reduction in the amount of solvent can reduce the initial thickness required, thereby reducing the need for multi-pass deposition. FIG. 40B is a cross-sectional view along reference line K2-K2 in FIG. 40A.

[0187] According to one example, a plurality of conductive traces or interconnects 74 are formed on blanket insulating layer 52 that does not include channels or grooves for conductive traces or interconnects 74 to be deposited from bond pads 50 on die 18 to leads 12. FIG. 40C is a cross-sectional view of integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line M2-M2 of FIG. 40A. FIG. 40D is a cross-sectional view of integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line W2-W2 of FIG. 40A, showing insulating layer 52 extending down the vertical sides of die 18 to die pad 46 having conductive traces or interconnects 74 on top of insulating layer 52. Because there are no channels or grooves in the insulating layer 52 (e.g., Figures 40C and 40D) for containing the interconnects 74, the shape of the resulting conductive traces or interconnects 74 can be nearly any desired shape, including square, rectangular, semicircular, depending on the type, amount, and viscosity of the conductive material printed or deposited, as well as the number of layers applied and cured.

[0188] According to another example, insulating layer 52 is a blanket layer having rectangular channels or grooves 58 for subsequent conductive material to be deposited from bond pads 50 on die 18 to leads 12. FIG. 40E is a cross-sectional view of integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 along reference line M2-M2 in FIG. 40A. Conductive traces or interconnects 74 are formed partially (see FIG. 40E) or completely (not shown) within rectangular channels or grooves 58, giving the conductive traces or interconnects a rectangular shape. If additional conductive material is deposited and / or has a higher viscosity and / or if curing occurs immediately after the conductive material is applied, a portion of conductive traces or interconnects 74 may extend above rectangular channels or grooves 58. Figure 40F is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 along reference line W2-W2 of Figure 40A, showing insulating layer 52 extending down from the vertical side of die 18 to die pad 46.

[0189] According to yet another example, insulating layer 52 is a blanket layer having semicircular (i.e., half-circular) channels or grooves 60 for subsequent conductive material to be deposited from bond pads 50 on die 18 to leads 12. FIG. 40G is a cross-sectional view of integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 along reference line M2-M2 in FIG. 40A. Conductive traces or interconnects 74 are formed partially (see FIG. 40G) or completely (not shown) within semicircular channels or grooves 60, providing conductive traces or interconnects 74 with a semicircular shape within insulating layer 52. Conductive traces or interconnects 74 may extend over semicircular channels or grooves 60, resulting in more fully circular conductive traces or interconnects 74 if additional conductive material is deposited and / or has a higher viscosity and / or is cured immediately after the conductive material is applied. FIG. 40H is a cross-sectional view of integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line W2-W2 of FIG. 40A.

[0190] According to yet another example, insulating layer 52 is a blanket layer having v-shaped channels or grooves 62 for subsequent conductive material deposited from bond pads 50 on die 18 to leads 12. FIG. 40I is a cross-sectional view of integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 along reference line M2-M2 in FIG. 40A. Conductive traces or interconnects 74 are formed partially (see FIG. 40I) or completely (not shown) within v-shaped channels or grooves 62, giving conductive traces or interconnects 74 the appearance of a v-shape within insulating layer 52. Conductive traces or interconnects 74 can extend above v-shaped channels or grooves 62, resulting in a higher v-shaped conductive trace or interconnect 74 if additional conductive material is deposited and / or has a higher viscosity and / or is cured immediately after the conductive material is applied. FIG. 40J is a cross-sectional view of integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line W2-W2 of FIG. 40A.

[0191] 41A shows an example where a plurality of conductive traces or interconnects 74 are printed or formed on two spaced apart half blanket insulating layers 64 (e.g., FIGS. 27A-27J) applied as a base layer, each spanning across a top surface of a portion of a lead finger 12 in a pre-molded lead frame 46, across the pre-molded lead frame 42, onto one side of a die 18, and across a portion of the top of the die 18 just beyond a bond pad 50 on the die 18 (e.g., at 512 in FIG. 5). In one example, one end of each conductive trace or interconnect 74 extends down through a respective through hole or void 54 in one of the half blanket insulating layers 64 to a bond pad 50 on the die 18, and another opposite end of the conductive trace or interconnect 74 extends down through a through hole or void 56 to a top surface of a corresponding lead 12 on the lead frame 46. In another example, solder balls, solder paste, or other conductive material is printed or deposited in the through-holes or voids 54 and 56 before the conductive traces or interconnects are printed or deposited (not shown). In this example, one end of the conductive traces or interconnects 74 extends to the solder balls, solder paste, or other conductive material in the through-holes or voids 54, and the other end of the conductive traces or interconnects 74 extends to the solder balls, solder paste, or other conductive material in the through-holes or voids 54. The above process is repeated to connect each of the remaining bond pads 50 on the die 18 to the top surface of a corresponding respective lead 12 of the lead frame 46. Optionally, the conductive traces or interconnects 74 may be cured after each layer of conductive material is applied (e.g., at 902 in FIG. 9), or after multiple layers of conductive material are applied.

[0192] Each conductive trace or interconnect 74 follows the topology of one of the insulating layers 64 that follows the contours of the topology on the lead frame 46 and the die 18 while smoothing out turns in the Z-axis. As seen in FIG. 41A, each of the interconnects 74 couples a bond pad 50 on the die 18 to a corresponding lead 12 on the pre-molded lead frame 46. In the example of FIG. 41A, a conductive trace or interconnect 74 couples each of the six bond pads 50 on the die 18 to a corresponding one of the six leads on the pre-molded lead frame 46. Each conductive trace or interconnect 74 can be formed or deposited using one of the printing techniques previously described. Each conductive trace or interconnect 74 can be formed from conductive ink, conductive polymer, metal-filled epoxy, sintered metal powder, liquid-assisted sintered particles, solder paste, and the like. The selected conductive material preferably has a modulus of elasticity of less than 3.4 GPa, more preferably less than 2 GPa, to avoid excessive stress on the assembly. The thickness of the conductive layer 74 can range from about 2 μm to 35 μm. A more preferred range is about 2 μm to 20 μm or less, and even more preferred is about 2 μm to about 10 μm. When inkjet printing is used, the inkjet solvent deposited material has a solvent, i.e., initial thickness, and after the solvent dissipates, the remaining material forms the conductive traces or interconnects 74 at a reduced thickness. To achieve the desired thickness, multiple inkjet depositions can be performed (e.g., at 1002 in FIG. 10). Inkjet deposition allows for precise placement of material by using a "drop-on-demand" (DOD) technique, in which a reservoir of liquid has a nozzle and a small amount of liquid is extruded from the nozzle in response to an electrical signal. The liquid forms droplets as it falls vertically onto a surface.

[0193] The precision of the inkjet deposition tool allows deposition of liquid material in some areas and not in others as the tool moves across the surface (or as the surface moves under the tool if the tool is fixed). The conductive material can be placed very precisely, even in small areas, so no etching or material removal step is required to remove the material after inkjet deposition. To achieve the desired thickness of the conductive trace or interconnect 74, a single deposition can be performed, or multiple inkjet depositions can be performed (e.g., at 1002 in FIG. 10). Single pass deposition is more preferable for increasing manufacturing throughput and reducing costs, but may not produce as precise and / or desired results as multi-pass depositions. As additional inkjet materials are developed, a reduction in the amount of solvent can reduce the initial thickness required, thereby reducing the need for multi-pass depositions. FIG. 41B is a cross-sectional view of FIG. 41A along reference line N2-N2.

[0194] According to one example, a plurality of conductive traces or interconnects 74 are formed on top of each half blanket insulating layer 64 that does not include channels or grooves for the conductive traces or interconnects 74 to be deposited from bond pads 50 on die 18 to leads 12. FIG. 41C is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line P2-P2 of FIG. 41A. FIG. 41D is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line Q2-Q2 of FIG. 41A, showing die pad 46 with each insulating layer 64 extending down a vertical side of die 18 and having conductive traces or interconnects 74 on top of insulating layer 64. Because there are no channels or grooves in the insulating layer 64 (e.g., Figures 41C and 41D) to contain the interconnects 74, the shape of the resulting conductive traces or interconnects 74 can be nearly any shape, including square, rectangular, semicircular, or V-shaped, depending on the type, amount, and viscosity of the conductive material printed or deposited, as well as the number of layers applied and cured.

[0195] According to another example, half blanket insulating layer 64 includes rectangular channels or grooves 58 for subsequent conductive material to be deposited from bond pads 50 on die 18 to leads 12. FIG. 41E is a cross-sectional view of integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 along reference line P2-P2 of FIG. 41A. Conductive traces or interconnects 74 are formed partially (see FIG. 41E) or completely (not shown) within rectangular channels or grooves 58, providing the conductive traces or interconnects 74 with a rectangular shape. If additional conductive material is deposited and / or has a higher viscosity and / or is cured immediately after the conductive material is applied, a portion of conductive traces or interconnects 74 may extend above rectangular channels or grooves 58. Figure 41F is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attachment material 22 to the top surface of die attachment pad 14 of pre-molded lead frame unit 46 along reference line Q2-Q2 in Figure 41A, showing insulating layer 64 extending down the vertical side of die 18 relative to die pad 46.

[0196] According to yet another example, insulating layer 64 includes semicircular (i.e., half-circular) channels or grooves 60 for subsequent conductive material to be deposited from bond pads 50 on die 18 to leads 12. FIG. 41G is a cross-sectional view of integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 along reference line P2-P2 of FIG. 41A. Conductive traces or interconnects 74 are formed partially (see FIG. 1G) or completely (not shown) within semicircular channels or grooves 60, providing the conductive traces or interconnects 74 with a semicircular shape. Conductive traces or interconnects 74 can extend over semicircular channels or grooves 60, resulting in more fully circular conductive traces or interconnects 74 if additional conductive material is deposited and / or has a higher viscosity and / or is cured immediately after the conductive material is applied. FIG. 41H is a cross-sectional view of integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line Q2-Q2 of FIG. 41A.

[0197] According to yet another example, insulating layer 64 includes a v-shaped channel or groove 62 for subsequent conductive material to be deposited from bond pad 50 on die 18 to leads 12. FIG. 41I is a cross-sectional view of integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of pre-molded leadframe unit 46 along reference line P2-P2 of FIG. 41A. Conductive traces or interconnects 74 are formed partially (see FIG. 41I) or completely (not shown) within v-shaped channel or groove 62, giving conductive traces or interconnects 74 a v-shaped appearance. Conductive traces or interconnects 74 can extend above v-shaped channel or groove 62, resulting in a higher v-shaped conductive trace or interconnect 74 if additional conductive material is deposited and / or has a higher viscosity and / or is cured immediately after the conductive material is applied. FIG. 41J is a cross-sectional view of integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line Q2-Q2 of FIG. 41A.

[0198] 42A shows an example where conductive layers 74 are printed or formed on individual insulating layers 66 (e.g., FIGS. 28A-28J) that are applied as a base layer, each extending onto the top surface of a portion of a lead finger 12 in pre-molded lead frame 46, across pre-molded 42, onto one side of die 18, and across a portion of the top of die 18 just beyond bond pad 50 on die 18 (e.g., at 512 in FIG. 5). In one example, one end of each conductive trace or interconnect 74 extends down through a respective through hole or void 54 in individual insulating layer 66 to a bond pad 50 on die 18, and another opposite end of each conductive trace or interconnect 74 extends down through a respective through hole or void 56 to the top surface of a corresponding lead 12 on lead frame 46. In another example, solder balls, solder paste, or other conductive material is printed or deposited in the through-holes or voids 54 and 56 before the conductive traces or interconnects are printed or deposited (not shown). In this example, one end of the conductive traces or interconnects 74 extends to the solder balls, solder paste, or other conductive material in the through-holes or voids 54, and the other end of the conductive traces or interconnects 74 extends to the solder balls, solder paste, or other conductive material in the through-holes or voids 54. The above process is repeated to connect each of the remaining bond pads 50 on the die 18 to the top surface of a corresponding respective lead 12 of the lead frame 46. Optionally, the conductive traces or interconnects 74 may be cured after each layer of conductive material is applied (e.g., at 902 in FIG. 9), or after multiple layers of conductive material are applied.

[0199] Each conductive trace or interconnect 74 follows the topology of the individual insulating layers 66, which follow the contours of the topology on the lead frame 46 and the die 18, while smoothing out turns in the Z-axis. As seen in FIG. 42A, each of the interconnects 74 couples a bond pad 50 on the die 18 to a corresponding lead 12 on the pre-molded lead frame 46. In the example of FIG. 42A, a conductive trace or interconnect 74 couples each of the six bond pads 50 on the die 18 to a corresponding one of the six leads on the pre-molded lead frame 46. Each conductive trace or interconnect 74 may be formed or deposited using one of several printing techniques previously identified. Each conductive trace or interconnect 74 may be formed from conductive ink, conductive polymer, metal-filled epoxy, sintered metal powder, liquid-assisted sintered particles, solder paste, and the like. The selected conductive material preferably has a modulus of elasticity of less than 3.4 GPa, more preferably less than 2 GPa, to avoid excessive stress on the assembly. The thickness of the conductive layer 74 can range from about 2 μm to 35 μm. A more preferred range is from about 2 μm to 20 μm or less, and even more preferred is from about 2 μm to about 10 μm. When inkjet printing is used, the inkjet solvent deposited material has a solvent, i.e., initial thickness, and after the solvent dissipates, the remaining material forms the conductive traces or interconnects 74 at a reduced thickness. To achieve the desired thickness, multiple inkjet depositions can be performed (e.g., at 1002 in FIG. 10). Inkjet deposition allows for precise placement of material by using a "drop-on-demand" (DOD) technique, in which a reservoir of liquid has a nozzle and a small amount of liquid is extruded from the nozzle in response to an electrical signal. The liquid forms droplets as it falls vertically onto a surface.

[0200] The precision of the inkjet deposition tool allows deposition of liquid material in some areas and not in other areas as the tool moves across the surface (or as the surface moves under the tool if the tool is fixed). The conductive material can be placed very precisely, even in small areas, so no etching or material removal step is required to remove the material after inkjet deposition. To achieve the desired thickness of the conductive trace or interconnect 74, a single deposition can be performed, or multiple inkjet depositions can be performed (e.g., at 1002 in FIG. 10). Single pass deposition is more preferable for increasing manufacturing throughput and reducing costs, but may not produce the precise and / or desired results as multi-pass depositions. As additional inkjet materials are developed, a reduction in the amount of solvent can reduce the initial thickness required, thereby reducing the need for multi-pass depositions. FIG. 42B is a cross-sectional view of FIG. 42A along reference line R2-R2.

[0201] According to one example, each of the plurality of conductive traces or interconnects 74 is formed on a respective insulating layer 66 that does not include channels or grooves for the conductive traces or interconnects 74 to be deposited from bond pads 50 on the die 18 to the leads 12. FIG. 42C is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line T2-T2 of FIG. 42A. FIG. 42D is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line U2-U2 of FIG. 42A, showing each insulating layer 66 extending down a vertical side of the die 18 to the die pad 46 having a conductive trace or interconnect 74 on top of each insulating layer 66. Because there are no channels or grooves in the insulating layer 66 (e.g., FIGS. 42C and 42D) to contain the interconnects 74, the shape of the resulting conductive traces or interconnects 74 can be nearly any shape, including square, rectangular, semicircular, or v-shaped, depending on the type, amount, and viscosity of the conductive material printed or deposited, as well as the number of layers applied and cured.

[0202] According to another example, each individual insulating layer 66 includes a rectangular channel or groove 58 for subsequent conductive material to be deposited from bond pad 50 on die 18 to leads 12. FIG. 42E is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of pre-molded leadframe unit 46 along reference line T2-T2 of FIG. 42A. Conductive traces or interconnects 74 are formed partially (see FIG. 50E) or completely (not shown) within rectangular channels or grooves 58, providing the conductive traces or interconnects 74 with a rectangular shape. If additional conductive material is deposited and / or has a higher viscosity and / or is cured immediately after the conductive material is applied, a portion of the conductive traces or interconnects 74 may extend above rectangular channels or grooves 58. Figure 42F is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 along reference line U2-U2 in Figure 42A, showing individual insulating layers 66 extending down from the vertical sides of the die 18 to the die pad 46.

[0203] According to yet another example, insulating layer 66 includes semicircular (i.e., half-circular) channels or grooves 60 for subsequent conductive material to be deposited from bond pads 50 on die 18 to leads 12. FIG. 42G is a cross-sectional view of integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line T2-T2 of FIG. 42A. Conductive traces or interconnects 74 are formed partially (see FIG. 42G) or completely (not shown) within semicircular channels or grooves 60, providing the conductive traces or interconnects 74 with a semicircular shape. Conductive traces or interconnects 74 may extend over semicircular channels or grooves 60, resulting in more fully circular conductive traces or interconnects 74 if additional conductive material is deposited and / or has a higher viscosity and / or is cured immediately after the conductive material is applied. FIG. 42H is a cross-sectional view of integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line U2-U2 of FIG. 42A.

[0204] According to yet another example, each insulating layer 66 includes a v-shaped channel or groove 62 for subsequent conductive material to be deposited from bond pad 50 on die 18 to leads 12. FIG. 42I is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of pre-molded leadframe unit 46 along reference line T2-T2 of FIG. 42A. Conductive traces or interconnects 74 are formed partially (see FIG. 50I) or completely (not shown) within v-shaped channel or groove 62, giving conductive traces or interconnects 74 a v-shaped appearance. Conductive traces or interconnects 74 can extend above v-shaped channel or groove 62, resulting in a higher v-shaped conductive trace or interconnect 74 if additional conductive material is deposited and / or has a higher viscosity and / or is cured immediately after the conductive material is applied. FIG. 42J is a cross-sectional view of integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line U2-U2 of FIG. 42A.

[0205] 43A-43L show another example in which a non-screen printing process 1000 is performed using a print head 68 controlled to translate along a controlled lateral direction or path 71 while directing conductive material along a vertical direction 73 to obtain a desired profile of conductive traces or interconnects 74 (e.g., FIGS. 40A-40J) on a blanket insulating layer 52, a half blanket insulating layer 64 (e.g., FIGS. 41A-41J), or an individual insulating layer 66 (e.g., FIGS. 42A-42J). In one example, the process is performed using an inkjet print head 68 having a position controller, such as a servo controller, configured to translate and control the position of the print head 68 in three dimensions (e.g., the X and Y directions shown in the figures, as well as the orthogonal Z direction off-page in FIGS. 43A-43L). In one example, the printing system translates the print head 68 in the XZ plane while controlling the Y-direction spacing between the top surface of the lead frame 46, die 18, and the print head 68. The printing system also, in one example, controls the supply of conductive material from the nozzles of the print head, e.g., turning printing on and off to facilitate precise, high-resolution control over where conductive material is printed and not printed. The non-screen printing process 1000 also provides control over the thickness (e.g., Y direction) of the deposited conductive material via one or more of the deposition rates and controls the time that the print head 68 is positioned over a particular area of ​​the lead frame 46 and / or die 18. This facilitates printing conductive material to different thicknesses in different locations in a particular implementation.

[0206] To obtain a desired profile of conductive traces or interconnects 74 along a non-horizontal surface, the conductive material may be formed or applied in multiple passes with each pass dispensing viscous material on the Z dimension only at the desired XY location. The viscosity of the material as well as exposure to temperature, light, or gas can hold the partially cured material in place. FIG. 43A shows the die 18 attached to the pre-mold lead frame 46 prior to applying the conductive material. FIG. 43B shows the result of a first pass of printing conductive material by the print head 68. FIG. 43C shows the result of a second pass of printing conductive material by the print head 68. FIG. 43D shows the result of a third pass of printing conductive material by the print head 68. FIG. 43E shows the result of a fourth pass of printing conductive material by the print head 68. FIG. 43F shows the result of a fifth pass of printing conductive material by the print head 68. FIG. 43G shows the result of a sixth pass of printing conductive material by the print head 68. FIG. 43H shows the result of a seventh pass of printing conductive material by the print head 68. FIG. 43I shows the result of an eighth pass of printing conductive material by print head 68. FIG. 43J shows the result of a ninth pass of printing conductive material by print head 68. FIG. 43K shows the result of a tenth pass of printing conductive material by print head 68. FIG. 43L shows the result of a final pass of printing conductive material by print head 68. Although FIGS. 43B-L show a total of eleven passes of printing conductive material by print head 68, more or fewer passes may actually be used depending on many factors including the type of conductive material used, the viscosity of the conductive material, the desired thickness of the conductive material, the desired resolution of control of the deposition of the conductive material, etc.

[0207] Figures 45A, 44B, 45A, 45B, 46A, and 46B show an alternative chip-on-lead (COL) packaged electronic device. The major difference between the alternative chip-on-lead (COL) packaged electronic device and the previously described devices is the lead frame 46 in the COL device, which has a die attach pad 14 and leads 12 spaced from the die attach pad, which is replaced with a lead frame that includes leads but does not include a die attach pad. In the case of a COL device, the semiconductor die is attached directly to and supported by the leads, rather than to a die attach pad such as die attach pad 14. The actual steps for manufacturing a COL device are otherwise substantially similar to those previously described for devices having a die attach pad with leads spaced from the die attach pad (see Figures 40A-43L) and will not be repeated here. Second or Covering Insulation Layer

[0208] 47A-56L show an electronic assembly that has undergone fabrication according to the example method 500 of FIG. 5 with the implementation at 514. In an example, a second or overlying insulating layer is applied over the exposed portions of the conductive traces or interconnects (74) and over any exposed portions of the base or base insulating layer (52, 64, 66) adjacent to the conductive layers, such that each conductive trace or interconnect is wrapped between the base or base insulating layer and the second or overlying insulating layer, and thus sufficient to protect the conductive traces or interconnects from short circuits and / or other structural damage, such as structural stresses related to thermal coefficient of expansion. The second or overlying insulating layer is preferably, but not necessarily, of a similar material as the base or base insulating layer.

[0209] Blanket-covering insulation layer on top of blanket base or basic insulation layer

[0210] 47A shows that a second insulating layer, e.g., a blanket coated insulating layer 76, is printed, deposited, formed, or otherwise applied over the exposed portions of the blanket base or base insulating layer 52 and the exposed portions of the conductive traces or interconnects 74 on the base or base insulating layer 52 (see FIGS. 40A and 40B), including over a portion of the top surface of the premolded leadframe 46, across the premolded 42, across one side of the die 18, across the top of the die 18, down the other side of the die 18, across the premolded 42 on the other side of the premolded leadframe 46, and over a portion of the top surface of the lead fingers 12 on the other side of the premolded leadframe 46 (e.g., at 514 in FIG. 5). Optionally, the blanket coated insulating layer 76 can be cured at this point or later with additional layers. The blanket coated insulating layer 76 can be a polymer, epoxy, silicone, mold, or other insulator. The blanket coated insulating layer 76 conforms to the topology on the blanket base or basic insulating layer 52 and the contours of the conductive traces or interconnects 74 formed on the blanket base or basic insulating layer 52, at least sufficient to ensure that all conductive traces or interconnects 74 are wrapped or sealed between the blanket base or basic insulating layer 52 and the blanket coated insulating layer 76. As seen in FIG. 47A, the blanket coated insulating layer 76 covers the blanket base or basic insulating layer 52, which in turn covers the top surface of the die 18, the side surfaces of the die 18 adjacent bond pads 50, and the conductive traces or interconnects 74 on the blanket base or basic insulating layer 52. The blanket coated insulating layer 76 can be formed or deposited using one of several techniques, such as screen printing, photolithography and etching, CVD, PVD, vacuum deposition, inkjet printing, spray coating, microdispensing, aerosol jet, ElectroHydroDynamic (EHD) techniques, having suitable insulating properties.

[0211] If inkjet printing is used, the blanket coated insulating layer 76 can be formed from inkjet deposition compatible polymers such as polyimide inks, thermosetting epoxy-based polymer inks, and UV curable acrylate inks. To avoid excessive stress on the assembly, it is preferable to use polymers with a modulus of elasticity less than 3.4 GPa, more preferably less than 2 GPa. The thickness of the blanket coated insulating layer 76 can range from about 2 μm to 35 μm. A more preferred range is about 2 μm to 20 μm or less, and even more preferably from about 2 μm to about 10 μm. Inkjet printer solvent deposited materials have a solvent, i.e., initial thickness, so that after the solvent dissipates, the remaining material forms an insulating layer with a reduced thickness. Multiple inkjet depositions can be performed (e.g., at 1302 in FIG. 13) to achieve the desired thickness. Inkjet deposition allows for precise placement of material by using a "drop-on-demand" (DOD) technique, in which a container of liquid has a nozzle and a small amount of liquid is extruded from the nozzle in response to an electrical signal. The liquid forms droplets as it falls vertically onto a surface.

[0212] The precision of the inkjet deposition tool allows deposition of liquid material in some areas and precludes deposition of liquid material in other areas as the tool moves across the surface (or as the surface moves under the tool if the tool is fixed). The insulating material can be placed so precisely, even in small areas, that no etching or material removal step is required to remove the material after inkjet deposition. Single pass deposition increases manufacturing throughput and reduces costs, but may not provide the more precise and / or desired results of multi-pass deposition. As additional inkjet materials are developed, a reduction in the amount of solvent can reduce the initial thickness required, thereby reducing the need for multi-pass deposition. FIG. 47B is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 along reference line K4-K4 of FIG. 47A. The orientation of blanket base or basic insulating layer 52, conductive traces or interconnects 74, and blanket over insulating layer 76 are also shown in FIG. 47A.

[0213] FIG 47C is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of a pre-molded leadframe unit 46 along reference line L4-L4 of FIG 47A, according to one example. In FIG 47C, a blanket coating insulating layer 76 is shown covering the top and side surfaces of the blanket base or basic insulating layer 52. However, some examples may not require the blanket coating insulating layer 76 to extend laterally beyond the side surfaces of the blanket base or basic insulating layer 52 when the conductive traces or interconnects 74 are otherwise encapsulated within the blanket base or basic insulating layer 52 and blanket coating insulating layer 76. FIG 47D is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line M4-M4 in FIG 47A, showing that blanket base or base insulating layer 52, conductive traces or interconnects 74, and blanket overlying insulating layer 76 extend down from the vertical sides of the die 18 to the die pad 46. FIG 47E is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line W4-W4 in FIG 47A, showing that conductive traces or interconnects 74 are now oriented horizontally on blanket base or base insulating layer 52 to prepare for the conductive traces or interconnects 74 to extend horizontally to the leads 12. Figure 47F is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded lead frame unit 46 along reference line V4-V4 in Figure 47A, showing the terminal ends of each conductive trace or interconnect 74 as it extends downward through a through hole or void 56 in blanket base or foundation layer 52 to contact the upper surface of each lead 12.

[0214] FIG. 47G is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of pre-molded leadframe unit 46 along reference line L4-L4 in FIG. 47A. In this example, blanket base or base insulating layer 52 includes rectangular channels or grooves 58 filled with conductive material (e.g., conductive traces or interconnects 74) from bond pads 50 to leads 12 on die 18. In FIG. 47G, blanket overcoat insulating layer 76 is shown covering the top and side surfaces of blanket base or base insulating layer 52. However, some examples may not require blanket overcoat insulating layer 76 to extend laterally beyond the side surfaces of blanket base or base insulating layer 52 when conductive traces or interconnects 74 are otherwise encapsulated within blanket base or base insulating layer 52 and blanket overcoat insulating layer 76. FIG 47H is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line M4-M4 in FIG 47A, showing that blanket base or basic insulating layer 52, conductive traces or interconnects 74, and blanket overlying insulating layer 76 extend down from the vertical sides of the die 18 to the die pad 46. FIG 47I is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line W4-W4 in FIG 47A, showing that conductive traces or interconnects 74 are now oriented horizontally on blanket base or basic insulating layer 52 to prepare for the conductive traces or interconnects 74 to extend horizontally to the leads 12.Figure 47J is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded lead frame unit 46 along reference line V4-V4 in Figure 47A, showing the terminal ends of each conductive trace or interconnect 74 as it extends downward through a through hole or void 56 in blanket base or foundation layer 52 to contact the upper surface of each lead 12.

[0215] FIG. 47K is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of pre-molded leadframe unit 46 along reference line L4-L4 in FIG. 47A. In this example, blanket base or base insulating layer 52 includes semi-circular channels or grooves 60 filled with conductive material (e.g., conductive traces or interconnects 74) from bond pads 50 to leads 12 on die 18. In FIG. 47K, blanket overcoat insulating layer 76 is shown covering the top and side surfaces of blanket base or base insulating layer 52. However, some examples may not require blanket overcoat insulating layer 76 to extend laterally beyond the side surfaces of blanket base or base insulating layer 52 when conductive traces or interconnects 74 are otherwise encapsulated within blanket base or base insulating layer 52 and blanket overcoat insulating layer 76. FIG 47L is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line M4-M4 in FIG 47A, showing that blanket base or basic insulating layer 52, conductive traces or interconnects 74, and blanket overlying insulating layer 76 extend down from the vertical sides of the die 18 to the die pad 46. FIG 47M is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line W4-W4 in FIG 47A, showing that conductive traces or interconnects 74 are now oriented horizontally on blanket base or basic insulating layer 52 to prepare for the conductive traces or interconnects 74 to extend horizontally to the leads 12.Figure 47N is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded lead frame unit 46 along reference line V4-V4 in Figure 47A, showing the terminal ends of each conductive trace or interconnect 74 as it extends downward through a through hole or void 56 in blanket base or foundation layer 52 to contact the upper surface of each lead 12.

[0216] FIG. 47O is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of a pre-molded leadframe unit 46 along reference line L4-L4 in FIG. 47A. In this example, blanket base or base insulating layer 52 includes v-shaped channels or grooves 62 filled with conductive material (e.g., conductive traces or interconnects 74) from bond pads 50 to leads 12 on die 18. In FIG. 47O, blanket overcoat insulating layer 76 is shown covering the top and side surfaces of blanket base or base insulating layer 52. However, some examples may not require blanket overcoat insulating layer 76 to extend laterally beyond the side surfaces of blanket base or base insulating layer 52 when conductive traces or interconnects 74 are otherwise encapsulated within blanket base or base insulating layer 52 and blanket overcoat insulating layer 76. FIG 47P is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line M4-M4 in FIG 47A, showing that blanket base or basic insulating layer 52, conductive traces or interconnects 74, and blanket overlying insulating layer 76 extend down from the vertical sides of the die 18 to the die pad 46. FIG 47Q is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line W4-W4 in FIG 47A, showing that conductive traces or interconnects 74 are now oriented horizontally on blanket base or basic insulating layer 52 to prepare for the conductive traces or interconnects 74 to extend horizontally to the leads 12.Figure 47R is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded lead frame unit 46 along reference line V4-V4 in Figure 47A, showing the terminal ends of each conductive trace or interconnect 74 as it extends downward through a through hole or void 56 in blanket base or foundation layer 52 to contact the upper surface of each lead 12.

[0217] Blanket-covered insulation layer on top of half-blanket base or foundation layer

[0218] 48A shows that a second insulating layer, e.g., a blanket coated insulating layer 76, is printed, deposited, formed, or otherwise applied over the exposed portions of the half blanket base or base insulating layer 64 and the exposed portions of the conductive traces or interconnects 74 on the half blanket base or base insulating layer 66 (see FIGS. 41A and 41B), each extending over a portion of the top surface of the lead fingers 12 in the pre-molded lead frame 46, across the pre-molded lead frame 42, and onto one side of the die 18 just beyond the top of the bond pad 50 that is closest to the side of the die 18 to which the respective half blanket base or base insulating layer 64 is adjacent (e.g., 514 in FIG. 5). The area on the top of the die 18 between the half blanket base or base insulating layer 64 remains uncovered by any base or base layer. Optionally, the blanket coated insulating layer 76 can be cured at this point or later with additional layers. The blanket coated insulating layer 76 may be a polymer, epoxy, silicone, mold, or other insulator. The blanket coated insulating layer 76 conforms to the topology on the half blanket base or basic insulating layer 66 and the contours of the conductive traces or interconnects 74 formed on the half blanket base or basic insulating layer 64, and is sufficient to ensure that at least all of the conductive traces or interconnects 74 are wrapped or sealed between the half blanket base or basic insulating layer 64 and the blanket coated insulating layer 76. As seen in FIG. 48A, the blanket coated insulating layer 76 covers the half blanket base or basic insulating layer 64, the conductive traces or interconnects 74 on the half blanket base or basic insulating layer 66, and the uninsulated portion of the top of the die 18 between the half blanket base or basic insulating layer 64. Also, although this example shows two half blanket bases or basic insulating layers 64, more than two layers may be used, each accommodating two or more layers of conductive traces or interconnects 74.The blanket coated insulating layer 76 can be formed or deposited using one of several techniques, such as screen printing, photolithography and etching, CVD, PVD, vacuum deposition, inkjet printing, spray coating, microdispensing, aerosol jet, ElectroHydroDynamic (EHD) techniques, having suitable insulating properties.

[0219] If inkjet printing is used, the blanket coated insulating layer 76 can be formed from inkjet deposition compatible polymers such as polyimide inks, thermosetting epoxy-based polymer inks, and UV curable acrylate inks. To avoid excessive stress on the assembly, it is preferable to use polymers with a modulus of elasticity less than 3.4 GPa, more preferably less than 2 GPa. The thickness of the blanket coated insulating layer 76 can range from about 2 μm to 35 μm. A more preferred range is about 2 μm to 20 μm or less, and even more preferably from about 2 μm to about 10 μm. Inkjet printer solvent deposited materials have a solvent, i.e., initial thickness, so that after the solvent dissipates, the remaining material forms an insulating layer with a reduced thickness. Multiple inkjet depositions can be performed (e.g., at 1302 in FIG. 13) to achieve the desired thickness. Inkjet deposition allows for precise placement of material by using a "drop-on-demand" (DOD) technique, in which a container of liquid has a nozzle and a small amount of liquid is extruded from the nozzle in response to an electrical signal. The liquid forms droplets as it falls vertically onto a surface.

[0220] The precision of the inkjet deposition tool allows deposition of liquid material in some areas and precludes deposition of liquid material in other areas as the tool moves across the surface (or as the surface moves under the tool if the tool is fixed). The insulating material can be placed very precisely, even in small areas, so no etching or material removal steps are required to remove the material after inkjet deposition. Single pass deposition increases manufacturing throughput and reduces costs, but may not provide the more precise and / or desired results of multi-pass deposition. As additional inkjet materials are developed, a reduction in the amount of solvent can reduce the initial thickness required, thereby reducing the need for multi-pass deposition. FIG. 48B is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded lead frame unit 46 along reference line K5-K5 of FIG. 48A. The orientation of half blanket base or basic insulating layer 64, conductive traces or interconnects 74, and blanket over insulating layer 76 are also shown in FIG. 48A.

[0221] 48C is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of a pre-molded leadframe unit 46 along reference line L5-L5 of FIG. 48A, according to one example. In FIG. 48C, a blanket coating insulating layer 76 is shown covering the top and side surfaces of the half blanket base or basic insulating layer 64. However, some examples may not require the blanket coating insulating layer 76 to extend laterally beyond the side surfaces of the half blanket base or basic insulating layer 64 when the conductive traces or interconnects 74 are otherwise encapsulated within the half blanket base or basic insulating layer 64 and blanket coating insulating layer 76. 48D is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line M5-M5 in FIG. 48A , showing one of half blanket base or basic insulating layer 64, conductive traces or interconnects 74, and blanket over insulating layer 76 extending down the vertical sides of die 18 to die pad 46. FIG. 48E is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line W5-W5 in FIG. 48A , showing that conductive traces or interconnects 74 are now oriented horizontally on half blanket base or basic insulating layer 64 to prepare for conductive traces or interconnects 74 to extend horizontally to leads 12. Figure 48F is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded lead frame unit 46 along reference line V5-V5 in Figure 48A, showing the terminal ends of each conductive trace or interconnect 74 as it extends downward through a through hole or void 56 in the half blanket base or foundation layer 64 to contact the upper surface of each lead 12.

[0222] FIG. 48G is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 along reference line L5-L5 in FIG. 48A. In this example, each half blanket base or base insulating layer 64 includes a rectangular channel or groove 58 filled with conductive material (e.g., conductive traces or interconnects 74) from bond pads 50 on die 18 to leads 12. In FIG. 48G, a blanket overcoat insulating layer 76 is shown covering the top and side surfaces of half blanket base or base insulating layer 64. However, some examples may not require blanket overcoat insulating layer 76 to extend laterally beyond the side surfaces of half blanket base or base insulating layer 64 when conductive traces or interconnects 74 are otherwise encapsulated within half blanket base or base insulating layer 64 and blanket overcoat insulating layer 76. FIG 48H is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line M5-M5 in FIG 48A, showing half blanket base or basic insulating layer 64, conductive traces or interconnects 74, and blanket over insulating layer 76 extending down the vertical sides of die 18 to die pad 46. FIG 48I is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line W5-W5 in FIG 48A, showing conductive traces or interconnects 74 now oriented horizontally on half blanket base or basic insulating layer 64 to prepare for conductive traces or interconnects 74 to extend horizontally to leads 12.Figure 48J is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of the die attach pad 14 of a pre-molded lead frame unit 46 along reference line V5-V5 in Figure 48A, showing the terminal ends of each conductive trace or interconnect 74 as it extends downward through a through hole or void 56 in the half blanket base or foundation layer 64 to contact the upper surface of each lead 12.

[0223] FIG. 48K is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of pre-molded leadframe unit 46 along reference line L5-L5 of FIG. 48A. In this example, half blanket base or base insulating layer 64 includes semicircular channels or grooves 60 filled with conductive material (e.g., conductive traces or interconnects 74) from bond pads 50 to leads 12 on die 18. In FIG. 48K, blanket over insulating layer 76 is shown covering the top and side surfaces of half blanket base or base insulating layer 64. However, some examples may not require blanket over insulating layer 76 to extend laterally beyond the side surfaces of half blanket base or base insulating layer 64 when conductive traces or interconnects 74 are otherwise encapsulated within half blanket base or base insulating layer 64 and blanket over insulating layer 76. FIG 48L is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line M5-M5 in FIG 48A, showing half blanket base or basic insulating layer 64, conductive traces or interconnects 74, and blanket over insulating layer 76 extending down from the vertical sides of die 18 to die pad 46. FIG 48M is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line W5-W5 in FIG 48A, showing that conductive traces or interconnects 74 are now oriented horizontally on half blanket base or basic insulating layer 64 to prepare for conductive traces or interconnects 74 to extend horizontally to leads 12.Figure 48N is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded lead frame unit 46 along reference line V5-V5 in Figure 48A, showing the terminal ends of each conductive trace or interconnect 74 as it extends downward through a through hole or void 56 in the half blanket base or foundation layer 64 to contact the upper surface of each lead 12.

[0224] FIG. 48O is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of a pre-molded leadframe unit 46 along reference line L5-L5 in FIG. 48A. In this example, a half blanket base or base insulating layer 64 includes a v-shaped channel or groove 62 filled with a conductive material (e.g., conductive traces or interconnects 74) from bond pads 50 on the die 18 to leads 12. In FIG. 48O, a blanket overcoat insulating layer 76 is shown covering the top and side surfaces of the half blanket base or base insulating layer 64. However, some examples may not require the blanket overcoat insulating layer 76 to extend laterally beyond the side surfaces of the half blanket base or base insulating layer 64 when the conductive traces or interconnects 74 are otherwise encapsulated within the half blanket base or base insulating layer 64 and blanket overcoat insulating layer 76. FIG 48P is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line M5-M5 in FIG 48A, showing the half blanket base or basic insulating layer 64, the conductive traces or interconnects 74, and the blanket over insulating layer 76 extending down from the vertical sides of the die 18 to the die pad 46. FIG 48Q is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line W5-W5 in FIG 48A, showing that the conductive traces or interconnects 74 are now oriented horizontally on the half blanket base or basic insulating layer 64 to prepare for the conductive traces or interconnects 74 to extend horizontally to the leads 12.Figure 48R is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded lead frame unit 46 along reference line V5-V5 in Figure 48A, showing the terminal ends of each conductive trace or interconnect 74 as it extends downward through a through hole or void 56 in the half blanket base or foundation layer 64 to contact the upper surface of each lead 12.

[0225] Blanket-coated insulation layer over each base or basic insulation layer

[0226] 49A shows a second insulating layer, e.g., a blanket coated insulating layer 76, printed, deposited, formed, or otherwise applied over the exposed portions of the individual base or base insulating layers 66 and the exposed portions of each conductive trace or interconnect 74 on the individual blanket base or base insulating layers 66 (see FIGS. 42A and 42B ), each extending over a portion of the top surface of a lead finger 12 in the pre-molded lead frame 46, across the pre-mold 42, onto one side of the die 18, just beyond the bond pad 50 closest to the side of the die 18 to which each individual base or base insulating layer 66 is adjacent, and across a portion of the top of the die 18 (e.g., at 514 in FIG. 5 ). A number of areas remain uncovered by any base or base layer between the individual base or base insulating layers 66 on each side of the top of the die, and on the top of the die 18 between the two rows of die on the top side of the die. Optionally, the blanket coated insulating layer 76 can be cured at this point or with additional layers later. The blanket coated insulating layer 76 can be a polymer, epoxy, silicone, mold, or other insulator. The blanket coated insulating layer 76 conforms to the topology on the individual base or base insulating layer 66 and the contours of the conductive traces or interconnects 74 formed on the individual base or base insulating layer 66, and is sufficient to ensure that at least all conductive traces or interconnects 74 are wrapped or encapsulated between each individual base or base insulating layer 66 and the blanket coated insulating layer 76. As seen in FIG. 49A, the blanket coated insulating layer 76 covers all individual base or base insulating layers 66, the conductive traces or interconnects 74 on the half blanket base or base insulating layer 66, and the uninsulated portions of the top of the die 18 between the individual base or base insulating layers 66. The blanket coated insulating layer 76 can be formed or deposited using one of several techniques, such as screen printing, photolithography and etching, CVD, PVD, vacuum deposition, inkjet printing, spray coating, microdispensing, aerosol jet, ElectroHydroDynamic (EHD) techniques, having suitable insulating properties.

[0227] If inkjet printing is used, the blanket coated insulating layer 76 can be formed from inkjet deposition compatible polymers such as polyimide inks, thermosetting epoxy-based polymer inks, and UV curable acrylate inks. To avoid excessive stress on the assembly, it is preferable to use polymers with a modulus of elasticity less than 3.4 GPa, more preferably less than 2 GPa. The thickness of the blanket coated insulating layer 76 can range from about 2 μm to 35 μm. A more preferred range is about 2 μm to 20 μm or less, and even more preferably from about 2 μm to about 10 μm. Inkjet printer solvent deposited materials have a solvent, i.e., initial thickness, so that after the solvent dissipates, the remaining material forms an insulating layer with a reduced thickness. Multiple inkjet depositions can be performed (e.g., at 1302 in FIG. 13) to achieve the desired thickness. Inkjet deposition allows for precise placement of material by using a "drop-on-demand" (DOD) technique, in which a container of liquid has a nozzle and a small amount of liquid is extruded from the nozzle in response to an electrical signal. The liquid forms droplets as it falls vertically onto a surface.

[0228] The precision of the inkjet deposition tool allows deposition of liquid material in some areas and precludes deposition of liquid material in other areas as the tool moves across the surface (or as the surface moves under the tool if the tool is fixed). The insulating material can be placed very precisely, even in small areas, so no etching or material removal steps are required to remove the material after inkjet deposition. Single pass deposition increases manufacturing throughput and reduces costs, but may not provide the more precise and / or desired results of multi-pass deposition. As additional inkjet materials are developed, a reduction in the amount of solvent can reduce the initial thickness required, thereby reducing the need for multi-pass deposition. FIG. 49B is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 along reference line K6-K6 of FIG. 49A. The orientation of the individual base or foundation insulating layer 66, conductive trace 9 interconnects 74, and blanket coated insulating layer 76 are also shown in FIG. 49A.

[0229] FIG 49C is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of a pre-molded leadframe unit 46 along reference line L6-L6 of FIG 49A, according to one example. In FIG 49C, a blanket overcoat insulating layer 76 is shown over the top and side surfaces of the individual base or base insulating layers 66. FIG 49D is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of a pre-molded leadframe unit 46 along reference line M6-M6 of FIG 49A, showing the individual base or base insulating layers 66 (three shown), conductive traces or interconnects 74, and blanket overcoat insulating layers 76 extending down from the vertical sides of the die 18 to the die pad 46. FIG 49E is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line W6-W6 in FIG 49A, showing conductive traces or interconnects 74, where each conductive trace or interconnect 74 is oriented horizontally on a respective base or base insulating layer 66 in preparation for extending horizontally to a lead 12. FIG 49F is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line V6-V6 in FIG 49A, showing an end of each conductive trace or interconnect 74 as it extends downwardly through a through hole or void 56 in a respective base or base layer 66 to abut an upper surface of a respective lead 12.

[0230] FIG. 49G is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line L6-L6 in FIG. 49A. In this example, each individual base or base insulating layer 66 includes a rectangular channel or groove 58 filled with conductive material (e.g., conductive traces or interconnects 74) from bond pads 50 to leads 12 on die 18. In FIG. 49G, a blanket overcoat insulating layer 76 is shown covering the top and side surfaces of each individual base or base insulating layer 66. FIG. 49H is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line M6-M6 in FIG. 49A, showing each individual base or base insulating layer 66, conductive traces or interconnects 74, and blanket overcoat insulating layer 76 extending down the vertical sides of die 18 to die pad 46. FIG 49I is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line W6-W6 in FIG 49A and shows conductive traces or interconnects 74, each oriented horizontally on a respective base or base insulating layer 66 in preparation for extending horizontally to a lead 12. FIG 49J is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line V6-V6 in FIG 49A and shows a terminal end of each conductive trace or interconnect 74 as it extends downwardly through a through hole or void 56 in a respective base or base layer 66 to abut an upper surface of a respective lead 12.

[0231] Figure 49K is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line L6-L6 in Figure 49A. In this example, each individual base or base insulating layer 66 includes a semi-circular channel or groove 60 filled with conductive material (e.g., conductive traces or interconnects 74) from bond pads 50 on die 18 to leads 12. In Figure 49K, a blanket over insulating layer 76 is shown covering the top and side surfaces of each base or base insulating layer 66. FIG 49L is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line M6-M6 in FIG 49A, showing the individual base or base insulating layer 66, conductive traces or interconnects 74, and blanket coated insulating layer 76 extending down the vertical sides of the die 18 to the die pad 46. FIG 49M is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line W6-W6 in FIG 49A, showing the conductive traces or interconnects 74, with each conductive trace or interconnect oriented horizontally on its respective base or base insulating layer 66 to prepare the conductive traces or interconnects 74 to extend horizontally to the leads 12. Figure 49N is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded lead frame unit 46 along reference line V6-V6 in Figure 49A, showing the terminal ends of each conductive trace or interconnect 74 as they extend downward through the through holes or voids 56 of each individual base or foundation layer 66 to contact the upper surface of each lead 12.

[0232] FIG. 49O is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line L6-L6 in FIG. 49A. In this example, each base or base insulating layer 66 includes a v-shaped channel or groove 62 filled with conductive material (e.g., conductive traces or interconnects 74) from bond pads 50 on the die 18 to leads 12. In FIG. 49O, a blanket overcoat insulating layer 76 is shown covering the top and side surfaces of each base or base insulating layer 66. FIG. 49P is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line M6-M6 in FIG. 49A, showing each base or base insulating layer 66, conductive traces or interconnects 74, and blanket overcoat insulating layer 76 extending down the vertical sides of the die 18 to the die pad 46. FIG 49Q is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line W6-W6 in FIG 49A, showing that conductive traces or interconnects 74 are now oriented horizontally on their respective base or base insulating layer 66 to prepare for the conductive traces or interconnects 74 to extend horizontally to leads 12. FIG 49R is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line V6-V6 in FIG 49A, showing the terminal end of each conductive trace or interconnect 74 as it extends downward through a through-hole or void 56 in half blanket base or base layer 64 to abut the upper surface of a respective lead 12.

[0233] A half blanket insulation layer on top of a blanket base or basic insulation layer

[0234] FIG. 50A shows two half blanket coated insulating layers 78, each printed, deposited, formed, or otherwise applied over the exposed portions of the blanket base or basic insulating layer 52 and the exposed portions of the conductive traces or interconnects 74 on the base or basic insulating layer 52 (see FIGS. 40A and 40B), covering a portion of the top surface of the pre-molded lead frame 46, across the pre-molded 42, over one side of the die 18, across the top of the die 18, down the other side of the die 18, across the pre-molded 42 on the other side of the pre-molded lead frame 46, and a portion of the top surface of the lead fingers 12 on the other side of the pre-molded lead frame 46 (e.g., at 514 in FIG. 5). Optionally, the half blanket coated insulating layer 78 may be cured at this point or later with additional layers. The half blanket coated insulating layer 78 may be a polymer, epoxy, silicone, mold, or other insulator. Each half blanket coated insulating layer 78 follows the topology on the blanket base or basic insulating layer 52 and the contours of the conductive traces or interconnects 74 formed on the blanket base or basic insulating layer 52, at least sufficient to ensure that all conductive traces or interconnects 74 are wrapped or sealed between the blanket base or basic insulating layer 52 and each half blanket coated insulating layer 78. As seen in FIG. 50A, each half blanket coated insulating layer 78 covers a portion of the blanket base or basic insulating layer 52, which covers the top surface of the die 18, the side surfaces of the die 18 that are adjacent bond pads 50, and the conductive traces or interconnects 74 on the blanket base or basic insulating layer 52. The half blanket coated insulating layer 78 can be formed or deposited using one of several techniques, such as screen printing, photolithography and etching, CVD, PVD, vacuum deposition, inkjet printing, spray coating, microdispensing, aerosol jet, ElectroHydroDynamic (EHD) techniques, having suitable insulating properties.

[0235] If inkjet printing is used, the half blanket coated insulating layer 78 can be formed from inkjet deposition compatible polymers such as polyimide inks, heat curable epoxy-based polymer inks, and UV curable acrylate inks. To avoid excessive stress on the assembly, it is preferable to use polymers with a modulus of elasticity less than 3.4 GPa, more preferably less than 2 GPa. The thickness of the blanket coated insulating layer 76 can range from about 2 μm to 35 μm. A more preferred range is about 2 μm to 20 μm or less, and even more preferably from about 2 μm to about 10 μm. Inkjet printer solvent deposited material has a solvent, i.e., initial thickness, so that after the solvent dissipates, the remaining material forms an insulating layer with a reduced thickness. Multiple inkjet depositions can be performed (e.g., at 1302 in FIG. 13) to achieve the desired thickness. Inkjet deposition allows for precise placement of material by using a "drop on demand" (DOD) technique, in which a reservoir of liquid has a nozzle and a small amount of liquid is extruded from the nozzle in response to an electrical signal. Liquids form droplets when dropped vertically onto a surface.

[0236] The precision of the inkjet deposition tool allows deposition of liquid material in some areas and precludes deposition of liquid material in other areas as the tool moves across the surface (or as the surface moves under the tool if the tool is fixed). The insulating material can be placed very precisely, even in small areas, so no etching or material removal steps are required to remove the material after inkjet deposition. Single pass deposition increases manufacturing throughput and reduces costs, but may not provide the more precise and / or desired results of multi-pass deposition. As additional inkjet materials are developed, a reduction in the amount of solvent can reduce the initial thickness required, thereby reducing the need for multi-pass deposition. FIG. 50B is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded lead frame unit 46 along reference line N4-N4 of FIG. 50A. The orientation of blanket base or basic insulating layer 52, conductive traces or interconnects 74, and half blanket coated insulating layer 78 are also shown in FIG. 50A.

[0237] 50C is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of a pre-molded leadframe unit 46 along reference line O4-O4 of FIG. 50A, according to one example. In FIG. 50C, a half blanket coated insulating layer 78 is shown covering the top and side surfaces of a portion of the blanket base or basic insulating layer 52. However, some examples may not require the half blanket coated insulating layer 78 to extend laterally beyond the side surfaces of the blanket base or basic insulating layer 52 when the conductive traces or interconnects 74 are otherwise encapsulated within the blanket base or basic insulating layer 52 and each half blanket coated insulating layer 78. 50D is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line P4-P4 in FIG. 50A , showing blanket base or basic insulating layer 52, conductive traces or interconnects 74, and half blanket coated insulating layer 78 extending down the vertical sides of die 18 to die pad 46. FIG. 50E is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line Q4-Q4 in FIG. 50A , showing that conductive traces or interconnects 74 are now oriented horizontally on blanket base or basic insulating layer 52 to prepare for conductive traces or interconnects 74 to extend horizontally to leads 12. Figure 50F is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded lead frame unit 46 along reference line X4-X4 in Figure 50A, showing the terminal ends of each conductive trace or interconnect 74 as it extends downward through a through hole or void 56 in blanket base or foundation layer 52 to contact the upper surface of each lead 12.

[0238] FIG. 50G is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of a pre-molded leadframe unit 46 along reference line O4-O4 in FIG. 50A. In this example, blanket base or basic insulating layer 52 includes rectangular channels or grooves 58 filled with conductive material (e.g., conductive traces or interconnects 74) from bond pads 50 to leads 12 on die 18. In FIG. 50G, a half blanket coated insulating layer 78 is shown covering a portion of the top and side surfaces of blanket base or basic insulating layer 52. However, some examples may not require half blanket coated insulating layer 78 to extend laterally beyond the side surfaces of blanket base or basic insulating layer 52 when conductive traces or interconnects 74 are otherwise encapsulated within blanket base or basic insulating layer 52 and half blanket coated insulating layer 78. FIG 50H is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line P4-P4 in FIG 50A, showing blanket base or basic insulating layer 52, conductive traces or interconnects 74, and half blanket coated insulating layer 78 extending down the vertical sides of die 18 to die pad 46. FIG 50I is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line Q4-Q4 in FIG 50A, showing conductive traces or interconnects 74 oriented horizontally on blanket base or basic insulating layer 52 to prepare for conductive traces or interconnects 74 to extend horizontally to leads 12.Figure 50J is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded lead frame unit 46 along reference line X4-X4 in Figure 50A, showing the terminal ends of each conductive trace or interconnect 74 as it extends downward through a through hole or void 56 in blanket base or foundation layer 52 to contact the upper surface of each lead 12.

[0239] FIG. 50K is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of a pre-molded leadframe unit 46 along reference line O4-O4 in FIG. 50A. In this example, blanket base or basic insulating layer 52 includes semi-circular channels or grooves 60 filled with conductive material (e.g., conductive traces or interconnects 74) from bond pads 50 to leads 12 on die 18. In FIG. 50K, a half blanket coated insulating layer 78 is shown covering the top surface and a portion of the side surfaces of blanket base or basic insulating layer 52. However, some examples may not require half blanket coated insulating layer 78 to extend laterally beyond the side surfaces of blanket base or basic insulating layer 52 when conductive traces or interconnects 74 are otherwise encapsulated within blanket base or basic insulating layer 52 and half blanket coated insulating layer 78. FIG 50L is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line P4-P4 in FIG 50A, showing blanket base or basic insulating layer 52, conductive traces or interconnects 74, and half blanket coated insulating layer 78 extending down from a vertical side of the die 18 to the die pad 46. FIG 50M is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line Q4-Q4 in FIG 50A, showing that conductive traces or interconnects 74 are now oriented horizontally on blanket base or basic insulating layer 52 to prepare for the conductive traces or interconnects 74 to extend horizontally to the leads 12.Figure 50N is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of the die attach pad 14 of a pre-molded lead frame unit 46 along reference line X4-X4 of Figure 590, showing the terminal ends of each conductive trace or interconnect 74 as it extends downward through a through hole or void 56 in the blanket base or foundation layer 52 to contact the upper surface of each lead 12.

[0240] FIG. 50O is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of a pre-molded leadframe unit 46 along reference line O4-O4 in FIG. 50A. In this example, blanket base or base insulating layer 52 includes a v-shaped channel or groove 62 filled with conductive material (e.g., conductive traces or interconnects 74) from bond pads 50 to leads 12 on the die 18. In FIG. 50O, a half blanket coated insulating layer 78 is shown covering a portion of the top and side surfaces of blanket base or base insulating layer 52. However, some examples may not require half blanket coated insulating layer 78 to extend laterally beyond the side surfaces of blanket base or base insulating layer 52 when conductive traces or interconnects 74 are otherwise encapsulated within blanket base or base insulating layer 52 and half blanket coated insulating layer 78. FIG 50P is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line P4-P4 in FIG 50A, showing blanket base or basic insulating layer 52, conductive traces or interconnects 74, and half blanket coated insulating layer 78 extending down from a vertical side of the die 18 to the die pad 46. FIG 50Q is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line Q4-Q4 in FIG 50A, showing that conductive traces or interconnects 74 are now oriented horizontally on blanket base or basic insulating layer 52 to prepare for the conductive traces or interconnects 74 to extend horizontally to the leads 12.Figure 50R is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded lead frame unit 46 along reference line X4-X4 in Figure 50A, showing the terminal ends of each conductive trace or interconnect 74 as it extends downward through a through hole or void 56 in blanket base or foundation layer 52 to contact the upper surface of each lead 12.

[0241] Half-blanket base or half-blanket cover insulation layer on top of basic insulation layer

[0242] 51A shows two half blanket coated insulating layers 78 each printed, deposited, formed, or otherwise applied over the exposed portions of the half blanket base or base insulating layer 64 and the exposed portions of the conductive traces or interconnects 74 on the half blanket base or base insulating layer 66 (see FIGS. 41A and 41B), each extending over a portion of the top surface of the lead fingers 12 in the pre-molded lead frame 46, across the pre-molded lead frame 42, onto one side of the die 18, and across a portion of the top of the die 18 just beyond the bond pads 50 closest to the side of the die 18 to which the respective half blanket base or base insulating layer 64 is adjacent (e.g., at 514 in FIG. 5). The areas on the top of the die 18 between the half blanket base or base insulating layers 64 remain uncovered by any base or base layer. Optionally, the half blanket coated insulating layers 78 can be cured at this point or later with additional layers. The half blanket coated insulating layer 78 may be a polymer, epoxy, silicone, mold, or other insulator. Each half blanket coated insulating layer 78 conforms to the topology on the respective half blanket base or basic insulating layer 64 and the contours of the conductive traces or interconnects 74 formed on the respective half blanket base or basic insulating layer 64, and is at least sufficient to ensure that all conductive traces or interconnects 74 are wrapped or sealed between the half blanket base or basic insulating layer 64 and the half blanket coated insulating layer 78. As seen in FIG. 60A, each half blanket coated insulating layer 78 covers the half blanket base or basic insulating layer 64, the conductive traces or interconnects 74 on the half blanket base or basic insulating layer 64. Also, although this embodiment shows two half blanket coated insulating layers 78, each covering a respective half blanket base or base insulating layer 64, two or more half blanket coated insulating layers and a half blanket base or base insulating layer pairing wrapping or surrounding one or more conductive traces or interconnects 74 may be used.The half blanket coated insulating layer 78 can be formed or deposited using one of several techniques, such as screen printing, photolithography and etching, CVD, PVD, vacuum deposition, inkjet printing, spray coating, microdispensing, aerosol jet, ElectroHydroDynamic (EHD) techniques, having suitable insulating properties.

[0243] If inkjet printing is used, the half blanket coated insulating layer 78 can be formed from inkjet deposition compatible polymers such as polyimide inks, heat curable epoxy-based polymer inks, and UV curable acrylate inks. To avoid excessive stress on the assembly, it is preferable to use polymers with a modulus of elasticity less than 3.4 GPa, more preferably less than 2 GPa. The thickness of the blanket coated insulating layer 76 can range from about 2 μm to 35 μm. A more preferred range is about 2 μm to 20 μm or less, and even more preferably from about 2 μm to about 10 μm. Inkjet printer solvent deposited material has a solvent, i.e., initial thickness, so that after the solvent dissipates, the remaining material forms an insulating layer with a reduced thickness. Multiple inkjet depositions can be performed (e.g., at 1302 in FIG. 13) to achieve the desired thickness. Inkjet deposition allows for precise placement of material by using a "drop on demand" (DOD) technique, in which a reservoir of liquid has a nozzle and a small amount of liquid is extruded from the nozzle in response to an electrical signal. Liquids form droplets when dropped vertically onto a surface.

[0244] The precision of the inkjet deposition tool allows deposition of liquid material in some areas and precludes deposition of liquid material in other areas as the tool moves across the surface (or as the surface moves under the tool if the tool is fixed). The insulating material can be placed very precisely, even in small areas, so no etching or material removal steps are required to remove the material after inkjet deposition. Single pass deposition increases manufacturing throughput and reduces costs, but may not provide the more precise and / or desired results of multi-pass deposition. As additional inkjet materials are developed, a reduction in the amount of solvent can reduce the initial thickness required, thereby reducing the need for multi-pass deposition. FIG. 51B is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded lead frame unit 46 along reference line N5-N5 of FIG. 51A. The orientation of half blanket base or basic insulating layer 64, conductive traces or interconnects 74, and half blanket over insulating layer 78 are also shown in FIG. 51A.

[0245] 51C is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of a pre-molded leadframe unit 46 along reference line O5-O5 of FIG. 51A, according to one example. In FIG. 51C, a half blanket coated insulating layer 78 is shown covering the top and side surfaces of the half blanket base or basic insulating layer 64. However, some examples may not require the half blanket coated insulating layer 78 to extend laterally beyond the side surfaces of the half blanket base or basic insulating layer 64 when the conductive traces or interconnects 74 are otherwise encapsulated within the half blanket base or basic insulating layer 64 and half blanket coated insulating layer 78. 51D is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line P5-P5 in FIG. 51A, showing half blanket base or basic insulating layer 64, conductive traces or interconnects 74, and half blanket over insulating layer 78 extending up the vertical sides of die 18 to die pad 46. FIG. 51E is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line Q5-Q5 in FIG. 51A, showing that conductive traces or interconnects 74 are now oriented horizontally on half blanket base or basic insulating layer 64 to prepare for conductive traces or interconnects 74 to extend horizontally to leads 12. Figure 51F is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded lead frame unit 46 along reference line X5-X5 in Figure 51A, showing the terminal ends of each conductive trace or interconnect 74 as it extends downward through a through hole or void 56 in the half blanket base or foundation layer 64 to contact the upper surface of each lead 12.

[0246] FIG. 51G is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of pre-molded leadframe unit 46 along reference line O5-O5 in FIG. 51A. In this example, each half blanket base or base insulating layer 64 includes a rectangular channel or groove 58 filled with conductive material (e.g., conductive traces or interconnects 74) from bond pads 50 to leads 12 on die 18. In FIG. 51G, half blanket coated insulating layer 78 is shown covering the top and side surfaces of half blanket base or base insulating layer 64. However, some examples may not require half blanket coated insulating layer 78 to extend laterally beyond the side surfaces of half blanket base or base insulating layer 64 when conductive traces or interconnects 74 are otherwise encapsulated within half blanket base or base insulating layer 64 and half blanket coated insulating layer 76. 51H is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line P5-P5 in FIG. 51A, showing half blanket base or basic insulating layer 64, conductive traces or interconnects 74, and half blanket over insulating layer 78 extending up the vertical sides of die 18 to die pad 46. FIG. 51I is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line Q5-Q5 in FIG. 51A, showing that conductive traces or interconnects 74 are now oriented horizontally on half blanket base or basic insulating layer 64 to prepare for conductive traces or interconnects 74 to extend horizontally to leads 12.Figure 51J is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded lead frame unit 46 along reference line X5-X5 in Figure 51A, showing the terminal ends of each conductive trace or interconnect 74 as it extends downward through a through hole or void 56 in the half blanket base or foundation layer 64 to contact the upper surface of each lead 12.

[0247] FIG. 51K is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of pre-molded leadframe unit 46 along reference line O5-O5 in FIG. 51A. In this example, half blanket base or basic insulating layer 64 includes semi-circular channels or grooves 60 filled with conductive material (e.g., conductive traces or interconnects 74) from bond pads 50 to leads 12 on die 18. In FIG. 51K, half blanket coated insulating layer 78 is shown covering the top and side surfaces of half blanket base or basic insulating layer 64. However, some examples may not require half blanket coated insulating layer 78 to extend laterally beyond the side surfaces of half blanket base or basic insulating layer 64 when conductive traces or interconnects 74 are otherwise encapsulated within half blanket base or basic insulating layer 64 and half blanket coated insulating layer 78. 51L is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line P5-P5 in FIG. 51A, showing half blanket base or basic insulating layer 64, conductive traces or interconnects 74, and half blanket over insulating layer 78 extending up the vertical sides of die 18 to die pad 46. FIG. 51M is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line Q5-Q5 in FIG. 51A, showing that conductive traces or interconnects 74 are now oriented horizontally on half blanket base or basic insulating layer 64 to prepare for conductive traces or interconnects 74 to extend horizontally to leads 12.Figure 51N is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of the die attach pad 14 of a pre-molded lead frame unit 46 along reference line X5-X5 in Figure 51A, showing the terminal ends of each conductive trace or interconnect 74 as it extends downward through a through hole or void 56 in the half blanket base or foundation layer 64 to contact the upper surface of each lead 12.

[0248] FIG. 51O is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of a pre-molded leadframe unit 46 along reference line O5-O5 in FIG. 51A. In this example, a half blanket base or base insulating layer 64 includes a v-shaped channel or groove 62 filled with a conductive material (e.g., conductive traces or interconnects 74) from bond pads 50 to leads 12 on the die 18. In FIG. 51O, a half blanket coated insulating layer 78 is shown covering the top and side surfaces of the half blanket base or base insulating layer 64. However, some examples may not require the blanket coated insulating layer 76 to extend laterally beyond the side surfaces of the half blanket base or base insulating layer 64 when the conductive traces or interconnects 74 are otherwise encapsulated within the half blanket base or base insulating layer 64 and half blanket coated insulating layer 78. 51P is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line P5-P5 in FIG. 51A , showing half blanket base or basic insulating layer 64, conductive traces or interconnects 74, and half blanket over insulating layer 78 extending up the vertical sides of die 18 to die pad 46. FIG. 51Q is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line Q5-Q5 in FIG. 51A , showing that conductive traces or interconnects 74 are now oriented horizontally on half blanket base or basic insulating layer 64 to prepare for conductive traces or interconnects 74 to extend horizontally to leads 12.Figure 51R is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded lead frame unit 46 along reference line X5-X5 in Figure 51A, showing the terminal ends of each conductive trace or interconnect 74 as it extends downward through a through hole or void 56 in the half blanket base or foundation layer 64 to contact the upper surface of each lead 12.

[0249] Half blanket insulation layer over each base or basic insulation layer

[0250] 52A shows two half blanket coated insulating layers 76, each printed, deposited, formed, or otherwise applied over the exposed portions of an individual base or base insulating layer 66 and the exposed portions of each conductive trace or interconnect 74 on the individual blanket base or base insulating layer 66 (see FIGS. 42A and 42B ), each extending over a portion of the top surface of the lead fingers 12 in the pre-molded lead frame 46, across the pre-molded lead frame 42, onto one side of the die 18, and across a portion of the top of the die 18 just beyond the bond pad 50 closest to the side of the die 18 that each individual base or base insulating layer 66 is adjacent to (e.g., at 514 in FIG. 5 ). A number of areas remain uncovered by any base or base layer between the individual base or base insulating layers 66 on each side of the top of the die, and on the top of the die 18 between the two rows of die on the top side of the die. Optionally, the half blanket coated insulating layer 78 can be cured at this point or later with additional layers. The half blanket coated insulating layer 78 can be a polymer, epoxy, silicone, mold, or other insulator. The half blanket coated insulating layer 78 conforms to the topology on the individual base or basic insulating layer 66 and the contours of the conductive traces or interconnects 74 formed on the individual base or basic insulating layer 66, and is sufficient to ensure that at least all conductive traces or interconnects 74 are wrapped or encapsulated between each individual base or basic insulating layer 66 and the half blanket coated insulating layer 78. As seen in FIG. 52A, the half blanket coated insulating layer 78 covers the plurality of individual base or basic insulating layers 66, the conductive traces or interconnects 74 on the half blanket base or basic insulating layer 66, and the uninsulated portions of the top of the die 18 between the individual base or basic insulating layers 66. The half blanket coated insulating layer 78 can be formed or deposited using one of several techniques, such as screen printing, photolithography and etching, CVD, PVD, vacuum deposition, inkjet printing, spray coating, microdispensing, aerosol jet, ElectroHydroDynamic (EHD) techniques, having suitable insulating properties.

[0251] If inkjet printing is used, the blanket coated insulating layer 76 can be formed from inkjet deposition compatible polymers such as polyimide inks, thermosetting epoxy-based polymer inks, and UV curable acrylate inks. To avoid excessive stress on the assembly, it is preferable to use polymers with a modulus of elasticity less than 3.4 GPa, more preferably less than 2 GPa. The thickness of the blanket coated insulating layer 76 can range from about 2 μm to 35 μm. A more preferred range is about 2 μm to 20 μm or less, and even more preferably from about 2 μm to about 10 μm. Inkjet printer solvent deposited materials have a solvent, i.e., initial thickness, so that after the solvent dissipates, the remaining material forms an insulating layer with a reduced thickness. Multiple inkjet depositions can be performed (e.g., at 1302 in FIG. 13) to achieve the desired thickness. Inkjet deposition allows for precise placement of material by using a "drop-on-demand" (DOD) technique, in which a container of liquid has a nozzle and a small amount of liquid is extruded from the nozzle in response to an electrical signal. The liquid forms droplets as it falls vertically onto a surface.

[0252] The precision of the inkjet deposition tool allows deposition of liquid material in some areas and precludes deposition of liquid material in other areas as the tool moves across the surface (or as the surface moves under the tool if the tool is fixed). The insulating material can be placed very precisely, even in small areas, so no etching or material removal steps are required to remove the material after inkjet deposition. Single pass deposition increases manufacturing throughput and reduces costs, but may not provide the more precise and / or desired results of multi-pass deposition. As additional inkjet materials are developed, a reduction in the amount of solvent can reduce the initial thickness required, thereby reducing the need for multi-pass deposition. FIG. 52B is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded lead frame unit 46 along reference line N6-N6 of FIG. 52A. The orientation of the individual base or basic insulating layer 66, conductive traces or interconnects 74, and half blanket coated insulating layer 78 are also shown in FIG. 52A.

[0253] FIG 52C is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line O6-O6 of FIG 52A, according to one example. In FIG 52C, a half blanket coated insulating layer 78 is shown over the top and side surfaces of the individual base or base insulating layers 66. FIG 52D is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line P6-P6 of FIG 52A, showing the individual base or base insulating layers 66 (three shown), conductive traces or interconnects 74, and half blanket coated insulating layers 78 extending down from the vertical sides of the die 18 to the die pad 46. FIG 52E is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line Q6-Q6 in FIG 52A, showing conductive traces or interconnects 74, each oriented horizontally on an individual base or base insulating layer 66 to prepare for the conductive traces or interconnects 74 to extend horizontally to a lead 12. FIG 52F is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line X6-X6 in FIG 52A, showing the terminal end of each conductive trace or interconnect 74 as it extends downwardly through a through-hole or void 56 in a respective individual base or base layer 66 to abut the upper surface of a respective lead 12.

[0254] FIG. 52G is a cross-sectional view of integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line O6-O6 of FIG. 52A.

[0255] FIG. 52H is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top side of the die attach pad of a pre-molded leadframe unit 46 along reference line P6-P6 in FIG. 52A, showing the individual base or basic insulating layers 66, conductive traces or interconnects 74, and a half blanket coated insulating layer 78 extending down from the vertical sides of the die 18 to the die pad 46.

[0256] FIG 52I is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line Q6-Q6 in FIG 52A, showing that each conductive trace or interconnect 74 is now oriented horizontally on the half blanket base or base insulating layer 52 to prepare for the conductive trace or interconnect 74 to extend horizontally to the leads 12. FIG 52J is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line X6-X6 in FIG 52A, showing the terminal end of each conductive trace or interconnect 74 as it extends downward through a through hole or void 56 in a respective base or base layer 66 to abut the upper surface of a respective lead 12.

[0257] Figure 52K is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line O6-O6 in Figure 52A. In this example, each individual base or base insulating layer 66 includes a semi-circular channel or groove 60 filled with conductive material (e.g., conductive traces or interconnects 74) from bond pads 50 on die 18 to leads 12. In Figure 52K, a half blanket coated insulating layer 76 is shown covering the top and side surfaces of each individual base or base insulating layer 66. FIG 52L is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top side of the die attach pad of a pre-molded leadframe unit 46 taken along reference line P6-P6 in FIG 52A, showing the individual base or base insulating layer 66, conductive traces or interconnects 74, and half blanket coated insulating layer 78 extending up the vertical sides of the die 18 to the die pad 46. FIG 52M is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of the die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line Q6-Q6 in FIG 52A, showing the conductive traces or interconnects 74, each oriented horizontally on their respective individual base or base insulating layer 66 to prepare the conductive traces or interconnects 74 to extend horizontally to the leads 12. Figure 52N is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded lead frame unit 46 along reference line X6-X6 in Figure 52A, showing the ends of each conductive trace or interconnect 74 as it extends downward through a through hole or void 56 in each individual base or foundation layer 66 to contact the upper surface of each lead 12.

[0258] Figure 52O is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line O6-O6 in Figure 52A. In this example, each base or base insulating layer 66 includes a v-shaped channel or groove 62 filled with conductive material (e.g., conductive traces or interconnects 74) from bond pads 50 on die 18 to leads 12. In Figure 52O, a half blanket coated insulating layer 78 is shown covering the top and side surfaces of each base or base insulating layer 66. FIG 52P is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top side of the die attach pad of a pre-molded leadframe unit 46 taken along reference line P6-P6 in FIG 52A, showing the individual base or base insulating layers 66, conductive traces or interconnects 74, and half blanket coated insulating layer 78 extending down from the vertical sides of the die 18 to the die pad 46. FIG 52Q is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of the die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line Q6-Q6 in FIG 52A, showing that the conductive traces or interconnects 74 are now oriented horizontally on their respective individual base or base insulating layers 66 to prepare them to extend horizontally to the leads 12. Figure 52R is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded lead frame unit 46 along reference line X6-X6 in Figure 52A, showing the terminal ends of each conductive trace or interconnect 74 as they extend downward through through holes or voids 56 in individual base or foundation layers 66 to contact the upper surface of each lead 12.

[0259] Individual overlying insulation layers on a blanket base or base insulation layer

[0260] FIG. 53A shows individual overlying insulating layers 80, each printed, deposited, formed, or otherwise applied over an exposed portion of the half blanket base or basic insulating layer 52 and the exposed portions of the conductive traces or interconnects 74 on the base or basic insulating layer 52 (see FIGS. 40A and 40B), covering a portion of the top surface of the lead fingers 12 in the premolded lead frame 46, across the premolded 42, over one side of the die 18, across the top of the die 18, down the other side of the die 18, across the premolded 42 on the other side of the premolded lead frame 46, and a portion of the top surface of the lead fingers 12 on the other side of the premolded lead frame 46 (e.g., at 514 in FIG. 5). Optionally, the individual overlying insulating layers 80 can be cured at this point or later with additional layers. The individual overlying insulating layers 80 can be polymers, epoxies, silicones, molds, or other insulators. Each individual covering insulating layer 80 follows the topology on the half blanket base or basic insulating layer 52 and the contours of the conductive traces or interconnects 74 formed on the blanket base or basic insulating layer 52, at least sufficient to ensure that all conductive traces or interconnects 74 are wrapped or sealed between the blanket base or basic insulating layer 52 and the individual covering insulating layer 80. As seen in FIG. 53A, each individual covering insulating layer 80 covers a portion of the half blanket base or basic insulating layer 52, which covers the top surface of the die 18, the side surfaces of the die 18 adjacent bond pads 50, and the conductive traces or interconnects 74 on the half blanket base or basic insulating layer 52. The individual covering insulating layers 80 can be formed or deposited using one of several techniques, such as screen printing, photolithography and etching, CVD, PVD, vacuum deposition, inkjet printing, spray coating, microdispensing, aerosol jet, ElectroHydroDynamic (EHD) techniques, having suitable insulating properties.

[0261] If inkjet printing is used, the individual overlying insulating layers 80 can be formed from inkjet deposition compatible polymers such as polyimide inks, heat curable epoxy-based polymer inks, and UV curable acrylate inks. To avoid excessive stress on the assembly, it is preferable to use polymers with a modulus of elasticity less than 3.4 GPa, more preferably less than 2 GPa. The thickness of the blanket overlying insulating layer 76 can range from about 2 μm to 35 μm. A more preferred range is about 2 μm to 20 μm or less, and even more preferably from about 2 μm to about 10 μm. Inkjet printer solvent deposited material has a solvent, i.e., initial thickness, so that after the solvent dissipates, the remaining material forms an insulating layer with a reduced thickness. Multiple inkjet depositions can be performed (e.g., at 1302 in FIG. 13) to achieve the desired thickness. Inkjet deposition allows for precise placement of material by using a "drop-on-demand" (DOD) technique, in which a container of liquid has a nozzle and a small amount of liquid is extruded from the nozzle in response to an electrical signal. The liquid forms droplets as it falls vertically onto a surface.

[0262] The precision of the inkjet deposition tool allows deposition of liquid material in some areas and precludes deposition of liquid material in other areas as the tool moves across the surface (or as the surface moves under the tool if the tool is fixed). The insulating material can be placed very precisely, even in small areas, so no etching or material removal steps are required to remove the material after inkjet deposition. Single pass deposition increases manufacturing throughput and reduces costs, but may not provide the more precise and / or desired results of multi-pass deposition. As additional inkjet materials are developed, a reduction in the amount of solvent can reduce the initial thickness required, thereby reducing the need for multi-pass deposition. FIG. 53B is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded leadframe unit 46 along reference line R4-R4 of FIG. 53A. The orientations of blanket base or basic insulating layer 52, conductive traces or interconnects 74, and individual overlying insulating layers 80 are also shown in FIG. 53A.

[0263] FIG. 53C is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of a pre-molded leadframe unit 46 along reference line S4-S4 of FIG. 53A, according to one example. In FIG. 53C, individual overlying insulating layers 78 are shown over blanket base or base insulating layer 52. Each individual overlying insulating layer covers a respective conductive trace or interconnect on half blanket base or base insulating layer 52. FIG. 53D is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of a pre-molded leadframe unit 46 along reference line T4-T4 of FIG. 53A, showing half blanket base or base insulating layer 52, conductive traces or interconnects 74, and individual overlying insulating layers 80 extending down from vertical sides of die 18 to die pad 46. FIG 53E is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line U4-U4 in FIG 53A, showing that conductive traces or interconnects 74 are now oriented horizontally on half blanket base or base insulating layer 52 to prepare for conductor traces or interconnects 74 to extend horizontally to leads 12. FIG 53F is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line Y4-Y4 in FIG 53A, showing the terminal ends of each conductive trace or interconnect 74 as it extends downward through a through hole or void 56 in half blanket base or base layer 52 to contact the upper surface of a respective lead 12.

[0264] Figure 53G is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line S4-S4 in Figure 53A. In this example, half blanket base or base insulating layer 52 includes rectangular channels or grooves 58 filled with conductive material (e.g., conductive traces or interconnects 74) from bond pads 50 to leads 12 on die 18. In Figure 53G, individual overlying insulating layers 78 are shown over blanket base or base insulating layer 52. Each individual overlying insulating layer covers a respective conductive trace or interconnect 74. FIG 53H is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line T4-T4 in FIG 53A, showing blanket base or basic insulating layer 52, conductive traces or interconnects 74, and individual overlying insulating layers 80 extending up the vertical sides of the die 18 to the die pad 46. FIG 53I is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line U4-U4 in FIG 53A, showing that conductive traces or interconnects 74 are now oriented horizontally on blanket base or basic insulating layer 52 to prepare for the conductor traces or interconnects 74 to extend horizontally to the leads 12. Figure 53J is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of the die attach pad 14 of a pre-molded lead frame unit 46 along reference line Y4-Y4 in Figure 53A, showing the terminal ends of each conductive trace or interconnect 74 as it extends downward through a through hole or void 56 in the blanket base or foundation layer 52 to contact the upper surface of each lead 12.

[0265] Figure 53K is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line S4-S4 in Figure 53A. In this example, blanket base or basic insulating layer 52 includes semi-circular channels or grooves 60 filled with conductive material (e.g., conductive traces or interconnects 74) from bond pads 50 to leads 12 on die 18. Individual overlying insulating layers 80 are shown in Figure 53K, each covering a conductive trace or interconnect 74 and a portion of blanket base or basic insulating layer 52. FIG 53L is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line T4-T4 in FIG 53A, showing blanket base or basic insulating layer 52, conductive traces or interconnects 74, and individual overlying insulating layers 80 extending down from the vertical sides of the die 18 to the die pad 46. FIG 53M is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line U4-U4 in FIG 53A, showing that conductive traces or interconnects 74 are now oriented horizontally on blanket base or basic insulating layer 52 to prepare for the conductor traces or interconnects 74 to extend horizontally to the leads 12. Figure 53N is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attachment material 22 to the top surface of the die attachment pad 14 of a pre-molded lead frame unit 46 along reference line Y4-Y4 in Figure 53A, showing the terminal ends of each conductive trace or interconnect 74 as it extends downward through a through hole or void 56 in the blanket base or foundation layer 52 to contact the upper surface of each lead 12.

[0266] Figure 53O is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line S4-S4 in Figure 53A. In this example, blanket base or basic insulating layer 52 includes v-shaped channels or grooves 62 filled with conductive material (e.g., conductive traces or interconnects 74) from bond pads 50 on die 18 to leads 12. In Figure 53O, individual overlying insulating layers 80 are shown each covering the conductive traces or interconnects 74 and a portion of blanket base or basic insulating layer 52. FIG 53P is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line T4-T4 in FIG 53A, showing blanket base or basic insulating layer 52, conductive traces or interconnects 74, and individual overlying insulating layers 80 extending up the vertical sides of the die 18 to the die pad 46. FIG 53Q is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line U4-U4 in FIG 53A, showing that conductive traces or interconnects 74 are now oriented horizontally on blanket base or basic insulating layer 52 in preparation for extending horizontally to leads 12. Figure 53R is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of the die attach pad 14 of a pre-molded lead frame unit 46 along reference line Y4-Y4 in Figure 53A, showing the terminal ends of each conductive trace or interconnect 74 as it extends downward through a through hole or void 56 in the blanket base or foundation layer 52 to contact the upper surface of each lead 12.

[0267] Individual overlay insulation layers on a half blanket base or base insulation layer

[0268] 54A shows individual overlying insulating layers 80, each printed, deposited, formed, or otherwise applied over the exposed portions of the half blanket base or base insulating layer 64 and the exposed portions of the conductive traces or interconnects 74 on the half blanket base or base insulating layer 66 (see FIGS. 41A and 41B), each extending over a portion of the top surface of the lead fingers 12 in the pre-molded lead frame 46, across the pre-molded lead frame 42, onto one side of the die 18, and across a portion of the top of the die 18 just beyond the bond pad 50 closest to the side of the die 18 to which the respective half blanket base or base insulating layer 64 is adjacent (e.g., at 514 in FIG. 5). The areas on the top of the die 18 between the half blanket base or base insulating layers 64 remain uncovered by any base or base layer. Optionally, the individual overlying insulating layers 80 can be cured at this point or later with additional layers. The individual covering insulating layers 80 may be polymers, epoxies, silicones, molds, or other insulators. Each individual covering insulating layer 80 follows the topology on the respective half blanket base or basic insulating layer 64 and the contours of the conductive traces or interconnects 74 formed on the respective half blanket base or basic insulating layer 64, at least sufficient to ensure that all conductive traces or interconnects 74 are wrapped or sealed between the half blanket base or basic insulating layer 64 and the respective covering insulating layer 80. As seen in FIG. 54A, each half blanket covering insulating layer 80 covers a portion of the half blanket base or basic insulating layer 64 and the conductive traces or interconnects 74 on the half blanket base or basic insulating layer 64. The individual covering insulating layers 80 may be formed or deposited using one of several techniques, such as screen printing, photolithography and etching, CVD, PVD, vacuum deposition, inkjet printing, spray coating, microdispensing, aerosol jet, ElectroHydroDynamic (EHD) techniques, having suitable insulating properties.

[0269] If inkjet printing is used, the individual overlying insulating layers 80 can be formed from inkjet deposition compatible polymers such as polyimide inks, heat curable epoxy-based polymer inks, and UV curable acrylate inks. To avoid excessive stress on the assembly, it is preferable to use polymers with a modulus of elasticity less than 3.4 GPa, more preferably less than 2 GPa. The thickness of the blanket overlying insulating layer 76 can range from about 2 μm to 35 μm. A more preferred range is about 2 μm to 20 μm or less, and even more preferably from about 2 μm to about 10 μm. Inkjet printer solvent deposited material has a solvent, i.e., initial thickness, so that after the solvent dissipates, the remaining material forms an insulating layer with a reduced thickness. Multiple inkjet depositions can be performed (e.g., at 1302 in FIG. 13) to achieve the desired thickness. Inkjet deposition allows for precise placement of material by using a "drop-on-demand" (DOD) technique, in which a container of liquid has a nozzle and a small amount of liquid is extruded from the nozzle in response to an electrical signal. The liquid forms droplets as it falls vertically onto a surface.

[0270] The precision of the inkjet deposition tool allows deposition of liquid material in some areas and precludes deposition of liquid material in other areas as the tool moves across the surface (or as the surface moves under the tool if the tool is fixed). The insulating material can be placed very precisely, even in small areas, so no etching or material removal steps are required to remove the material after inkjet deposition. Single pass deposition increases manufacturing throughput and reduces costs, but may not provide the more precise and / or desired results of multi-pass deposition. As additional inkjet materials are developed, a reduction in the amount of solvent can reduce the initial thickness required, thereby reducing the need for multi-pass deposition. FIG. 54B is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded leadframe unit 46 along reference line R5-R5 of FIG. 54A. The orientation of half blanket base or basic insulating layer 64, conductive traces or interconnects 74, and individual overlying insulating layers 80 are also shown in FIG. 54A.

[0271] FIG 54C is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line S5-S5 of FIG 54A according to one example. In FIG 54C, an individual overlying insulating layer 80 is shown over a portion of half blanket base or base insulating layer 64. FIG 54D is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line T5-T5 of FIG 54A showing half blanket base or base insulating layer 64, conductive traces or interconnects 74, and individual overlying insulating layer 80 extending up vertical sides of die 18 to die pad 46. FIG 54E is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line U5-U5 in FIG 54A, showing that conductive traces or interconnects 74 are now oriented horizontally on half blanket base or base insulating layer 64 to prepare for conductive traces or interconnects 74 to extend horizontally to leads 12. FIG 54F is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line Y5-Y5 in FIG 54A, showing the terminal ends of each conductive trace or interconnect 74 as it extends downward through a through hole or void 56 in half blanket base or base layer 64 to abut the upper surface of each lead 12.

[0272] FIG. 54G is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line S5-S5 of FIG. 54A. In this example, each half blanket base or base insulating layer 64 includes a rectangular channel or groove 58 filled with conductive material (e.g., conductive traces or interconnects 74) from bond pads 50 on die 18 to leads 12. In FIG. 54G, individual insulating layers 80 are shown overlying half blanket base or base insulating layer 64. FIG. 54H is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line T5-T5 of FIG. 54A, showing half blanket base or base insulating layer 64, conductive traces or interconnects 74, and individual overlying insulating layers 80 extending down from the vertical sides of die 18 to die pad 46. FIG 54I is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line U5-U5 in FIG 54A, showing that conductive traces or interconnects 74 are now oriented horizontally on half blanket base or base insulating layer 64 to prepare for conductive traces or interconnects 74 to extend horizontally to leads 12. FIG 54J is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line Y5-Y5 in FIG 54A, showing the terminal end of each conductive trace or interconnect 74 as it extends downward through a through hole or void 56 in half blanket base or base layer 64 to contact the upper surface of a respective lead 12.

[0273] Figure 54K is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line S5-S5 of Figure 54A. In this example, a half blanket base or basic insulating layer 64 includes semi-circular channels or grooves 60 filled with conductive material (e.g., conductive traces or interconnects 74) from bond pads 50 to leads 12 on die 18. In Figure 54K, a separate overlying insulating layer 80 is shown covering a portion of the conductive traces or interconnects 74 of the half blanket base or basic insulating layer 64. FIG 54L is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line T5-T5 in FIG 54A, showing half blanket base or base insulating layer 64, conductive traces or interconnects 74, and individual overlying insulating layers 80 extending up the vertical sides of the die 18 to the die pad 46. FIG 54M is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line U5-U5 in FIG 54A, showing that the conductive traces or interconnects 74 are now oriented horizontally on the half blanket base or base insulating layer 64 to prepare for the conductive traces or interconnects 74 to extend horizontally to the leads 12. Figure 54N is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attachment material 22 to the top surface of the die attachment pad 14 of a pre-molded lead frame unit 46 along reference line Y5-Y5 in Figure 54A, showing the terminal ends of each conductive trace or interconnect 74 as it extends downward through a through hole or void 56 in the half blanket base or foundation layer 64 to contact the upper surface of each lead 12.

[0274] Figure 54O is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line S5-S5 in Figure 54A. In this example, a half blanket base or base insulating layer 64 includes v-shaped channels or grooves 62 filled with conductive material (e.g., conductive traces or interconnects 74) from bond pads 50 on the die 18 to the leads 12. In Figure 54O, a separate overlying insulating layer 80 is shown over a portion of the half blanket base or base insulating layer 64. FIG 54P is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line T5-T5 in FIG 54A, showing half blanket base or basic insulating layer 64, conductive traces or interconnects 74, and individual overlying insulating layers 80 extending down from the vertical sides of the die 18 to the die pad 46. FIG 54Q is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line U5-U5 in FIG 54A, showing that the conductive traces or interconnects 74 are now oriented horizontally on the half blanket base or basic insulating layer 64 to prepare for the conductive traces or interconnects 74 to extend horizontally to the leads 12. Figure 54R is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded lead frame unit 46 along reference line Y5-Y5 in Figure 54A, showing the terminal ends of each conductive trace or interconnect 74 as they extend downward through the through holes or voids 56 in the half blanket base or foundation layer 64 to contact the upper surface of each lead 12.

[0275] Each covering insulation layer on each base or basic insulation layer

[0276] 55A shows individual overlying insulating layers 80, each printed, deposited, formed, or otherwise applied over the exposed portions of an individual base or base insulating layer 66 and the exposed portions of each conductive trace or interconnect 74 on an individual blanket base or base insulating layer 66 (see FIGS. 42A and 42B), each extending over a portion of the top surface of a lead finger 12 in pre-molded lead frame 46, across pre-molded lead frame 42, onto one side of die 18, and across a portion of the top of die 18 just beyond the bond pad 50 closest to the side of die 18 to which each individual base or base insulating layer 66 is adjacent (e.g., at 514 in FIG. 5). A number of areas remain uncovered by any base or base layer between the individual base or base insulating layers 66 on each side of the top of the die, and on the top of the die 18 between the two rows of die on the top side of the die. Optionally, the individual covering insulating layers 80 can be cured at this point or later with additional layers. The individual covering insulating layers 80 can be polymers, epoxies, silicones, molds, or other insulators. The individual covering insulating layers 80 conform to the topology on the individual base or basic insulating layers 66 and the contours of the conductive traces or interconnects 74 formed on the individual base or basic insulating layers 66, at least sufficient to ensure that each conductive trace or interconnect 74 is wrapped or sealed between the individual base or basic insulating layers 66 and the individual covering insulating layers 80. As seen in FIG. 55A, each individual covering insulating layer 80 covers the individual base or basic insulating layers 66 and the conductive traces or interconnects 74 printed or formed thereon. The individual overlying insulating layers 80 can be formed or deposited using one of several techniques, such as screen printing, photolithography and etching, CVD, PVD, vacuum deposition, inkjet printing, spray coating, microdispensing, aerosol jet, ElectroHydroDynamic (EHD) techniques, having suitable insulating properties.

[0277] If inkjet printing is used, the individual overlying insulating layers 80 can be formed from inkjet deposition compatible polymers such as polyimide inks, heat curable epoxy-based polymer inks, and UV curable acrylate inks. To avoid excessive stress on the assembly, it is preferable to use polymers with a modulus of elasticity less than 3.4 GPa, more preferably less than 2 GPa. The thickness of the blanket overlying insulating layer 76 can range from about 2 μm to 35 μm. A more preferred range is about 2 μm to 20 μm or less, and even more preferably from about 2 μm to about 10 μm. Inkjet printer solvent deposited material has a solvent, i.e., initial thickness, so that after the solvent dissipates, the remaining material forms an insulating layer with a reduced thickness. Multiple inkjet depositions can be performed (e.g., at 1302 in FIG. 13) to achieve the desired thickness. Inkjet deposition allows for precise placement of material by using a "drop-on-demand" (DOD) technique, in which a container of liquid has a nozzle and a small amount of liquid is extruded from the nozzle in response to an electrical signal. The liquid forms droplets as it falls vertically onto a surface.

[0278] The precision of the inkjet deposition tool allows deposition of liquid material in some areas and precludes deposition of liquid material in other areas as the tool moves across the surface (or as the surface moves under the tool if the tool is fixed). The insulating material can be placed very precisely, even in small areas, so no etching or material removal steps are required to remove the material after inkjet deposition. Single pass deposition increases manufacturing throughput and reduces costs, but may not provide the more precise and / or desired results of multi-pass deposition. As additional inkjet materials are developed, a reduction in the amount of solvent can reduce the initial thickness required, thereby reducing the need for multi-pass deposition. FIG. 55B is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded leadframe unit 46 along reference line R6-R6 of FIG. 55A. The orientation of the individual base or basic insulating layer 66, conductive traces or interconnects 74, and individual overlying insulating layer 80 are also shown in FIG. 55A.

[0279] FIG 55C is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of a pre-molded leadframe unit 46 along reference line S6-S6 of FIG 55A, according to one example. In FIG 55C, individual overlying insulating layers 80 are shown each overlying an individual base or base insulating layer 66. FIG 55D is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of a pre-molded leadframe unit 46 along reference line T6-T6 of FIG 55A, showing individual base or base insulating layers 66 (three shown), conductive traces or interconnects 74, and individual overlying insulating layers 80 (three shown) extending down the vertical sides of the die 18 to the die pad 46. FIG 55E is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line U6-U6 in FIG 55A, showing that conductive traces or interconnects 74 are now each oriented horizontally on an individual base or base insulating layer 66 to prepare for the conductive traces or interconnects 74 to extend horizontally to the leads 12. FIG 55F is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line Y6-Y6 in FIG 55A, showing the end of each conductive trace or interconnect 74 as it extends downwardly through a through hole or void 56 in each individual base or base layer 66 to abut the upper surface of a respective lead 12.

[0280] FIG. 55G is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line S6-S6 in FIG. 55A. In this example, each individual base or base insulating layer 66 includes a rectangular channel or groove 58 filled with conductive material (e.g., conductive traces or interconnects 74) from bond pads 50 on die 18 to leads 12. FIG. 55H is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line T6-T6 in FIG. 55A, showing the individual base or base insulating layer 66, conductive traces or interconnects 74, and individual overlying insulating layers 80 extending down from the vertical sides of die 18 to die pad 46. FIG 55I is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line U6-U6 in FIG 55A, showing that conductive traces or interconnects 74 are now each oriented horizontally on an individual base or base insulating layer 66 such that conductive traces or interconnects 74 are arranged to extend horizontally to conductive traces or interconnects 12. FIG 55J is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line Y6-Y6 in FIG 55A, showing an end of each conductive trace or interconnect 74 as it extends downwardly through a through hole or void 56 in each individual base or base layer 66 to abut an upper surface of a respective lead 12.

[0281] FIG. 55K is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line S6-S6 in FIG. 55A. In this example, each individual base or base insulating layer 66 includes a semi-circular channel or groove 60 filled with conductive material (e.g., conductive traces or interconnects 74) from bond pads 50 on die 18 to leads 12. Each individual overlying insulating layer 80 is shown overlying each individual base or base insulating layer 66 in FIG. 55L is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line T6-T6 in FIG. 55A, showing each individual base or base insulating layer 66, conductive traces or interconnects 74, and each overlying insulating layer 80 extending down from the vertical sides of die 18 to die pad 46. FIG 55M is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line U6-U6 in FIG 55A, showing that conductive traces or interconnects 74 are now each oriented horizontally on their respective base or base insulating layer 66 to prepare for the conductive traces or interconnects 74 to extend horizontally to the leads 12. FIG 55N is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to a top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line Y6-Y6 in FIG 55A, showing the ends of each conductive trace or interconnect 74 as it extends downwardly through a through hole or void 56 in each respective base or base layer 66 to abut the upper surface of a respective lead 12.

[0282] FIG. 55O is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line S6-S6 in FIG. 55A. In this example, each base or base insulating layer 66 includes a v-shaped channel or groove 62 filled with conductive material (e.g., conductive traces or interconnects 74) from bond pad 50 on die 18 to leads 12. In FIG. 55O, individual overlying insulating layers 80 are shown overlying individual base or base insulating layers 66. FIG. 55P is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top side of die attach pad 14 of pre-molded leadframe unit 46 taken along reference line T6-T6 in FIG. 55A, showing individual base or base insulating layers 66, conductive traces or interconnects 74, and individual overlying insulating layers 80 extending down from the vertical sides of die 18 to die pad 46. FIGURE 55Q is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line U6-U6 in FIGURE 55A, showing that conductive traces or interconnects 74 are now oriented horizontally on the respective base or base insulating layer 66 to prepare for the conductive traces or interconnects 74 to extend horizontally to the leads 12. FIGURE 55R is a cross-sectional view of an integrated circuit (IC) die 18 attached via die attach material 22 to the top surface of die attach pad 14 of a pre-molded leadframe unit 46 taken along reference line Y6-Y6 in FIGURE 55A, showing the terminal ends of each conductive trace or interconnect 74 as it extends downward through a through-hole or void 56 in the respective base or base layer 66 to abut the upper surface of a respective lead 12.

[0283] 56A-56L show an example where a non-screen printing process 1300 is performed with a print head 68 controlled to translate along a controlled lateral direction or path 75 while directing insulating material along a vertical direction 77 to obtain a desired profile of a blanket coated insulating layer 76 (e.g., FIGS. 47A-49R), a half blanket coated insulating layer 78 (e.g., FIGS. 50A-52R), or an individual insulating layer 80 (e.g., FIGS. 53A-53R). In one example, the process is performed with an inkjet print head 68 having a position controller, such as a servo controller, configured to translate and control the position of the print head 68 in three dimensions (e.g., the X and Y directions shown in the figures, and the orthogonal Z direction off-page in FIGS. 56A-56L). In one implementation, the printing system translates the print head 68 in the XZ plane while controlling the Y-direction spacing between the top side of the lead frame 46, the die 18, and the print head 68. The printing system in one example also controls the supply of insulating material from the nozzles of the print head to print on and off, for example, to facilitate precise, high-resolution control over where insulating material is printed and not printed. The non-screen printing process 1300 also provides control over the thickness (e.g., in the Y direction) of the deposited insulating material via one or more of the deposition rates and controls the time that the print head 68 is positioned over a particular area of ​​the lead frame 48 and / or die 18. This facilitates printing different thicknesses of insulating material in different locations in a particular implementation.

[0284] To obtain the desired contours of the insulating layers 76, 78, and 80 along the non-horizontal surfaces, the insulating material may be formed or applied in multiple passes, with each pass dispensing viscous material on the Z dimension only at the desired XY location. The viscosity of the material, as well as exposure to temperature, light, or gas, can hold the partially cured material in place. FIG. 56A shows the die 18 attached to the pre-mold lead frame 48 prior to application of the cover layer insulating material. FIG. 56B shows the result of a first pass of printing the cover layer insulating material by the print head 68. FIG. 56C shows the result of a second pass of printing the cover layer insulating material by the print head 68. FIG. 56D shows the result of a third pass of printing the cover layer insulating material by the print head 68. FIG. 56E shows the result of a fourth pass of printing the cover layer insulating material by the print head 68. FIG. 56F shows the result of a fifth pass of printing the cover layer insulating material by the print head 68. FIG. 56G shows the result of a sixth pass of printing the cover layer insulating material by the print head 68. FIG. 56H shows the result of a seventh pass of printing of cover layer insulating material by the print head 68. FIG. 56I shows the result of an eighth pass of printing of cover layer insulating material by the print head 68. FIG. 56J shows the result of a ninth pass of printing of cover layer insulating material by the print head 68. FIG. 56K shows the result of a tenth pass of printing of cover layer insulating material by the print head 68. FIG. 56L shows the result of a final pass of printing of cover layer insulating material by the print head 68. Curing can occur after each pass, or after multiple passes. Although FIGS. 56B-56L show a total of eleven passes of insulating material by the print head 68, more or fewer passes may actually be used depending on many factors including the type of insulating material used, the viscosity of the insulating material, the desired thickness of the insulating material, the desired resolution of control of the deposition of the insulating material, etc. Also, in the example of depositing a blanket insulating layer 76, a portion of the blanket insulating layer 76 extends across the top surface of the die 18 between the bond pads 50 on opposite sides of the die 18 (not shown in Figures 56K and 56L).

[0285] Figures 57A-65B show an alternative chip-on-lead (COL) packaged electronic device. The major difference between the alternative chip-on-lead (COL) packaged electronic device and the previously described apparatus is lead frame 46 in the COL device, which has die attach pad 14 and leads 12 spaced from the die attach pad, replaced with a lead frame that includes leads but does not include a die attach pad. In the case of a COL device, the semiconductor die is attached directly to and supported by the leads, rather than to a die attach pad such as die attach pad 14. The actual steps for manufacturing a COL device are otherwise substantially similar to the fabrication previously described for devices having a die attach pad with leads spaced from the die attach pad (see Figures 47A-56L) and will not be repeated here.

[0286] Packaging Details

[0287] In electronics manufacturing, integrated circuit packaging is the final stage of semiconductor device manufacturing, where a block of semiconductor material is sealed in a supporting case that prevents physical damage and corrosion. The case, known as a "package," supports the electrical contacts that connect the device to a circuit board. In the integrated circuit industry, this process is often called packaging. Other names include semiconductor device assembly, assembly, encapsulation, or sealing. The packaging stage is followed by testing of the integrated circuit. This term is sometimes confused with electronic packaging, which is the mounting and interconnection of integrated circuits (and other components) onto a printed circuit board. The current-carrying traces that run from the die, through the package, and into the printed circuit board (PCB) have very different electrical characteristics compared to on-chip signals. They require special design techniques and require much more power than signals confined to the chip itself. It is therefore important that materials used as electrical contacts exhibit properties such as low resistance, low capacitance, and low inductance.

[0288] Both the structure and materials must prioritize signal transmission characteristics while minimizing any parasitic elements that may adversely affect the signal. Controlling these characteristics becomes increasingly important as other technologies begin to speed up. Packaging delays can be nearly half the delay of high performance computers, and this bottleneck in speed is expected to increase. Cost is a factor in the selection of integrated circuit packaging. In some instances, an inexpensive plastic package can dissipate up to 2W of heat, which is sufficient for many simple applications, while a similar ceramic package can dissipate up to 50W in the same scenario. As chips within packages get smaller and faster, they also tend to run hotter. Then, as the need for more efficient heat dissipation increases, the cost of packaging increases accordingly. In general, the smaller and more complex the package needs to be, the more expensive it is to manufacture.

[0289] Using known molding or encapsulation techniques, any of the above-mentioned devices can be coated with a thick insulating layer 82 (e.g., plastic) to at least cover or completely encapsulate the top side of the device as shown in Figs. 66A and 66B to produce a packaged semiconductor device 84. Such coatings are typical in the semiconductor industry and are primarily for mechanical strength and cosmetic appearance. Fig. 66A shows a top view of a packaged semiconductor device using plastic encapsulation. Fig. 66B shows a side view of the packaged device of Fig. 66A. Fig. 67A shows a top view of a (COL) packaged semiconductor device 85 using plastic encapsulation. Fig. 67B shows a side view of the (COL) packaged device of Fig. 67A. However, since no wire bonds or wire loops are used in the above examples, there are no sensitive wire loops and zero hole topologies, and physical pressure can be applied to the pre-encapsulated surface of the semiconductor device. This allows multiple encapsulation options such as lamination, transfer molding, injection molding, casting, potting, 3D printing, scribe dispense, screen printing, spray coating, spin coating, dipping, dam and fill, etc., as shown in FIG. 68. Since the initial insulating and conductive layers provide most of the reliability, the encapsulation material can be optimized for adhesion, trading off moisture permeability, ionic stability, etc. The top surface of the encapsulation material can be planarized with a hot plate while encapsulating. When the second insulating layer (e.g., cover layer 76, 78, or 80) completely covers the sensitive parts, the encapsulant does not contact the die or interconnects. This significantly reduces the reliability and manufacturability requirements.

[0290] Figures 69A and 69B show schematic diagrams of the package assembly process described above, from creating or selecting a leadframe through molding and device singulation. Figure 70 shows a side view of a packaged semiconductor device 84 soldered or otherwise electrically connected to a printed wiring board (PWB) that is used to perform its designed function.

[0291] Although the above examples are described as being implemented in a quad flat no-lead (QFN) package, the techniques described above are applicable to almost any semiconductor die / leadframe combination where there is a desire to replace the wire bonds between the semiconductor die and the leadframe with printed conductive interconnects. Examples contemplated include through-hole packages, surface mount, chip carriers, pin grid arrays, flat packages (other than QFN), small outline packages, etc. Printing Technology:

[0292] There are several printing techniques that can be used to print various of the insulating layers, conductive interconnects, and protective coating layers mentioned above. Although inkjet printing is described as being used throughout the examples above, other printing techniques can also be used, including aerosol jet, μTP, laser transfer, spray, EHD, and microdispense.

[0293] Inkjet printing:

[0294] Inkjet printing can be divided into two categories: Continuous Inkjet (CIJ - continuous stream of ink) and Drop on Demand (DOD). DOD is further divided into three categories: Valve Jet (which uses a needle valve and solenoid to control the flow of ink), Thermal Inkjet (where electrical current is applied to a small heating element, which heats up rapidly, vaporizing and bubbling the ink in the printhead chamber, forcing the ink out of the nozzle), and Piezoelectric Inkjet, which is the focus here. Inkjet printing equipment for printing the above insulating layers, conductive interconnects, and protective packaging coatings is available from the following companies: Meyer Burger, Ceradrop, M-Solv, Kateeva, Notion, UniJet, TEL, SEMES, Heraeus. Alternatively, an inkjet printing device can be designed using the design in Figure 71 as a starting point. Inkjet printing characteristics currently allow for >10m 2 / h throughput; best print resolution (μm) of 2-10; print layer thickness (μm) of 0.01-1. Inkjet printing's strengths currently include digital scalability and non-contact versatility. Inkjet printing's weaknesses currently include clogging issues, complex ink formulations, and throughput.

[0295] Aerosol Jet:

[0296] The technology was developed by Optomec. The working principle is based on the use of a deposition head to eject a high density aerosol of micro droplets that is generated in a vessel (1) and travels through a tube (2) to reach the head (3). The head generates a high speed collimated mist stream through an aerodynamic focusing nozzle, and a sheath gas emerges from the side of the nozzle. This technology allows the use of low temperature processing (e.g. materials with 100°C constraints) and is compatible with substrates such as polycarbonate or polyester. The only current manufacturer of aerosol jet technology is Optomec. Alternatively, an aerosol jet printing device can be designed using the design in Figure 72 as a starting point. Aerosol jet printing characteristics are currently well within the realm of 1-10m. 2 / h throughput; best print resolution (µm) of 5-10; print layer thickness (µm) of 0.01-10. Strengths of aerosol jet printing currently include Z-flexibility, selectivity, and conformality. Weaknesses of aerosol jet printing currently include coffee stains / rings; interactions; gas / substrate.

[0297] spray:

[0298] Ultrasonic spray coating uses ultrasound to turn liquid ejected through a nozzle into a mist of uniform micron-sized droplets. The working principle is to send liquid through a channel through an ultrasonic generator, and calculate the waves generated by the ultrasonic system and the distance from the spray surface to generate the mist. The frequency used determines the droplet size. Combinations of air, nozzle type, and generated ultrasonic waves could be used to generate different shapes of spray mist, such as jet, vortex, and width. Ultrasonic spray printing equipment for printing selected ones of the above insulating layers, conductive interconnects, and protective packaging coatings is available from the following companies: SOSS MicroTec; EVG; SONO TEK Corporation; siconnex; OEMGROUP; Nordson; M-SOLV; MYCRONIC; MEI. Alternatively, an ultrasonic spray printing device can be designed using the design in Figure 73 as a starting point. Inkjet printing characteristics are currently limited to >10m 2 Included are throughput of 10 ...

[0299] Microdispensing:

[0300] Microdispense is the 3D printing of pastes, inks, and other fluids that are exceptionally small, e.g., in the picoliter or nanoliter range. Mechanically, it is similar to jetting technology, but dispenses fluids much closer to the substrate surface, resulting in much finer and more precise printed structures. Ultrasonic spray printing equipment for printing selected ones of the insulating layers, conductive interconnects, and protective packaging coatings described above is available from the following companies: VERMES; Preflow; PVA; MicroFab; Microdrop; MYCRONIC. Alternatively, a microdispense printing device can be designed using the design in Figure 74 as a starting point. Microdispense printing characteristics currently range from 0.1 to 0.1 m. 2 / h throughput, best print resolution (µm) of 10-500, and print layer thickness (µm) of 50-500. Strengths of microdispense printing currently include a wide range of materials, scalability. Weaknesses of microdispense printing currently include low throughput.

[0301] EHD / Electrospray:

[0302] Electrofluid jet printing (EHD) is an alternative to inkjet printers and aerosol printing. This technique allows for very fine printing capabilities. The process was originally developed for photovoltaic applications as a non-contact technique with very fine features to avoid shadowing. This technique uses a minimal amount of liquid / ink (IpL). EHD / electrospray printing equipment for printing selected ones of the above insulating layers, conductive traces, and protective packaging coatings is available from CENJET. Alternatively, an EHD / electrospray printing equipment can be designed using the design in Figure 75 as a starting point. Microdispense printing characteristics are currently in the 1-5m range. 2 / h throughput, best printing resolution (μm) of 0.01-0.1, and printing layer thickness (μm) of 0.1-0.5. Strengths of EHD / electrospray printing currently include excellent spatial resolution. Weaknesses of EHD / electrospray printing currently include low throughput.

[0303] Laser-induced forward transfer:

[0304] Laser-induced forward transfer (LIFT) is a digital printing technique that uses a pulsed laser beam as a driving force to project material from a donor thin film towards a receiving substrate, on which it is ultimately deposited as voxels (3D picture elements). This working principle allows LIFT to work with both solid and liquid donor films, which gives this technique an unprecedented wide range of printable materials and therefore makes it highly competitive compared to other digital techniques such as inkjet printing. Not only can LIFT access a much wider range of ink viscosities and packed particle sizes, but the possibility of printing from solid films allows single-step printing of multilayers and entire devices, and even 3D printing. This versatility leads to a wide range of application areas, from the creation of chemical sensors to tissue engineering, from graphics manufacturing to printed electronics. This description provides an extensive review of the LIFT technique, from its origins to recent achievements, focusing on fundamental aspects of both its working principle and transfer dynamics, as well as its wide range of applications.

[0305] Laser-induced forward transfer (LIFT) printing equipment for printing selected ones of the above insulating layers, conductive interconnects, and protective package coatings is available from the following companies: orbotech, uniqarta, COHERENT. Alternatively, a laser-induced forward transfer (LIFT) printing device can be designed using the design in Figure 76 as a starting point. LIFT printing characteristics currently include throughput of >lm units / h; best print resolution (μm) of 0.1-1; and print layer thickness (μm) of 0.1-010. Strengths of LIFT printing currently include scalability, versatility. Weaknesses of LIFT printing currently include cleanroom integration, possible interactions, and laser / material ejection.

[0306] ink:

[0307] Functional inks are classified into three groups: 1) conductive, 2) dielectric, and 3) semiconducting. Conductive inks can be metallic (Au, Ag, Cu, etc.) and are useful for forming interconnects (such as interconnect (74) discussed above), electrodes, antennas, traces, bus bars, etc. Dielectric inks are useful for insulating multilayer circuit elements (such as the base and overlying insulating layers 52, 64, and 66 discussed above) and crossovers to enable multilayer applications. Dielectric inks are primarily based on metal oxide particles and tend to be very thick in the form of a paste or thick liquid, often with a viscosity of over 20,000 mPa·s. Functional inks can be custom formulated or obtained from companies that specialize in developing various types of conductive and insulating inks, including Dupont, Cleopatra, and Agfa.

[0308] Alternative implementation:

[0309] Alternatively, multiple interconnect shapes, sizes, materials, and contacts can be formed within a single die. For example, as shown in FIG. 77A, conductive trace or interconnect 86 is an extension of conductive trace or interconnect 74 on the top surface of die 18 between two bond pads 50 on die 18. Although two connections on die 18 are shown, more connections can be used. This can be useful for connecting multiple grounds or multiple voltage sources together. Another alternative implementation shown in FIG. 77A is...

Claims

1. 1. A method of making a semiconductor device, comprising the steps of: forming a first insulating structure extending from a first bond pad of the semiconductor die to a first conductive lead; forming a first conductive trace on a first insulating structure from the first bond pad to the first conductive lead; forming a second insulating structure on the first conductive trace extending from the first bond pad to the first conductive lead; forming a third insulating structure extending from a second bond pad of the semiconductor die to a second conductive lead; A method comprising:

2. 2. The method of claim 1 , The method, wherein the first insulating structure and the second insulating structure encapsulate the first conductive trace.

3. 2. The method of claim 1 , The method, wherein the first insulating structure further extends from the second bond pad to the second conductive lead.

4. 2. The method of claim 1 , The method further includes forming a second conductive trace on the third insulating structure from the second bond pad to the second conductive lead.

5. 5. The method of claim 4, The method further includes forming a fourth insulating structure on the second conductive trace.

6. 6. The method of claim 5, The method, wherein the third and fourth insulating structures encapsulate the second conductive trace.

7. 2. The method of claim 1 , 11. The method of claim 10, further comprising providing a die attach pad spaced apart from the first and second conductive leads, the semiconductor die having a first surface for attachment to the die attach pad.

8. 8. The method of claim 7, The method, wherein the semiconductor die further has a second surface opposite the first surface and attached to the conductive leads.

9. 2. The method of claim 1 , The method, wherein the first insulating structure has a first end that surrounds but does not completely cover the respective bond pad.

10. 2. The method of claim 1 , The method, wherein the first conductive trace is part of a leadframe that is pre-molded to fill gaps between metal lead sections with an insulating material such as mold compound, epoxy, polymer or ceramic.

11. 2. The method of claim 1 , The method, wherein the first conductive lead is part of a pre-taped leadframe.

12. 2. The method of claim 1 , The method further includes forming a channel in the first insulating structure for receiving at least a portion of the first conductive trace.

13. 5. The method of claim 4, The method, wherein the first and second conductive traces are made using a conductive ink, a conductive polymer, a metal filled epoxy, a sintered metal powder, a liquid assisted sintered particles, a solder paste, or a solder powder.

14. 2. The method of claim 1 , the semiconductor die having a first surface on which the bond pads are formed, a second surface opposite the first surface, and a side extending from the first surface to the second surface; The method of claim 1, wherein the first insulating structure extends along the first surface and the side from the first bond pad to the first conductive lead.

15. 2. The method of claim 1 , The method, wherein the first insulating structure and the second insulating structure comprise the same material.

16. 2. The method of claim 1 , The method, wherein the first insulating structure includes a trough that contains the first conductive trace.

17. 2. The method of claim 1 , the method further comprising applying an encapsulation layer by laminating, injection molding, transfer molding, spraying, casting, 3D printing, dispensing, potting, screen printing, or spin coating over the first surface of the semiconductor die, the first insulating structure, the second insulating structure, and at least a portion of each conductive lead.

18. 2. The method of claim 1 , The method, wherein the first and second insulating structures comprise a polymer, an epoxy, or a silicone.

19. A method for making a semiconductor device, comprising the steps of: forming a first insulating structure extending from a first bond pad of a semiconductor die to a first conductive lead and extending from a second bond pad of the semiconductor die to a second conductive lead; forming a first conductive trace on the first insulating structure from the first bond pad to the first conductive lead; forming a second insulating structure on the first conductive trace extending from the first bond pad to the first conductive lead; forming a second conductive trace on the first insulating structure from the second bond pad to the second conductive lead; A method comprising:

20. 20. The method of claim 19, The method further includes forming a third insulating structure on the second conductive trace.

21. 21. The method of claim 20, The method, wherein the first and third insulating structures encapsulate the second conductive trace.

22. 20. The method of claim 19, The method, wherein the second insulating structure further covers the second conductive trace from the second bond pad to the second conductive lead.

23. 23. The method of claim 22, The method, wherein the first and second insulating structures encapsulate the first and second conductive traces.

24. 20. The method of claim 19, The method, wherein the first and second conductive traces are made using a conductive ink, a conductive polymer, a metal filled epoxy, a sintered metal powder, a liquid assisted sintered particles, a solder paste, or a solder powder.

25. 20. The method of claim 19, The method, wherein the first and second conductive traces comprise different shapes, sizes, materials, and current carrying capacities within the same semiconductor device.

26. 20. The method of claim 19, The method, wherein the first conductive trace has a first width and the second conductive trace has a second width different than the first width.

27. 20. The method of claim 19, The method, wherein the first conductive trace comprises a first material and the second conductive trace comprises a second material different from the first material.

28. The method of claim 19, comprising: The method, wherein the first insulating structure and the second insulating structure encapsulate the first conductive trace.

29. The method of claim 19, comprising: The method, wherein the second insulating structure further extends from the second bond pad to the second conductive lead.

30. The method of claim 19, comprising:

11. The method of claim 10, further comprising providing a die attach pad, the conductive leads being spaced apart from the die attach pad, the die attach pad having a first surface on which the semiconductor die is attached.

31. The method of claim 30, comprising: The method, wherein the semiconductor die further has a second surface opposite the first surface and attached to the conductive leads.

32. The method of claim 19, comprising: the first insulating structure having a first end that surrounds but does not completely cover the respective pad.

33. The method of claim 19, comprising: The method, wherein the first conductive trace is part of a pre-molded leadframe for filling gaps between metal lead sections with an insulating material such as mold compound, epoxy, polymer or ceramic.

34. The method of claim 19, comprising: The method, wherein the first conductive lead is part of a pre-taped lead frame.

35. The method of claim 19, comprising: The method further includes forming a channel in the first insulating structure for receiving at least a portion of the first conductive trace.

36. The method of claim 19, comprising: the semiconductor die having a first surface on which the bond pads are formed, a second surface opposite the first surface, and a side extending from the first surface to the second surface; The method of claim 1, wherein the first insulating structure extends along the first surface and the side from the first bond pad to the first conductive lead.

37. The method of claim 19, comprising: The method, wherein the first insulating structure and the second insulating structure comprise the same material.

38. The method of claim 19, comprising: The method, wherein the first insulating structure includes a trough that contains the first conductive trace.

39. The method of claim 19, comprising: the method further comprising applying an encapsulation layer by laminating, injection molding, transfer molding, spraying, casting, 3D printing, dispensing, potting, screen printing, or spin coating over the first surface of the semiconductor die, the first insulating structure, the second insulating structure, and at least a portion of each conductive lead.

40. The method of claim 19, comprising: The method, wherein the first and second insulating structures comprise a polymer, an epoxy, or a silicone.

41. A method for making a semiconductor device, comprising the steps of: forming a first insulating structure extending from a first bond pad of the semiconductor die to a first conductive lead; forming a first conductive trace on the first insulating structure from the first bond pad to the first conductive lead, the first conductive trace being part of a leadframe that has been pre-molded to fill gaps between metal lead sections with an insulating material such as mold compound, epoxy, polymer or ceramic, the thickness of the pre-molding being approximately the same as a thickness of the leads; forming a second insulating structure on the first conductive trace extending from the first bond pad to the first conductive lead; A method comprising:

42. A method for making a semiconductor device, comprising the steps of: forming a first insulating structure from a first bond pad of a semiconductor die to a first conductive lead, the first insulating structure comprising a thickness in a range of 5 to 20 microns; forming a first conductive trace on the first insulating structure from the first bond pad to the first conductive lead; forming a second insulating structure on the first conductive trace extending from the first bond pad to the first conductive lead; A method comprising:

43. A method for making a semiconductor device, comprising the steps of: forming a first insulating structure extending from a first bond pad of the semiconductor die to a first conductive lead; forming a first conductive trace on the first insulating structure from the first bond pad to the first conductive lead; forming a second insulating structure on the first conductive trace extending from the first bond pad to the first conductive lead; Including, The method, wherein the first insulating structure, the first conductive trace and the second insulating layer follow a contour of a topology from the first conductive lead to the first bond pad.

44. A method for making a semiconductor device, comprising the steps of: forming a first insulating structure extending from a first bond pad of the semiconductor die to a first conductive lead; forming a first conductive trace on the first insulating structure from the first bond pad to the first conductive lead, the first conductive trace having a thickness in the range of 5 to 30 microns; forming a second insulating structure on the first conductive trace extending from the first bond pad to the first conductive lead; A method comprising:

45. 2. The method of claim 1 , forming a first insulating structure extending from a first bond pad of a semiconductor die to a first conductive lead, the first insulating structure having a first thickness on opposing edges and a second thickness at a central portion between the opposing edges, the first thickness being greater than the second thickness; forming a first conductive trace on the first insulating structure from the first bond pad to the first conductive lead; forming a second insulating structure on the first conductive trace extending from the first bond pad to the first conductive lead; A method comprising:

46. 46. ​​The method of claim 45, The method, wherein the first conductive trace does not extend above the opposing edges.

47. A method for making a semiconductor device, comprising the steps of: forming a first insulating structure extending from a first bond pad of the semiconductor die to a first conductive lead; forming a first conductive trace on the first insulating structure from the first bond pad to the first conductive lead; forming a second insulating structure on the first conductive trace extending from the first bond pad to the first conductive lead; Including, A method according to claim 1, wherein a transition region between the first insulating structure and the first conductive trace is configured with a mixing ratio gradient in the transition region.

48. A method for making a semiconductor device, comprising the steps of: forming a first insulating structure extending from a first bond pad of the semiconductor die to a first conductive lead; forming a first conductive trace on the first insulating structure from the first bond pad to the first conductive lead; forming a second insulating structure on the first conductive trace extending from the first bond pad to the first conductive lead; Including, A method according to claim 1, wherein a transition region between the first conductive trace and the second insulating structure is configured with a mixing ratio gradient in the transition region.

49. A method for making a semiconductor device, comprising the steps of: forming a first insulating structure extending from a first bond pad of the semiconductor die to a first conductive lead; forming a first conductive trace on the first insulating structure from the first bond pad to the first conductive lead, the first conductive trace having one of a rectangular, square, triangular, circular, and semicircular cross-sectional shape; forming a second insulating structure on the first conductive trace extending from the first bond pad to the first conductive lead; A method comprising:

50. A method for making a semiconductor device, comprising the steps of: forming a first insulating structure extending from a first bond pad of the semiconductor die to a first conductive lead; forming a first conductive trace on the first insulating structure from the first bond pad to the first conductive lead; forming a second insulating structure on the first conductive trace extending from the first bond pad to the first conductive lead; Including, The method, wherein material is applied in multiple passes to obtain a desired profile of an insulating layer along a non-horizontal surface of the semiconductor die, with each pass dispensing viscous material in the Z dimension only at a desired XY location.

51. 51. The method of claim 50, A method in which the viscosity of the material and exposure to temperature, light, or gases hold the partially cured material in place.

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