Successive Approximation Register Analog-to-Digital Converter

Abstract

1. A successive approximation analog-to-digital (100) converter comprising an input (102) for receiving an input analog voltage and an amplifier (202), the amplifier (202) having a first set of electrical attributes in a sample phase and a second set of electrical attributes in a conversion phase that differ from the first set of electrical attributes.

Description

[Technical field]

[0001] This example relates to analog-to-digital converters (ADCs), and more specifically, to successive approximation register (SAR) ADCs.

[0002] A SAR ADC converts an analog input voltage signal into a digital output value, sometimes referred to as a code. It does this by continuously comparing the input to an internally generated, varying reference voltage. With each successive comparison, the reference voltage is adjusted to converge toward the value of the analog input voltage signal, while each such adjustment and comparison determines a respective bit of the SAR ADC output code. Also, as the difference between the input voltage and the reference voltage converges in this manner, the reference voltage change becomes smaller with each successive comparison, and therefore the smaller reference voltage and difference are more susceptible to errors.

[0003] SAR ADCs may be embodied as or as part of an integrated circuit (IC). Thus, IC design considerations are factors for SAR ADCs, such as the area and power consumed by the device. Also, as SAR ADCs advance to operate, for example, at higher speeds and with a larger number of output bits, additional design considerations are directed to output accuracy. For example, noise affects the SAR ADC input signal, the components that process the input signal, and the proper assessment of the convergence difference between the input signal and a reference voltage. Thus, the effects of noise may be considered to the extent that they can cause signal state changes greater than the least significant bit (LSB) resolution of the device, potentially causing errors in the output or limiting the resolution of the output code.

[0004] While the above considerations are generally common to most SAR ADCs, some designers may prioritize different design considerations, for example, considering different noise sources and designs to mitigate the effects of noise. Accordingly, examples are provided herein that may improve upon various such noise considerations and other concepts, as described further below. Summary of the Invention

[0005] A successive approximation analog-to-digital converter is provided that includes an input for receiving an input analog voltage. The successive approximation analog-to-digital converter further includes sample phase circuitry and conversion phase circuitry. The sample phase circuitry includes an amplifier, provides the amplifier with a first set of electrical attributes, and is for sampling the input analog voltage in a sample phase. The conversion phase circuitry includes the amplifier, provides the amplifier with a second set of electrical attributes different from the first set of electrical attributes, and is for converting a comparison of the sampled input analog voltage to a reference voltage to a digital value in a conversion phase.

[0006] Other aspects are also described and claimed. [Brief description of the drawings]

[0007] [Figure 1] 1 illustrates a schematic diagram of a SAR ADC of an example embodiment;

[0008] [Diagram 2] 2 illustrates a schematic diagram of the SAR ADC of FIG. 1, with additional details shown for the comparator of FIG. 1.

[0009] [Diagram 3] FIG. 2 shows a schematic diagram of a SAR ADC 100, which comprises three switches arranged to operate in the sample phase.

[0010] [Figure 4] FIG. 2 shows a schematic diagram of a SAR ADC 100, which comprises three switches arranged to operate in a conversion phase.

[0011] [Diagram 5]2 shows a schematic diagram of a SAR ADC amplifier 202 to more fully illustrate selective tuning of the amplifier electrical characteristics between sample phases versus conversion phases. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] FIG. 1 illustrates a schematic diagram of an exemplary embodiment of a SAR ADC 100. The SAR ADC receives an analog input voltage VIN at an input node 102 and ultimately generates a CODE corresponding to the magnitude of VIN in an N-bit register 104. In particular, VIN is connected to the input node 102 with a first of two switch throws of an input switch 106. The input switch 106 has a pole connected to a first plate of a sample capacitor 108, and the input switch 106 has a second throw connected to an output node 110 of a digital-to-analog converter (DAC) 112. The second plate of the sampling capacitor 108 is connected to a throw of a first bias switch 114, which is connected to receive a bias voltage Vbias via the first bias switch 114. The throw of the first bias switch 114 is also connected as an input to a comparator 116. The output of the comparator 116 is connected to the register 104. When the SAR ADC 100 completes the conversion of VIN, a first output 118 of the register 104 provides the CODE output, and a second output 120 of the register 104 provides the CODE output, as determined in its entirety, to the input of the DAC 112. Note that the capacitance of the sampling capacitor 108 may be implemented as part of the same capacitor or capacitive element as the DAC 112, although for simplicity they are shown herein as separate structures. Note further that the illustrated switches (including the input switch 106 and the first bias switch 114) are functional representations that may be implemented using various circuit elements, such as transistors.

[0013] The general operation of the SAR ADC 100 is as follows, with additional structural and operational details provided below. The SAR ADC 100 in a first phase sample VIN and thereafter in a second phase performs a conversion by iteratively comparing the sampled VIN to different internally generated reference voltages provided by the DAC 112. The transition between the sample phase and the iterative conversion phase is performed in part by the input switch 106 and the first bias switch 114, as described below. The overall SAR ADC 100 operation is also improved by implementing an auto-zeroing (AZ) sample phase noise suppression (AZSPNS) aspect in the sample phase, generally shown in FIG. 1 as a control input to the comparator 116, and described below. The sample phase and one or more iterative conversion phases together determine successive bits stored in the N-bit register 104, and completing all iterations completes the total number N bits in the register 104 as CODE at the output 118. For example, VIN is sampled in a sample phase, and then in the first iteration of the conversion phase, the sample VIN is compared by the comparator 116 to an analog reference voltage Varef, where Varef is output by the DAC 112 in response to CODE and then output in the register 104. For example, in the first iteration of the conversion phase, the most significant bit (MSB) of the V bit in the register 104 is set high, while all the less significant bits in the register 104 are set low. So, in this first iteration of the conversion phase, the SAR ADC 100 compares VIN to a voltage Varef corresponding to the MSB high value in the N-bit register 104. If VIN is greater in the comparison, the MSB remains high (or is overwritten) and the next less significant bit is set for the next conversion phase iteration. If VIN is less in the comparison, the MSB is zeroed and the next less significant bit is set for the next conversion phase iteration. The above process is repeated for each successive iteration until all N bits in the N-bit register 104 have been set to establish a corresponding Varef that is compared to VIN as described above.Once all iterations are completed, the N-bit value in the N-bit register 104 is output as CODE, which represents the magnitude of VIN.

[0014] FIG. 2 illustrates a schematic diagram of the SAR ADC 100 with additional details shown for the comparator 116. The comparator 116 includes an amplifier stage 200, which is shown to include a single amplifier 202 as an example. The amplifier 202 is shown to receive an AZSPNS, and the electrical attributes of the amplifier 202 are selectively adjusted to be different, for example, during the sample phase compared to the conversion phase, as described below, which further improves the AZ performance of the SAR ADC 100. An input of the amplifier 202 is connected to the throw of the first bias switch 114, and an output of the amplifier 202 is connected to a first plate of an AZ capacitor 204. A second plate of the AZ capacitor 204 is connected to the throw of an AZ switch 206. The AZ switch 206 pivots in the direction indicated by the AZSPNS arrow during sample phase auto-zeroing. A pole of the AZ switch 206 is connected to Vbias. The throw of the AZ switch 206 is also connected as an input to a latch 208. The output of the latch 208 is the output of the comparator 116 and is connected to the N-bit register 104 as previously described. The latch 208 may operate as a threshold detector such that if its input is below the threshold, the latch output is logic low, or if its input is above the threshold, the latch output is logic high. Alternatively, the amplifier 202 may consist of multiple cascaded capacitively coupled stages, each stage having an AZ switch at its input. The coupling capacitor of the last of these cascaded stages is connected to the input of the latch 208.

[0015] FIG. 3 illustrates the schematic diagram of FIG. 2 of the SAR ADC 100 with three switches arranged to operate in the sample phase. In the sample phase, two different voltages are sampled and stored on respective capacitors. Specifically, the input switch 106 connects VIN to the first plate of the sampling capacitor 108, while the first bias switch 114 connects Vbias to both the amplifier 202 (or to the multiplier amplifier, if applicable) and the second plate of the sampling capacitor 108, thereby providing a low impedance to that capacitor plate. Thus, Vbias serves the dual purpose of biasing the amplifier 202 and providing a low impedance to the capacitor 108. Thus, VIN is sampled onto the sampling capacitor 108. The AZSPNS is also asserted during the sample phase to place (close) the AZ switch 206 and to control the amplifier 202, the latter of which selectively adjusts electrical attributes during the sample phase to further improve noise immunity, as described below. In particular, during the sample phase, the AZSPNS controlled amplifier 202 outputs an AZ voltage Vaz to a first plate of an AZ capacitor 204, and when an AZ switch 206 is closed, thereby connecting a low impedance of Vbias to the second plate of that capacitor, Vaz is sampled onto that AZ capacitor 204. The closed AZ switch 206 also connects Vbias to the input of a latch 208, biasing the input of the latch 208 for correct operation during the conversion phase. Due to the fact that the input of the amplifier 202 is connected to a constant voltage Vbias during the sampling phase, Vaz represents the offset of the amplifier 202 plus noise.

[0016] FIG. 4 shows a schematic diagram of the SAR ADC 100 of FIG. 2, with its three switches arranged inversely to those of FIG. 3, so that in FIG. 4 the SAR ADC 100 operates iteratively in the conversion phase. In the conversion phase, the input switch 106 connects the DAC 112 analog reference voltage Varef to the sampled voltage VIN already on the sampling capacitor 108 from the previous sample phase. The difference between these two voltages, Varef-VIN, is thus input to the comparator 116 and thereby to its amplifier 202. Recalling from above that in the first conversion phase iteration Varef is approximately half the voltage capacitance of the DAC 112, the difference provided by Varef-VIN is essentially a comparison of these two voltages, where if the difference is positive, Varef is greater than VIN, and if the difference is negative, VIN is greater than Varef. At the same time, AZSPNS is deasserted, thereby adjusting the conversion phase electrical attributes of the amplifier 202 to be different from those of the sample phase. Thus, the amplifier 202 operates under the conversion phase electrical properties and outputs a voltage G(VIN-Vref), where G is the gain of the amplifier 202 and (VIN-Vref) is the input voltage to the amplifier 202. The output voltage G(VIN-Vref) is coupled to the AZ capacitor 204, which recalls that it stored the AZ voltage Vaz in the previous sample phase. Thus, in the conversion phase, Vaz is subtracted from G(VIN-Vref), thereby essentially nullifying the effect that the offset and noise of the amplifier 202 may otherwise have on the operation of the SAR ADC 100. Also, the differential voltage (G(VIN-Vref)-Vaz) from the AZ capacitor 204 is connected to the input of a latch 208. The latch 208 outputs either a logic low or high based on whether (G(VIN-Vref)-Vaz) exceeds the threshold limit of the latch 208, and that logic value is written into the bit position in the N-bit register 104 that was originally high for the current conversion phase iteration.

[0017] The above description of the first conversion phase iteration of the SAR ADC 100 repeats to produce a total of N conversion phase iterations, each iteration corresponding to a respective bit in the N-bit register 104. Thus, following the first iteration, N-1 successive iterations occur, each iteration for the next less significant bit in the N-bit register 104, and so on until all N bits in the register 104 have been processed through a respective conversion phase iteration. Upon completion of these operations, the N bits in the N-bit register 104 represent a digital approximation of VIN and are provided at the output 118 as CODE.

[0018] FIG. 5 shows a more detailed schematic diagram of the amplifier 202 (FIGS. 2-4) and further details an exemplary embodiment of a structure for selective adjustment of the electrical attributes of the amplifier 202 to be different between the sample phase and the conversion phase, and a method of operation of the selective adjustment. For reference to the previous figures, FIG. 5 also includes a first bias switch 114 and an AZ capacitor 204 external to the amplifier 202. The throw of the first bias switch 114 is connected to the input 202IN of the amplifier 202. The input 202IN is connected to the input of a transconductor 500, which together with a resistor 504 provides the gain G introduced earlier. The output of the transconductor 500 is connected to a node 502. The node 502 is connected to ground via a resistor 504. The node 502 is also connected to a pole of a noise suppression switch 506. A noise suppression switch 506 closes during sample phase auto-zeroing when AZSPNS is asserted (and opens when it is deasserted). The throw of noise suppression switch 506 is connected to ground through a capacitor 508. Node 502 is also connected to the input of a zero-unity buffer 510, the output of which provides the output of amplifier 202.

[0019] The operation of amplifier 202 of Figure 5 is generally described above. Additional discussion will now be provided regarding the selective adjustment of its electrical characteristics during the sample phase versus conversion phase.

[0020] Recall that during the sample phase, AZ is simultaneously implemented and AZSPNS is asserted. Thus, in FIG. 5, during the sample phase, capacitor 508 is connected to node 502 via noise suppression switch 506 (e.g., connected to ground in parallel with resistor 504 at the amplifier output). With both resistor 504 and capacitor 508 connected to the output of transconductance 500, the electrical attributes of amplifier 202 are selectively adjusted, i.e., the 3 dB cutoff corner of amplifier 202 is reduced. Thus, the lower 3 dB cutoff corner reduces the amplifier bandwidth (except at higher frequencies) compared to when node 502 is not capacitively coupled to ground in this manner. Relatedly, as known in the art, the transconductance of the amplifier (e.g., transconductance 500) provides thermal noise. However, in the illustrated embodiment, the selectively reduced bandwidth of the sample phase provided herein by including the capacitance of capacitor 508 during sample phase AZ operation filters out the higher frequency portion of the amplifier thermal noise. This reduces the amount of thermal noise energy that might otherwise appear in Vaz (see Figures 3 and 4). Thus, using the switched-in capacitance of Figure 5, Vaz is generated as a thermal noise suppressed AZ voltage, which is buffered by buffer 510 and then stored in AZ capacitor 204 as shown in Figure 2.

[0021] As described above, a number N of conversion phase iterations follow the sample phase. Recall that in the conversion phase iterations, AZSPN is deasserted, which results in the noise suppression switch 506 of FIG. 5 being opened and the capacitor 508 being disconnected from the node 502, thereby increasing the bandwidth of the amplifier 202 and allowing the conversion phase iterations to occur at a rate that is not as reduced as the capacitor 508 portion of the amplified output during that phase. Thus, the conversion phase proceeds as described above, with the improvement that the AZ functionality provided by the voltage Vaz and stored on the AZ capacitor 204 better offsets the output of the amplifier 202 due to the reduced bandwidth noise suppression during the immediately preceding sample phase. More specifically, conventional AZ is directed to either DC or relatively low frequency (e.g., 10 Hz or less, sometimes referred to as flicker) noise, which is relatively constant over a relatively long period of time compared to the sample rate of the SAR ADC, which may be on the order of hundreds of KHz to several MHz. Thus, such a conventional AZ approach may store such noise in an offset capacitor, which is then auto-zeroed in the subsequent phase. However, higher frequency noise may also emerge from thermal noise, along with longer duration noise, and the long duration period storing the conventional AZ offset may or will include higher frequency thermal noise, which may in fact be quite conflicting between phases, given the relatively high frequency nature of thermal noise compared to DC and flicker noise. In other words, higher frequency thermal noise during sampling is not necessarily correlated with the same noise and its offset during conversion. Thus, the exemplary embodiment reduces the accumulation of high frequency noise during AZ by selectively adjusting the electrical characteristics of the amplifier stage 200 during AZ, thereby improving the signal-to-noise ratio (SNR) of the SAR ADC 100 when switching to the conversion phase. This improves device operation, such as data conversion accuracy.

[0022] From the above, various examples include an ADC, such as a SAR ADC, with improved performance by selectively adjusting ADC electrical attributes during different ADC phases of operation. The adjustments made desirably reduce possible accumulation of higher frequency noise as part of the AZ offset voltage during the sample phase. Also, in an example embodiment, the selectively adjusted electrical characteristics include changing the bandwidth of an amplifier stage differently in the ADC sample phase relative to its conversion phase. Also, the selectively adjusted bandwidth may be achieved by changing the amplifier signal path capacitance differently in the sample phase than in the conversion phase, for example, by switching a capacitor in and out of the amplifier output signal path in the sample phase and the conversion phase, respectively. Also, in an example embodiment, the changed capacitance is implemented in a first amplifier of a cascaded amplifier when the amplifier stage includes multiple amplifiers, since the gain of the first amplifier is most impacted when cascaded through multiple amplifiers. Also, while the above attributes have been shown and described, variations in various parameters, including dimensions, are contemplated, and the foregoing provides only some examples, others will be ascertainable by one of ordinary skill in the art from the teachings herein. Accordingly, additional modifications are possible in the described embodiments, and other embodiments are possible, all within the scope of the following claims.

Claims

1. 1. A circuit comprising: an input configured to receive an input analog voltage; a first switch having a first input coupled to an input of the circuit, a second input coupled to receive a reference voltage, and an output; a first capacitor coupled to an output of the first switch; a comparator comprising an amplifier, a third capacitor coupled to the amplifier, and a latch coupled to the third capacitor; Including, The circuit, wherein the amplifier includes a transconductor having an input coupled to the first capacitor and an output, a buffer coupled to the output of the transconductor, a second capacitor coupled to a ground node, and a second switch coupled between the second capacitor and the output of the transconductor.

2. 2. The circuit of claim 1, The circuit further includes a third switch having an input coupled to receive a bias voltage and an output coupled to the latch.

3. 3. The circuit of claim 2, The circuit, wherein the second switch and the third switch are coupled to be controlled by an auto-zeroing signal.

4. 2. The circuit of claim 1, The circuit further includes a digital-to-analog converter coupled to a second input of the first switch for providing the reference voltage.

5. The circuit of claim 1, the circuit further comprising a resistor coupled in parallel with the second switch and the second capacitor between the output of the transconductor and the ground node.

6. 1. A successive approximation analog-to-digital converter, comprising: an input for receiving an input analog voltage; a circuit element including an amplifier, the circuit element being configured to provide a first set of electrical attributes to the amplifier and sample the input analog voltage in a sample phase, the circuit element being further configured to provide a second set of electrical attributes to the amplifier different from the first set of electrical attributes and convert a comparison of the sampled input analog voltage to a reference voltage into a digital value in a conversion phase; Including, 2. A successive approximation analog-to-digital converter, wherein the circuit element is further configured to switch a capacitance between the output of the amplifier and a fixed potential during the sample phase and to decouple a capacitance between the output of the amplifier and the fixed potential during the conversion phase.

7. 7. The successive approximation analog-to-digital converter according to claim 6, The successive approximation analog-to-digital converter, wherein the circuit element is further configured to iteratively convert a comparison of the samples of the input analog voltage to each reference voltage iterated during the conversion phase into a digital value.

8. 7. The successive approximation analog-to-digital converter according to claim 6, the circuit element is further configured to provide the first set of electrical properties to an output of the amplifier; The circuit element is further configured to provide an output of the amplifier with the second set of electrical properties.

9. 9. The successive approximation analog-to-digital converter according to claim 8, The successive approximation analog-to-digital converter, wherein the first set of electrical attributes and the second set of electrical attributes include a frequency bandwidth.

10. 9. The successive approximation analog-to-digital converter according to claim 8, 11. A successive approximation analog-to-digital converter, wherein the first set of electrical attributes comprises a first frequency bandwidth, and the second set of electrical attributes comprises a second frequency bandwidth greater than the first frequency bandwidth.

11. 7. The successive approximation analog-to-digital converter according to claim 6, 1. A successive approximation analog-to-digital converter, wherein the first set of electrical attributes includes a first frequency bandwidth having a first upper corner frequency, and the second set of electrical attributes includes a second frequency bandwidth having a second upper corner frequency greater than the first upper corner frequency.

12. 7. The successive approximation analog-to-digital converter according to claim 6, The successive approximation analog-to-digital converter, wherein the first set of electrical attributes and the second set of electrical attributes include a frequency bandwidth.

13. 7. The successive approximation analog-to-digital converter according to claim 6, 11. A successive approximation analog-to-digital converter, wherein the first set of electrical attributes comprises a first frequency bandwidth, and the second set of electrical attributes comprises a second frequency bandwidth greater than the first frequency bandwidth.

14. 7. The successive approximation analog-to-digital converter according to claim 6, A successive approximation analog-to-digital converter, wherein the amplifier comprises a first amplifier of a cascade of amplifiers.

15. 7. The successive approximation analog-to-digital converter according to claim 6, The successive approximation analog-to-digital converter further comprising a digital-to-analog converter for outputting the reference voltage.

16. 16. The successive approximation analog-to-digital converter according to claim 15, a digital-to-analog converter including a digital value for outputting the reference voltage; 11. A successive approximation analog-to-digital converter, wherein the circuit element is further configured to convert a comparison of a sampling of the input analog voltage for a number of iterations, each iteration converting to a digital value against its respective reference voltage in the conversion phase, the number of iterations being equal to N.

17. 7. The successive approximation analog-to-digital converter according to claim 6, A successive approximation analog-to-digital converter, wherein the first set of electrical attributes provides reduced thermal noise in the amplifier relative to thermal noise in the amplifier in the second set of electrical attributes.

18. A method for successive approximation of a digital code from an input analog voltage, comprising: sampling an input analog voltage in a sample phase with an amplifier having a first set of electrical properties, the sampling including switchably coupling the capacitor to an output of the amplifier such that the capacitor is coupled between the output of the amplifier and a ground node; converting a comparison of the sampled input analog voltage to a reference voltage in a conversion phase into a digital value while providing the amplifier with a second set of electrical attributes different from the first set of electrical attributes, the converting including disconnecting the capacitor from an output of the amplifier; A method comprising:

19. 20. The method of claim 18, The method of claim 1, wherein the first set of electrical attributes comprises a first frequency bandwidth and the second set of electrical attributes comprises a second frequency bandwidth that is greater than the first frequency bandwidth.

20. 20. The method of claim 18, the first set of electrical attributes includes a first frequency bandwidth having a first upper corner frequency, and the second set of electrical attributes includes a second frequency bandwidth having a second upper corner frequency that is greater than the first upper corner frequency.

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