Dynamic residual amplification circuit based on charge sampling

Abstract

The invention provides a dynamic residual amplification circuit based on charge sampling, and relates to the technical field of integrated circuits, the dynamic residual amplification circuit comprises an integrating circuit, a logic circuit, a charge pump and a zero-cross detection circuit, the integrating circuit is connected with the logic circuit and the zero-cross detection circuit, the integrating circuit converts a sampled input differential signal into a constant current, and the constant current is connected with the charge pump. The output node is continuously charged or discharged, so that the input differential signal is converted into a current integral quantity; the zero-cross detection circuit monitors the output voltage of the integrating circuit in real time, and when the output voltage is greater than or equal to the common mode voltage VCM, the moment when the output voltage is equal to the common mode voltage VCM is converted into a digital clock edge; the logic circuit is connected with the charge pump and outputs digital pulses to the charge pump according to the digital clock edge so as to control the reset time sequence of the whole dynamic residual amplification circuit; the charge pump is configured to output a residual voltage modulated by the digital pulse in response to the digital pulse. The application helps to improve the linearity of the residual signal.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a dynamic residual amplifier circuit based on charge sampling. Background Technology

[0002] With the rapid development of the Internet of Things, wearable devices, and mobile terminals, higher demands are placed on the performance and power consumption of ADCs. The residual amplifier circuit is a crucial analog module in a Pipelined SAR ADC, playing a vital role in bridging the gap between different components. The residual amplifier circuit accounts for a significant portion of the power consumption in a Pipelined SAR ADC, and its power consumption level has a substantial impact on the overall power consumption of the ADC.

[0003] Chinese patent application CN119010909A discloses a dual-channel pipeline SAR ADC with residual transfer and amplification, comprising an N-stage successive approximation analog-to-digital converter and an (N-1)-stage residual processing circuit, where N is an integer greater than or equal to 2. Each residual processing circuit includes two structurally identical residual transfer and amplification circuits. Each successive approximation analog-to-digital converter is connected via the residual processing circuit. The residual transfer circuit is implemented using a passive charge-sharing method, and the residual amplification circuit is implemented using an active closed-loop residual amplifier. However, the passive charge-sharing residual transfer in the above scheme suffers from quantization noise and nonlinear residuals caused by non-ideal switched capacitors. Under large-signal and high-speed operation, the linearity of the residual signal is difficult to meet the requirements of closed-loop amplification. Therefore, it is necessary to provide an ultra-low-power reference circuit with small area and wide voltage domain to improve the linearity of the residual signal. Summary of the Invention

[0004] In view of this, the present invention proposes a dynamic residual amplifier circuit based on charge sampling. The input differential signal is converted into a constant current through an integrator circuit and continuously charged and discharged to the output node, which greatly reduces noise and sampling uncertainty. The fully dynamic working mode reduces the impact of static errors such as bias current and device drift on the residual accuracy and improves the linearity of the residual signal.

[0005] This invention provides a dynamic residual amplifier circuit based on charge sampling, comprising an integrator circuit, a logic circuit, a charge pump, and a zero-crossing detection circuit, wherein... The integrator circuit is connected to the logic circuit and the zero-crossing detection circuit respectively. The integrator circuit is used to convert the sampled input differential signal into a constant current and continuously charge or discharge the output node to convert the input differential signal into an integral current quantity. The zero-crossing detection circuit is used to monitor the output voltage of the integrator circuit in real time, and convert the moment when the output voltage is greater than or equal to the common mode voltage VCM into a digital clock edge. The logic circuit is connected to the charge pump, and the logic circuit is used to output digital pulses to the charge pump according to the digital clock edge to control the reset timing of the entire dynamic residual amplifier circuit. The charge pump is used to respond to the digital pulse to output a residual voltage modulated by the digital pulse.

[0006] Based on the above technical solutions, preferably, the integrating circuit includes a differential input circuit, a bias adjustment circuit, and an integrating capacitor circuit. The differential input circuit is connected to the bias adjustment circuit and the integrating capacitor circuit respectively. The differential input circuit is used to convert the input voltage difference into a differential current. The bias adjustment circuit is used to provide a constant bias current to the differential input circuit. The integrating capacitor circuit is used to accumulate charge on the differential current.

[0007] Based on the above technical solution, preferably, the differential input circuit includes NMOS transistors MN3 and MN4, load transistor MP1, and load transistor MP2. NMOS transistors MN3 and MN4 form an input differential pair. The common terminal of load transistors MP1 and MP2 is connected to the positive power rail VDD. The gate of load transistor MP1 is connected to the gate of load transistor MP2 and the bias adjustment circuit. The drain of load transistor MP1 is connected to the drain of NMOS transistor MN3 and the integrating capacitor circuit. The drain of load transistor MP2 is connected to the drain of NMOS transistor MN4 and the integrating capacitor circuit. The common terminal of NMOS transistors MN3 and MN4 is connected to the bias adjustment circuit.

[0008] More preferably, the bias adjustment circuit includes a tail current switch MN1 and a tail current transistor MN2. The source of the tail current switch MN1 is grounded, the gate of the tail current switch MN1 is connected to the differential input circuit, the drain of the tail current switch MN1 is connected to the source of the tail current transistor MN2, the gate of the tail current transistor MN2 is connected to a digitally programmable bias interface, and the drain of the tail current transistor MN2 is connected to the differential input circuit.

[0009] More preferably, the integrating capacitor circuit includes an output node VN, an output node VP, a capacitor C1, and a capacitor C2. The output node VN is connected to the differential input circuit, the logic circuit, and one end of the capacitor C1, respectively, and the other end of the capacitor C1 is grounded. The output node VP is connected to the differential input circuit, the logic circuit, and one end of the capacitor C2, respectively, and the other end of the capacitor C2 is grounded.

[0010] More preferably, the logic circuit includes comparator A1, comparator A2, flip-flop D1, flip-flop D2, and a NAND gate. The inverting input of comparator A1 is connected to the integrator circuit, the non-inverting input of comparator A1 is connected to the zero-crossing detection circuit, the output of comparator A1 is connected to the second pin of flip-flop D1, the first pin of flip-flop D1 is connected to the positive power rail VDD, and the common terminal of the third pin of flip-flop D1 and the third pin of flip-flop D2 is connected to the input of the NAND gate. The fourth pin of flip-flop D1... The pins are connected to the output node UP. The inverting input of comparator A2 is connected to the integrator circuit. The non-inverting input of comparator A2 is connected to the zero-crossing detection circuit. The output of comparator A2 is connected to the second pin of flip-flop D2. The first pin of flip-flop D2 is connected to the positive power rail VDD. The fourth pin of flip-flop D1 is connected to the output node DN. The output node UP is connected to the first output of the NAND gate and the charge pump. The output node DN is connected to the second output of the NAND gate and the charge pump.

[0011] More preferably, the charge pump includes a charge pump circuit and a reset switch circuit. The charge pump circuit is connected to the reset switch circuit and the logic circuit, respectively. The charge pump circuit is used to turn on or off the built-in current source in the charge pump circuit in response to digital pulses sent by the logic circuit. The reset switch circuit is used to reset the output node VOP or the output node VON to the same common mode voltage VCM before each cycle decision.

[0012] More preferably, the charge pump circuit includes current sources U1, U2, U3, and U4, switches S1, S2, S3, and S4, an output node VOP, and an output node VON. The two ends of current source U1 are respectively connected to the positive power rail VDD and one end of switch S1. The two ends of current source U2 are respectively connected to the positive power rail VDD and one end of switch S2. The two ends of current source U3 are respectively connected to ground GND and one end of switch S3. The two ends of current source U1 are respectively connected to ground GND and one end of switch S4. The other ends of switches S1 and S3 are both connected to the reset switch circuit through the output node VOP. The other ends of switches S2 and S4 are both connected to the reset switch circuit through the output node VON.

[0013] More preferably, the reset switch circuit includes a first reset switch, a second reset switch, switches clks1 and clks2, capacitor C3, and capacitor C4. One end of the first reset switch is connected to one end of the charge pump circuit and one end of the switch clks1, and the other end of the first reset switch is connected to the logic circuit. One end of the second reset switch is connected to one end of the charge pump circuit and one end of the switch clks2, and the other end of the second reset switch is connected to the logic circuit. The other end of the switch clks1 is grounded through capacitor C3, and the other end of the switch clks2 is grounded through capacitor C4.

[0014] More preferably, the zero-crossing detection circuit includes NMOS transistors MN5, MN6, MN7, PMOS transistors MP3, MP4, and MP5. The first common terminal of PMOS transistor MP4 and NMOS transistor MN6 is connected to the output node VIP, and the second common terminal of PMOS transistor MP4 and NMOS transistor MN6 is connected to the internal node VB. The source of PMOS transistor MP4 is connected to the drain of PMOS transistor MP3 and the source of PMOS transistor MP5, respectively. The gate of S-channel transistor MP3 is connected to the internal node VB and the gate of NMOS transistor MN5, respectively. The source of PMOS transistor MP3 is connected to the positive power rail VDD. The first common terminal of PMOS transistor MP5 and NMOS transistor MN7 is connected to the output node Vout. The second common terminal of PMOS transistor MP5 and NMOS transistor MN7 is connected to the output node Vin. The source of NMOS transistor MN7 is connected to the drain of NMOS transistor MN5 and the source of NMOS transistor MN6, respectively. The source of NMOS transistor MN5 is grounded.

[0015] The dynamic residual amplifier circuit based on charge sampling provided by this invention has the following advantages over the prior art: (1) The input differential signal is converted into a constant current by the integrator circuit and continuously charged and discharged to the output node, which is equivalent to performing accurate current-time integration on the input signal, greatly reducing noise and sampling uncertainty. The zero-point detection circuit captures the moment when the integral output intersects with the common mode voltage VCM in real time and converts it into a digital edge to ensure the time reference of the residual amplification factor. Furthermore, the integration-amplification process can be dynamically extended or shortened according to the input amplitude by the zero-point detection trigger logic circuit and the charge pump reset, and the equivalent gain can be automatically adjusted. No fixed-width external clock is required. The amplifier can converge quickly under both large and small signals, improving bandwidth utilization and system throughput. At the same time, the charge pump only works when the digital pulse arrives. The extremely short conduction time takes into account both high-speed response and energy consumption optimization. Both integration and zero-point detection have natural common mode noise suppression capabilities relative to the common mode level VCM. The full dynamic working mode reduces the impact of static errors such as bias current and device drift on the residual accuracy, and improves the linearity of the residual signal and the temperature stability of the dynamic residual amplifier circuit.

[0016] (2) The differential input circuit linearly converts the input voltage difference into differential current and greatly suppresses nonlinear distortion with the help of symmetrical structure and matching devices. The constant tail current provided by the bias adjustment circuit ensures the transconductance stability of the input stage when it operates in a wide dynamic range, further improving the conversion accuracy. The bias adjustment circuit can adjust the constant current amplitude and flexibly control the bandwidth and noise-bandwidth product of the input stage, supporting switching between high-speed and low-power modes. At the same time, the integration process has a natural low-pass filtering effect on high-frequency interference, reducing the system's sensitivity to external RF and digital switching noise. The differential input devices and bias current sources adopt a long channel / current mirror design with low temperature coefficient and small drift, ensuring that the integration constant and gain remain stable in a wide temperature range. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A circuit diagram of a dynamic residual amplifier circuit based on charge sampling provided for this invention; Figure 2 The circuit diagram of the zero-crossing detection circuit provided by the present invention.

[0019] Explanation of reference numerals in the attached diagram: 1. Integrating circuit; 2. Logic circuit; 3. Charge pump; 4. Zero-crossing detection circuit. Detailed Implementation

[0020] The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0021] Unless otherwise defined, the technical or scientific terms used in this invention shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms "an" or "a" and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms "connected" or "linked" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up," "down," "left," "right," etc., are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship also changes accordingly.

[0022] like Figure 1 As shown, this invention provides a dynamic residual amplifier circuit based on charge sampling, including an integrator circuit 1, a logic circuit 2, a charge pump 3, and a zero-crossing detection circuit 4, wherein... Integrating circuit 1 is connected to logic circuit 2 and zero-crossing detection circuit 4 respectively. Integrating circuit 1 is used to convert the sampled input differential signal into a constant current and continuously charge or discharge the output node to convert the input differential signal into an integral current quantity. The zero-crossing detection circuit 4 is used to monitor the output voltage of the integrating circuit 1 in real time, and converts the moment when the output voltage is greater than or equal to the common mode voltage VCM into a digital clock edge. Logic circuit 2 is connected to charge pump 3. Logic circuit 2 is used to output digital pulses to charge pump 3 according to the digital clock edge in order to control the reset timing of the entire dynamic residual amplifier circuit. Charge pump 3 is used to respond to digital pulses to output a residual voltage modulated by the digital pulses.

[0023] In this embodiment, the integrating circuit 1 includes a differential input circuit, a bias adjustment circuit, and an integrating capacitor circuit. The differential input circuit is connected to the bias adjustment circuit and the integrating capacitor circuit respectively. The differential input circuit is used to convert the input voltage difference into a differential current. The bias adjustment circuit is used to provide a constant bias current to the differential input circuit. The integrating capacitor circuit is used to accumulate charge on the differential current.

[0024] The differential input circuit includes NMOS transistors MN3 and MN4, load transistors MP1 and MP2. NMOS transistors MN3 and MN4 form an input differential pair. The common terminal of load transistors MP1 and MP2 is connected to the positive power rail VDD. The gate of load transistor MP1 is connected to the gate of load transistor MP2 and the bias adjustment circuit. The drain of load transistor MP1 is connected to the drain of NMOS transistor MN3 and the integrating capacitor circuit. The drain of load transistor MP2 is connected to the drain of NMOS transistor MN4 and the integrating capacitor circuit. The common terminal of NMOS transistors MN3 and MN4 is connected to the bias adjustment circuit.

[0025] The bias adjustment circuit includes a tail current switch MN1 and a tail current transistor MN2. The source of the tail current switch MN1 is grounded, the gate of the tail current switch MN1 is connected to the differential input circuit, the drain of the tail current switch MN1 is connected to the source of the tail current transistor MN2, the gate of the tail current transistor MN2 is connected to the digital programmable bias interface, and the drain of the tail current transistor MN2 is connected to the differential input circuit.

[0026] The integrating capacitor circuit includes output node VN, output node VP, capacitor C1, and capacitor C2. Output node VN is connected to the differential input circuit, logic circuit 2, and one end of capacitor C1, respectively. The other end of capacitor C1 is grounded. Output node VP is connected to the differential input circuit, logic circuit 2, and one end of capacitor C2, respectively. The other end of capacitor C2 is grounded.

[0027] In this embodiment, two NMOS transistors, MN3 and MN4, are used to form a differential pair, with their gates connected to Vip and Vin, respectively. When there is a differential-mode voltage between Vip and Vin, this differential pair will convert the input voltage difference into two slightly different drain currents. A load transistor MP1 and a load transistor MP2 are connected in series at the drains of NMOS transistors MN3 and MN4, respectively. The sources of load transistors MP1 and MP2 are connected to a positive voltage VDD, and their gates are biased by an internal small amplifier (labeled AMP), forming a folded-load structure. This significantly increases the output impedance, increases the voltage gain, and ensures sufficient swing and linearity under different input conditions. MN1 at the bottom of the differential pair provides a constant tail current, and its drain is connected to the sources of MN3 and MN4; MN1 is connected in series with MN2, and a set of digital control signals TRIM<N:0> is connected to the gate of MN2. By assigning different digital codes to TRIM during silicon wafer testing or operation, the on / off state of several parallel or series-connected small transistors on MN2 can be switched, thereby finely adjusting the tail current flowing through the differential pair to achieve the purpose of adjusting transconductance, bandwidth, and offset compensation. At the two output nodes (labeled VN and VP) connecting MP1, MP2 and MN3, MN4, an integrating capacitor C1 and C2 are connected in parallel with each other. When the differential pair is turned on, the differential-mode current injects or extracts charge from these two capacitors through the PMOS load. The voltage across the capacitors changes linearly with time, and the slope is proportional to the input voltage difference multiplied by the transistor transconductance and divided by the capacitance value.

[0028] In one example, the components include a tail current switch MN1, a tail current transistor MN2, input differential pairs MN3 and MN4, and load transistors MP1 and MP2. In the reset state, the integrator outputs VP and VN are reset to VDD. In the amplification state, VP and VN begin to discharge at different rates, and a time window signal is obtained after zero-crossing detection. The discharge rate can be adjusted by regulating the tail current transistor, thus achieving gain tuning.

[0029] In this embodiment, the differential input circuit linearly converts the input voltage difference into a differential current, and significantly suppresses nonlinear distortion with the help of a symmetrical structure and matching devices. The constant tail current provided by the bias adjustment circuit ensures the transconductance stability of the input stage when operating over a wide dynamic range, further improving the conversion accuracy. The bias adjustment circuit can adjust the constant current amplitude, flexibly control the bandwidth and noise-bandwidth product of the input stage, and support switching between high-speed and low-power modes. At the same time, the integration process has a natural low-pass filtering effect on high-frequency interference, reducing the system's sensitivity to external RF and digital switching noise. Both the differential input devices and the bias current source adopt a long-channel / current mirror design, with low temperature coefficient and small drift, ensuring that the integration constant and gain remain stable over a wide temperature range.

[0030] Furthermore, the logic circuit 2 includes a comparator A1, a comparator A2, a flip-flop D1, a flip-flop D2, and a NAND gate. The inverting input terminal of the comparator A1 is connected to the integrating circuit 1, the non-inverting input terminal of the comparator A1 is connected to the zero-crossing detection circuit 4, the output terminal of the comparator A1 is connected to the second pin of the flip-flop D1, the first pin of the flip-flop D1 is connected to the positive power rail terminal VDD, the common terminal of the third pin of the flip-flop D1 and the third pin of the flip-flop D2 is connected to the input terminal of the NAND gate, the fourth pin of the flip-flop D1 is connected to the output node UP, the inverting input terminal of the comparator A2 is connected to the integrating circuit 1, the non-inverting input terminal of the comparator A2 is connected to the zero-crossing detection circuit 4, the output terminal of the comparator A2 is connected to the second pin of the flip-flop D2, the first pin of the flip-flop D2 is connected to the positive power rail terminal VDD, the fourth pin of the flip-flop D1 is connected to the output node DN, the output node UP is respectively connected to the first output terminal of the NAND gate and the charge pump, and the output node DN is respectively connected to the second output terminal of the NAND gate and the charge pump.

[0031] In this embodiment, the positive input of the first comparator A1 is connected to VOP, and the negative input is connected to the midpoint voltage VCM; the positive input of the second comparator A2 is connected to VCM, and the negative input is connected to VON. The functions of the comparator A1 and the comparator A2 are to determine whether the current remaining voltage is positive-biased (VOP > VCM) or negative-biased (VON < VCM), and output two digital levels. The output of each comparator is sent to its respective D flip-flop (with asynchronous Reset). When Reset is pulled high, the Q outputs of both flip-flops are cleared; after Reset is pulled low, the next clock edge (clks2) locks in the comparison results simultaneously, ensuring that the UP / DN signals are synchronized and free of glitches. The two latched Qs may be "10" or "01" (theoretically never both "11" at the same time). Through the NAND gate circuit, they are converted into a pair of mutually exclusive outputs. If the upper comparator determines positive, the final outputs are UP = 1 and DN = 0; if the lower comparator determines negative, the outputs are UP = 0 and DN = 1. The generated UP pulse drives the subsequent charge pump 3 to inject charge into the positive-side capacitor and extract charge from the negative-side capacitor; the DN pulse does the opposite. Each time UP or DN causes a fixed amount of voltage step on the integrating capacitor, completing one-bit approximation correction of the SAR.

[0032] It can be understood that when RST = 1, the previous UP and DN are cleared; when RST → 0, it enters the comparison stage; when the clks2 edge arrives, the comparison results of both paths are simultaneously locked into the D flip-flop; the decoding logic outputs mutually exclusive UP or DN; the charge pump 3 adds / subtracts the residual voltage according to UP / DN, and enters the next-bit cycle.

[0033] The charge pump 3 includes a charge pump circuit and a reset switch circuit. The charge pump circuit is connected to the reset switch circuit and the logic circuit 2 respectively. The charge pump circuit is used to turn on or off the built-in current source in the charge pump circuit by responding to the digital pulse sent by the logic circuit 2. The reset switch circuit is used to reset the output node VOP or output node VON to the same common mode voltage VCM before each cycle decision.

[0034] The charge pump circuit includes current sources U1, U2, U3, and U4, switches S1, S2, S3, and S4, output node VOP, and output node VON. The two ends of current source U1 are connected to the positive power rail VDD and one end of switch S1, respectively. The two ends of current source U2 are connected to the positive power rail VDD and one end of switch S2, respectively. The two ends of current source U3 are connected to ground GND and one end of switch S3, respectively. The two ends of current source U1 are connected to ground GND and one end of switch S4, respectively. The other ends of switches S1 and S3 are connected to the reset switch circuit through output node VOP, and the other ends of switches S2 and S4 are connected to the reset switch circuit through output node VON.

[0035] The reset switch circuit includes a first reset switch, a second reset switch, switches clks1 and clks2, capacitor C3, and capacitor C4. One end of the first reset switch is connected to the charge pump circuit and one end of switch clks1, and the other end of the first reset switch is connected to logic circuit 2. One end of the second reset switch is connected to the charge pump circuit and one end of switch clks2, and the other end of the second reset switch is connected to logic circuit 2. The other end of switch clks1 is grounded through capacitor C3, and the other end of switch clks2 is grounded through capacitor C4.

[0036] In one example, at each of the two integration nodes VOP and VON, there are two pairs of current sources: the top two current sources are connected to the positive power supply and controlled by the DN signal, while the bottom two current sources are grounded and controlled by the UP signal. When the DN pulse is active, the upper current sources conduct, causing charge to be withdrawn from one capacitor and injected into the other (i.e., forming a step voltage between C3 and C4); when the UP pulse is active, the lower current sources conduct, performing charge injection / withdrawal in the opposite direction. Each UP or DN pulse injects or removes an equal amount of charge from C3 and C4 according to a fixed amount of I×t, thereby generating a fixed-amplitude voltage step at the two nodes.

[0037] The RST signal controls two switches. When RST goes high, VOP and VON are simultaneously shorted to the common mode voltage VCM. This step clears the residue from the previous integration, pre-charging C3 and C4 to the midpoint level, ensuring that each SAR decision starts from zero reference. The two switches controlled by clks2 connect or isolate C3 and C4 to nodes VOP and VON respectively. During the sampling / integration phase (clks2 active), the switches are closed, allowing the current source to charge and discharge the capacitors. During the hold phase (clks2 inactive), the switches are open, maintaining the charge on the capacitors and the resulting voltage.

[0038] Furthermore, after the first-stage sub-ADC completes its conversion, a flag signal is generated to control the residual amplifier to enter the amplification state; when the first-stage sub-ADC enters the sampling stage, the sampling signal puts the residual amplifier in the reset state until the first-stage sub-ADC completes its conversion. The first-stage sub-ADC includes an integration circuit 1, a logic circuit 2, and a zero-crossing detection circuit 4, while the second-stage sub-ADC includes a reset switch circuit in the charge pump 3.

[0039] Integrating circuit 1 and zero-crossing detection circuit 4 form a voltage-to-time converter (VTC), which converts the residual voltage from the first-stage sub-ADC into a time window. Charge pump 3 and the sampling capacitor of the second-stage sub-ADC can be considered a time-to-voltage converter (TVC). The time window signal controls charge pump 3 to charge and discharge the sampling capacitor of the second-stage SAR ADC, converting the time window into an output voltage difference. The time window signal generated by the VTC has a negative temperature coefficient; using a current with a positive temperature coefficient to charge charge pump 3 achieves temperature compensation for the gain. The tail current transistor is controlled by a digital tuning signal.

[0040] AMP and RST are two non-overlapping clock signals used as control signals for the amplifier. When AMP is high, the residual amplifier circuit is in amplification mode; when RST is high, it is in reset mode. AMP is generated by the clock signal of the first-stage sub-ADC and the enable signal indicating completion of the conversion. During the first-stage sampling and conversion, the residual amplifier is in reset mode; after sampling, it enters amplification mode until the next sampling of the first-stage sub-ADC begins. clks2 is the sampling clock for the second stage, controlled by the flag signal indicating completion of the second-stage conversion, which controls the second-stage ADC to enter sampling mode. The second-stage ADC samples the output voltage of the residual amplifier. When AMP changes from high to low, the sampling phase ends, and clks2 goes low.

[0041] Temperature changes affect the threshold voltages of individual transistors, which in turn affects the discharge rate of the integrator, thus impacting the voltage difference generated by the VTC module. The threshold voltage of the MOSFET decreases with increasing temperature, while the discharge rate of the integrator increases with temperature. This faster discharge rate leads to a smaller time window for VTC generation, thus affecting its gain. The temperature coefficient can be simplified to a linear function:

[0042] Where T is the absolute temperature, and if the gain of TVC It has a positive temperature coefficient:

[0043] Multiplying this by the negative temperature coefficient gain of VTC yields a quantity that changes very little with temperature:

[0044] Where a1 is the first time constant, a2 is the second time constant, b1 is the first deviation constant, and b2 is the second deviation constant. By adjusting the circuit parameters so that the coefficient of the first term in the above equation is close to 0, and because the coefficient of the second term is much smaller than that of the constant term, the charge pump current can be adjusted appropriately. The temperature coefficient can achieve a gain with zero temperature coefficient.

[0045] The zero-crossing detection circuit 4 includes NMOS transistors MN5, MN6, MN7, PMOS transistors MP3, MP4, and MP5. The first common terminal of PMOS transistor MP4 and NMOS transistor MN6 is connected to the output node VIP. The second common terminal of PMOS transistor MP4 and NMOS transistor MN6 is connected to the internal node VB. The source of PMOS transistor MP4 is connected to the drain of PMOS transistor MP3 and the source of PMOS transistor MP5. The gate of PMOS transistor MP3 is connected to the internal node VB and the gate of NMOS transistor MN5. The source of PMOS transistor MP3 is connected to the positive power rail VDD. The first common terminal of PMOS transistor MP5 and NMOS transistor MN7 is connected to the output node Vout. The second common terminal of PMOS transistor MP5 and NMOS transistor MN7 is connected to the output node Vin. The source of NMOS transistor MN7 is connected to the drain of NMOS transistor MN5 and the source of NMOS transistor MN6. The source of NMOS transistor MN5 is grounded.

[0046] In this embodiment, the gate and drain of MP1 are connected to VB, and its source is connected to VDD; the gate and source of MN1 are both connected to VB, and its drain is grounded. These two MOSFETs are connected in series between the VB points, automatically clamping VB to a stable potential and providing a bias node independent of an external clock. The drains / sources of MP2 and MN2 are connected in pairs, with one terminal being VB and the other terminal being the input Vip; their gates are directly connected to Vip. When Vip rises above the threshold of MN2 or falls below the threshold of MP2, the corresponding transistor turns on, forming a channel between VB and Vip. In other words, by using the input level to turn this pair of complementary transistors on or off, VB can be sampled to a certain level on Vip. MP3 and MN3 have the same structure as MP1 and MN1, except that their gates are connected to Vin, one end of their drain / source is connected to VB, and the other end is connected to the output Vout. When Vin is sufficiently high / low, MP3 or MN3 turns on, connecting VB to Vout, and the potential of VB is transferred to Vout.

[0047] Understandably, MP1 and MN1 automatically clamp VB to a stable midpoint potential without a clock. Vip itself drives MP2 / MN2, causing VB to temporarily follow the level of Vip (equivalent to sampling the input to the internal node VB). Subsequently, Vin drives MP3 / MN3, sending the voltage stored on VB to the output node Vout (equivalent to releasing the internal charge to the output). After the input switching, this set of self-biased + complementary switches completes the action of switching Vip to Vout via VB, without relying on an external clock, but using the input's own threshold to control the on / off state.

[0048] In this embodiment, the input differential signal is converted into a constant current by the integrator circuit 1 and continuously charged and discharged to the output node, which is equivalent to performing a precise current-time integration of the input signal, greatly reducing noise and sampling uncertainty. The zero-point detection circuit captures the moment when the integrated output intersects with the common mode voltage VCM in real time and converts it into a digital edge to ensure the time reference of the residual amplification factor. Furthermore, the zero-point detection triggers the logic circuit 2 and the charge pump 3 for reset. The integration-amplification process can be dynamically extended or shortened according to the input amplitude, automatically adjusting the equivalent gain without the need for a fixed-width external clock. The amplifier can converge quickly under both large and small signals, improving bandwidth utilization and system throughput. At the same time, the charge pump 3 only operates when the digital pulse arrives, and the extremely short conduction time balances high-speed response and energy consumption optimization. Both integration and zero-point detection have natural common mode noise suppression capabilities relative to the common mode level VCM. The fully dynamic operation mode reduces the impact of static errors such as bias current and device drift on the residual accuracy, improving the linearity of the residual signal and the temperature stability of the dynamic residual amplifier circuit.

[0049] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A dynamic residual amplifier circuit based on charge sampling, characterized in that, It includes an integrating circuit (1), a logic circuit (2), a charge pump (3), and a zero-crossing detection circuit (4), wherein, The integrator circuit (1) is connected to the logic circuit (2) and the zero-crossing detection circuit (4) respectively. The integrator circuit (1) is used to convert the sampled input differential signal into a constant current and continuously charge or discharge the output node to convert the input differential signal into an integral current quantity. The zero-crossing detection circuit (4) is used to monitor the output voltage of the integrator circuit (1) in real time, and convert the moment when the output voltage is greater than or equal to the common mode voltage VCM into a digital clock edge. The logic circuit (2) is connected to the charge pump (3). The logic circuit (2) is used to output digital pulses to the charge pump (3) according to the digital clock edge to control the reset timing of the entire dynamic residual amplifier circuit. The charge pump (3) is used to respond to the digital pulse to output a residual voltage modulated by the digital pulse.

2. The dynamic residual amplifier circuit based on charge sampling as described in claim 1, characterized in that, The integrating circuit (1) includes a differential input circuit, a bias adjustment circuit, and an integrating capacitor circuit. The differential input circuit is connected to the bias adjustment circuit and the integrating capacitor circuit respectively. The differential input circuit is used to convert the input voltage difference into a differential current. The bias adjustment circuit is used to provide a constant bias current to the differential input circuit. The integrating capacitor circuit is used to accumulate charge on the differential current.

3. The dynamic residual amplifier circuit based on charge sampling as described in claim 2, characterized in that, The differential input circuit includes NMOS transistors MN3 and MN4, load transistor MP1, and load transistor MP2. NMOS transistors MN3 and MN4 form an input differential pair. The common terminal of load transistors MP1 and MP2 is connected to the positive power rail VDD. The gate of load transistor MP1 is connected to the gate of load transistor MP2 and the bias adjustment circuit. The drain of load transistor MP1 is connected to the drain of NMOS transistor MN3 and the integrating capacitor circuit. The drain of load transistor MP2 is connected to the drain of NMOS transistor MN4 and the integrating capacitor circuit. The common terminal of NMOS transistors MN3 and MN4 is connected to the bias adjustment circuit.

4. The dynamic residual amplifier circuit based on charge sampling as described in claim 2, characterized in that, The bias adjustment circuit includes a tail current switch MN1 and a tail current transistor MN2. The source of the tail current switch MN1 is grounded, the gate of the tail current switch MN1 is connected to the differential input circuit, the drain of the tail current switch MN1 is connected to the source of the tail current transistor MN2, the gate of the tail current transistor MN2 is connected to the digital programmable bias interface, and the drain of the tail current transistor MN2 is connected to the differential input circuit.

5. The dynamic residual amplifier circuit based on charge sampling as described in claim 2, characterized in that, The integrating capacitor circuit includes an output node VN, an output node VP, a capacitor C1, and a capacitor C2. The output node VN is connected to one end of the differential input circuit, the logic circuit (2), and the capacitor C1, respectively. The other end of the capacitor C1 is grounded. The output node VP is connected to one end of the differential input circuit, the logic circuit (2), and the capacitor C2, respectively. The other end of the capacitor C2 is grounded.

6. The dynamic residual amplifier circuit based on charge sampling as described in claim 1, characterized in that, The logic circuit (2) includes comparator A1, comparator A2, flip-flop D1, flip-flop D2, and a NAND gate. The inverting input of comparator A1 is connected to the integrator circuit (1), the non-inverting input of comparator A1 is connected to the zero-crossing detection circuit (4), the output of comparator A1 is connected to the second pin of flip-flop D1, the first pin of flip-flop D1 is connected to the positive power rail VDD, the common terminal of the third pin of flip-flop D1 and the third pin of flip-flop D2 is connected to the input of the NAND gate, and the fourth pin of flip-flop D1 is connected to... The output node UP is connected, the inverting input of the comparator A2 is connected to the integrator circuit (1), the non-inverting input of the comparator A2 is connected to the zero-crossing detection circuit (4), the output of the comparator A2 is connected to the second pin of the flip-flop D2, the first pin of the flip-flop D2 is connected to the positive power rail VDD, the fourth pin of the flip-flop D1 is connected to the output node DN, the output node UP is connected to the first output of the NAND gate and the charge pump, and the output node DN is connected to the second output of the NAND gate and the charge pump.

7. The dynamic residual amplifier circuit based on charge sampling as described in claim 1, characterized in that, The charge pump (3) includes a charge pump circuit and a reset switch circuit. The charge pump circuit is connected to the reset switch circuit and the logic circuit (2) respectively. The charge pump circuit is used to turn on or off the built-in current source in the charge pump circuit by responding to the digital pulse sent by the logic circuit (2). The reset switch circuit is used to reset the output node VOP or output node VON to the same common mode voltage VCM before each cycle decision.

8. The dynamic residual amplifier circuit based on charge sampling as described in claim 7, characterized in that, The charge pump circuit includes current sources U1, U2, U3, and U4, switches S1, S2, S3, and S4, an output node VOP, and an output node VON. The two ends of current source U1 are connected to the positive power rail VDD and one end of switch S1, respectively. The two ends of current source U2 are connected to the positive power rail VDD and one end of switch S2, respectively. The two ends of current source U3 are connected to ground GND and one end of switch S3, respectively. The two ends of current source U1 are connected to ground GND and one end of switch S4, respectively. The other ends of switches S1 and S3 are connected to the reset switch circuit via the output node VOP. The other ends of switches S2 and S4 are connected to the reset switch circuit via the output node VON.

9. The dynamic residual amplifier circuit based on charge sampling as described in claim 7, characterized in that, The reset switch circuit includes a first reset switch, a second reset switch, switches clks1 and clks2, capacitor C3 and capacitor C4. One end of the first reset switch is connected to one end of the charge pump circuit and one end of the switch clks1, and the other end of the first reset switch is connected to the logic circuit (2). One end of the second reset switch is connected to one end of the charge pump circuit and one end of the switch clks2, and the other end of the second reset switch is connected to the logic circuit (2). The other end of the switch clks1 is grounded through the capacitor C3, and the other end of the switch clks2 is grounded through the capacitor C4.

10. A dynamic residual amplifier circuit based on charge sampling as described in claim 1, characterized in that, The zero-crossing detection circuit (4) includes NMOS transistors MN5, MN6, MN7, MP3, MP4, and MP5. The first common terminal of MP4 and NMOS transistor MN6 is connected to the output node VIP, and the second common terminal of MP4 and NMOS transistor MN6 is connected to the internal node VB. The source of MP4 is connected to the drain of MP3 and the source of MP5, respectively. The gate of P3 is connected to the internal node VB and the gate of the NMOS transistor MN5, respectively. The source of the PMOS transistor MP3 is connected to the positive power rail VDD. The first common terminal of the PMOS transistor MP5 and the NMOS transistor MN7 is connected to the output node Vout. The second common terminal of the PMOS transistor MP5 and the NMOS transistor MN7 is connected to the output node Vin. The source of the NMOS transistor MN7 is connected to the drain of the NMOS transistor MN5 and the source of the NMOS transistor MN6, respectively. The source of the NMOS transistor MN5 is grounded.

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