Calibration of parametric errors in digital-to-time converters

Abstract

In some examples, the circuit includes a clock divider (102) and a calibration circuit (104) coupled to the clock divider. The clock divider includes a digital-to-time converter (DTC) (204). The calibration circuit is configured to determine a gain error and a parametric integral nonlinearity (INL) error of the DTC, determine gain and INL adjustment values ​​to compensate for the gain and INL errors, and modify operation of the DTC according to the gain and INL adjustment values ​​to correct the gain and INL errors.

Description

[Background technology]

[0001] Various electrical components in an electronic system operate at different clock frequencies. As a result, a first clock signal having a first frequency may be divided to form a second clock signal having a second frequency. Some techniques for implementing this division may limit their usefulness. Summary of the Invention

[0002] In some examples, a circuit includes a multi-modulus (MM) divider, a digital delta-sigma modulator, a digital-to-time converter (DTC), and a calibration circuit. The MM divider has a first input configured to receive an input clock signal, a second input, and an output. The delta-sigma modulator has a first input configured to receive a division value, a second input coupled to the output of the MM divider, a first output coupled to the second input of the MM divider, and a second output. The DTC has a first input, a second input, a third input, and an output, the first input coupled to the output of the MM divider and the second input coupled to the second output of the delta-sigma modulator. The calibration circuit has a first input coupled to the DTC output, a second input coupled to the second output of the delta-sigma modulator, and an output coupled to a third DTC input.

[0003] In some examples, a circuit includes a clock divider and a calibration circuit coupled to the clock divider. The clock divider includes a digital-to-time converter (DTC). The calibration circuit is configured to determine a gain error and a parametric integral nonlinearity (INL) error of the DTC, determine gain and INL adjustment values ​​to compensate for the gain and INL errors, and modify operation of the DTC in response to the gain and INL adjustment values ​​to correct the gain and INL errors.

[0004] In some examples, a system includes a controller, a clock divider, a calibration circuit, and a component. The controller is configured to provide a control signal. The clock divider is coupled to the controller and includes a DTC, the DTC configured to modify a received clock signal according to the control signal to form a modified clock signal. The calibration circuit is coupled to the clock divider. The calibration circuit is configured to determine a gain error and a parametric integral nonlinearity (INL) error of the DTC, determine gain and INL adjustment values ​​to compensate for the gain and INL errors, and modify operation of the DTC in response to the gain and INL adjustment values ​​to correct the gain and INL errors. The component is coupled to the clock divider and configured to receive the modified clock signal from the clock divider and operate according to the modified clock signal. [Brief description of the drawings]

[0005] [Figure 1] FIG. 1 is a block diagram of an electronic device in accordance with various examples.

[0006] [Diagram 2] 1 is a block diagram of a clock divider with a calibration circuit, in accordance with various examples.

[0007] [Diagram 3] 1 is a block diagram of a clock divider with a calibration circuit, in accordance with various examples.

[0008] [Figure 4] 1 is a block diagram of a calibrated phase-locked loop (PLL) in accordance with various examples.

[0009] [Diagram 5] 1 is a block diagram of a calibration PLL in accordance with various examples.

[0010] [Figure 6] 1 is a block diagram of a calibration PLL in accordance with various examples.

[0011] [Figure 7] 1 is a block diagram of a calibration PLL in accordance with various examples.

[0012] [Figure 8] 1 is a block diagram of a calibration PLL in accordance with various examples.

[0013] [Figure 9] 1 is a block diagram of a calibration PLL in accordance with various examples.

[0014] [Figure 10] 1 is a block diagram of a PLL including a clock divider with a calibration circuit, in accordance with various examples.

[0015] [Figure 11] 1 is a block diagram of a PLL including a clock divider with a calibration circuit, in accordance with various examples.

[0016] [Figure 12] FIG. 2 is a block diagram of a detector in accordance with various examples.

[0017] [Figure 13] FIG. 2 is a block diagram of a detector in accordance with various examples.

[0018] [Figure 14] FIG. 2 is a block diagram of a detector in accordance with various examples.

[0019] [Figure 15] 5A-5C are timing diagrams of signals in a clock divider, in accordance with various examples.

[0020] [Figure 16] 1 is a diagram of basis functions according to various examples;

[0021] [Figure 17] 1 is a diagram of extended basis functions, according to various examples;

[0022] [Figure 18] 1 is a diagram of simplified basis functions, according to various examples.

[0023] [Figure 19] 1 is a transient simulation of gain and parametric integral nonlinearity (INL) correction in a clock divider, in accordance with various examples.

[0024] [Figure 20A] 1 is a diagram illustrating a phase noise spectrum of a clock divider with INL cancellation disabled, in accordance with various examples.

[0025] [Figure 20B] 1 is a diagram illustrating a phase noise spectrum of a clock divider with INL cancellation enabled, in accordance with various examples. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] There are several techniques for clock division, such as integer division. However, integer division may be limited in its usefulness due to the integer relationship that exists between the input clock signal and the output clock signal, which limits the resolution of the selectable output clock signal frequency. One solution to avoid such limitations on the output frequency resolution is to implement a fractional output divider (FOD). A fractional output divider dynamically changes its division value in time to divide the input clock signal such that the average divided clock frequency is not constrained to the integer relationship between the input clock signal and the divided clock signal. Here, the divided clock signal has an average frequency corresponding to a programmed value. However, the dynamically changing division value may cause an instantaneous phase error in the divided clock signal, which may result in jitter in the divided clock signal. Jitter may be viewed as the instantaneous time change between a rising edge of the divided clock signal and a corresponding rising edge of an ideal clock signal having the same frequency as the average frequency of the divided clock signal.

[0027] In some examples, the ideal clock signal is a periodic clock signal (e.g., each clock cycle has the same period). Phase error can cause the period of the divided clock to vary from clock cycle to clock cycle and not match the period of the ideal clock signal. This mismatch can be corrected, such as by a digital-to-time converter (DTC) that modifies the divided clock signal according to a residual error signal that quantifies the phase or time error between the input clock signal and the divided clock signal. However, implementations of the DTC can introduce correction errors as the DTC modifies the divided clock signal to counteract the residual error signal due to dynamic changes in the division value. Such correction errors include gain error, parametric integral nonlinearity (INL) error, and mismatch error. Gain error corresponds to the error of the full-scale range in time of the DTC compared to an ideal full-scale range corresponding to the input clock period or an integer multiple of the input clock period. INL corresponds to the error under the assumption of zero gain error, which can be described as a function of the input residual that controls the DTC. Mismatch errors correspond to errors in the individual settings of the input residuals that do not easily lend themselves to being described as a function of the input residuals that control the DTC.

[0028] Because the mismatch error does not easily lend itself to being described as a function of the input residuals that control the DTC, the correction of the mismatch error may be performed via a look-up table (LUT). If the mismatch error is relatively stable over temperature, measurements and calculations to determine the LUT entry values ​​may be performed offline. In such an example, the remaining errors of concern are gain error and INL error, which may vary significantly with temperature. Thus, the gain error and INL error may be corrected substantially continuously, rather than offline. In some examples, the continuous correction of the gain error and INL error involves an offline calibration of the mismatch error via the LUT.

[0029] The described examples provide a circuit useful for correcting gain and INL errors introduced in forming a clock signal. For example, the described circuit can estimate gain and INL error values, determine gain and INL adjustment values, and modify the gain and INL of the DTC according to the gain and INL adjustment values ​​to modify the gain and INL errors of the DTC, so that their impact on the output clock signal can be mitigated. In some examples, such calibration can provide an output clock signal that is periodic in nature and approximately equivalent to an ideal clock signal, while avoiding the constraint of an integer relationship between the input clock signal and the output clock signal and mitigating the impact of gain or INL errors introduced in the process of forming the output clock signal.

[0030] FIG. 1 is a block diagram of an electronic device 100 according to various examples. The electronic device 100 may be any suitable device, the scope of which is not limited herein. For example, the electronic device 100 may be a device in which it is useful to have a second clock signal having a second frequency that varies from a first frequency of a first clock signal, such as by frequency division or frequency multiplication techniques. Thus, the electronic device 100 includes a clock divider 102. The clock divider 102 may be of various forms, such as an FOD. The FOD may be implemented in an open loop context, such as a frequency divider, or in a closed loop context, such as in a phase-locked loop. The clock divider 102 includes a calibration circuit 104. In various examples, the calibration circuit 104 estimates, calculates, or otherwise determines an error of or associated with the clock divider 102, determines an adjustment value based on the error, and corrects such error by correcting or calibrating the clock divider 102 based on the adjustment value.

[0031] The electronic device 100 also includes a controller 106. The controller 106 may be coupled to the clock divider 102 and / or the calibration circuit 104 and may provide various control signals or other data to the clock divider 102 and / or the calibration circuit 104. These signals may include at least a reference clock (e.g., an input clock to the clock divider 102) and a frequency by which the clock divider 102 divides the input clock (or a value by which the clock divider 102 divides the input clock) to form an output clock. In other examples, the reference clock is provided by another component (not shown), such as an oscillator or a phase-locked loop, such as a fractional-N or integer-N frequency synthesizer. In some examples, the controller 106 receives the output clock from the clock divider 102. In other examples, the electronic device 100 includes a component 108. The component 108 may be coupled to the clock divider 102 and may receive the output clock signal from the clock divider 102. In various examples, component 108 is any suitable component, such as a radio transceiver, a frequency divider, a phase-locked loop (e.g., a fractional-N or integer-N frequency synthesizer, etc.), a component useful in communications or other signaling, or other component that may benefit from receiving an output clock signal that has a frequency that is different from the input clock and that is set with high resolution.

[0032] FIG. 2 is a block diagram of a clock divider 102 with a calibration circuit 104 according to various examples. In some examples, the clock divider 102 shown in FIG. 2 is an open-loop FOD. In some examples, the clock divider 102 includes a multi-modulus (MM) divider 202, a digital delta-sigma modulator 206, a DTC 204, and a calibration circuit 104. In some examples, the MM divider 202 has a first input configured to receive an input clock signal, such as a reference clock signal shown as clk_ref in FIG. 2. The MM divider 202 also has a second input and an output. The delta-sigma modulator 206 has a first input configured to receive a division value including integer and fractional components, shown as Div Val in FIG. 2. The division value may be in a digital format or digital domain and is converted by the delta-sigma modulator 206 into a series of division values, shown as N in FIG. 2, whose average corresponds to Div Val. The delta-sigma modulator 206 has a first output coupled to the second input of the MM divider 202 and provides N to the MM divider 202 via this coupling. The delta-sigma modulator 206 further includes a second input coupled to the output of the MM divider 202 and a second output. The DTC 204 has a first input coupled to the output of the MM divider 202, a second input coupled to the second output of the delta-sigma modulator 206, a third input, and an output. In some examples, the DTC 204 receives a residual error signal, shown as Res in FIG. 2, from the delta-sigma modulator 206. The DTC 204 provides an output clock signal, shown as clk_out in FIG. 2, at its output. The calibration circuit 104 has a first input coupled to the output of the DTC 204, a second input coupled to the second output of the delta-sigma modulator 206, and an output coupled to a third input of the DTC 204. In some examples, the calibration circuit 104 has a third input coupled to the output of the MM divider 202 .

[0033] In one example of operation, the delta-sigma modulator 206 receives Div Val, determines N based on Div Val, and provides N to the MM divider 202. The delta-sigma modulator 206 also provides Res at its second output. The MM divider 202 receives clk_ref and N and provides a divided clock signal, shown as clk_div in FIG. 2, based thereon. The DTC 204 receives clk_div and Res and provides clk_out based thereon. The calibration circuit 104 receives clk_div, clk_out, and Res and determines gain and INL error adjustment values ​​for calibrating the clock divider 102 to mitigate gain and INL errors introduced by the DTC 204 into the clk_out. In some examples, the calibration circuit 104 also corrects mismatch errors in the DTC 204, such as via a LUT, as described above.

[0034] 3 is a block diagram of a clock divider 102 with a calibration circuit 104 according to various examples. The clock divider 102 and the calibration circuit 104 are coupled and operated as described above with reference to FIG. 2, and the description will not be repeated with reference to FIG. 3. In some examples, the calibration circuit 104 includes a calibration phase-locked loop (PLL) 302, a correlation circuit 304, a filter and accumulation circuit 306, an INL compensation circuit 308, and a gain compensation circuit 310. The calibration PLL 302 has an input coupled to the output of the DTC 204 and an output. The correlation circuit 304 has a first input coupled to the output of the calibration PLL 302, a second input coupled to the second output of the delta-sigma modulator 206, a first output, and a second output. The filter and accumulate circuit 306 has a first input coupled to the first output of the correlation circuit 304, a second input coupled to the second output of the correlation circuit 304, a first output, and a second output. The INL compensation circuit 308 has a first input coupled to the output of the MM divider 202, a second input coupled to the second output of the delta-sigma modulator 206, a third input coupled to the second output of the filter and accumulate circuit 306, and an output coupled to the second input of the DTC 204. In some examples, the coupling between the output of the INL compensation circuit 308 and the second input of the DTC 204 replaces the coupling between the second output of the delta-sigma modulator 206 and the second input of the DTC 204 described above with reference to FIG. 2. The gain compensation circuit 310 has an input coupled to the first output of the filter and accumulate circuit 306 and an output coupled to the third input of the DTC 204. In some examples, a LUT (not shown) is coupled between the second output of the delta-sigma modulator 206 and the DTC 204 to correct for mismatch errors in the DTC.

[0035] In one example of operation, the calibration PLL 302 receives clk_out and determines a phase error signal, shown as PDcal in FIG. 3, based on clk_out. PDcal provides the instantaneous phase error of clk_out to the correlation circuit 304, which performs a correlation based on PDcal, Res, and basis functions of gain error and INL error. Depending on the application, PDcal indicates whether the phase error is positive or negative and may be determined, for example, by a bang-bang phase detector (not shown) or any other suitable component. PDcal is then correlated with the signal based on Res and the basis functions. For example, Res is mapped by the correlation circuit 304 according to one or more basis functions, and the resulting signal may be filtered and may have an offset applied. In some examples, this filtering is essentially high pass. In some examples, filtering and application of offsets are optional and either may be omitted. Correlation is then performed by the correlation circuit 304, which first multiplies PDcal with a signal created by mapping Res according to one or more basis functions, and then filters by the correlation filter of the correlation circuit 304 to obtain a correlated error value. For example, based on this correlation, the correlation circuit 304 provides a gain correlated error value (Corr_gain) and an INL correlated error value (Corr_INL). The filter and accumulation circuit 306 receives the gain correlated error value and the INL correlated error value and determines a gain adjustment value (Gain_adj) and an INL adjustment value (INL_adj). The filter and accumulation circuit 306 provides Gain_adj to the DTC 204 and provides INL_adj to the INL compensation circuit 308. In some examples, Gain_adj is provided to a delta-sigma digital-to-analog converter (DAC) (not shown) of the gain compensation circuit 310 to control the DTC 204 to correct the determined gain error. For example, the resistance, current, voltage, or capacitance of the DTC 204 may be modified according to Gain_adj to correct the determined gain error.The INL compensation circuit 308 receives clk_div (e.g., for clocking the INL compensation circuit 308), Res, and INL_adj, and determines a compensated residual error signal based thereon. In some examples, the INL compensation circuit 308 includes an adder that adds INL_adj to Res to determine the compensated residual error signal. The INL compensation circuit 308 may also include registers that store data related to determining the compensated residual error signal, and these registers may be clocked by clk_div. The compensated residual error signal may be determined by the INL compensation circuit 308 based on the input signal it receives, via a calculation (e.g., via an adder, as described above), a LUT, or both. The INL compensation circuit 308 provides the compensated residual error signal to the DTC 204. In other examples, the addition of INL_adj and Res is performed within the DTC 204, such that the INL compensation circuit 308 is omitted, and the DTC 204 directly receives INL_adj instead of the compensated residual error signal. Based on the compensated residual error signal and Gain_adj, the DTC 204 applies compensation to the determination and provision of clk_out to reduce the effect of gain and / or INL errors of the DTC 204 on the value of clk_out.

[0036] 4 is a block diagram of the calibration PLL 302 according to various examples. In some examples, the calibration PLL 302 includes a linear phase detector (PD) 402, a loop filter 404, a bang-bang phase detector (BB PD) 408, a tuning control circuit 410, a voltage controlled oscillator (VCO) 412, and a divider 414. In some examples, the linear PD 402 has a first input configured to receive clk_out (e.g., coupled to an output of the DTC 204 to receive clk_out), a second input, and an output. The loop filter 404 has an input coupled to an output of the linear PD 402, and an output. The BB PD 408 has a first input configured to receive clk_out (e.g., coupled to an output of the DTC 204 to receive clk_out), a second input, and an output. The BB PD 408 provides PDcal at its output. The tuning control circuit 410, which may be omitted in some implementations, has an input coupled to the output of the BB PD 408 and an output. The VCO 412 has an output and has an input coupled to the output of the loop filter 404 or the tuning control circuit 410, which may include analog circuitry and / or digital logic. The frequency divider 414 has an input coupled to the output of the VCO 412 and an output coupled to the second input of the linear PD 402 (if not omitted) and the second input of the BB PD 408. The frequency divider 414 provides a frequency divider output signal at its output, shown as Div Out in FIG. 4.

[0037] In one example of operation, the linear PD 402 provides a frequency lock between clk_out and Div Out to maintain a linear relationship between them during steady-state operation of the calibration PLL 302. The output signal of the linear PD 402 is filtered by the loop filter 404 and provided to the VCO 412. The BB PD 408 shifts the phase of Div Out such that the BB PD 408 switches between a positive phase error value and a negative phase error value during steady-state operation. Thus, the BB PD 408 provides a PDcal that indicates whether the phase error of clk_out is negative or positive with respect to Div Out. For example, a first value of PDcal indicates that the phase error of clk_out is positive, and a second value of PDcal indicates that the phase error of clk_out is negative. Thus, the PDcal alternates between two output values ​​that have approximately equal probability of occurrence during steady-state operation of the calibration PLL 302. For example, if PDcal indicates that the phase of clk_out is negative more frequently, tuning control circuit 410 sends a correction signal to VCO 412 to shift the phase of VCO 412, which is combined with the output of loop filter 404 so that PDcal has approximately equal probability of negative and positive values. Similar functionality is performed if PDcal indicates that the phase of clk_out is positive more frequently. Divider 414 divides the output signal of VCO 412 by a programmed value to provide Div Out at the same frequency as clk_out while facilitating operation of VCO 412 at a frequency within the operating limits of VCO 412.

[0038] 5 is a block diagram of the calibration PLL 302 according to various examples. In some examples, the calibration PLL 302 includes a linear PD 502, a loop filter 504, a BB PD 506, a tuning control circuit 508, a VCO 510, and a divider 512. In some examples, the linear PD 502 includes a d flip-flop 514, a d flip-flop 516, an AND gate 518, and a delay circuit 520. The loop filter 504 includes a resistor 522, an inverter 524, a resistor 526, a capacitor 528, a resistor 530, and a capacitor 532. The VCO 510 includes a varactor 534 and a varactor 536. In some examples, the d flip-flop 514 has a data input that receives a logic 1 value, a clock input that receives clk_out, a reset input, and an output. D flip-flop 516 has a data input receiving a logic one value, a clock input receiving Div Out, a reset input, and an output. AND gate 518 has a first input coupled to the output of d flip-flop 514, a second input coupled to the output of d flip-flop 516, and an output. Delay circuit 520 has an input coupled to the output of AND gate 518 and an output coupled to the reset inputs of d flip-flop 514 and d flip-flop 516. Resistor 522 is coupled between the output of d flip-flop 514 and node 540. Inverter 524 has an input coupled to the output of d flip-flop 516 and an output coupled to node 540 via resistor 526. Capacitor 528 is coupled between node 540 and a ground voltage potential. Resistor 530 is coupled between node 540 and node 542. Capacitor 532 is coupled between node 542 and a ground voltage potential. Varactor 534 has an input coupled to node 542 and an output. Varactor 536 has an input coupled to the output of tuning control circuit 508 and an output. The output signals provided at the respective outputs of varactor 534 and varactor 536 are summed to provide a signal, shown in FIG. 5 as Fvco, having a frequency determined based on the capacitance of varactor 534 and varactor 536.The linear PD 502 and loop filter 504 enable the phase and frequency of Div Out to be locked to clk_out according to linear dynamics, while the BB PD 506 and tuning control circuit 508 provide phase alignment of clk_out and Div Out so that PDcal alternates between two output values ​​that have approximately equal probability of occurrence during steady-state operation, as described above.

[0039] 6 is a block diagram of the calibration PLL 302 according to various examples. In some examples, the calibration PLL includes a linear PD 602, a loop filter 604, a BB PD 606, a BB control circuit 608, a digital delta-sigma DAC 610, a DAC and filter circuit 612, a VCO 614, and a frequency divider 616. In some examples, the VCO 614 is substantially similar to the VCO 510 of FIG. 5, and the description thereof will not be repeated here with reference to FIG. 6. In some examples, the linear PD 602, the loop filter 604, the BB PD 606, and the frequency divider 616 are substantially similar to the linear PD 402, the loop filter 404, the BB PD 408, and the frequency divider 414 described above with reference to FIG. 4, and the description thereof will not be repeated here with reference to FIG. 6. The BB control circuit 608 has an input coupled to the output of the BB PD 606 and an output. The digital delta-sigma modulator 610 has an input coupled to the output of the BB control circuit 608 and an output. The DAC and filter circuit 612 has an input coupled to the output of the digital delta-sigma modulator 610 and an output coupled to the VCO 614.

[0040] In one example of operation, the BB control circuit 608 provides a BB tuning signal based on a PDcal as provided by the BB PD 606. The BB control circuit 608 may provide the BB tuning signal according to any suitable processing, such as via a decimator, an accumulator, a gear shift, etc. The digital delta-sigma modulator 610 and the DAC and filter circuit 612 convert the BB tuning signal from a digital format or domain to an analog signal suitable for controlling the VCO 614. In some examples, the DAC and filter circuit 612 may be omitted and the VCO 614 may include an array of capacitors (not shown) coupled to the digital delta-sigma modulator 610 to achieve a more digital implementation for providing the BB tuning signal.

[0041] FIG. 7 is a block diagram of a calibration PLL 302 according to various examples. In some examples, the calibration PLL 302 of FIG. 7 includes elements of the calibration PLL 302 of FIG. 6 and is labeled accordingly. The description of these components will not be repeated here with reference to FIG. 7. The calibration PLL 302 also includes a measurement circuit 702 and a frequency control circuit 704. The measurement circuit 702 has a first input configured to receive clk_out, a second input coupled to the output of the frequency divider 616, and an output. The frequency control circuit 704 has an input coupled to the output of the measurement circuit 702 and an output coupled to the input of the DAC and filter circuit 612. The measurement circuit 702 and the frequency control circuit 704 form an auxiliary frequency control path that increases the frequency tuning range of the VCO 614. In some examples, the DAC and filter circuit 612 may be omitted and the VCO 614 may include an array of capacitors coupled to the digital delta-sigma modulator 610 and the frequency control circuit 704 to achieve a more digital implementation for providing the BB tuning signal and auxiliary frequency control path.

[0042] FIG. 8 is a block diagram of the calibration PLL 302 according to various examples. In some examples, the calibration PLL 302 of FIG. 8 includes elements of the calibration PLL 302 of FIG. 7 and is labeled accordingly. The description of these components will not be repeated here with reference to FIG. 8. The calibration PLL 302 also includes a division value selection circuit 802. The division value selection circuit 802 has a first input coupled to an input of the DAC and filter circuit 612, a second input configured to receive an enable signal, and an output coupled to the divider 616. In some examples, the division value selection circuit 802 selects a value by which the divider 616 divides the output signal of the VCO 614 so that the BB tuning signal is kept within the programmed limits of the VCO 614 to achieve proper operation, for example, for frequency control of the VCO 614.

[0043] FIG. 9 is a block diagram of a calibration PLL 302 according to various examples. In some examples, the calibration PLL 302 of FIG. 9 includes some of the elements of the calibration PLL 302 of FIG. 7 and is labeled accordingly. The description of these components will not be repeated here with reference to FIG. 9. The calibration circuit 302 includes a plurality of VCOs 902, each of which may be coupled as the VCO 614. In some examples, a VCO of the VCOs 902 operating at a lowest frequency suitable for a particular application of the calibration PLL 302 may provide a VCO output signal, thereby reducing the power consumption of the calibration PLL 302 compared to other examples such as those of FIG. 6-FIG. 9.

[0044] 10 is a block diagram of a PLL 1000 including a clock divider 102 with a calibration circuit 104 according to various examples. In some examples, the PLL 1000 includes the clock divider 102 in its closed loop feedback to perform frequency multiplication from F_ref to F_vco according to Div Val. In some examples, the PLL 1000 includes a detector 1002, a VCO 1006, a divider 1008, a MM divider 1010, a DTC 1012, and a delta-sigma modulator 1014. In some examples, the PLL 1000 of FIG. 10 may provide filtering of jitter introduced by the DTC 1012 via the detector 1002 that is not provided by the clock divider 102 of FIG. 2 described herein above.

[0045] In an example implementation, the detector 1002 has a first input configured to receive a reference signal F_ref, a second input, a first output, and a second output. The VCO 1006 has an input coupled to the first output of the detector 1002, and an output. The divider 1008 has an input coupled to the output of the VCO 1006, and an output where the divider 1008 is configured to provide clk_out. In some implementations, in examples where a high output signal frequency is provided by the PLL 1000, the divider 1008 may be omitted. In some examples, the divider 1008 may include multiple dividers to create multiple output signals, which may be signals at different frequencies. The MM divider 1010 has a first input coupled to the output of the VCO 1006, a second input, and an output. The DTC 1012 has a first input coupled to the output of the MM divider 1010, a second input, a third input, and an output coupled to the second input of the detector 1002. The delta-sigma modulator 1014 has an input coupled to the output of the MM divider 1010, a first output coupled to the second input of the MM divider 1010, and a second output. The calibration circuit 104 has a first input coupled to the second output of the detector 1002, a second input coupled to the second output of the delta-sigma modulator 1014, and an output coupled to the DTC 1012.

[0046] In one example of the operation of the PLL 1000, the detector 1002 compares the output of the DTC 1012, shown as clk_out in FIG. 10, to F_ref. Based on this comparison, the detector 1002 provides PDcal to the calibration circuit 104 and provides a control signal, shown as Vctrl in FIG. 10, that is provided to the VCO 1006 to achieve phase lock at steady state. The frequency of the output signal of the VCO 1006 is determined by the frequency of F_ref multiplied by Div Val. Fvco as provided by the VCO 1006 may be provided directly as an output of the PLL 1000 or may be divided by the divider 1008 to one or more frequencies. Alternatively, the PLL 1000 may omit the calibration PLL and provide filtering of high frequency noise introduced by the DTC 1012.

[0047] The MM divider 1010 receives the output of the VCO 1006 and N from the delta-sigma modulator 1014 and provides a divided clock signal, shown as clk_div in FIG. 10, based thereon. The DTC 1012 receives clk_div and a calibration signal and provides clk_out based thereon. The calibration circuit 104 receives PDcal from the detector 1002 and Res from the delta-sigma modulator 1014 and based thereon performs correlation according to basis functions, each of which is a function of Res, as described herein above, to determine and provide a calibration signal. Based on the calibration signal, the DTC 1012 applies compensation to the determination and provision of clk_out to reduce the effect of gain and / or INL errors of the DTC 1012 on the value of clk_out. In some examples, the PLL 1000 continuously adjusts the calibration signal provided by the calibration circuit 104 so that the correlation values ​​determined by the compensation circuit for the gain and INL errors of the DTC 1012 converge to zero on average.

[0048] Figure 11 is a block diagram of a PLL 1000 with a calibration circuit 104, in accordance with various examples. The PLL 1000 is coupled and operated as described above with reference to Figure 10, and some of the description will not be repeated with reference to Figure 11. In some examples, the calibration circuit 104 includes a correlation circuit 1016, a filter and accumulation circuit 1018, an INL compensation circuit 1020, and a gain compensation circuit 1022.

[0049] In an example implementation, detector 1002 has a first input configured to receive F_ref, a second input, a first output, and a second output. VCO 1006 has an input coupled to the first output of detector 1002 and an output. Divider 1008 has an input coupled to the output of VCO 1006 and an output configured for divider 1008 to provide clk_out. In another example, divider 1008 is omitted since Fvco is provided as clk_out. MM divider 1010 has a first input coupled to the output of VCO 1006, a second input, and an output. DTC 1012 has a first input coupled to the output of MM divider 1010, a second input, a third input, and an output coupled to the second input of detector 1002. The delta-sigma modulator 1014 has an input coupled to the output of the MM divider 1010, a first output coupled to a second input of the MM divider 1010, and a second output. The correlation circuit 1016 has a first input coupled to the second output of the detector 1002, a second input coupled to the second output of the delta-sigma modulator 1014, a first output, and a second output. The filter and accumulate circuit 1018 has a first input coupled to the first output of the correlation circuit 1016, a second input coupled to the second output of the correlation circuit 1016, a first output, and a second output. The INL compensation circuit 1020 has a first input coupled to the second output of the delta-sigma modulator 1014, a second input coupled to the second output of the filter and accumulate circuit 1018, and an output coupled to a third input of the DTC 1012. The gain compensation circuit 1022 has an input coupled to a first output of the filter and accumulation circuit 1018 and an output coupled to a second input of the DTC 1012. In some examples, the gain compensation circuit 1022 functions substantially similarly to the gain compensation circuit 310 of FIG. 3, and such description will not be repeated here again with reference to FIG.

[0050] In one example of the operation of the PLL 1000, the detector 1002 compares the output of the DTC 1012, shown in FIG. 11 as clk_out, to a reference signal, shown in FIG. 11 as F_ref. Based on this comparison, the detector 1002 provides PDcal to the correlation circuit 1016 and provides a control signal, shown in FIG. 11 as Vctrl, to the VCO 1006. The frequency Fvco is determined by the frequency F_ref multiplied by the division value of the divider 1008, which is determined by a programmed value. Out as provided by the VCO 1006 may be provided directly as an output of the PLL 1000 or may be divided by the divider 1008 to one or more frequencies. Alternatively, the PLL 1000 may omit the calibration PLL and provide filtering of high frequency noise introduced by the DTC 1012.

[0051] The MM divider 1010 receives Fvco and N from the delta-sigma modulator 1014 and provides a divided clock signal, shown as clk_div in FIG. 11, based on the above. The DTC 1012 receives clk_div, the compensated residual error signal, and Gain_adj and provides clk_out based on the above. The correlation circuit 1016 receives PDcal from the detector 1002 and Res from the delta-sigma DAC 1014 and performs correlation according to basis functions, each of which is a function of Res, as described above in this specification, to determine and provide correlation values ​​for gain and INL, shown as Corr_gain and Corr_INL in FIG. 11, respectively. The filter and accumulate circuit 1018 receives Corr_gain and Corr_INL and determines gain and INL adjustment values, shown as INL_adj and Gain_adj in FIG. 11, based on the above. The INL compensation circuit 1020 receives Res and INL_adj and, based thereon, determines and provides a compensated residual error signal to the DTC 1012. Based on the compensated residual error signal and Gain_adj, the DTC 1012 applies compensation to the determination and provision of clk_out to reduce the effect of the gain error and / or INL error of the DTC 1012 on the value of clk_out. For example, the DTC 1012 may convert Gain_adj from a digital value to an analog value via a delta-sigma DAC (not shown) and may control the resistance, current, voltage, or capacitance of the DTC 1012 to correct the determined gain error based on the resulting analog value provided by the delta-sigma DAC. In some examples, the PLL 1000 continuously adjusts the calibration signal provided by the calibration circuit 104 such that a correlation value determined by the compensation circuit to the gain error and INL error of the DTC 1012 converges to zero on average. In some examples, a LUT (not shown) is coupled between the second output of the delta-sigma modulator 1014 and the DTC 1012 to correct mismatch errors in the DTC 1012.

[0052] 12 is a block diagram of a detector 1002 according to various examples. In some examples, the detector 1002 includes a linear PD 1202, a loop filter 1204, a BB PD 1208, and a tuning control circuit 1210. In some examples, the linear PD 1202, the loop filter 1204, the BB PD 1208, and the tuning control circuit 1210 are combined and operate substantially similarly to the linear PD 402, the loop filter 404, the BB PD 408, and the tuning control circuit 410 described above with reference to FIG. 4, with the signal Div Out of FIG. 4 being replaced by the signal Div of FIG. 12. Therefore, the description of these components will not be repeated here with reference to FIG. 12.

[0053] FIG. 13 is a block diagram of a detector 1002 according to various examples. In some examples, the detector 1002 includes a linear PD 1302, a loop filter 1304, an offset delay circuit 1306, and a BB PD 1308. The linear PD 1302 has a first input configured to receive F_ref, a second input configured to receive Div, and an output. The loop filter 1304 has a first input coupled to the output of the linear PD 1302, and an output to which Vctrl is provided. The offset delay circuit 1306 has a first input configured to receive Div, a second input configured to receive an offset calibration signal, and an output. The BB PD 1308 has a first input configured to receive F_ref, a second input coupled to the output of the offset delay circuit 1306, and an output to which PDcal is provided.

[0054] In one example of operation, the linear PD 1302 provides a phase lock between F_ref and Div and maintains a steady-state phase error between F_ref and Div according to the characteristics (including mismatch) of the detector 1002. The output signal of the linear PD 1302 is filtered by the loop filter 1304 and provided as Vctrl. The offset delay circuit 1306 delays Div according to an offset calibration signal that may be received from a control circuit (not shown) that monitors PDcal and shifts the phase of Div, so that the probability of negative and positive values ​​of PDcal eventually becomes approximately equal during steady-state operation of the detector 1002. Based on this shift, the BB PD 1308 provides a PDcal that indicates whether the instantaneous phase of F_ref is negative or positive with respect to the delayed Div. For example, a first value of PDcal indicates that the phase of F_ref is negative, and a second value of PDcal indicates that the phase of F_ref is positive.

[0055] 14 is a block diagram of a detector 1002 according to various examples. In some examples, the detector 1002 includes a linear PD 1402, a loop filter 1404, and an analog-to-digital converter (ADC) 1406. The linear PD 1402 has a first input configured to receive F_ref, a second input configured to receive Div, and an output. The loop filter 1404 has a first input coupled to the output of the linear PD 1402, a first output to which Vctrl is provided, and a second output. The ADC 1406 has a first input coupled to the second output of the loop filter 1404, a second input configured to receive an offset calibration signal, and an output to which PDcal is provided.

[0056] 15 is a timing diagram 1500 of signals in clock divider 102, in accordance with various examples. Timing diagram 1500 shows clk_ref, clk_div, and clk_out, as described herein above. As diagram 1500 shows, clk_div can have periods of different duration (e.g., jitter) that are corrected by DTC controlled by Res and the described error correction techniques in forming clk_out.

[0057] 16 is a diagram 1600 of basis functions that are computationally less complex to implement, according to various examples. Diagram 1600 shows gain basis functions 1605 and INL basis functions 1610. In some examples, gain basis functions 1605 and INL basis functions 1610 are orthogonal and each have a zero mean. In other examples, basis functions 1605 and 1610 may be non-orthogonal and / or non-zero mean components may be introduced.

[0058] 17 is a diagram 1700 of expanded basis functions, in accordance with various examples. Diagram 1700 shows gain basis function 1705, fundamental INL basis function 1710, and second harmonic INL basis function 1715. In some examples, gain basis function 1705, fundamental INL basis function 1710, and second harmonic INL basis function 1715 are orthogonal and each have a zero mean. In other examples, basis function 1705, basis function 1710, and basis function 1715 may be non-orthogonal and / or non-zero mean components may be introduced.

[0059] FIG. 18 is a diagram 1800 of simplified basis functions, according to various examples. Diagram 1800 illustrates gain basis functions 1805 and INL basis functions 1810. In some examples, gain basis functions 1805 and INL basis functions 1810 are orthogonal and each have a zero mean. In other examples, basis functions 1805 and 1810 may be non-orthogonal and / or non-zero mean components may be introduced. In some examples, the simplified basis functions are computationally simpler (e.g., require less computational complexity and / or power) than the basis functions of FIG. 16 and / or FIG. 17. In other examples, more complex basis functions may be useful, such as when the increased performance resulting from the more complex basis functions is worth the increased computational complexity and / or power associated with computing the more complex basis functions.

[0060] 19 is a transient simulation 1900 of gain and INL correction in a clock divider, in accordance with various examples. In some examples, the clock divider is clock divider 102 as described herein above. The transient simulation 1900 shows PDcal, Gain_adj, and INL_adj.

[0061] FIG. 20A is a phase noise spectrum 2000 of clk_out with INL cancellation disabled, according to various examples. In some examples, clk_out is provided by a clock divider 102 as described herein above. As shown in FIG. 20A, the left vertical axis represents the spectral density (L(f)) in units of decibels relative to carrier (dBc) per Hertz (Hz), the right vertical axis represents dBc, and the horizontal axis represents the frequency offset from the carrier frequency in units of megahertz (MHz). As the phase noise spectrum 2000 shows, in some examples of clock dividers with INL cancellation disabled, a spur having a magnitude, in this example about -39 dBc, may be present at a carrier frequency of about 156 MHz.

[0062] FIG. 20B is a phase noise spectrum 2005 of clk_out with INL cancellation enabled, according to various examples. In some examples, clk_out is provided by clock divider 102 as described herein above. The axis unit description of FIG. 20B may be the same as that of FIG. 20A. As shown by the phase noise spectrum 2005, in some examples of clock divider with INL cancellation enabled, the spurs shown in FIG. 20A are reduced, with this example showing a reduction from a value of about -39 dBc to a value of about -80 dBc.

[0063] The term "couple" is used throughout this specification. This term may encompass a connection, communication, or signal path that enables a functional relationship consistent with this description. For example, in a first example, device A is coupled to device B when device A provides a signal to control device B to perform an operation, or in a second example, device A is coupled to device B through an intervening component C, in which case the intervening component C does not substantially change the functional relationship between device A and device B, such that device B is controlled by device A through a control signal provided by device A.

[0064] A device that is "configured" to perform a certain task or function may be configured (e.g., programmed and / or wired) to perform that function by a manufacturer at the time of manufacture and / or may be configurable (or reconfigurable) by a user after manufacture to perform that function and / or other additional or alternative functions. Such configuration may be achieved by firmware and / or software programming of the device, by the construction and / or layout of the hardware components and interconnections of the device, or by a combination of these.

[0065] A circuit or device described herein as including certain components may instead be adapted to be coupled to those components to form the described circuit element or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be adapted to be coupled to some of the passive elements and / or sources to form the described structure, either during or after manufacture, e.g., by an end user and / or a third party.

[0066] Although certain components may be described herein as being of a particular process technology, these components may be replaced with components of other process technologies. Circuits described herein are reconfigurable to include such replaced components to provide functionality at least partially similar to that available prior to the replacement of the components. Components illustrated as resistors generally represent any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the illustrated resistor, unless otherwise noted. For example, a resistor or capacitor illustrated and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor illustrated and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as the single resistor or capacitor.

[0067] The phrase "ground potential" in the preceding description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable or suitable to the teachings of the present description. Unless otherwise specified, "about," "approximately," or "substantially" preceding a value means ±10 percent of the stated value. Modifications in the described examples are possible, and other examples are possible, within the scope of the claims.

Claims

1. 1. A circuit comprising: a multi-modulus (MM) divider having a first input configured to receive an input clock signal, a second input, and an output; a delta-sigma modulator having a first input configured to receive a division value, a second input coupled to an output of the MM divider, a first output coupled to the second input of the MM divider, and a second output; a digital-to-time converter (DTC) having a first input coupled to an output of the MM divider, a second input coupled to a second output of the delta-sigma modulator, a third input, and an output; a calibration circuit having a first input coupled to an output of the DTC, a second input coupled to a second output of the delta-sigma modulator, and an output coupled to a third input of the DTC; The circuit includes:

2. 2. The circuit of claim 1, The calibration circuitry comprises: a correlation circuit having a first input configured to receive a phase error signal, a second input coupled to a second output of the delta-sigma modulator, a first output, and a second output; a feedback control circuit having a first input coupled to a first output of the correlation circuit, a second input coupled to a second output of the correlation circuit, a first output, and a second output; a parametric integral nonlinearity (INL) compensation circuit having a first input coupled to an output of the MM divider, a second input coupled to a second output of the delta-sigma modulator, a third input coupled to a second output of the feedback control circuit, and an output coupled to a second input of the DTC; a gain compensation circuit having an input coupled to a first output of the feedback control circuit and an output coupled to a third input of the DTC; The circuit includes:

3. 3. The circuit of claim 2, the calibration circuit further includes a calibration phase-locked loop (PLL) having an input coupled to an output of the DTC and an output coupled to a first input of the correlation circuit and configured to provide the phase error signal; The calibration PLL a linear phase detector (PD) having a first input coupled to an output of the DTC, a second input, and an output; a loop filter having an input coupled to an output of the linear PD and an output; a bang-bang PD having a first input coupled to an output of the DTC, a second input, and an output coupled to a first input of the correlation circuit; a tuning control circuit having an input coupled to the output of the Bang-Bang PD, and an output; a voltage controlled oscillator (VCO) having an input coupled to an output of the loop filter and an output of the tuning control circuit, and an output; a frequency divider having an input coupled to an output of the VCO and an output coupled to a second input of the linear PD and a second input of the bang-bang PD; The circuit includes:

4. 2. The circuit of claim 1, a detector circuit having a first input configured to receive a reference signal, a second input coupled to an output of the DTC, a first output, and a second output; a voltage controlled oscillator (VCO) having an input coupled to the second output of the detector circuit and an output coupled to the first input of the MM divider; The circuit further comprises:

5. 5. A circuit according to claim 4, comprising: The calibration circuitry comprises: a correlation circuit having a first input coupled to the first output of the detector circuit, a second input coupled to the second output of the delta-sigma modulator, a first output, and a second output; a feedback control circuit having a first input coupled to a first output of the correlation circuit, a second input coupled to a second output of the correlation circuit, a first output, and a second output; a parametric integral nonlinearity (INL) compensation circuit having a first input coupled to an output of the MM divider, a second input coupled to a second output of the delta-sigma modulator, a third input coupled to a second output of the feedback control circuit, and an output coupled to a third input of the DTC; a gain compensation circuit having an input coupled to a first output of the feedback control circuit and an output coupled to a third input of the DTC; The circuit includes:

6. 6. The circuit of claim 5, The detector circuit comprises: a linear phase detector (PD) having a first input configured to receive the reference signal, a second input coupled to an output of the DTC, and an output; a loop filter having an input coupled to an output of the linear PD and an output coupled to an input of the VCO; a bang-bang PD having a first input configured to receive the reference signal, a second input coupled to an output of the DTC, and an output coupled to a first input of the correlation circuit; a tuning control circuit having an input coupled to an output of the bang-bang PD and an output coupled to an input of the VCO; The circuit includes:

7. 5. A circuit according to claim 4, comprising: The calibration circuitry comprises: comparing a signal from an output of the DTC to the reference signal to determine a phase error signal; correlating the phase error signal with a basis function of a residual error of the delta-sigma modulator to determine a correlation value; controlling a gain and a parametric integral nonlinearity (INL) adjustment of the DTC based on the correlation to converge the correlation value to zero mean; The circuit is configured as follows.

8. 2. The circuit of claim 1, The calibration circuitry comprises: comparing the signal at the output of the DTC to a second clock signal to determine a phase error signal; correlating the phase error signal with a basis function of a residual error of the delta-sigma modulator to determine a correlation value; controlling a gain and a parametric integral nonlinearity (INL) adjustment of the DTC based on the correlation to converge the correlation value to zero mean; The circuit is configured as follows.

9. 1. A circuit comprising: a clock divider including a digital-to-time converter (DTC); a calibration circuit coupled to the clock divider, determining a gain error and a parametric integral nonlinearity (INL) error of the DTC; determining a gain adjustment value and an INL adjustment value to compensate for the gain error and the INL error; modifying operation of the DTC according to the gain adjustment value and the INL adjustment value to correct the gain error and the INL error; The calibration circuit is configured to The circuit includes:

10. 10. The circuit of claim 9, The calibration circuitry comprises: comparing the output signal of the DTC with a reference signal to determine a phase error signal; correlating the phase error signal with a basis function of a residual error of a delta-sigma modulator of the clock divider to determine a correlation value; determining the gain adjustment value and the INL adjustment value based on the correlation value to converge the correlation value to zero mean; The circuitry is further configured to determine a gain error and an INL error of the DCT by:

11. 11. The circuit of claim 10, The circuit, wherein the calibration circuit includes a bang-bang phase detector configured to compare the reference signal with an output signal of the DTC to determine the phase error signal.

12. 11. The circuit of claim 10, The circuit, wherein the basis functions include at least one basis function for the phase error and at least one basis function for the INL error.

13. 13. The circuit of claim 12, The circuit, wherein the basis functions have zero DC component.

14. 13. The circuit of claim 12, The circuit, wherein the basis functions include a first basis function for a fundamental frequency and a second basis function for a second harmonic frequency.

15. 11. The circuit of claim 10, The circuit, wherein the calibration circuit is further configured to filter the basis functions before performing the correlation.

16. 10. The circuit of claim 9, The circuit, wherein the calibration circuit is further configured to correct mismatch errors of the DTC according to a lookup table.

17. 1. A system comprising: a controller configured to provide a control signal; a clock divider coupled to the controller, the clock divider including a digital-to-time converter (DTC) configured to modify a clock signal according to the control signal; a calibration circuit coupled to the clock divider, determining a gain error and a parametric integral nonlinearity (INL) error of the DTC; determining a gain adjustment value and an INL adjustment value to compensate for the gain error and the INL error; modifying operation of the DTC according to the gain adjustment value and the INL adjustment value to correct the gain error and the INL error; The calibration circuit is configured to a component coupled to the clock divider, the component configured to receive the modified clock signal from the clock divider and operate according to the modified clock signal; Including, the system.

18. 20. The system of claim 17, The calibration circuitry comprises: comparing the output signal of the DTC with a reference signal to determine a phase error signal; correlating the phase error signal with a basis function of a residual error of a delta-sigma modulator of the clock divider to determine a correlation value; determining the gain adjustment value and the INL adjustment value based on the correlation value to converge the correlation value to zero mean; The system is further configured to determine a gain error and an INL error of the DTC by:

19. 20. The system of claim 18, The system, wherein the calibration circuit includes a bang-bang phase detector configured to compare the reference signal with an output signal of the DTC to determine the phase error signal.

20. 20. The system of claim 18, The system, wherein the basis functions are orthogonal to one another, the basis functions including at least one basis function for the phase error and at least one basis function for the INL error.

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