Multi-AD channel verification method, system and equipment suitable for stability control device and medium

Abstract

The invention discloses a multi-AD channel verification method, system, equipment and medium suitable for a stability control device, and the method comprises the steps: carrying out the sampling from a power system through three AD channels, correspondingly obtaining sampling signals, and collecting a test mode signal through a test channel; performing double AD verification, and setting a corresponding abnormal mark as a corresponding normal or abnormal value according to a normal or abnormal result obtained through verification; and performing corresponding multi-AD channel logic operation verification according to the test mode signal and based on the result numerical value of the abnormal mark. By adopting the above technical scheme, through the introduced AD3 channel, on the basis of double-AD channel verification, pairwise verification of three AD channels can be carried out, direct locking of the device due to double AD abnormity is avoided, the fault tolerance of the stability control device is enhanced, and the stability of a power system is improved.

Description

Technical Field

[0001] The present invention relates to the field of power systems and automation technologies thereof, and in particular to a multi-AD channel verification method, system, equipment and medium suitable for a stabilization control device. Background Art

[0002] High-precision data acquisition is required in the power system. Therefore, the safety and stability control devices (hereinafter referred to as "stability control devices") in power grids and other power systems generally adopt dual AD (Analog-to-Digital Conversion) channel sampling. The dual AD channels can realize mutual verification of the two AD channel data, effectively avoiding errors in the single AD channel data, thereby ensuring the accuracy and reliability of the sampled data.

[0003] However, there are also problems with dual AD channel verification. For example, during the actual operation of the stabilization and control device, there may be problems such as sampling errors in an internal AD channel, resulting in abnormal dual AD channel verification results, that is, the difference between the dual AD sampling data is greater than or equal to the dual AD abnormal threshold value. If the stabilization and control device determines that the dual AD channel verification result is abnormal, the stabilization and control device will immediately execute protection measures such as locking logic function, tripping exit and exiting system operation.

[0004] Therefore, although the data sampling of the dual AD channels can ensure the accuracy of the data, if the sampling data of any AD channel is wrong and the dual AD channel verification result is abnormal, the stabilization and control device will immediately lock the logic function, trip the output, and exit the system operation, thereby affecting the continuous, safe and stable operation of the power system. Summary of the invention

[0005] Purpose of the invention: The present invention provides a multi-AD channel verification method, system, device and medium suitable for a stabilization control device, aiming to solve the technical problem in the prior art that if the sampling data of any one of the dual AD channels is erroneous, the dual AD channel verification result may be abnormal.

[0006] Technical solution: The present invention is a multi-AD channel verification method suitable for a stabilization control device, comprising: using AD1 channel, AD2 channel and AD3 channel to sample from the power system respectively, the corresponding sampling signals obtained are AD1 signal, AD2 signal and AD3 signal, and using the test channel to collect the test mode signal; performing double AD verification on the following AD signal groups, and setting the corresponding abnormal flag to the corresponding normal or abnormal value according to the normal or abnormal result obtained by the verification: AD1 signal and AD2 signal, the corresponding abnormal flag is channel 12 flag; AD2 signal and AD3 signal, the corresponding abnormal flag is channel 23 flag; AD1 signal and AD3 signal, the corresponding abnormal flag is channel 13 flag; according to the test mode signal, performing the following corresponding AD channel logic operation verification:

[0007] When the test mode signal is the zeroth signal, the following AD channel logic operation check is performed:

[0008] Mode0_Bs=Chn12_Flag,

[0009] Among them, Mode0_Bs represents the zeroth signal check result, and Chn12_Flag represents the channel 12 flag; if the value of the zeroth signal check result corresponds to normal, it is determined that the sampling of any channel of the AD1 channel and the AD2 channel is normal;

[0010] When the test mode signal is the first signal, the following AD channel logic operation check is performed:

[0011] Mode1_Bs=((Chn12_Flag)OR(Chn23_Flag)OR(Chn13_Flag)),

[0012] Among them, Mode1_Bs represents the first signal verification result, Chn23_Flag and Chn13_Flag represent channel 23 flag and channel 13 flag respectively; if the value of the first signal verification result corresponds to normal, it is determined that the sampling of any channel in the dual AD channels corresponding to the abnormal flag whose value corresponds to normal is normal.

[0013] Specifically, the double AD check is performed on the following AD signal group, and the normal or abnormal result obtained by the check includes: calculating the difference between the sampling signals of the two AD channels, if the difference is less than the standard deviation value, the check result is normal; if the difference is greater than or equal to the standard deviation value, and the duration is greater than or equal to the standard deviation time, the check result is abnormal.

[0014] Specifically, when the test mode signal is the second signal, the following AD channel logic operation check is performed:

[0015] Mode2_Bs=(((Chn12_Flag)AND(Chn23_Flag))OR((Chn12_Flag)AND(Chn13_Flag))OR((Chn13_Flag)AND(Chn23_Flag))),

[0016] Wherein, Mode2_Bs represents the second signal verification result; if the value of the second signal verification result corresponds to normal, it is determined that the sampling of any channel in the dual AD channels corresponding to the abnormal flag whose value corresponds to normal is normal.

[0017] Specifically, when the test mode signal is the third signal, the following AD channel logic operation check is performed:

[0018] If at the current moment, the difference between any two sampling signals is greater than or equal to the standard deviation value, the corresponding sampling signal is corrected. The correction method is: obtain multiple historical sampling signals at multiple sampling time points pushed back from the current moment, use the multiple historical sampling signals to obtain the corrected sampling signal at the current moment through interpolation calculation, use the corrected sampling signal as the sampling signal at the current moment, and perform the following logical operations based on the sampling signal at the current moment:

[0019] Mode3_Bs=((Chn12_Flag)AND(Chn23_Flag)AND(Chn13_Flag)),

[0020] Mode3_Bs represents the third signal verification result; if the value of the third signal verification result corresponds to normal, it is determined that the sampling of any channel among the three AD channels is normal.

[0021] Specifically, the method of acquiring multiple historical sampling signals at multiple sampling time points pushed back from the current moment, and using the multiple historical sampling signals to obtain the corrected sampling signal at the current moment through interpolation calculation includes:

[0022] The interpolation calculation is performed using the following formula:

[0023] y k =3y k-1 -3y k-2 +y k-3 ,

[0024] Among them, y k Represents the corrected sampling signal at the current moment, y k-1 ,y k-2 and k-3 They represent the historical sampling signals of the first sampling time point, the second sampling time point, and the third sampling time point pushed back from the current time, respectively. k ,y k-1,y k-2 and k-3 The intervals between them are equal.

[0025] Specifically, the abnormal flag has a value of 1 corresponding to a normal state and a value of 0 corresponding to an abnormal state.

[0026] The present invention also provides a multi-AD channel verification system suitable for a stabilization control device, comprising a first analog quantity conversion board, a second analog quantity conversion board and a digital signal processor, wherein: the first analog quantity conversion board is used to use the AD1 channel and the AD2 channel to sample from the power system respectively, and the corresponding sampling signals obtained are the AD1 signal and the AD2 signal, and the sampling signals are sent to the digital signal processor; the second analog quantity conversion board is used to use the AD3 channel to sample from the power system, and the corresponding sampling signal obtained is the AD3 signal, and the test channel is used to collect the test mode signal, and the sampling signal and the test mode signal are sent to the digital signal processor; the digital signal processor is used to perform the following corresponding AD channel logic operation verification according to the test mode signal:

[0027] When the test mode signal is the zeroth signal, the following AD channel logic operation check is performed:

[0028] Mode0_Bs=Chn12_Flag,

[0029] Among them, Mode0_Bs represents the zeroth signal check result, and Chn12_Flag represents the channel 12 flag; if the value of the zeroth signal check result corresponds to normal, it is determined that the sampling of any channel of the AD1 channel and the AD2 channel is normal;

[0030] When the test mode signal is the first signal, the following AD channel logic operation check is performed:

[0031] Mode1_Bs=((Chn12_Flag)OR(Chn23_Flag)OR(Chn13_Flag)),

[0032] Among them, Mode1_Bs represents the first signal verification result, Chn23_Flag and Chn13_Flag represent channel 23 flag and channel 13 flag respectively; if the value of the first signal verification result corresponds to normal, it is determined that the sampling of any channel in the dual AD channels corresponding to the abnormal flag whose value corresponds to normal is normal.

[0033] Specifically, the digital signal processor is further used for:

[0034] When the test mode signal is the second signal, the following AD channel logic operation check is performed:

[0035] Mode2_Bs=(((Chn12_Flag)AND(Chn23_Flag))OR((Chn12_Flag)AND(Chn13_Flag))OR((Chn13_Flag)AND(Chn23_Flag))),

[0036] Wherein, Mode2_Bs represents the second signal verification result; if the value of the second signal verification result corresponds to normal, it is determined that the sampling of any channel in the dual AD channels corresponding to the abnormal flag corresponding to the normal value is normal;

[0037] When the test mode signal is the third signal, the following AD channel logic operation check is performed:

[0038] If at the current moment, the difference between any two sampling signals is greater than or equal to the standard deviation value, the corresponding sampling signal is corrected. The correction method is: obtain multiple historical sampling signals at multiple sampling time points pushed back from the current moment, use the multiple historical sampling signals to obtain the corrected sampling signal at the current moment through interpolation calculation, use the corrected sampling signal as the sampling signal at the current moment, and perform the following logical operations based on the sampling signal at the current moment:

[0039] Mode3_Bs=((Chn12_Flag)AND(Chn23_Flag)AND(Chn13_Flag)),

[0040] Mode3_Bs represents the third signal verification result; if the value of the third signal verification result corresponds to normal, it is determined that the sampling of any channel among the three AD channels is normal.

[0041] The present invention also provides an electronic device, including a memory and a processor, wherein a computer program executable by the processor is stored in the memory, and when the computer program is executed by the processor, any multi-AD channel verification method applicable to a stabilization control device provided by the present invention is executed.

[0042] The present invention also provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of the multi-AD channel verification method applicable to a stabilization control device as described in any one of the items provided by the present invention are implemented.

[0043] Beneficial effect: Compared with the prior art, the present invention has the following significant advantages: by introducing the AD3 channel, on the basis of the dual AD channel verification, it is possible to perform two-by-two verification of the three AD channels with fault-tolerant space, thus avoiding the direct locking device of the dual AD abnormal stabilization control device, enhancing the fault tolerance of the stabilization control device, and improving the stability of the power system. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 A schematic diagram of the principle of a multi-AD channel verification method applicable to a stabilization control device provided by the present invention;

[0045] Figure 2 A schematic diagram of the principle of parabola interpolation calculation provided by the present invention;

[0046] Figure 3 A schematic flow chart of a multi-AD channel calibration method applicable to a stabilization control device provided by the present invention. DETAILED DESCRIPTION

[0047] The technical solution of the present invention is further described below in conjunction with the accompanying drawings.

[0048] See also Figure 3 , which is a flow chart of a multi-AD channel verification method applicable to a stabilization control device provided by the present invention.

[0049] In the embodiment of the present invention, AD1 channel, AD2 channel and AD3 channel are used to sample from the power system respectively, and the corresponding sampling signals obtained are AD1 signal, AD2 signal and AD3 signal, and the test channel (AD4 channel) is used to collect the test mode signal.

[0050] In the specific implementation, the AD channels (AD1 channel, AD2 channel and AD3 channel) convert the PT signal (Potential Transformer) or CT signal (Current Transformer) sampled from the actual operation signal of the power system into a digital signal, that is, the corresponding AD1 signal, AD2 signal and AD3 signal. Compared with the dual AD channel sampling in the prior art, one AD channel is added.

[0051] In an embodiment of the present invention, double AD verification is performed on the following AD signal groups, and according to the normal or abnormal results obtained by the verification, the corresponding abnormal flag is set to the corresponding normal or abnormal value: for AD1 signal and AD2 signal, the corresponding abnormal flag is the channel 12 flag; for AD2 signal and AD3 signal, the corresponding abnormal flag is the channel 23 flag; for AD1 signal and AD3 signal, the corresponding abnormal flag is the channel 13 flag.

[0052] In the embodiment of the present invention, the difference (absolute value of the difference) between the sampling signals of the two AD channels is calculated. If the difference is less than the standard deviation value, the verification result is normal; if the difference is greater than or equal to the standard deviation value and the duration is greater than or equal to the standard deviation time, the verification result is abnormal.

[0053] In the specific implementation, the dual AD abnormal alarm threshold value AD_Ab_Threshold is set (the standard deviation value can be set accordingly according to the actual application scenario), and the absolute values ​​of the difference in sampling signal data between the AD1 channel, AD2 channel and AD3 channel, the three AD channels are: AD_Chn12_Diff (AD1 channel and AD2 channel), AD_Chn23_Diff (AD2 channel and AD3 channel), AD_Chn13_Diff (AD1 channel and AD3 channel).

[0054] In a specific implementation, in the calculation of the dual AD channel check, taking the AD1 channel and the AD2 channel as an example, if AD_Chn12_Diff>=AD_Ab_Threshold, and the duration is greater than or equal to the standard deviation time (which can be set accordingly according to the application scenario), the dual AD abnormal flags corresponding to the AD1 channel and the AD2 channel are set to the corresponding abnormal values, that is, AD_Chn12_Ab_Flag (also Chn12_Flag, Chn23_Flag and Chn13_Flag in the present invention) can be 0, and the corresponding normal value can be 1. The same is true for other dual AD channel checks.

[0055] In the embodiment of the present invention, the following corresponding AD channel logic operation check is performed according to the test mode signal.

[0056] In the embodiment of the present invention, the abnormal flag has a value of 1 corresponding to a normal state and a value of 0 corresponding to an abnormal state.

[0057] In a specific implementation, the user can input a test mode signal to the test channel. When different test mode signals are input, a corresponding multi-AD channel verification method will be performed.

[0058] In the embodiment of the present invention, when the test mode signal (Mode_Set) is the zeroth signal, the following AD channel logic operation check is performed:

[0059] Mode0_Bs=Chn12_Flag,

[0060] Among them, Mode0_Bs represents the zeroth signal verification result, and Chn12_Flag represents the channel 12 flag; if the value of the zeroth signal verification result corresponds to normal, it is determined that the sampling of any channel of the AD1 channel and the AD2 channel is normal.

[0061] In a specific implementation, when the Mode_Set constant is set to the zeroth signal (for example, 0), the value of Mode0_Bs is 1 (corresponding to a normal value), indicating that the result of the dual AD channel verification is normal, the sampling of either the AD1 channel or the AD2 channel is normal, and the sampling signal of either channel can be used as a reference; if the value of Mode0_Bs is 0 (corresponding to an abnormal value), indicating that the result of the dual AD channel verification is abnormal, the sampling signals of neither the AD1 channel nor the AD2 channel can be used as a reference.

[0062] In a specific implementation, when the test mode signal is the zeroth signal, the following AD channel logic operation detection may also be performed:

[0063] Mode0_Ab=Chn12_Flag,

[0064] Among them, Mode0_Ab represents the zeroth signal detection result; if the corresponding value of the zeroth signal verification result is normal, similarly, it is determined that the sampling of any channel in the AD1 channel and the AD2 channel is normal. If the corresponding value of the zeroth signal verification result is abnormal, it can be prompted that the dual AD channels are abnormal, and the stabilization control device can perform safety measures such as locking.

[0065] In the embodiment of the present invention, when the test mode signal (Mode_Set) is the first signal, the following AD channel logic operation check is performed:

[0066] Mode1_Bs=((Chn12_Flag)OR(Chn23_Flag)OR(Chn13_Flag)),

[0067] Among them, Mode1_Bs represents the first signal verification result, Chn23_Flag and Chn13_Flag represent channel 23 flag and channel 13 flag respectively; if the value of the first signal verification result corresponds to normal, it is determined that the sampling of any channel in the dual AD channels corresponding to the abnormal flag whose value corresponds to normal is normal.

[0068] In a specific implementation, when the Mode_Set constant is set to the first signal (for example, Mode_Set=1), the value of Mode1_Bs is 1 (corresponding to a normal value). Among the three dual AD checks performed on the three AD channels, at least one AD check result is normal (for example, Chn23_Flag is 1, and the other two are 0, then 0or 1or 0=1). It can be determined that the sampling of any channel in the dual AD channels corresponding to the normal abnormal flag corresponding to the value is normal and can be used as a reference (in the case where Chn23_Flag is 1 and the other two are 0, the sampling of any channel in the AD2 channel and the AD3 channel can be used as a reference); if the value of Mode1_Bs is 0 (corresponding to an abnormal value), the sampling of the three AD channels may have problems and cannot be used as a reference. The stabilization control device can perform safety measures such as locking.

[0069] In a specific implementation, when the test mode signal is the first signal, the following AD channel logic operation detection may also be performed:

[0070] Mode1_Ab=((Chn12_Flag)AND(Chn23_Flag)AND(Chn13_Flag)),

[0071] If the value of Mode1_Ab is normal, corresponding to 1, it means that the three AD channels are normal. If the value of Mode1_Ab is abnormal, corresponding to 0, it means that at least one of the three AD channels is abnormal, which can indicate that the AD channel is abnormal.

[0072] In the embodiment of the present invention, when the test mode signal is the second signal, the following AD channel logic operation check is performed:

[0073] Mode2_Bs=(((Chn12_Flag)AND(Chn23_Flag))OR((Chn12_Flag)AND(Chn13_Flag))OR((Chn13_Flag)AND(Chn23_Flag))),

[0074] Wherein, Mode2_Bs represents the second signal verification result; if the value of the second signal verification result corresponds to normal, it is determined that the sampling of any channel in the dual AD channels corresponding to the abnormal flag whose value corresponds to normal is normal.

[0075] In a specific implementation, when the Mode_Set constant is set to the second signal (for example, Mode_Set=2), the value of Mode2_Bs is 1 (corresponding to a normal value), and among the three dual AD checks performed on the three AD channels, the results of at least two AD checks are normal (for example, Chn12_Flag and Chn23_Flag are 1, and Chn13_Flag is 0, then 1or 0or0=1), then it can be determined that the sampling of any channel in the dual AD channels corresponding to the abnormal flag corresponding to the normal value is normal and can be used as a reference (in the case where Chn12_Flag and Chn23_Flag are 1 and Chn13_Flag is 0, the sampling of any channel in the AD1 channel and the AD2 channel can be used as a reference, or the sampling of any channel in the AD2 channel and the AD3 channel can be used as a reference); if the value of Mode2_Bs is 0 (corresponding to an abnormal value), the sampling of the three AD channels may have problems and cannot be used as a reference, and the stabilization control device can perform safety measures such as locking.

[0076] In a specific implementation, when the test mode signal is the second signal, the following AD channel logic operation detection may also be performed:

[0077] Mode2_Ab=((Chn12_Flag)AND(Chn23_Flag)AND(Chn13_Flag)),

[0078] If the value of Mode2_Ab is normal, corresponding to 1, it means that the three AD channels are normal. If the value of Mode2_Ab is abnormal, corresponding to 0, it means that at least one of the three AD channels is abnormal, which can indicate that the AD channel is abnormal.

[0079] In a specific implementation, when the test mode signal is the zeroth signal, the AD channel logic operation verification is a traditional method. When the test mode signal is the first signal, the multi-AD channel verification is a multi-AD channel verification with fault tolerance space, which can avoid the problem of malfunction of the stabilization control device (exiting normal operation) caused by sampling errors in one AD channel, thereby improving the stability of the power system operation. Furthermore, when the test mode signal is the second signal, the multi-AD channel verification also has a certain fault tolerance space compared with the traditional verification method, and the verification pass standard is higher than the multi-AD channel verification of the first signal. This provides users with a multi-AD channel verification method with a variety of different verification standards based on fault tolerance space.

[0080] In the embodiment of the present invention, when the test mode signal is the third signal, the following AD channel logic operation check is performed:

[0081] If at the current moment, the difference between any two sampling signals is greater than or equal to the standard deviation value (that is, any one of Chn12_Flag, Chn23_Flag and Chn13_Flag is greater than or equal to the standard deviation value), the corresponding (one or two) sampling signals are corrected, and the correction method is: obtain multiple historical sampling signals at multiple sampling time points pushed back from the current moment, use the multiple historical sampling signals to obtain the corrected sampling signal at the current moment through interpolation calculation, use the corrected sampling signal as the sampling signal at the current moment, and perform the following logical operations based on the sampling signal at the current moment:

[0082] Mode3_Bs=((Chn12_Flag)AND(Chn23_Flag)AND(Chn13_Flag)),

[0083] Mode3_Bs represents the third signal verification result; if the value of the third signal verification result corresponds to normal, it is determined that the sampling of any channel among the three AD channels is normal.

[0084] In a specific implementation, when the test mode signal is the third signal, if at the current instant, the difference between any two sampled signals is less than the standard deviation value, the logic operation of the third signal multi-AD channel check can be directly performed.

[0085] In a specific implementation, the above-mentioned current moment does not necessarily refer to the moment of verification, and the moment when the difference between any two sampling signals is greater than or equal to the standard deviation value can be used as the current moment.

[0086] See also Figure 2 , which is a schematic diagram of the principle of parabola interpolation calculation provided by the present invention.

[0087] In the embodiment of the present invention, the following formula is used for interpolation calculation:

[0088] y k =3y k-1 -3y k-2 +y k-3 ,

[0089] Among them, y k Represents the corrected sampling signal at the current moment, y k-1 ,y k-2 and k-3 They represent the historical sampling signals of the first sampling time point, the second sampling time point, and the third sampling time point pushed back from the current time, respectively. k ,y k-1 ,y k-2 and k-3The intervals between them are equal, and the intervals are all sampling intervals.

[0090] In a specific implementation, the sampling signal at the current moment may be corrected multiple times, but the number of corrections may be limited. The maximum limit may be set by the user according to the application scenario, and is generally 5.

[0091] In a specific implementation, if a corrected sampling signal is obtained through interpolation calculation and is used to replace the sampling signal at the current moment, the new sampling signal at the current moment can be used for double AD verification to obtain the corresponding exception flag (Chn12_Flag, Chn23_Flag or Chn13_Flag), and perform subsequent Mode3_Bs calculation.

[0092] In a specific implementation, when the Mode_Set constant is set to the third signal (for example, Mode_Set=3), with or without correction of the sampling signal at the current moment, in the logical operation, the value of Mode3_Bs is 1 (corresponding to a normal value), and in the three double AD checks performed on the three AD channels, the results of the three AD checks are all normal (Chn12_Flag, Chn23_Flag and Chn13_Flag are all 1, then 1and 1and 1=1), then it can be determined that the sampling of the three AD channels is normal and can be used as a reference; if the value of Mode3_Bs is 0 (corresponding to an abnormal value), then at least one of the three AD channels may have a sampling problem and cannot be used as a reference, and the stabilization control device can perform safety measures such as locking.

[0093] In a specific implementation, when the test mode signal is the third signal, the following AD channel logic operation detection may also be performed:

[0094] Mode3_Ab=((Chn12_Flag)AND(Chn23_Flag)AND(Chn13_Flag)),

[0095] If the value of Mode3_Ab is normal, corresponding to 1, it means that the three AD channels are normal. If the value of Mode3_Ab is abnormal, corresponding to 0, it means that at least one of the three AD channels is abnormal, which can indicate that the AD channel is abnormal.

[0096] In a specific implementation, compared with the multi-AD channel verification of the first signal and the second signal, the verification requirement of the multi-AD channel verification of the third signal is higher, but based on the correction of the sampling signal at the current moment, there is also a certain error tolerance space.

[0097] In a specific implementation, when the test mode signal is the fourth signal, that is, when the Mode_Set constant is set to the fourth signal (for example, Mode_Set=4), it indicates that the stabilization control device is in an increased test state, and the sampling data source is switched from the actual PT / CT signal quantity to a small signal source. The maintenance mark of the stabilization control device turns on the maintenance light to remind the debugging personnel or users that the stabilization control device is in an increased test state, and the actual operating mode constant needs to be restored after debugging is completed.

[0098] See also Figure 1 , which is a schematic diagram of the principle of the multi-AD channel verification method applicable to the stabilization control device provided by the present invention.

[0099] The present invention also provides a multi-AD channel verification system suitable for a stabilization control device, comprising a first analog quantity conversion board, a second analog quantity conversion board and a digital signal processor, wherein: the first analog quantity conversion board is used to use the AD1 channel and the AD2 channel to sample from the power system respectively, and the corresponding sampling signals obtained are the AD1 signal and the AD2 signal, and the sampling signals are sent to the digital signal processor; the second analog quantity conversion board is used to use the AD3 channel to sample from the power system, and the corresponding sampling signal obtained is the AD3 signal, and the test channel is used to collect the test mode signal, and the sampling signal and the test mode signal are sent to the digital signal processor; the digital signal processor is used to perform the following corresponding AD channel logic operation verification according to the test mode signal:

[0100] When the test mode signal is the zeroth signal, the following AD channel logic operation check is performed:

[0101] Mode0_Bs=Chn12_Flag,

[0102] Among them, Mode0_Bs represents the zeroth signal check result, and Chn12_Flag represents the channel 12 flag; if the value of the zeroth signal check result corresponds to normal, it is determined that the sampling of any channel of the AD1 channel and the AD2 channel is normal;

[0103] When the test mode signal is the first signal, the following AD channel logic operation check is performed:

[0104] Mode1_Bs=((Chn12_Flag)OR(Chn23_Flag)OR(Chn13_Flag)),

[0105] Among them, Mode1_Bs represents the first signal verification result, Chn23_Flag and Chn13_Flag represent channel 23 flag and channel 13 flag respectively; if the value of the first signal verification result corresponds to normal, it is determined that the sampling of any channel in the dual AD channels corresponding to the abnormal flag whose value corresponds to normal is normal.

[0106] In a specific implementation, the first analog conversion board can be the original analog conversion board (e.g., ADC board, Analog-to-Digital Converter board) on the stabilization device, corresponding to the AD1 channel and the AD2 channel, and the second analog conversion board is an analog signal conversion board added to the stabilization device, corresponding to the AD3 channel and the AD4 channel (test channel). The digital signal processor can be a DSP (Digital Signal Processor, DSP) board, which is a microprocessor used to quickly execute digital signal processing algorithms.

[0107] In the embodiment of the present invention, the digital signal processor is further used for:

[0108] When the test mode signal is the second signal, the following AD channel logic operation check is performed:

[0109] Mode2_Bs=(((Chn12_Flag)AND(Chn23_Flag))OR((Chn12_Flag)AND(Chn13_Flag))OR((Chn13_Flag)AND(Chn23_Flag))),

[0110] Wherein, Mode2_Bs represents the second signal verification result; if the value of the second signal verification result corresponds to normal, it is determined that the sampling of any channel in the dual AD channels corresponding to the abnormal flag corresponding to the normal value is normal;

[0111] When the test mode signal is the third signal, the following AD channel logic operation check is performed:

[0112] If at the current moment, the difference between any two sampling signals is greater than or equal to the standard deviation value, the corresponding sampling signal is corrected. The correction method is: obtain multiple historical sampling signals at multiple sampling time points pushed back from the current moment, use the multiple historical sampling signals to obtain the corrected sampling signal at the current moment through interpolation calculation, use the corrected sampling signal as the sampling signal at the current moment, and perform the following logical operations based on the sampling signal at the current moment:

[0113] Mode3_Bs=((Chn12_Flag)AND(Chn23_Flag)AND(Chn13_Flag)),

[0114] Mode3_Bs represents the third signal verification result; if the value of the third signal verification result corresponds to normal, it is determined that the sampling of any channel among the three AD channels is normal.

[0115] In an embodiment of the present invention, the digital signal processor is used to calculate the difference between the sampling signals of the two AD channels. If the difference is less than the standard deviation value, the verification result is normal; if the difference is greater than or equal to the standard deviation value, and the duration is greater than or equal to the standard deviation time, the verification result is abnormal.

[0116] In the embodiment of the present invention, the digital signal processor is used to perform interpolation calculation using the following formula:

[0117] y k =3y k-1 -3y k-2 +y k-3 ,

[0118] Among them, y k Represents the corrected sampling signal at the current moment, y k-1 ,y k-2 and k-3 They represent the historical sampling signals of the first sampling time point, the second sampling time point, and the third sampling time point pushed back from the current time, respectively. k ,y k-1 ,y k-2 and k-3 The intervals between them are equal.

[0119] In the embodiment of the present invention, the abnormal flag has a value of 1 corresponding to a normal state and a value of 0 corresponding to an abnormal state.

[0120] The present invention also provides an electronic device, including a memory and a processor, wherein a computer program executable by the processor is stored in the memory, and when the computer program is executed by the processor, any one of the multi-AD channel verification methods applicable to a stabilization control device provided by the present invention is executed.

[0121] The present invention also provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of any one of the multi-AD channel verification methods applicable to a stabilization control device provided by the present invention are implemented.

[0122] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0123] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0124] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0125] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

Claims

1. A multi-AD channel verification method suitable for a stabilization control device, characterized in that: include: Use the AD1 channel, the AD2 channel and the AD3 channel to sample from the power system respectively, and the corresponding sampled signals obtained are the AD1 signal, the AD2 signal and the AD3 signal, and use the test channel to collect the test mode signal; Perform double AD verification on the following AD signal groups, and set the corresponding abnormal flag to the corresponding normal or abnormal value according to the normal or abnormal result obtained by the verification: AD1 signal and AD2 signal, the corresponding abnormal flag is channel 12 flag; AD2 signal and AD3 signal, the corresponding abnormal flag is channel 23 flag; AD1 signal and AD3 signal, the corresponding abnormal flag is channel 13 flag; According to the test mode signal, the following corresponding AD channel logic operation verification is performed: When the test mode signal is the zeroth signal, the following AD channel logic operation check is performed: Mode0_Bs=Chn12_Flag, Among them, Mode0_Bs represents the zeroth signal check result, and Chn12_Flag represents the channel 12 flag; if the value of the zeroth signal check result corresponds to normal, it is determined that the sampling of any channel of the AD1 channel and the AD2 channel is normal; When the test mode signal is the first signal, the following AD channel logic operation check is performed: Mode1_Bs=((Chn12_Flag)OR(Chn23_Flag)OR(Chn13_Flag)), Among them, Mode1_Bs represents the first signal verification result, Chn23_Flag and Chn13_Flag represent channel 23 flag and channel 13 flag respectively; if the value of the first signal verification result corresponds to normal, it is determined that the sampling of any channel in the dual AD channels corresponding to the abnormal flag whose value corresponds to normal is normal.

2. The multi-AD channel verification method applicable to a stabilization control device according to claim 1, characterized in that: The double AD check is performed on the following AD signal groups, and the normal or abnormal result obtained according to the check includes: Calculate the difference between the sampling signals of the two AD channels. If the difference is less than the standard deviation, the verification result is normal. If the difference is greater than or equal to the standard deviation and the duration is greater than or equal to the standard deviation time, the verification result is abnormal.

3. The multi-AD channel verification method applicable to a stabilization control device according to claim 2, characterized in that: Also includes: When the test mode signal is the second signal, the following AD channel logic operation check is performed: Mode2_Bs=(((Chn12_Flag)AND(Chn23_Flag))OR((Chn12_Flag)AND(Chn13_Flag))OR((Chn13_Flag)AND(Chn23_Flag))), Wherein, Mode2_Bs represents the second signal verification result; if the value of the second signal verification result corresponds to normal, it is determined that the sampling of any channel in the dual AD channels corresponding to the abnormal flag whose value corresponds to normal is normal.

4. The multi-AD channel verification method applicable to a stabilization control device according to claim 3, characterized in that: Also includes: When the test mode signal is the third signal, the following AD channel logic operation check is performed: If at the current moment, the difference between any two sampling signals is greater than or equal to the standard deviation value, the corresponding sampling signal is corrected. The correction method is: obtain multiple historical sampling signals at multiple sampling time points pushed back from the current moment, use the multiple historical sampling signals to obtain the corrected sampling signal at the current moment through interpolation calculation, use the corrected sampling signal as the sampling signal at the current moment, and perform the following logical operations based on the sampling signal at the current moment: Mode3_Bs=((Chn12_Flag)AND(Chn23_Flag)AND(Chn13_Flag)), Mode3_Bs represents the third signal verification result; if the value of the third signal verification result corresponds to normal, it is determined that the sampling of any channel among the three AD channels is normal.

5. The multi-AD channel verification method applicable to a stabilization control device according to claim 4, characterized in that: The method of obtaining a plurality of historical sampling signals at a plurality of sampling time points pushed back from the current time, and obtaining a corrected sampling signal at the current time by interpolation calculation using the plurality of historical sampling signals, comprises: The interpolation calculation is performed using the following formula: y k =3y k-1 -3y k-2 +y k-3 , Among them, y k Represents the corrected sampling signal at the current moment, y k-1 ,y k-2 and k-3 They represent the historical sampling signals of the first sampling time point, the second sampling time point, and the third sampling time point pushed back from the current time, respectively. k ,y k-1 ,y k-2 and k-3 The intervals between them are equal.

6. The multi-AD channel verification method applicable to a stabilization control device according to claim 5, characterized in that: The abnormal flag has a normal value of 1 and an abnormal value of 0.

7. A multi-AD channel verification system suitable for a stabilization control device, characterized in that: It includes a first analog conversion board, a second analog conversion board and a digital signal processor, wherein: The first analog conversion board is used to use the AD1 channel and the AD2 channel to sample from the power system respectively, and the corresponding sampled signals obtained are the AD1 signal and the AD2 signal, and the sampled signals are sent to the digital signal processor; The second analog conversion board is used to use the AD3 channel to sample from the power system, the corresponding sampled signal obtained is the AD3 signal, the test channel is used to collect the test mode signal, and the sampled signal and the test mode signal are sent to the digital signal processor; The digital signal processor is used to perform the following corresponding AD channel logic operation verification according to the test mode signal: When the test mode signal is the zeroth signal, the following AD channel logic operation check is performed: Mode0_Bs=Chn12_Flag, Among them, Mode0_Bs represents the zeroth signal check result, and Chn12_Flag represents the channel 12 flag; if the value of the zeroth signal check result corresponds to normal, it is determined that the sampling of any channel of the AD1 channel and the AD2 channel is normal; When the test mode signal is the first signal, the following AD channel logic operation check is performed: Mode1_Bs=((Chn12_Flag)OR(Chn23_Flag)OR(Chn13_Flag)), Among them, Mode1_Bs represents the first signal verification result, Chn23_Flag and Chn13_Flag represent channel 23 flag and channel 13 flag respectively; if the value of the first signal verification result corresponds to normal, it is determined that the sampling of any channel in the dual AD channels corresponding to the abnormal flag whose value corresponds to normal is normal.

8. The multi-AD channel verification system for a stabilization control device according to claim 7, characterized in that: The digital signal processor is further used for: When the test mode signal is the second signal, the following AD channel logic operation check is performed: Mode2_Bs=(((Chn12_Flag)AND(Chn23_Flag))OR((Chn12_Flag)AND(Chn13_Flag))OR((Chn13_Flag)AND(Chn23_Flag))), Wherein, Mode2_Bs represents the second signal verification result; if the value of the second signal verification result corresponds to normal, it is determined that the sampling of any channel in the dual AD channels corresponding to the abnormal flag corresponding to the normal value is normal; When the test mode signal is the third signal, the following AD channel logic operation check is performed: If at the current moment, the difference between any two sampling signals is greater than or equal to the standard deviation value, the corresponding sampling signal is corrected. The correction method is: obtain multiple historical sampling signals at multiple sampling time points pushed back from the current moment, use the multiple historical sampling signals to obtain the corrected sampling signal at the current moment through interpolation calculation, use the corrected sampling signal as the sampling signal at the current moment, and perform the following logical operations based on the sampling signal at the current moment: Mode3_Bs=((Chn12_Flag)AND(Chn23_Flag)AND(Chn13_Flag)), Mode3_Bs represents the third signal verification result; if the value of the third signal verification result corresponds to normal, it is determined that the sampling of any channel among the three AD channels is normal.

9. An electronic device, characterized in that: It comprises a memory and a processor, wherein a computer program executable by the processor is stored in the memory, and when the computer program is executed by the processor, the multi-AD channel verification method applicable to a stabilization control device as described in any one of claims 1 to 6 is executed.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the multi-AD channel verification method applicable to a stabilization control device as described in any one of claims 1 to 6 are implemented.

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