Comparator circuit for successive approximation type ADC

Abstract

The invention belongs to the technical field of analog integrated circuits, and particularly relates to a comparator circuit for a successive approximation type ADC (Analog to Digital Converter), which comprises a pre-amplifier stage circuit and a latch stage circuit, the pre-amplifier stage circuit is a cross coupling operational amplifier, and the latch stage circuit is a stroke-arm type latch comparator; a clock signal CLK is respectively input to the power supply ends of the cross coupling operational amplifier and the latch comparator; the positive input end of the cross-coupled operational amplifier is connected with a VIP signal, the negative input end of the cross-coupled operational amplifier is connected with a VIN signal, the negative output end of the cross-coupled operational amplifier is connected with the negative input end of the latch comparator, and the positive output end of the cross-coupled operational amplifier is connected with the positive input end of the latch comparator; a two-stage structure is adopted in the circuit structure, the characteristic that the first-stage operational amplifier is easy to process low voltage is combined with the characteristic that the second-stage latch is easy to process high voltage, and the voltage comparison speed of the comparator is effectively increased.

Description

Technical Field

[0001] The invention belongs to the technical field of analog integrated circuits, and in particular relates to a comparator circuit for a successive approximation ADC. Background Art

[0002] Analog-to-Digital Converter (ADC) is a bridge between analog signals and digital signals, and is one of the important products in the market of mixed analog and digital and SOC chips. ADC has been widely used in instrumentation, medical equipment, aerospace and other fields. Its accuracy, speed, power consumption and other indicators directly affect system performance. Successive approximation register (SAR) ADC was proposed in the 1970s. The working principle of successive approximation ADC is to gradually approximate the digital value of the input analog signal through a binary search algorithm. In terms of structure, it mainly consists of a sample-and-hold circuit, a comparator, a digital-to-analog converter (DAC) and a successive approximation register. The sample-and-hold circuit first samples the input analog signal and keeps it stable during the conversion process. The comparator compares the sampled and held signal with the analog voltage output by the DAC. The successive approximation register controls the DAC to output different analog voltage values ​​according to the comparison result, and determines the digital representation of the input analog signal bit by bit starting from the most significant bit. The whole process is repeated until the values ​​of all bits are determined, and finally the digital code representing the input analog signal is output. Among them, the comparator continuously compares the input analog signal with the output of the digital-to-analog converter. Its accuracy and performance determine the accuracy and speed of the entire conversion process. Therefore, the comparator has become the key to the design of successive approximation ADC. With the advent of the deep submicron era, traditional comparator structures, such as open-loop comparators, closed-loop comparators, latch comparators, etc., can no longer meet today's high-speed and high-precision requirements. Comparators have also gradually developed from a single structure to a multi-stage and multi-structure fusion. For a single-stage amplifier as a comparator, its comparison speed is usually difficult to meet the requirements; for latch comparators, although the speed has been improved, there are still disadvantages such as insufficient speed, severe kickback noise, excessive offset voltage, and high static power consumption in high-speed scenarios. Summary of the invention

[0003] In order to solve the problems existing in the above prior art, the present invention proposes a comparator circuit for a successive approximation ADC, and the circuit structure includes: a pre-amplifier stage circuit and a latch stage circuit; the pre-amplifier stage circuit is a cross-coupled operational amplifier, and the latch stage circuit is a strong-arm type latch comparator; the clock signal CLK is respectively input to the power supply terminals of the cross-coupled operational amplifier and the strong-arm type latch comparator; the positive input terminal of the cross-coupled operational amplifier is connected to the VIP signal, the negative input terminal of the cross-coupled operational amplifier is connected to the VIN signal, the negative output terminal of the cross-coupled operational amplifier is connected to the negative input terminal of the strong-arm type latch comparator, and the positive output terminal of the cross-coupled operational amplifier is connected to the positive input terminal of the strong-arm type latch comparator.

[0004] Beneficial effects of the present invention:

[0005] The circuit structure of the present invention adopts a two-stage structure, and the first-stage operational amplifier is easy to handle low voltages and the second-stage latch is easy to handle high voltages, which effectively improves the voltage comparison speed of the comparator. The first-stage operational amplifier of the present invention adopts a cross-coupled load structure, does not require a bias circuit and a common-mode feedback circuit, and saves circuit area and power consumption. The second-stage latch of the present invention adopts a strong-arm latch structure, which effectively improves the comparison speed and reduces static power consumption compared to the traditional latch. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 It is the overall circuit structure diagram of the present invention;

[0007] Figure 2 It is a structural diagram of a cross-coupled operational amplifier circuit of the present invention;

[0008] Figure 3 It is a circuit structure diagram of the strong-arm type latch comparator of the present invention. DETAILED DESCRIPTION

[0009] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0010] By adopting reasonable circuit structure and technical means, a high-speed and low-power comparator circuit that can be applied to successive approximation ADC is designed, which can significantly improve the voltage comparison speed, reduce the influence of noise and offset voltage, and reduce static power consumption. A comparator circuit structure diagram for successive approximation ADC, such as Figure 1 As shown, the first stage is the prevention amplifier stage, which is a cross-coupled operational amplifier, with input signals VIP and VIN, clock signal CLK, and output signals VN and VP. The second stage is the latch stage, which is a strong-arm latch, with input signals VP and VN, clock signal CLK, and output signals VOP and VON. The first prevention amplifier stage amplifies the input signals VIP and VIN under the control of the clock signal CLK to generate amplified signals VP and VN. At the same time, VP and VN are connected to the latch stage as input signals, and the comparison results VOP and VON are output under the control of the clock signal CLK.

[0011] Specifically, the structure of the comparator circuit for the successive approximation ADC includes: a pre-amplifier stage circuit and a latch stage circuit; the pre-amplifier stage circuit is a cross-coupled operational amplifier, and the latch stage circuit is a strong-arm type latch comparator; the clock signal CLK is respectively input to the power supply terminals of the cross-coupled operational amplifier and the strong-arm type latch comparator; the positive input terminal of the cross-coupled operational amplifier is connected to the VIP signal, the negative input terminal of the cross-coupled operational amplifier is connected to the VIN signal, the negative output terminal of the cross-coupled operational amplifier is connected to the negative input terminal of the strong-arm type latch comparator, and the positive output terminal of the cross-coupled operational amplifier is connected to the positive input terminal of the strong-arm type latch comparator.

[0012] like Figure 2 As shown in the figure, in the first-stage cross-coupled op amp structure, the positive input terminal is the gate VIP of the M1 tube, the negative input terminal is the gate VIN of the M2 tube, and the M5 and M6 tubes are in the form of diodes, which determines the output common-mode level of the op amp. No additional common-mode feedback is required, saving area resources and power consumption. The M3 and M4 tubes are connected in a cross-coupled form to increase the gain of the op amp and increase the input to the tube g m1 and control g m5 and g m3 The difference can increase the gain, and the cross-coupling connection does not require a bias circuit to provide a bias point, saving area resources and power consumption.

[0013] Specifically, the cross-coupled operational amplifier is composed of 4 PMOS tubes M3 to M6 and 5 NMOS tubes M0, M1, M2, M7, and M8; the sources of M0, M3, M4, M5, and M6 are respectively connected to the voltage source; the gate of M5 is respectively connected to the drain of M5, the drain of M3, the gate of M4, the drain of M7, and the drain of M1; the gate of M3 is respectively connected to the drain of M4, the drain of M6, the gate of M6, the drain of M2, and the drain of M8; the gate of M7 and the gate of M8 are both connected to the CLKB signal, and the source of M7 and the source of M8 are both grounded; the gate of M1 is connected to the VIP signal, and the source of M1 is respectively connected to the source of M2 and the drain of M0; the gate of M2 is connected to the VIN signal; and the gate of M0 is connected to the clock signal CLK.

[0014] The amplification gain of the cross-coupled operational amplifier is:

[0015]

[0016] Among them, V out is the output voltage, V in is the input voltage, g m1 is the transconductance of input tube M1, g m5 is the transconductance of the MOS diode M5 in the cross-coupled load tube, g m3 It is the transconductance of the cross tube M3 in the cross-coupled load tube.

[0017] According to the cross-coupled op amp structure described above, this structure adds M7 and M8 for reset on the basis of ordinary cross-coupled op amps. The purpose is to solve the op amp output error caused by the sharp change and inversion of the input differential signals VIP and VIN, and improve the correctness and accuracy of the comparator. The gate of the tail current tube M0 is connected to the clock signal CLK to control the operation and reset of the entire op amp, turning the op amp into a dynamic op amp and reducing power consumption.

[0018] like Figure 3 As shown, the positive input end of the second-stage strong-arm latch structure is the gate VP of the M10 tube, and the negative input end is the gate VN of the M11 tube. VP and VN are the output signals of the first-stage cross-coupled operational amplifier. The output signals are VON and VOP. M12, M13, M14, and M15 form a back-to-back cross-coupled connection mode.

[0019] Specifically, the strong-arm latch comparator includes: 5 NMOS tubes M9 to M13 and 6 PMOS tubes M14 to M19; the sources of M14, M15, M16, M17, M18 and M19 are all connected to the power supply voltage, and the gates of M16, M17, M18 and M19 are all connected to the clock signal CLK; the drain of M16 is connected to the drain of M14, the drain of M12, the gate of M15 and the gate of M19. and the gate of M13; the gate of M14 is connected to the gate of M12, the drain of M15, the drain of M17 and the drain of M13; the source of M12 is connected to the drain of M18 and the drain of M10; the gate of M10 is connected to the VP signal, and the source of M10 is connected to the source of M11 and the drain of M9; the source of M13 is connected to the drain of M19 and the drain of M11; the gate of M11 is connected to the VN signal; the source of M9 is grounded. And the drain of M14 in the strong-arm type latch comparator is used as the negative output terminal, and the drain of M15 in the strong-arm type latch comparator is used as the positive output terminal.

[0020] The time constant formula of the output node of the strong-arm latch comparator is:

[0021]

[0022] Where τ is the time constant, C L is the output node capacitance, g m It is the equivalent transconductance of latch output cross-coupling tubes M12 and M14.

[0023] This structure can increase gm and reduce G, thereby reducing the time constant τ of the output node and speeding up the comparison. The gates of M16 and M17 are connected to the clock signal CLK to reset the control output signal. M18 and M19 are also connected to the drain of input tubes M10 and M11 as reset signal tubes. The purpose is to eliminate the voltage difference from this point after the last comparison is completed, so that the VDS voltage of input tubes M10 and M11 is the same, reducing the impact of the channel length modulation effect, thereby improving the accuracy of the comparison.

[0024] The circuit principle of the present invention includes: a high-speed, low-power comparator circuit applied to a successive approximation ADC, including a front-stage cross-coupled operational amplifier module and a rear-stage strong-arm latch module. The working mode of the cross-coupled operational amplifier module is: when the clock signal CLK is high, the cross-coupled operational amplifier starts to work and outputs a differential amplified signal; when the clock signal CLK is low, the operational amplifier does not work, and the output signal is reset and pulled low; the input end of the cross-coupled operational amplifier is the gate of the NMOS tube M1 and M2, the input signal VIP and VIN, the drain of the NMOS tube M1, M2 and the drain of the NMOS tube M7, M8 are connected to reset and pull down the output level to prevent the generation of metastable state. The gate of the PMOS tube M3 and M4 is cross-connected with the output node VP and VN to form a cross-coupled tube, M5 and M6 are MOS diodes, and the combination of M3, M4, M5, and M6 improves the operational amplifier gain, and does not require a bias circuit and a common-mode feedback circuit, thereby reducing the area and power consumption. The output node is the drain of M1, M2, M3, and M4, which are VP and VN respectively. The working mode of the strong-arm latch module is: when the clock signal CLK is high, the latch works normally and outputs the comparison result; when the clock signal CLK is low, the latch stops working and the output signal is reset to a high level voltage. The input end of the strong-arm latch is the gate of the NMOS tubes M10 and M11, which is connected to the output ends VP and VN of the previous cross-coupled operational amplifier. The NMOS tubes M12 and M13 and the PMOS tubes M14 and M15 are cross-connected to form a back-to-back positive feedback structure. This structure increases the equivalent transconductance of the latch and reduces the time constant at the output nodes VOP and VON, thereby achieving the effect of increasing the speed. The source of the PMOS tubes M16 and M17 is connected to the power supply voltage, the drain is connected to the output node, and the gate is connected to the clock signal CLK. When the clock signal CLK is low, M16 and M17 are turned on, the latch is in the reset state, and the M16 and M17 tubes reset the output nodes to the power supply voltage at the same time. The gates of PMOS tubes M18 and M19 are connected to the time signal CLK, the sources are connected to the power supply voltage, and the drains are connected to the drains of input tubes M10 and M11. When the clock signal CLK is low, M18 and M19 are turned on, pulling the drain nodes of the two input tubes to the same potential, reducing the impact of the channel length modulation effect on the discharge current, thereby reducing the comparison error and improving the accuracy.

[0025] The present invention adopts a two-stage structure to design a high-speed and low-power comparator circuit. The first stage is a gain amplifier stage, which uses a dynamic operational amplifier with a cross-coupled load to simplify the circuit structure, reduce power consumption and eliminate kickback noise. The second stage has a strong-arm latch structure to improve the comparator speed. Similarly, the latch uses a dynamic structure to perform comparison and reset switching to reduce circuit power consumption.

[0026] Speed: The two-stage structure is adopted, and the combination of the front-stage operational amplifier and the high-speed latch effectively improves the voltage comparison speed;

[0027] In terms of reducing noise and offset voltage: a two-stage structure is adopted, the offset voltage and thermal noise of the second-stage latch are reduced by the gain of the first stage, and the kickback noise of the second-stage latch is eliminated due to the distance between the output node and the input node. At the same time, the offset voltage of the first-stage op amp is eliminated by using input offset storage technology.

[0028] In terms of reducing power consumption: both circuits use dynamic clock control and do not work during reset, which reduces the static power consumption of the comparator.

[0029] The functions of the cross-coupled op amp in the first stage are: 1. Pre-amplify the input voltage and pass the amplified voltage to the second-stage latch to improve the latch's operating speed. 2. Eliminate the kickback noise, thermal noise, and offset voltage generated by the second-stage strong-arm latch to improve accuracy. 3. The structure of the first-stage op amp adopts a cross-coupled structure. This op amp structure does not require an additional bias circuit or a common-mode feedback circuit to stabilize the output common-mode voltage, thus simplifying the circuit structure, reducing the area, and reducing power consumption. 4. The op amp uses a clock signal CLK control in order to stop the op amp from working when it is not needed, thus reducing static power consumption.

[0030] The second stage uses a strong-arm latch for the following purposes: 1. Compared with the traditional latch structure, the output node time constant of the strong-arm latch can be lower, thereby increasing the speed of the latch output result. 2. An additional reset circuit is added to counteract the non-ideal factors caused by the channel length modulation effect of the MOS tube, thereby improving the accuracy of the comparator.

[0031] The above embodiments further illustrate the purpose, technical solutions and advantages of the present invention in detail. It should be understood that the above embodiments are only preferred implementation modes of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made to the present invention within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A comparator circuit for a successive approximation ADC, characterized in that: include: Pre-amplifier stage circuit and latch stage circuit; the pre-amplifier stage circuit is a cross-coupled operational amplifier, and the latch stage circuit is a strong-arm type latch comparator; the clock signal CLK is respectively input to the power supply terminals of the cross-coupled operational amplifier and the strong-arm type latch comparator; the positive input terminal of the cross-coupled operational amplifier is connected to the VIP signal, the negative input terminal of the cross-coupled operational amplifier is connected to the VIN signal, the negative output terminal of the cross-coupled operational amplifier is connected to the negative input terminal of the strong-arm type latch comparator, and the positive output terminal of the cross-coupled operational amplifier is connected to the positive input terminal of the strong-arm type latch comparator.

2. A comparator circuit for a successive approximation register ADC according to claim 1, characterized in that: The cross-coupled operational amplifier consists of 4 PMOS tubes M3~M6 and 5 NMOS tubes M0, M1, M2, M7, and M8; the sources of M0, M3, M4, M5, and M6 are respectively connected to the voltage source; the gate of M5 is respectively connected to the drain of M5, the drain of M3, the gate of M4, the drain of M7, and the drain of M1; the gate of M3 is respectively connected to the drain of M4, the drain of M6, the gate of M6, the drain of M2, and the drain of M8; the gate of M7 and the gate of M8 are both connected to the CLKB signal, and the source of M7 and the source of M8 are both grounded; the gate of M1 is connected to the VIP signal, and the source of M1 is respectively connected to the source of M2 and the drain of M0; the gate of M2 is connected to the VIN signal; the gate of M0 is connected to the clock signal CLK.

3. A comparator circuit for a successive approximation register ADC according to claim 2, characterized in that: The amplification gain of the cross-coupled operational amplifier is: Among them, V out is the output voltage, V in is the input voltage, g m1 is the transconductance of input tube M1, g m5 is the transconductance of the MOS diode M5 in the cross-coupled load tube, g m3 is the transconductance of the cross tube M3 in the cross-coupled load tube.

4. The comparator circuit for a successive approximation register ADC according to claim 1, characterized in that: The strong-arm latch comparator includes: 5 NMOS tubes M9 to M13 and 6 PMOS tubes M14 to M19; the sources of M14, M15, M16, M17, M18 and M19 are all connected to the power supply voltage, and the gates of M16, M17, M18 and M19 are all connected to the clock signal CLK; the drain of M16 is connected to the drain of M14, the drain of M12, the gate of M15 and the gate of M19 respectively. The gate of M13 is connected to the gate of M14; the gate of M14 is connected to the gate of M12, the drain of M15, the drain of M17 and the drain of M13; the source of M12 is connected to the drain of M18 and the drain of M10; the gate of M10 is connected to the VP signal, and the source of M10 is connected to the source of M11 and the drain of M9; the source of M13 is connected to the drain of M19 and the drain of M11; the gate of M11 is connected to the VN signal; the source of M9 is grounded.

5. The comparator circuit for a successive approximation register ADC according to claim 4, characterized in that: The drain of M14 in the strong-arm type latch comparator serves as a negative output terminal, and the drain of M15 in the strong-arm type latch comparator serves as a positive output terminal.

6. A comparator circuit for a successive approximation register ADC according to claim 4, characterized in that: The time constant formula of the output node of the strong-arm latch comparator is: Where τ is the time constant, C L is the output node capacitance, g m It is the equivalent transconductance of latch output cross-coupling tubes M12 and M14.

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