Electromagnetic Interference Mitigation for Switching Regulators

Abstract

In the switching regulator driver (400), a sense circuit (402) has a transistor current input and a sense circuit output. A logic circuit (404) has a logic circuit input and first and second outputs. The logic circuit input is coupled to the sense circuit output. A counter (406) has a counter clock input, a counter control input, and a counter output. The counter clock input is coupled to the first output. The counter control input is coupled to the second output. The counter (406) is configured to provide a count value at the counter output. A programmable drive strength circuit (408) has a drive strength circuit input and a transistor control output. The drive strength circuit input is coupled to the counter output. The programmable drive strength circuit (408) is configured to adjust the drive current at the transistor control output based on the count value.

Description

[Technical field]

[0001] A switching regulator is an electronic circuit that converts an input direct current (DC) voltage into a DC output voltage that is either higher or lower in magnitude than the input DC voltage. Various types of switching regulators are available, including step-down converters, step-up converters, and step-down / step-up converters.

[0002] A buck converter, for example, includes a high-side transistor (acting as a switch) coupled to a low-side transistor (also acting as a switch) at a switch node. A controller asserts a control signal to alternately open and close the high-side and low-side transistors, thereby alternately opening a current path from (a) the input voltage through the high-side transistor to the switch node through the inductor and capacitor, and (b) ground through the low-side transistor to the switch node through the inductor and capacitor. By alternately opening and closing the high and low-side transistors, a square wave voltage (toggles between approximately the input voltage and ground) is generated on the switch node. The square wave has a duty cycle that is a function of the applied input voltage and the target output voltage, and is implemented by the controller for the high and low-side transistors. The square wave is then filtered by the inductor and capacitor to generate a DC output voltage, which can be used to power an electrical load. Summary of the Invention

[0003] In a switching regulator driver, a sense circuit has a transistor current input and a sense circuit output. A logic circuit has a logic circuit input and first and second outputs. The logic circuit input is coupled to the sense circuit output. A counter has a counter clock input, a counter control input, and a counter output. The counter clock input is coupled to the first output. The counter control input is coupled to the second output. The counter is configured to provide a count value at the counter output. A programmable drive strength circuit has a drive strength circuit input and a transistor control output. The drive strength circuit input is coupled to the counter output. The programmable drive strength circuit is configured to adjust the drive current at the transistor control output based on the count value. [Brief description of the drawings]

[0004] [Figure 1] 1 illustrates a portion of a buck converter according to an example.

[0005] [Diagram 2] FIG. 1 is a timing diagram illustrating switch node voltage ringing of a Buck converter in accordance with an example.

[0006] [Diagram 3] 1 is a timing diagram illustrating the operation of a driver to reduce switch node voltage ringing according to an example.

[0007] [Figure 4] FIG. 1 is a schematic diagram illustrating a transistor driver for reducing switch node voltage ringing, according to an example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] As mentioned above, a switching regulator converts an input voltage to an output voltage that is a different magnitude (higher or lower) than the input voltage. In a switching regulator, one or more transistors are opened and closed to generate a waveform on a switch node with a particular duty cycle. FIG. 1 illustrates a portion of a buck converter in which a high-side (HS) transistor is coupled to a low-side (LS) transistor at a switch node 110. In this example, both the HS and LS switches are n-channel field effect transistors (NFETs), but in other examples they may be implemented as other types of transistors. The drain of the HS transistor is coupled to an input voltage (Vin) and the source of the LS transistor is coupled to ground. The voltage on the switch node 110 is shown as Vsw. An inductor L1 is coupled to the switch and a capacitor Cout. The connection between the inductor L1 and the capacitor Cout is the output of the regulator (Vout). A driver 102 has an input that receives a digital input signal HS_EN from the controller 101. The driver 102 has an output that is coupled to the gate of the HS transistor. When HS_EN is asserted (e.g., logic high) by controller 101, driver 102 responds by generating a voltage at its output to turn on the HS transistor, and a current I_hs flows from Vin, through the HS transistor, through switch node 110, and into inductor L1. Similarly, driver 104 has an input that receives a digital input signal LS_EN from the controller, and also has an output that is coupled to the gate of the LS transistor. When LS_EN is asserted (e.g., logic high), driver 104 responds by generating a voltage at its output to turn on the LS transistor. When the LS transistor is on, a current I_ls flows from ground, through the LS transistor, through switch node 110, and into inductor L1.

[0009] Figure 1 also shows a parasitic inductance Lp_hs between the input voltage Vin and the drain of the HS transistor. There is also another parasitic inductance Lp-ls between the source of the LS transistor and ground. These parasitic inductances arise, for example, from connections to the circuit board on which the switching regulator is mounted, and from traces within the circuit board.

[0010] To avoid shoot-through current, the controller 101 does not command the drivers 102 and 104 to turn on both the HS and LS transistors at the same time. Instead, the controller 101 implements a "dead time" between switching the on / off states of the HS and LS transistors. For example, when the HS transistor is on (and the LS transistor is off), the controller 101 first deasserts HS_EN (e.g., logic low) to turn off the HS transistor. After a short period of time (dead time) to ensure that the HS transistor is off, the controller asserts LS_EN to cause the driver 104 to turn on the LS transistor. After turning off the LS transistor, a dead time is also imposed before turning on the HS transistor.

[0011] A switching regulator switches the on / off states of the HS and LS transistors at an application specific frequency. In one example, the switching frequency is in the range of 100 KHz to 1 MHz. During each switching cycle, both the HS and LS transistors are turned on (although not simultaneously). FIG. 2 is a timing diagram illustrating a portion of such a switching cycle. At 201, the LS transistor is on and the HS transistor is off. The LS_EN signal is deasserted (falling edge 202) and a dead time 203 ensures that neither transistor is on. The controller 101 asserts HS_EN high (rising edge 204).

[0012] Waveform 211 is the current through the LS transistor (I_ls). Waveform 213 is the current through the HS transistor (I_hs). It takes a finite amount of time for the LS transistor to turn completely off and stop conducting current following the following edge 202 of LS_EN and for the HS transistor to turn completely on following the rising edge 204 of HS_EN. The current I_ls drops quickly as shown at 205 and the current I_hs increases quickly as shown at 206. Waveforms 211 and 214 illustrate that ringing can occur on the currents I_hs and I_ls as the respective transistor transition states (HS transistor turns on and LS transistor turns off). The ringing occurs because a resonant circuit is formed that includes Lp_hs, the channel resistance of the HS transistor, and the parasitic capacitance of the switch node 110. Waveform 214 illustrates the switch node voltage Vsw. When the LS transistor is on, Vsw is initially low, then as the body diode of the LS transistor is forced forward biased to maintain the continuous flow of inductor current, it falls slightly negative during the dead time 203, as shown at 221, and then rings upward as the HS transistor turns on.

[0013] Ringing on the switch node 110 can generate conducted and radiated high frequency electromagnetic interference (EMI) that can unfortunately be received by other components in the system that share the same voltage domain of, for example, Vin. For example, in an automobile where Vin is the battery voltage, other circuits in the automobile may receive EMI signals from the voltage regulator. A technique described herein for reducing ringing in a switching regulator is to reduce the drive current to the gate of the HS transistor during the portion of the process to turn the HS transistor on during which higher level ringing may otherwise occur.

[0014] According to various examples, an adaptive high-side gate driver is described herein that partitions the drive current to the gate of the HS transistor into three phases. In the first phase, a relatively large magnitude but short duration drive current is provided to the gate of the HS transistor. This high current pulse causes the gate-source voltage (Vgs) to quickly reach the threshold voltage of the transistor. As the Vgs of the HS transistor increases toward the threshold voltage, the HS transistor is still off and cannot conduct any drain current, so switch node ringing cannot occur during this time period. In the following second phase, the drive current is reduced to a lower level to dampen the switch node ringing. As the switch node voltage begins to rise, the adaptive high-side gate driver increases the magnitude of the drive current to the gate of the HS transistor to complete the turn-on process of the transistor. The magnitude of the drive current during the second phase is programmable as described herein to make the drive current as large as possible to quickly turn on the transistor without causing excessive ringing on the switch node.

[0015] The embodiments described herein relate to an adaptive driver for the HS transistor. A similar adaptive driver for the LS transistor may not be included because the body diode of the LS transistor conducts before the LS transistor is turned "on", thereby mitigating the effect on the Lp_ls parasitic inductance due to the rate of change of current through the LS transistor.

[0016] FIG. 3 is a timing diagram illustrating a comparison between a switching regulator including an adaptive high-side gate driver described herein and a switching regulator including a conventional high-side gate driver. The conventional high-side gate driver applies a large drive current to the gate of the HS transistor to turn the transistor on. The dashed waveform is for the conventional high-side gate driver, and the solid curve is for the adaptive high-side gate driver. At time t0, the controller asserts an HS_EN signal (not shown in FIG. 3) causing the gate driver to begin turning on the HS transistor.

[0017] In a conventional high side gate driver, the driver rapidly increases the drive current to the gate of the HS transistor (as shown at 301) and maintains that high level of drive current until the HS transistor is fully turned on (as shown at 302). When the HS transistor channel begins to conduct, the drain current (Id(hs)) increases very rapidly as shown at 303 and then settles to a steady state current (304). A high degree of ringing on the switch node results as shown at 305.

[0018] For the adaptive high side gate driver described herein, the drive current to the gate is also high during the initial phase 311, causing the Vgs of the transistor to reach its threshold voltage. However, rather than maintaining the drive current at a high level (as in a conventional high side gate driver), the adaptive high side gate driver reduces the drive current as shown at 306. In one embodiment, the initial phase 311 occurs for a fixed period of time (e.g., 2 ns). The gate current during the second phase 312 is adaptively configured as described herein to be high to complete the turn-on process of the HS transistor while reducing the rate of change of the drain current as shown at 307 (compared to the higher rate of change at 303 for a conventional high side gate driver). By increasing the drain current at a lower rate, much less ringing results on the switch node as shown at 308. The third phase 313 begins in response to the adaptive high side gate driver detecting that the switch node voltage Vsw has begun to rise (as shown at 309). Once Vsw is determined to be rising, the drive current to the HS transistor can be increased again (310) without further exacerbating the switch node ringing.

[0019] Referring again to FIG. 1, a sudden increase in the drain current I_hs through the HS transistor results in a voltage drop across the parasitic inductance Lp_hs. The magnitude of the voltage drop across the parasitic inductance Lp_hs is the product of the rate of change of I_hs and the inductance of Lp_hs. Thus, as the rate of change of I_hs increases, the voltage drop across the parasitic inductance Lp_hs increases. The upper terminal of Lp_hs is tied to Vin, a fixed voltage. Therefore, the voltage drop across the parasitic inductance Lp_hs requires a voltage drop on the lower terminal of the inductance. The lower terminal of the parasitic inductance Lp_hs is the voltage on the drain of the HS transistor. As explained below, by monitoring the voltage on the drain of the HS transistor, it may be determined how rapidly I_hs is increasing as the HS transistor turns on. The adaptive high side gate driver compares the voltage on the drain of the HS transistor to a threshold. If the drain voltage of the HS transistor exceeds a threshold indicating that excessive ringing is likely to occur on I_hs and the switch node 110, then in the next switching cycle the adaptive high side gate driver reduces the drive current to the gate of the HS transistor during a second phase 312 (FIG. 3). The adaptive high side gate driver continues to reduce the drive current to the gate of the HS transistor in each subsequent switching cycle until the voltage on the drain of the HS transistor no longer exceeds the threshold.

[0020] Figure 4 is a schematic diagram illustrating an example of an adaptive high side gate driver that may be used to implement the gate driver 102 of Figure 1. The right side of the schematic shows an HS transistor coupled to a LS transistor at the switch node 110. The adaptive high side gate driver 400 includes a sense circuit 402, a logic circuit 404, a counter 406, a programmable drive strength circuit 408, a switch node transition detection circuit 410, an OR gate 412, NAND gates 441-444, a one shot 430, and a decoder 432. The description of the driver 400 is given below with reference to the three phases of the turn-on process of the HS transistor.

[0021] As mentioned above, the initial phase is a fixed (but short) period during which a relatively high level of drive current is provided to the gates of the HS transistors. The HS_EN signal is coupled to an input of one shot 430. One shot 430 has an output coupled to an input of OR gate 412. The output of OR gate 412 (and signal 415 on the output of the OR gate) is coupled to an "all select" input of decoder 432. Decoder 432 has a number of outputs, each of which is coupled to an input of a respective NAND gate 441-444. The other inputs of NAND gates 441-444 receive the HS_EN signal. Programmable drive strength circuit 408 includes a number of PFETs 451-454. The outputs of NAND gates 441-444 are coupled to the gates of the respective PFETs 451-454. The output signals from NAND gates 441-444 are logic low in response to both inputs of the gate being logic high. Thus, when HS_EN is logic high (causing the adaptive high side gate driver 400 to begin turning on the HS transistors), the output of the NAND gates 441-444 will be logic low in response to the output of the respective decoder being asserted high, thereby turning on that particular PFET 451-454. When a given PFET 451-454 is on, drive current flows through the PFET to the gate of the HS transistor. Thus, the decoder 432 turns on one or more of the PFETs 451-454, thereby controlling the amount of drive current to the gate of the HS transistor.

[0022] In response to a rising edge on HS_EN (which initiates the turn-on process of the HS transistors), one shot 430 generates an output pulse (logic high) for a duration implemented by the one shot. In one example, the width of the one shot's output pulse is 2ns, but may be other than 2ns if desired. The width of the one shot's output pulse is the amount of time that approximates the time it takes to increase the Vgs of the HS transistors from 0V to their threshold voltages. The short duration positive output pulse from one shot 430 results in a similar output pulse for signal 415 on the output of OR gate 412 (the other input of OR gate 412 is logic low at this point in the cycle). The short duration pulse on signal 415 is received by decoder 432 on its "all select" input, and in response, all of the decoder's output signals to NAND gates 441-444 are asserted high. At this point, both inputs of all NAND gates 441-444 are logic high, which causes the output signals from the NAND gates 441-444 to the gates of all PFETs 451-454 in the programmable driver strength circuit 408 to be logic low, thereby turning on all of the PFETs 451-454 and providing a large drive current (the maximum current that the programmable drive strength circuit 408 can generate) to the gates of the HS transistors.

[0023] During this initial phase, the high level drive current provided by the programmable driver strength circuit 408 to the gate of the HS transistor rapidly raises the Vgs of the HS transistor towards the threshold voltage of the HS transistor. The one-shot output pulse then transitions low again, causing the output signal 415 from the OR gate 414 to become a logic low. The signal 415 going logic low coincides with the end of the first phase 311 and the beginning of the second phase 312.

[0024] The second phase 312 begins with the decoder 432 switching from turning on all of the PFETs 451-454 to turning on only a subset of the PFETs according to the count value CNT1 from the counter 406. By turning on some but not all of the PFETs 451-454, the magnitude of the drive current to the gate of the HS transistor is reduced (shown as 306 in FIG. 3). During the second phase 312, the Vgs of the HS transistor reaches a threshold voltage and drain current begins to flow through the HS transistor. The sense circuit 402 includes a capacitor C1 and resistors R1 and R2. C1 is coupled between VIN and thus the drain 427 of the HS transistor and R1. Node A is the connection point between C1 and R1. The combination of C1 and R1 forms a high pass filter for high pass filtering the voltage on the drain of the HS transistor. As mentioned above, a sudden inrush of drain current to the gate of the HS transistor causes a voltage drop on the drain of the HS transistor (whose magnitude is proportional to the rate of change of current through the HS transistor) due to the parasitic inductance Lp_HS (Figure 1).

[0025] The logic circuit 404 includes comparators 421 and 422, a dual latch 424, an exclusive NOR gate 426, and a flip-flop 428. In this example, the comparators 421 and 422 are current comparators, but in other embodiments may be implemented as voltage comparators. In this example, the positive inputs (+) of the comparators 421 and 422 are coupled together and to a resistor R2. The voltage of the positive input comparator is approximately constant. Thus, the current through R2, I_R2, is a function of the voltage on node A, which is the filtered output of the high pass filter that includes C1 and R1. As the voltage on the drain of HS decreases rapidly, the voltage on node A also decreases rapidly. As a result of the drop in the voltage on node A, the current I_R2 increases.

[0026] Comparator 421 compares current I_R2 to a reference current IREF1. Comparator 422 compares current I_R2 to a reference current IREF2. In one embodiment, IREF2 is a current greater than IREF1. COMP1 is an output signal from comparator 421 and COMP2 is an output signal from comparator 422. In response to I_R2 being greater than IREF2, comparator 422 asserts COMP2 to a logic high state. In response to I_R2 being less than IREF2, comparator 422 forces COMP2 to a logic low state. Similarly, in response to I_R2 being greater than IREF1, comparator 421 asserts COMP1 to a logic high state. In response to I_R2 being less than IREF1, comparator 421 forces COMP1 to a logic low state. Thus, COMP1 and COMP2 indicate whether I_R2 is above both reference currents, below both reference currents, or between the reference currents.

[0027] I_R2 greater than both reference currents indicates that the drain current through the HS transistor is increasing at a high enough rate that excessive ringing on the switch node 110 is likely, and so the drive current to the gate of the HS transistor should be reduced. i_R2 less than IREF2 and greater than IREF1 (i.e., i_R2 is in the range between the reference currents) indicates that the rate of change of the HS transistor's drain current (i_hs) is not large enough to create harmful switch node voltage ringing, and the drive current should not be changed. I_R2 below both reference currents indicates that harmful switch node voltage ringing is unlikely, but that the magnitude of the drive current to the gate of the HS transistor may be increased to speed up the turn-on process of the HS transistor without also creating excessive switch node voltage ringing.

[0028] COMP1 and COMP2 are latched by dual latch 424. The signal into the clock input of dual latch 424 is L2H, which is the output signal from comparator 461 in switch node transition detection circuit 410 (described below). Comparator 461 compares the switch node voltage Vsw with a reference voltage (approximately 0V) to detect when Vsw is rising. Signal L2H is the output signal from comparator 461 and is therefore asserted high (point 309 in FIG. 3) in response to Vsw starting to rise.

[0029] The latched COMP2 signal is coupled to an up / down control input of a counter 406. A logic low on the latched COMP2 signal on the up / down control input causes the counter 406 to count up (i.e., increment its output count value CNT1). Alternatively, a logic high on the latched COMP2 signal on the up / down control input causes the counter 406 to count down (decrement CNT1). The counter 406 is clocked in response to a rising edge on the counter's clock input, and the clock signal to the counter is provided by the Q output of a flip-flop 428. A data (D) input of the flip-flop 428 is coupled to the output of an exclusive-NOR gate 426. The latched COMP1 and COMP2 signals are coupled to the inputs of the exclusive-NOR gate 426. The output signal UPDATE from the exclusive-NOR gate 426 is a logic 0 when its inputs have opposite polarities (one input is 0 and the other input is 1). Otherwise (both inputs are 0 or both inputs are 1), UPDATE becomes logic 1. UPDATE being logic 1 indicates that (a) I_R2 is too large and the drive current to the HS transistor should be reduced during the second phase of the subsequent cycle of the turn-on process for the HS transistor, or (b) I_R2 is too small and the drive current to the gate of the HS transistor should be increased. UPDATE being logic 0 indicates that the drive current to the gate of the HS transistor should not be changed.

[0030] Flip-flop 428 is clocked by a signal labeled HS_ON. HS_ON is asserted high in response to the HS transistor being fully on, for example when its gate-source voltage reaches its maximum value, thereby indicating that the switch node voltage Vsw has reached and settled at a value near the input voltage Vin. HS_EN is connected to the active-low CLR input, which, when asserted low, resets the Q output (provided to the clock input of counter 406). In some embodiments, flip-flop 428 is replaced by an AND gate with UPDATE and HS_ON on its inputs. UPDATE is a logic 1 and is clocked through flip-flop 428 to clock counter 406, thereby incrementing or decrementing the counter's output count value CNT1, when I_R2 is greater than both reference currents IREF1 and IREF2, or when I_R2 is less than both reference currents. In one example, counter 406 is a 3-bit counter, and therefore CNT1 is a 3-bit binary value, however, counter 406 may be a 2-bit or greater than 3-bit counter in other embodiments.

[0031] The counting direction of counter 406 is controlled by the latched COMP2 signal on the counter's up / down control input. COMP2 is high in response to I_R2 being greater than IREF2. IREF2 is greater than IREF1, so COMP2 being logic high indicates that I_R2 is greater than both reference currents. In response to COMP2 being logic high, counter 406 is configured to count down, thereby decrementing CNT1 the next time the counter is clocked. In response to COMP2 being logic low, counter 406 is configured to count up, thereby incrementing CNT1 the next time the counter is clocked.

[0032] 4, decoder 432 converts the binary CNT1 count value on its select input to a thermometric code and provides the thermometric code to NAND gates 441-444. In one example, programmable drive strength circuit 408 includes eight PFETs, with a NAND gate 441-444 for each of the eight PFETs. The three-bit CNT1 value, in this example, is converted by decoder 432 from an eight-bit thermometric code (minimum 1) to eight NAND gates, thereby individually turning the eight PFETs on or off. For example, if CNT1 is a decimal 6 (110 in binary), then the gate signals to seven of the eight PFETs (6+minimum 1) are pulled low (the remaining gate signals are logic high) to turn on the seven PFETs. If CNT1 is decimal 2 (010 in binary), then the gate signals to three of the eight PFETs (2 + min 1) are pulled low (the remaining five gate signals are logic high), turning on only three of the eight PFETs.

[0033] Once the HS transistors are fully on, upon high assertion of L2H from comparator 461, COMP1 and COMP2 are latched via dual latch 424. The latched COMP1 and COMP2 signals are then used to control counter 406 to cause a change in CNT1 (if I_R2 is greater than both reference currents or less than both reference currents), thereby increasing the drive current of the HS transistors (if I_R2 is less than both reference currents) or decreasing the drive current (if I_R2 is greater than both reference currents). If I_R2 is between the IREF1 and IREF2 reference currents, the UPDATE from the exclusive NOR gate is logic 0, the output of flip-flop 428 is logic 0, and counter 406 is not clocked; if counter 406 is not clocked, there is no update to CNT1 and the drive current strength remains unchanged.

[0034] During the second phase 312 of the HS transistor turn-on process, the programmable drive strength circuit 408 is configured to adjust the magnitude of the drive current to the gate of the HS transistor based on the count value CNT1 from the counter 406. The example of FIG. 4 includes a decoder 432 that converts the binary count value CNT1 into a thermometric code for turning the PFETs 451-454 on and off. The PFETs are approximately equal in size, so that approximately the same amount of current flows through each PFET (when "on") to the gate of the HS transistor. In another embodiment, the PFETs 451-454 may be binary weighted, so that the drive current through one PFET is 1×, the drive current through another PFET is 2×, the drive current through another PFET is 4×, and so on. In an embodiment in which the PFETs 451-454 are binary weighted, the decoder may be omitted and the binary count value CNT1 may be provided to the NAND gates 441-444.

[0035] In response to switch node transition detection circuit 410 detecting a rise in switch node voltage Vsw, second phase 312 ends and third phase 313 begins. Switch node transition detection circuit 410 generates output signal 467 to an input of OR gate 412. When asserted high, output signal 467 causes (via OR gate 412 and NAND gate 414) signal 415 to become logic high again (signal 415 was logic high during first phase 311 and then low during second phase 312). When signal 415 is logic high, decoder 432 responds (as it did during first phase 311) by turning on all of PFETs 451-454 in programmable drive strength circuit 408, thereby allowing a larger drive current (310 in FIG. 3) to flow to the gate of the HS transistor.

[0036] The switch node transition detection circuit 410 includes a comparator 461, a driver delay compensation circuit 462, a flip-flop 463, a counter 464, a delay line 465, and a multiplexer 466. As described above, the comparator 461 asserts the L2H signal to a logic high state, thereby indicating that Vsw is increasing. The L2H signal from the comparator 461 is coupled to the D input of the flip-flop 463. The driver delay compensation circuit 462 is a delay element (e.g., one or more series-connected buffers, inverters, etc.) that drives the clock input of the flip-flop 463. The flip-flop 463 determines the count direction (up or down) of the counter 464. The counter 464 is clocked every switching cycle by HS_ON, and its output CNT2 determines the length of the delay line 465 via the multiplexer 466. The output 467 of multiplexer 466 is delayed HS_EN by delay line 465 and coupled to an input of OR gate 412 (external to switch node transition detection circuit 410) and an input of driver delay compensation circuit 462. The output 467 of multiplexer 466 is asserted logic high to initiate phase 313. Collectively, the elements of switch node transition detection circuit 410 implement a time loop.

[0037] The purpose of the time loop created by the switch node transition detection circuit 410 is to match all engagements of the PFETs 451-454 in the programmable drive strength circuit 408 to the rising voltage of the switch node 110 so that a comparison can be made. However, simply comparing the output 467 of the multiplexer 466 with the output of the comparator 461 (L2H) is not sufficient as the output 467 will generally lead to L2H being asserted and therefore always asserting L2H. Therefore, a time correction is implemented by the driver delay compensation circuit 462. The amount of delay added to the signal 467 by the driver delay compensation circuit 462 takes into account the total propagation delay of the signal 467 through the OR gate 412, the decoder 432, the NAND gates 441-444, the programmable drive strength circuit 408 to gate signals to the HS FETs, and the delay of the comparator 461. The driver delay compensation circuit 462 may be implemented using a chain of serially connected logic gates to match the delays of the above elements. Given the minimum variability in the above-mentioned total propagation delay of signal 467, driver delay compensation circuit 462 generates a corresponding rising edge on the clock input to flip-flop 463 that occurs when the third phase 313 should begin.

[0038] Flip-flop 463 has outputs Q and Qbar output. In this example, the Qbar output of flip-flop 463 is used. When the output signal from driver delay compensation circuit 462 clocks flip-flop 463, the Qbar output from the flip-flop is either 0 or 1. If Vsw has started to rise (L2H is 1) when flip-flop 463 clocks, the Qbar output will be 0. Otherwise, if Vsw has not yet started to rise (L2H is 0) when the flip-flop clocks, the Qbar output will be 1. Thus, flip-flop 463 acts as a time comparator, and the logic state of the Qbar output indicates whether Vsw has started to rise when the third phase 313 is expected to begin.

[0039] The Qbar output of flip-flop 463 is coupled to an up / down control input of counter 464. Counter 464 is an up / down counter that increments its output count value CNT2 in response to a logic state of 1 at the up / down control input and decrements CNT2 in response to a logic state of 0 at the up / down control input.

[0040] Delay line 465 includes a number of serially connected delay elements 465a-465d. There may be any number of delay elements. In one example, each delay element 465a-465d implements a delay of 250 picoseconds (ps). The input to delay line 465 is HS_EN. The output signal from delay element 465a is HS_EN delayed by 250 ps. Delay element 465b adds an additional 250 ps delay, so the output signal from delay element 465b is HS_EN delayed by 500 ps, ​​and so on.

[0041] The junctions between adjacent delay elements in the delay line 465 are tapped and provided to the inputs of a multiplexer 466. The output count value CNT2 of the counter is the select signal of the multiplexer 466. When CNT2 increments, the output signal from the subsequent delay (larger delay) element 465a-465d is selected as the output signal of the multiplexer. When CNT2 decrements, the output signal from the previous delay (smaller delay) element 465a-465d is selected as the output signal of the multiplexer.

[0042] The clock input to counter 464 is HS_ON (described above). When the HS transistor is fully turned on, HS_ON is asserted high, clocking counter 464 to increment or decrement CNT2. If Vsw is not starting to rise (L2H is 0) when flip-flop 463 is clocked, the up / down control input of counter 464 will be 1, which causes counter 464 to count up. If Vsw is starting to rise (L2H is 1) when flip-flop 463 is clocked, the up / down control input of counter 464 will be 0, which causes counter 464 to count down. The amount of time delay between the rising edge of HS_EN and the rising edge of the multiplexer output signal 467 is adjusted to increment until the time delay is equal to the duration of the second phase 312. If so, a positive assertion of signal 467 from multiplexer 466 causes decoder 432 to turn on all of PFETs 451 - 454 in the programmable drive strength circuit during the third phase 313 .

[0043] As counter 464 counts up and increases the time delay, eventually the flip-flop will clock at a point when Vsw has already started to rise, meaning the D input of the flip-flop will be 1, the Qbar output will be 0, and the s up / down control input of the counter will be 0. If the up / down control input is 0, the counter is configured to count down at that point. Counter 464 may toggle between being configured as an up counter and a down counter with each subsequent switching cycle. However, the amount of time delay (e.g., 250 ps) of delay elements 465a-465d is small enough that repeatedly changing the starting point of the third phase 313 is not enough to substantially increase the ringing on switch node 110.

[0044] In this description, the term "couple" may encompass a connection, communication, or signal path that enables a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action, then (A) in a first example, device A is coupled to device B by a direct connection, or (b) in a second example, device A is coupled to device B via an intervening component C, where intervening component C does not change the functional relationship between device A and device B, such that device B is controlled by device A via a control signal generated by device A.

[0045] A device that is "configured to" perform a certain task or function may be configured (e.g., programmed and / or hardwired) at the time of manufacture by a manufacturer to perform that function and / or may be configurable (or reconfigurable) by a user after manufacture to perform that function and / or other additional or alternative functions. Such configuration may be through firmware and / or software programming of the device, through the construction and / or layout of the hardware components, through the interconnections of the device, or through a combination thereof.

[0046] As used herein, the terms "terminal," "node," "interconnect," "pin," and "lead" are used interchangeably. Unless otherwise noted, these terms are used generally to mean an interconnection between, or the termination of, a device element, a circuit element, an integrated circuit, a device, or other electronic or semiconductor component.

[0047] A circuit or device described herein as including certain components may instead be adapted to be coupled to those components to form the described circuit or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current sources) may instead include only the semiconductor elements in a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and / or sources during or after manufacture, e.g., by an end user and / or a third party, to form the described structure.

[0048] Although the use of particular transistors is described herein, other transistors (or equivalent devices) may be substituted. For example, a p-channel field effect transistor ("PFET") may be replaced with an NFET with little or no change to the circuit. Also, other types of transistors may be used, such as bipolar junction transistors (BJTs).

[0049] As used herein, a reference to a field effect transistor (FET) being "on" means that the FET's conductive channel is present and drain current is flowing through the FET. As used herein, a reference to a FET being "off" means that the FET's conductive channel is not present and drain current is not flowing through the FET. However, an "off" FET may have current flowing through the transistor's body diode.

[0050] The circuits described herein are reconfigurable to include additional or different components to provide functionality at least partially similar to that available prior to component replacement. A component shown as a resistor generally represents any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the resistor shown, unless otherwise indicated. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as a single resistor or capacitor.

[0051] Use of the term "ground" in the preceding description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable or suitable for the teachings of this description. As used herein, unless otherwise specified, "about," "approximately," or "substantially" preceding a parameter means within + / - 10% of that parameter.

[0052] Modifications may be made to the exemplary embodiments described, and other embodiments are possible, within the scope of the invention.

Claims

1. A device comprising: a sensing circuit having a sensing circuit output; a logic circuit having a logic circuit input coupled to the sense circuit output, a first logic circuit output, and a second logic circuit output, the logic circuit including an exclusive-OR gate having a gate output coupled to the first logic circuit output; a first counter having a first counter input coupled to the first logic circuit output, a second counter input coupled to the second logic circuit output, and a counter output, the first counter being configured to provide a count value at the counter output; a drive circuit having a drive circuit input coupled to the counter output, the drive circuit configured to generate a drive current based on the count value; Including, the device.

2. 2. The device of claim 1, The device further includes a decoder coupled between the counter output and the driver circuit input.

3. 2. The device of claim 1, The logic circuit comprises: Detecting whether a rate of change of a drain current of the transistor exceeds a threshold value; adjusting the first logic circuit output or the second logic circuit output to change the count value in response to the rate of change of the drain current exceeding the threshold. The device is configured to:

4. 2. The device of claim 1, The logic circuit comprises: Detecting whether a signal indicative of a rate of change of a drain current of the transistor exceeds first and second thresholds; adjusting the first logic circuit output or the second logic circuit output to increment the count value in response to the signal exceeding the first and second thresholds; adjusting the first logic circuit output or the second logic circuit output to decrement the count value in response to the signal falling below the first and second thresholds. The device is configured to:

5. 5. The device of claim 4, wherein the logic circuit comprises: The device is further configured to, in response to the signal being between the first threshold and the second threshold, adjust the first logic circuit output or the second logic circuit output to prevent the first counter from incrementing or decrementing the count value.

6. 2. The device of claim 1, The device, wherein the sensing circuit includes a high pass filter.

7. 2. The device of claim 1, The logic circuit comprises: a first comparator having a comparator output coupled to the second logic circuit output and first and second comparator inputs; a second comparator having a second comparator output and third and fourth comparator inputs; a flip-flop having a flip-flop input coupled to a gate output of the exclusive-OR gate and a flip-flop output coupled to the first logic circuit output; The device further comprises:

8. 2. The device of claim 1, The logic circuit comprises: Detecting whether a rate of change of a drain current of the transistor exceeds a threshold value; adjusting the first logic circuit output or the second logic circuit output to change the count value in response to the rate of change of the drain current exceeding the threshold. It is configured as follows: the drive circuitry is further configured to reduce the dynamic current in response to the changed count value; The device, A switch node transition detection circuit, comprising: Detecting whether the transistor is turned on; providing a signal to the logic circuit in response to detecting that the transistor is turned on; The switch node transition detection circuit further includes a switch node transition detection circuit configured to: The device, wherein the drive circuit is further configured to increase the drive current at a control terminal of the transistor in response to the provided signal.

9. 2. The device of claim 1, a comparator having a comparator output; a delay circuit having a delay circuit output; a flip-flop having a first flip-flop input coupled to the delay circuit output, a second flip-flop input coupled to the comparator output, and a flip-flop output; The device further comprises:

10. 10. The device of claim 9, The device further includes a second counter having a third counter input coupled to the flip-flop output.

11. A device comprising: a sensing circuit having a sensing circuit output; a first comparator having a first comparator output and a first comparator input coupled to the sense circuit output; a second comparator having a second comparator output and a second comparator input coupled to the sense circuit output; a logic gate having a logic gate output, a first logic gate input coupled to the first comparator output, and a second logic gate input coupled to the second comparator output; a first counter having a first counter input coupled to the logic gate output, a second counter input coupled to the second comparator output, and a first counter output; a first flip-flop having a first flip-flop output; a second counter having a third counter input coupled to the first flip-flop output and a second counter output; a driver circuit having a driver circuit input coupled to the first counter output and to the second counter output; Including, the device.

12. 12. The device of claim 11, The device, wherein the logic gate is an exclusive OR gate.

13. 12. The device of claim 11, The device further includes a second flip-flop having a second flip-flop input coupled to the logic gate output.

14. 12. The device of claim 11, The device, wherein the sensing circuit includes a high pass filter.

15. 12. The device of claim 11, a delay circuit having a delay circuit input coupled to the first counter output and a delay circuit output coupled to the driver circuit input.

16. A device comprising: a sensing circuit having a sensing circuit output; a logic circuit having a logic circuit input coupled to the sensing circuit output and first and second logic circuit outputs; a driver circuit having a driver circuit input and a driver circuit output; a counter having a first counter input coupled to the first logic circuit output, a second counter input coupled to the second logic circuit output, and a counter output coupled to the driver circuit input, the counter being configured to provide a count value at the counter output; Including, during a first phase, the drive circuit is configured to provide a fixed level of drive current to the drive circuit output; During a second phase, the drive circuit is configured to provide a variable level of the drive current at the drive circuit output.

17. 17. The device of claim 16, a decoder coupled between the counter output and the driver input, the decoder configured to convert the count value into a signal; The device, wherein the driver circuit is further configured to receive the signal at the driver circuit input.

18. 17. The device of claim 16, The logic circuit comprises: Detecting whether a rate of change of a drain current of the transistor exceeds a threshold value; adjusting the first logic circuit output or the second logic circuit output to change the count value in response to the rate of change of the drain current exceeding the threshold. The device is configured to:

19. 17. The device of claim 16, The logic circuit comprises: Detecting whether a signal indicative of a rate of change of a drain current of the transistor exceeds first and second thresholds; adjusting the first logic circuit output or the second logic circuit output to increment the count value in response to the signal exceeding the first and second thresholds; adjusting the first logic circuit output or the second logic circuit output in response to the signal falling below the first and second thresholds to decrement the count value. The device is configured to:

20. 17. The device of claim 16, a comparator having a comparator output; a delay circuit having a delay circuit output; a flip-flop having a clock input coupled to said delay circuit output, a data input coupled to said comparator output, and an output; The device further comprises:

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