Multilayer inductor having discrete metal laminate patterns

Abstract

The inductor includes a first metallization layer multi-turn trace. The inductor also includes a second metallization layer multi-turn trace coupled to the first metallization layer multi-turn trace through at least one first via. The inductor further includes a plurality of discrete third metallization layer trace segments coupled to the second metallization layer multi-turn trace through a plurality of second vias.

Description

Claiming priority

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. patent application Ser. No. 17 / 195,220, filed March 8, 2021, and entitled "STACKED INDUCTOR HAVING DISCRETE METAL-STACK PATTERN," the disclosure of which is expressly incorporated by reference in its entirety. [Technical field]

[0002] Aspects of the present disclosure relate to semiconductor devices, and more particularly, to stacked inductors having a discrete metal-stack pattern. [Background technology]

[0003]

[0003] Wireless communication devices incorporate radio frequency (RF) modules that facilitate the communications and features that users expect. As wireless systems become more prevalent and include more capabilities, chips have become more complex to produce. Fifth generation (5G) new radio (NR) wireless communication devices incorporate the latest generation of electric dies, packing many features and devices into modules that are smaller and have smaller and smaller interconnects. As the density of these modules increases, inductors are critical to performance and can occupy significant area on the die.

[0004]

[0004] Design challenges for mobile radio frequency (RF) chips, such as mobile RF transceivers, include analog / RF performance considerations, including mismatch, noise, and other performance considerations. The design of these mobile RF transceivers includes the use of passive devices, such as inductors, to suppress resonances, and / or for filtering, bypassing, and coupling. These inductors are integrated into high power system-on-chip devices, such as application processors and graphics processors.

[0005]

[0005] In this example, the passive devices of the mobile RF transceiver may include high performance inductor components. For example, analog integrated circuits use various types of passive devices, such as integrated inductors. The use of integrated inductors may consume significant area on a laminate or package substrate and may also lead to higher insertion loss and lower quality (Q) factors. It is desirable to improve the key performance indicators (KPIs) of the integrated inductors to provide higher Q factors while providing improved heat dissipation. The integrated inductors may be used for millimeter wave (mmW) filters in 5G NR RF modules. Summary of the Invention

[0006]

[0006] The inductor includes a first metallization layer multi-turn trace. The inductor also includes a second metallization layer multi-turn trace coupled to the first metallization layer multi-turn trace through at least one first via. The inductor further includes a plurality of discrete third metallization layer trace segments coupled to the second metallization layer multi-turn trace through a plurality of second vias.

[0007] A method for fabricating a stacked inductor having a discrete metal-stack pattern is described. The method includes forming a first metallization layer multi-turn trace. The method also includes forming a second metallization layer multi-turn trace coupled to the first metallization layer multi-turn trace through at least one first via. The method further includes forming a plurality of discrete third metallization layer trace segments coupled to the second metallization layer multi-turn trace through a plurality of second vias.

[0008] A radio frequency front-end (RFFE) module is described. The RFFE module includes a semiconductor die and an integrated passive device (IPD) filter die coupled to the semiconductor die. The IPD die is comprised of an inductor. The inductor includes a first metallization layer multi-turn trace. The inductor also includes a second metallization layer multi-turn trace coupled to the first metallization layer multi-turn trace through at least one first via. The inductor further includes a plurality of discrete third metallization layer trace segments coupled to the second metallization layer multi-turn trace through a plurality of second vias.

[0009]

[0009] This section outlines rather broadly the features and technical advantages of the present disclosure in order that the detailed description that follows may be better understood. Additional features and advantages of the present disclosure will be described below. It should be appreciated by those skilled in the art that this disclosure may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present disclosure. Such equivalent structures should also be realized by those skilled in the art without departing from the teachings of the present disclosure as set forth in the appended claims. The novel features believed to be characteristic of the present disclosure, both as to its organization and method of operation, together with further objects and advantages, will be better understood from the following description when considered in conjunction with the accompanying figures. It should be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only, and is not intended as a definition of the limits of the present disclosure.

[0010] For a more complete understanding of the present disclosure, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: [Brief description of the drawings]

[0011] [Figure 1] 1 is a schematic diagram of a radio frequency front-end (RFFE) module employing passive devices. [Diagram 2]

[0012] Schematic diagram of a radio frequency front-end (RFFE) module employing passive devices for a chipset. [Diagram 3]

[0013] FIG. 1 is a block diagram illustrating a cross-sectional view of a radio frequency front-end (RFFE) module including a semiconductor die and an integrated passive device (IPD) filter die, in accordance with an embodiment of the present disclosure. [Figure 4A]

[0014] FIG. 2 is a block diagram illustrating a top view of a stacked inductor having a discrete metal stack pattern, according to an aspect of the present disclosure. [Figure 4B]FIG. 2 is a block diagram illustrating a perspective view of a stacked inductor having a discrete metal stack pattern according to an aspect of the present disclosure. [Diagram 5]

[0015] FIG. 2 illustrates an overhead view of a stacked inductor having a discrete metal stack pattern, according to an aspect of the present disclosure. [Figure 6A]

[0016] 1 is a perspective view illustrating a stacked inductor having a discrete metal stack pattern according to an aspect of the present disclosure. [Figure 6B] 1 is a cross-sectional view illustrating a stacked inductor having a discrete metal stack pattern according to an aspect of the present disclosure. [Figure 7A]

[0017] 6B is an inductance versus frequency graph of a laminated inductor having the discrete metal laminate pattern of FIG. 6A according to an embodiment of the present disclosure. [Figure 7B] 6B is a quality factor versus frequency graph of a stacked inductor having the discrete metal stack pattern of FIG. 6A according to an embodiment of the present disclosure. [Figure 8]

[0018] FIG. 2 is a process flow diagram illustrating a method for fabricating a stacked inductor having a discrete metal stack pattern according to an aspect of the present disclosure. [Figure 9]

[0019] FIG. 1 is a block diagram illustrating an example wireless communication system in which the configurations of the present disclosure may be advantageously employed. [Figure 10]

[0020] 1 is a block diagram illustrating a design workstation used for circuit, layout, and logic design of semiconductor components according to one configuration. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012]

[0021] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be implemented. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be implemented without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0013]

[0022] As explained herein, the use of the term "and / or" is intended to indicate an "inclusive or" and the use of the term "or" is intended to indicate an "exclusive or". As explained herein, the term "exemplary" as used throughout this description means "serving as an example, instance, or illustration" and should not necessarily be construed as preferred or advantageous over other exemplary configurations. As explained herein, the term "coupled" as used throughout this description means "connected electrically, mechanically, or otherwise, whether directly or indirectly through an intervening connection (e.g., a switch)" and is not necessarily limited to a physical connection. Also, the connection can be such that objects are permanently connected or removably connected. The connection can be through a switch. As explained herein, the term "proximate" as used throughout this description means "adjacent, very close, next to, or in close proximity". As explained herein, the term "on" as used throughout this description means "directly on" in some configurations and "indirectly on" in other configurations.

[0014]

[0023] Mobile radio frequency (RF) chips (e.g., mobile RF transceivers) have migrated to deep sub-micron processing nodes due to cost and power consumption considerations. Designing mobile RF transceivers is complicated by the addition of circuit functionality to support improved communications, such as fifth-generation (5G) new radio (NR) communication systems. Additional design challenges for mobile RF transceivers include the use of passive devices, which directly impact analog RF performance considerations, including mismatch, noise, and other performance considerations.

[0015]

[0024] Passive devices in mobile radio frequency (RF) transceivers may include high performance inductor components. For example, analog integrated circuits use various types of passive devices, such as integrated inductors. An inductor is an example of an electric device used to temporarily store energy in a magnetic field in a wire coil according to an inductance value. This inductance value provides a measure of the ratio of voltage to the rate of change of current passing through the inductor. When the current flowing through the inductor changes, energy is temporarily stored in the magnetic field in the coil. In addition to their magnetic field storage capabilities, inductors are often used in alternating current (AC) electronic devices, such as wireless devices. For example, mobile RF transceiver designs include the use of inductors with improved inductance density while reducing magnetic losses at millimeter wave (mmW) frequencies (e.g., Frequency Range 2 (FR2)).

[0016]

[0025] A radio frequency front-end (RFFE) module may include a 5G broadband FR2 filter that includes a capacitor and an inductor. Unfortunately, the integrated inductor in the 5G broadband FR2 filter may suffer from a degraded quality (Q) factor. The integrated inductor may also cause heat dissipation issues in the 5G broadband FR2 filter. During operation of the 5G NR broadband FR2 filter, the power dissipation is related to the Q factor of the inductor. The heat dissipation is also related to both the Q factor of the inductor and the electromigration (EM) of the inductor. The inductor may be formed with a stack of back-end-of-line (BEOL) metallization layers, but the inductance value is reduced as the stack increases.

[0017]

[0026] Various aspects of the present disclosure provide a stacked inductor having a discrete metal stack pattern. The process flow for fabrication of a stacked inductor having a discrete metal stack pattern may include front-end-of-line (FEOL), middle-of-line (MOL), and back-end-of-line (BEOL) processing. It will be understood that the term "layer" includes a film and is not to be construed as indicating a vertical or horizontal thickness unless otherwise specified. As described, the term "substrate" may refer to a substrate of a diced wafer or may refer to a substrate of an undiced wafer. Similarly, the terms "chip" and "die" may be used interchangeably.

[0018]

[0027] As described, a back-end-of-line (BEOL) interconnect layer may refer to a conductive interconnect layer (e.g., first interconnect layer (M1), or metal 1 M1, metal 2 (M2), metal 3 (M3), metal 4 (M4), etc.) for electrically coupling to a front-end-of-line (FEOL) active device of an integrated circuit. Various BEOL interconnect layers are formed in a corresponding BEOL interconnect layer, in which a lower BEOL interconnect layer uses a thinner metal layer relative to a higher BEOL interconnect level. A BEOL interconnect layer may be electrically coupled to a middle-of-line (MOL) interconnect layer, for example, to connect M1 to an oxide diffusion (OD) layer of the integrated circuit. The MOL interconnect layer may include a zero interconnect layer (M0) for connecting M1 to an active device layer of the integrated circuit. A first via (V2) in the BEOL may connect M2 to M3 or other layers of the BEOL interconnect layer.

[0019]

[0028] According to aspects of the present disclosure, a radio frequency front-end (RFFE) module includes a filter configured with a stacked inductor having a discrete metal stack pattern. Aspects of the present disclosure improve key performance indicators (KPIs) of the inductor in the broadband filter by implementing an improved metal stack pattern to provide a special design for a 5G NR broadband FR2 filter. The special design improves the inductor metal layer by providing a novel inductor metal stack pattern. This special design may reconfigure the metal thickness in current-congested areas of the broadband filter. In some aspects of the present disclosure, this special design may add more metal layers to thermal hot spots of the broadband filter. Some aspects of the present disclosure provide customized metal stack patterns to provide the desired on-inductance of the inductor. These customized metal stack patterns beneficially improve the electrical performance of the broadband filter while improving thermal mitigation.

[0020]

[0029] 1 is a schematic diagram of a radio frequency front-end (RFFE) module 100 employing passive devices including an inductor 118 (e.g., a stacked inductor having a discrete metal stack pattern). The RFFE module 100 includes a power amplifier 102, a diplexer / filter 104, and a radio frequency (RF) switch module 106. The power amplifier 102 amplifies the signal to a certain power level for transmission. The diplexer / filter 104 filters the input / output signal according to a variety of different parameters, including frequency, insertion loss, rejection, or other similar parameters. The RF switch module 106 may also select certain portions of the input signal to pass to the remainder of the RFFE module 100.

[0021]

[0030] The radio frequency front-end (RFFE) module 100 also includes tuner circuitry 112 (e.g., first tuner circuitry 112A and second tuner circuitry 112B), a diplexer 190, a capacitor 116, an inductor 118, a ground terminal 115, and an antenna 114. The tuner circuitry 112 (e.g., first tuner circuitry 112A and second tuner circuitry 112B) includes components such as a tuner, a portable data entry terminal (PDET), and a housekeeping analog to digital converter (HKADC). The tuner circuitry 112 may perform impedance tuning (e.g., voltage standing wave ratio (VSWR) optimization) for the antenna 114. The RFFE module 100 also includes a passive combiner 108 coupled to a wireless transceiver (WTR) 120. The passive combiner 108 combines the detected power from the first tuner circuitry 112A and the second tuner circuitry 112B. The wireless transceiver 120 processes the information from the passive combiner 108 and provides the information to a modem 130 (e.g., a mobile station modem (MSM)). The modem 130 provides a digital signal to an application processor (AP) 140.

[0022]

[0031] As shown in FIG. 1, the diplexer 190 is between the tuner components of the tuner circuitry 112 and the capacitor 116, the inductor 118 (e.g., a stacked inductor having a discrete metal stack pattern), and the antenna 114. The diplexer 190 may be disposed between the antenna 114 and the tuner circuitry 112 to provide high system performance from the radio frequency front end (RFFE) module 100 to a chipset including the wireless transceiver 120, the modem 130, and the application processor 140. The diplexer 190 performs frequency domain multiplexing for both high and low band frequencies. After the diplexer 190 performs its frequency multiplexing function on the input signal, the output of the diplexer 190 is fed to an optional inductor / capacitor (LC) network including the capacitor 116 and the inductor 118. The LC network may provide an additional impedance matching component for the antenna 114, if desired. A signal having a particular frequency is then transmitted or received by antenna 114. Although single capacitors and inductors are shown, multiple components are also envisioned.

[0023]

[0032] 2 is a schematic diagram of a radio frequency integrated circuit (RFIC) chip 200 having a wireless local area network (WLAN) (e.g., Wi-Fi) module 170 including a first diplexer 190-1 and a radio frequency front end (RFFE) module 150 including a second diplexer 190-2 for a chipset 160, the second diplexer including a stacked inductor having a discrete metal stack pattern. The Wi-Fi module 170 includes a first diplexer 190-1 that communicatively couples an antenna 192 to the wireless local area network module (e.g., WLAN module 172). The RFFE module 150 includes a second diplexer 190-2 that communicatively couples an antenna 194 to a wireless transceiver (WTR) 120 through a duplexer 180. The wireless transceiver 120 and the WLAN module 172 of the Wi-Fi module 170 are coupled to a modem (Mobile Station Modem (MSM), e.g., a baseband modem) 130, which is powered by a power source 152 through a power management integrated circuit (PMIC) 156. The chipset 160 also includes capacitors 162 and 164, and an inductor 166 for providing signal integrity.

[0024]

[0033] The power management integrated circuit (PMIC) 156, the modem 130, the wireless transceiver 120, and the wireless local area network (WLAN) module 172 each include a capacitor (e.g., 158, 132, 122, and 174) and operate according to a clock 154. Also, an inductor 166 couples the modem 130 to the PMIC 156. The design of the radio frequency integrated circuit (RFIC) chip 200, according to an aspect of the present disclosure, includes a stacked inductor having a discrete metal stack pattern.

[0025]

[0034] 3 is a block diagram illustrating a cross-sectional view of a radio frequency front-end (RFFE) module 300 including a semiconductor die and an integrated passive device (IPD) filter die according to an embodiment of the disclosure. In this example, the RFFE module 300 includes a semiconductor die 350 and an integrated passive device (IPD) filter die 320 supported by a substrate 310. The semiconductor die 350 may be an active die having a semiconductor substrate 360 ​​(e.g., an active silicon substrate) coupled to package balls 302 through a back-end-of-line (BEOL) layer 370. The BEOL layer 370 includes multiple BEOL metallization layers (M1, M2, M3, ..., Mn) on the semiconductor substrate 360 ​​(e.g., a diced silicon wafer). A redistribution layer 312 is coupled to the package balls 302.

[0026]

[0035] The IPD filter die 320 includes a substrate 330 (e.g., a passive substrate) coupled to package balls 302 through a back-end-of-line (BEOL) layer 340. The redistribution layer 312 is coupled to the IPD filter die 320 through the package balls 302. In some embodiments, the substrate 330 is made of glass and the IPD filter die 320 is a glass-substrate integrated passive device (GIPD) filter die. The IPD filter die 320 may implement a 5G NR broadband FR2 filter. According to an embodiment of the present disclosure, the IPD filter die 320 includes a stacked inductor having a discrete metal stack pattern, as shown in FIG. 4A and FIG. 4B.

[0027]

[0036] 4A and 4B are block diagrams illustrating top and perspective views of a stacked inductor having a discrete metal stack pattern in a broadband filter according to an embodiment of the disclosure. As shown in FIG. 4A, the broadband filter 410 can be the IPD filter die 320 of FIG. 3, such as a radio frequency (RF) filter and / or a radio frequency (RF) module. FIG. 4B illustrates a perspective view of a stacked inductor 420 having a varying discrete metal stack pattern according to an embodiment of the disclosure. For example, the stacked inductor 420 includes a first discrete metal stack pattern 430, a second discrete metal stack pattern 440, and a third discrete metal stack pattern 450 of a multilayer inductor.

[0028]

[0037] In this example, the first discrete metal stack pattern 430 and the third discrete metal stack pattern 450 are composed of M1 and M2 metallization layers. Also, the second discrete metal stack pattern 440 is composed of M1, M2, and M3 metallization layers. The increased thickness of the second discrete metal stack pattern 440 can reduce the inductance while increasing the quality (Q) factor of the stacked inductor 420. The improved Q factor provided by the second discrete metal stack pattern 440 also improves the heat dissipation handling capability while reducing the resistance of the second discrete metal stack pattern 440. In contrast, the first discrete metal stack pattern 430 and the third discrete metal stack pattern 450 have an increased inductance relative to the second discrete metal stack pattern 440. The inductance of the first discrete metal stack pattern 430 is less than the inductance of the third discrete metal stack pattern 450 due to the smaller area of ​​the first discrete metal stack pattern 430 .

[0029]

[0038] In an embodiment of the present disclosure, the stacked inductor 420 is constructed using one or more of the discrete metal stack patterns of FIG. 4B depending on the desired characteristics of the stacked inductor 420. For example, additional discrete metal stack layers may be provided to thermal hot spots of the broadband filter 410 using the second discrete metal stack pattern 440. Also, the metal thickness of the stacked inductor 420 may be adjusted in dense areas of the broadband filter 410 using the third discrete metal stack pattern 450. Similarly, the layers of the stacked inductor 420 may be adjusted, such as reducing the area of ​​the layers, using the first discrete metal stack pattern 430. The discrete metal stack pattern of FIG. 4B allows for improved electrical performance and thermal mitigation of the broadband filter 410 of FIG. 4A.

[0030]

[0039] FIG. 5 illustrates an overhead view of a stacked inductor having a discrete metal stack pattern according to an embodiment of the disclosure. The stacked inductor 500 shown in FIG. 5 is similar to the stacked inductor 420 shown in FIG. 4A and FIG. 4B. In this example, the stacked inductor 500 is constructed with a multi-turn trace including a line trace segment and an angled joint trace segment. The angled joint trace segment is shown at a forty-five degree (45°) angle. The multi-turn trace of the stacked inductor 500 is constructed with an M1 metallization layer, however, the multi-turn trace of the stacked inductor 500 may be constructed with an M2 metallization layer stacked on the M1 metallization layer as shown in FIG. 4B.

[0031]

[0040] In this embodiment of the disclosure, a corner 502 of the stacked inductor 500 is selected for formation of a discrete metal stack pattern. In this example, the corner 502 of the stacked inductor 500 includes an angled joint trace segment and a line trace segment of the stacked inductor 500. The corner 502 is comprised of a first angled joint trace segment 520 between a first line trace segment 510 and a third line trace segment 530 of the stacked inductor 500. In this example, the first angled joint trace segment 520 is also shown with a 45 degree joint and is comprised of the M1 metallization layer. In this embodiment of the disclosure, a second angled joint trace segment 540 is formed from the M2 metallization layer and is laminated onto the first angled joint trace segment 520 to form a discrete metal stack pattern 550.

[0032]

[0041] 6A and 6B are perspective and cross-sectional views illustrating a stacked inductor 600 having a discrete metal stack pattern according to an embodiment of the disclosure. The stacked inductor 600 shown in FIG. 6A is similar to the stacked inductor 500 shown in FIG. 5, including the discrete metal stack pattern. In this embodiment of the disclosure, the stacked inductor 600 includes a stacked multi-turn trace 610 comprised of an M2 metallization layer stacked on an M1 metallization layer that includes a discrete metal stack pattern formed in a predetermined portion. Although shown as including an M2 metallization layer stacked on an M1 metallization layer, the stacked multi-turn trace 610 may be comprised of a single metallization layer, as shown in FIG. 4B.

[0033]

[0042] In this example, a first angled trace segment 630 of the M3 metallization layer is formed on the stacked multi-turn trace 610 proximate the first port 602. Similarly, a second angled joint trace segment 670 of the M3 metallization layer is formed on the stacked multi-turn trace 610 proximate the second port 604 of the stacked inductor 600. The stacked inductor 600 also includes a first angled trace segment 630, a second angled trace segment 640, and a third angled trace segment 660 of the M3 metallization layer formed on the stacked multi-turn trace 610. The stacked inductor 600 further includes a line trace segment 650 of the M3 metallization layer formed on the stacked multi-turn trace 610. Cross-sectional views along cut lines 606 and 608 are shown in FIG. 6B.

[0034]

[0043] 6B is a cross-sectional view illustrating a stacked inductor 600 having a discrete metal stack pattern according to an embodiment of the disclosure. In this example, the cross-sectional view 680 of the stacked inductor 600 illustrates portions of the first angled trace segment 630 and the second angled trace segment 640 along cut lines 606 and 608 of FIG. 6A. In this configuration, the first angled trace segment 630 and the second angled trace segment 640 are coupled to the stacked multi-turn trace 610 through via V2. The stacked multi-turn trace 610 is also comprised of an M2 metallization layer that is stacked on an M1 metallization layer and coupled through via V1.

[0035]

[0044] 7A and 7B illustrate inductance versus frequency graphs and quality factor versus frequency graphs for a laminated inductor having the discrete metal stack pattern of FIG. 6A according to an embodiment of the present disclosure. FIG. 7A illustrates an inductance versus frequency graph 700 showing a target inductance of 1.41 nano-henries (nH). FIG. 7B illustrates a quality (Q) factor versus frequency graph 750 showing a target Q factor of 72. The target inductance and target Q factor are shown in the highlighted area 710 for the laminated inductor 600 having the discrete metal stack pattern of FIG. 6A according to an embodiment of the present disclosure.

[0036]

[0045] FIG. 8 is a process flow diagram illustrating a method for fabricating a stacked inductor having a discrete metal stack pattern according to one embodiment of the present disclosure. The method 800 begins at block 802, where a first metallization layer multi-turn trace is formed. For example, as shown in FIG. 6A, the stacked inductor 600 includes a stacked multi-turn trace 610 composed of an M2 metallization layer stacked on an M1 metallization layer including a discrete metal stack pattern formed in a predetermined portion. In block 804, a second metallization layer multi-turn trace is formed to couple to the first metallization layer multi-turn trace through a first via. For example, as shown in FIG. 6B, the stacked multi-turn trace 610 is composed of an M2 metallization layer stacked on an M1 metallization layer and coupled through a via V1.

[0037]

[0046] At block 806, a discrete third metallization layer trace segment(s) is formed to be coupled to the second metallization layer multi-turn trace through a second via. For example, as shown in FIG. 6B, an M3 metallization layer angled joint trace segment 620 is formed on the stacked multi-turn trace 610 proximate to the first port 602. Similarly, an M3 metallization layer second angled joint trace segment 670 is formed on the stacked multi-turn trace 610 proximate to the second port 604 of the stacked inductor 600. The stacked inductor 600 also includes an M3 metallization layer first angled trace segment 630, a second angled trace segment 640, and a third angled trace segment 660 formed on the stacked multi-turn trace 610. The stacked inductor 600 further includes an M3 metallization layer line trace segment 650 formed on the stacked multi-turn trace 610. The discrete third metallization layer trace segments follow the shape of the second metallization layer multi-turn trace according to a predetermined pattern.

[0038]

[0047] Aspects of the present disclosure improve key performance indicators (KPIs) of inductors in broadband filters by implementing improved metal stack patterns to provide special designs for 5G NR broadband FR2 filters. The special designs improve inductor metal layers by providing novel inductor metal stack patterns. The special designs may reconfigure metal thickness in current-congested areas of the broadband filters. In some aspects, the special designs may add more metal layers to thermal hot spots (e.g., up to 100° C.) of the broadband filters. Some aspects of the present disclosure provide customized metal stack patterns to provide the desired on-inductance of the inductors. These customized metal stack patterns beneficially improve the electrical performance (e.g., insertion loss and rejection) of the broadband filters while improving thermal mitigation. The customized metal stack patterns also improve the chemical mechanical polishing (CMP) ratio for thick copper (Cu) layer processing.

[0039]

[0048] FIG. 9 is a block diagram illustrating an example wireless communication system 900 in which aspects of the present disclosure may be advantageously employed. For illustrative purposes, FIG. 9 shows three remote units 920, 930, and 950 and two base stations 940. It will be appreciated that the wireless communication system may have many more remote units and base stations. The remote units 920, 930, and 950 include integrated circuit (IC) devices 925A, 925C, and 925B that include the disclosed stacked inductors having discrete metal stack patterns. It will be appreciated that other devices, such as base stations, switching devices, and network equipment, may also include the disclosed stacked inductors. FIG. 9 shows forward link signals 980 from the base station 940 to the remote units 920, 930, and 950, and reverse link signals 990 from the remote units 920, 930, and 950 to the base station 940.

[0040]

[0049] In FIG. 9, remote unit 920 is shown as a mobile phone, remote unit 930 is shown as a portable computer, and remote unit 950 is shown as a fixed location remote unit in a wireless local loop system. For example, the remote units may be mobile phones, portable personal communication system (PCS) units, portable data units such as personal data assistants, fixed location data units such as GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, meter reading equipment, or other devices that store or retrieve data or computer instructions, or combinations thereof. Although FIG. 9 illustrates remote units according to aspects of the disclosure, the disclosure is not limited to these exemplary illustrated units. Aspects of the disclosure may be suitably employed in many devices, including the disclosed stacked inductors.

[0041]

[0050] FIG. 10 is a block diagram illustrating a design workstation used for circuit, layout, and logic design of semiconductor components, such as the stacked inductors disclosed above. The design workstation 1000 includes a hard disk 1001 that stores operating system software, support files, and design software, such as Cadence or OrCAD. The design workstation 1000 also includes a display 1002 to facilitate the design of a circuit 1010 or a radio frequency (RF) component 1012, such as a stacked inductor. A storage medium 1004 is provided for tangibly storing the design of the circuit 1010 or RF component 1012 (e.g., a stacked inductor having a discrete metal stack pattern). The design of the circuit 1010 or RF component 1012 may be stored on the storage medium 1004 in a file format, such as GDSII or GERBER. The storage medium 1004 may be a compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a hard disk, a flash memory, or other suitable device. Additionally, the design workstation 1000 includes a drive device 1003 for receiving input from the storage medium 1004 and for writing output to the storage medium 1004 .

[0042]

[0051] Example implementations are described in the following numbered clauses.

[0043] 1. A first metallization layer multi-turn trace; a second metallization layer multi-turn trace coupled to the first metallization layer multi-turn trace through at least one first via; a plurality of discrete third metallization layer trace segments coupled to the second metallization layer multi-turn trace through a plurality of second vias; An inductor comprising:

[0044] 2. The inductor of clause 1, wherein the plurality of discrete third metallization layer trace segments follow a shape of the second metallization layer multi-turn trace according to a predetermined pattern.

[0045] 3. The inductor of clause 1 or 2, wherein the first metallization layer multi-turn trace comprises an angled joint trace segment and / or a line trace segment joined to an angled trace segment.

[0046] 4. An inductor according to any one of clauses 1 to 3, wherein a thickness of a first one (the third metallization layer trace segment) of the plurality of discrete third metallization layer trace segments is different from a thickness of a second one (the third metallization layer trace segment) of the plurality of discrete third metallization layer trace segments.

[0047] 5. The inductor of any of clauses 1-4, wherein the plurality of discrete third metallization layer trace segments comprises line trace segments, angled joint trace segments, or angled trace segments.

[0048] 6. An inductor according to any one of clauses 1 to 5, wherein the inductor is integrated into an integrated passive device (IPD).

[0049] 7. The inductor of clause 6, wherein the IPD is integrated into a radio frequency (RF) filter.

[0050] 8. The inductor of clause 6, wherein the IPD is integrated into a radio frequency (RF) module.

[0051] 9. A method for making a laminated inductor having a discrete metal laminate pattern, comprising: forming a first metallization layer multi-turn trace; forming a second metallization layer multi-turn trace coupled to the first metallization layer multi-turn trace through at least one first via; forming a plurality of discrete third metallization layer trace segments coupled to the second metallization layer multi-turn trace through a plurality of second vias; A method comprising:

[0052] 10. The method of clause 9, wherein forming the plurality of discrete third metallization layer trace segments comprises depositing a plurality of discrete third metallization layer trace segments that follow a shape of the second metallization layer multi-turn trace according to a predetermined pattern.

[0053] 11. The method of clause 9 or 10, wherein forming the first metallization layer multi-turn trace comprises forming angled joint trace segments and / or line trace segments joined to angled trace segments.

[0054] 12. The method of any of clauses 9-11, wherein forming the plurality of discrete third metallization layer trace segments comprises forming line trace segments, angled trace segments, or angled joint trace segments.

[0055] 13. The method of any of clauses 9-12, further comprising integrating the stacked inductor into an integrated passive device (IPD).

[0056] 14. Any of the methods of clause 13, further comprising integrating the IPD with a radio frequency (RF) filter.

[0057] 15. Any of the methods of clause 13, further comprising integrating the IPD into a radio frequency (RF) module.

[0058] 16. A radio frequency front-end (RFFE) module, comprising: A semiconductor die; an integrated passive device (IPD) die coupled to the semiconductor die and comprising an inductor, the inductor comprising: A first metallization layer multi-turn trace; a second metallization layer multi-turn trace coupled to the first metallization layer multi-turn trace through at least one first via; and An RFFE module comprising a plurality of discrete third metallization layer trace segments coupled to the second metallization layer multi-turn trace through a plurality of second vias.

[0059] 17. The RFFE module of clause 16, wherein a plurality of discrete third metallization layer trace segments follow a shape of a second metallization layer multi-turn trace according to a predetermined pattern.

[0060] 18. The RFFE module of clause 16 or 17, wherein the first metallization layer multi-turn trace comprises an angled joint trace segment and / or a line trace segment joined to an angled trace segment.

[0061] 19. The RFFE module of any of clauses 16-18, wherein a thickness of a first one of the plurality of discrete third metallization layer trace segments (the third metallization layer trace segment) is different from a thickness of a second one of the plurality of discrete third metallization layer trace segments (the third metallization layer trace segment).

[0062] 20. The RFFE module of any of clauses 16-19, wherein the plurality of discrete third metallization layer trace segments comprises line trace segments, angled joint trace segments, or angled trace segments.

[0063]

[0052] The data recorded on the storage medium 1004 may specify logic circuit configurations, pattern data for photolithography masks, or mask pattern data for continuous writing tools such as electron beam lithography. The data may further include logic verification data, such as timing diagrams or net circuits associated with logic simulations. Providing the data on the storage medium 1004 facilitates the design of the circuit 1010 or radio frequency (RF) component 1012 by reducing the number of processes for designing a semiconductor wafer.

[0064]

[0053] For a firmware and / or software implementation, the methodologies may be implemented with modules (e.g., procedures, functions, and so on) that perform the functions described herein. Machine-readable media tangibly embodied with instructions may be used in implementing the methodologies described herein. For example, software code may be stored in a memory and executed by a processor unit. The memory may be implemented within the processor unit or external to the processor unit. As used herein, the term "memory" may refer to long-term, short-term, volatile, non-volatile, or other types of memory and is not limited to a specific type or number of memories or the type of medium on which the memory is stored.

[0065]

[0054] If implemented in firmware and / or software, the functions may be stored as one or more instructions or code on a computer-readable medium. Examples include computer-readable media having data structures encoded thereon and computer-readable media having a computer program encoded thereon. Computer-readable media include physical computer storage media. Storage media may be any available medium that can be accessed by a computer. By way of example and not limitation, such computer-readable media may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), compact disk read-only memory (CD-ROM) or other optical disk storage, magnetic disk storage or other magnetic storage devices, or other media that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. Disk and disc, as used herein, include compact discs (CDs), laser discs, optical disks, digital versatile discs (DVDs), floppy disks and Blu-ray discs, although disks typically reproduce data magnetically while discs reproduce data optically by means of a laser. Combinations of the above should also be included within the scope of computer readable media.

[0066]

[0055] In addition to being stored on a computer-readable medium, the instructions and / or data may be provided as signals on a transmission medium included in a communications device. For example, a communications device may include a transceiver having signals indicative of the instructions and data. The instructions and data are configured to cause one or more processors to implement the functions outlined in the claims.

[0067]

[0056] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and modifications can be made herein without departing from the technology of the present disclosure as defined by the appended claims. For example, relative terms such as "upper" and "lower" are used in reference to a substrate or electronic device. Of course, if the substrate or electronic device is inverted, upper becomes lower and vice versa. Also, if oriented sideways, upper and lower may refer to both sides of the substrate or electronic device. Furthermore, the scope of the present application is not intended to be limited to the particular configurations of the processes, machines, manufactures, compositions, means, methods, and steps described herein. As one skilled in the art would readily recognize from the present disclosure, any process, machine, manufacture, composition, means, method, or step now existing or to be developed in the future that performs substantially the same function or achieves substantially the same results as the corresponding configurations described herein may be utilized in accordance with the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufactures, compositions, means, methods, or steps.

[0068]

[0057] Those skilled in the art will further recognize that the various exemplary logic blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability of hardware and software, the various exemplary components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the particular application and design constraints imposed on the overall system. A skilled artisan may implement the described functionality in various ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0069]

[0058] The various example logic blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed by a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in alternative examples, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0070]

[0059] The steps of a method or algorithm described in connection with the present disclosure may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software module may reside in a random access memory (RAM), a flash memory, a read only memory (ROM), an erasable programmable read only memory (EPROM), an electrically erasable programmable read only memory (EEPROM), a register, a hard disk, a removable disk, a compact disk read only memory (CD-ROM), or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an application specific integrated circuit (ASIC). The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.

[0071]

[0060] In one or more exemplary designs, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. Storage media may be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), compact disk read-only memory (CD-ROM) or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store specified program code means in the form of instructions or data structures and that can be accessed by a general purpose or special purpose computer, or a general purpose or special purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, except that disks typically reproduce data magnetically while discs reproduce data optically with lasers.Combinations of the above should also be included within the scope of computer-readable media.

[0072]

[0061] The preceding description of the present disclosure is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the present disclosure. Thus, the present disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. a first metallization layer multi-turn trace; a second metallization layer multi-turn trace coupled to the first metallization layer multi-turn trace through at least one first via; a plurality of discrete third metallization layer trace segments, each segment coupled to the second metallization layer multi-turn trace through a plurality of second vias, the plurality of discrete third metallization layer trace segments comprising angled joint trace segments or angled trace segments, the angled joint trace segments having an angle of 45 degrees; An inductor comprising:

2. The inductor of claim 1 , wherein the plurality of discrete third metallization layer trace segments follow a shape of the second metallization layer multi-turn trace according to a predetermined pattern.

3. 2. The inductor of claim 1 , wherein the first metallization layer multi-turn trace comprises an angled joint trace segment and / or a line trace segment coupled to an angled trace segment, the angled joint trace segment having an angle of 45 degrees.

4. 2. The inductor of claim 1 , wherein a thickness of a first one of the plurality of discrete third metallization layer trace segments is different from a thickness of a second one of the plurality of discrete third metallization layer trace segments.

5. The inductor of claim 1 , wherein the inductor is integrated into an integrated passive device (IPD).

6. The inductor of claim 5 , wherein the IPD is integrated into a radio frequency (RF) filter.

7. The inductor of claim 5 , wherein the IPD is integrated into a radio frequency (RF) module.

8. 1. A method for fabricating a stacked inductor having a discrete metal stack pattern, comprising: forming a first metallization layer multi-turn trace; forming a second metallization layer multi-turn trace coupled to the first metallization layer multi-turn trace through at least one first via; forming a plurality of discrete third metallization layer trace segments coupled to the second metallization layer multi-turn trace through a plurality of second vias, wherein forming the plurality of discrete third metallization layer trace segments comprises forming angled trace segments or angled joint trace segments, each of the angled joint trace segments having an angle of 45 degrees. A method comprising:

9. 9. The method of claim 8, wherein forming the plurality of discrete third metallization layer trace segments comprises depositing the plurality of discrete third metallization layer trace segments that follow a shape of the second metallization layer multi-turn trace according to a predetermined pattern.

10. 9. The method of claim 8, wherein forming the first metallization layer multi-turn trace comprises forming angled joint trace segments and / or line trace segments joined to angled trace segments, the angled joint trace segments each having an angle of 45 degrees.

11. The method of claim 8 , further comprising integrating the stacked inductor into an integrated passive device (IPD).

12. The method of claim 11 , further comprising integrating the IPD with a radio frequency (RF) filter.

13. The method of claim 11 , further comprising integrating the IPD into a radio frequency (RF) module.

14. 1. A radio frequency front end (RFFE) module, comprising: A semiconductor die; an integrated passive device (IPD) die coupled to the semiconductor die, the IPD die comprising the inductor of claim 1; 1. An RFFE module comprising:

15. The RFFE of claim 14, wherein the plurality of discrete third metallization layer trace segments are positioned at thermal hot spots of the IPD.

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