Field-programmable ferroelectric diodes for reconfigurable in-memory computing

Abstract

Ferroelectric diodes made of materials such as aluminum scandium nitride (AiScN) or hafnium zirconium oxide (HfZrO2) can be formed on top of semiconductor structures such as COMOS wafers to create storage memory cells, search ternary content addressable memory (TCAM) cells, and / or neural circuits. The diodes are non-volatile and field programmable by pulsing to analog states depending on the number of pulses, with high on / off and self-rectifying ratios. Cells can be formed, for example, with two diodes of opposite polarity or without transistors to form, for example, a 0T-2R structure.

Description

[Technical field]

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 167,765, filed March 30, 2021, entitled "Field-programmable ferro-diodes for reconfigurable in-memory-computing," the contents of which are incorporated herein by reference.

[0002] This invention was made with Government support under HR0011-20-9-0046 awarded by the Department of Defense. The Government has certain rights in this invention. [Background technology]

[0003] This application relates to the application of ferroelectric diodes in storage, retrieval and computing systems. Summary of the Invention

[0004] By leveraging the unique properties of field-programmable ferroelectric diodes (ferro-diodes) constructed from the ferroelectric material Aluminum Scandium Nitride (AlScN), we demonstrate a reconfigurable architecture including zero transistors (0T) that enables multiple data-intensive applications such as storage, search, and neural networks. Specifically, we demonstrate ferroelectric diodes (ferro-diodes) that are nonvolatile, have high on / off ratios of >104, high self-rectification ratios of >104, and are compatible with CMOS back-end-of-line (BEOL) processing. Based on these unique properties, we describe a novel nonvolatile ternary content addressable memory (TCAM) using 0 transistor / 2 resistor memory (0T-2R) cells. Due to the absence of transistors, the 0T-2R TCAM is the most compact design, with a search delay of <100ps based on SPICE simulations.

[0005] In addition to scandium, other dopants can be used in forming aluminum nitride ferrodiodes. Such ferrodiodes can be used in a variety of circuits and systems.

[0006] We also experimentally demonstrate a 4-bit ferrodiode synapse with high linearity and symmetric synergy / decay characteristics, enabling applications to high-precision, low-latency neural network inference. Our architecture design is benchmarked against experimental ferrodiode data and the LeNet-5 architecture in the PyTorch framework. The results show an inference accuracy of 97.5% on the MNIST dataset, approaching the ideal software-level inference.

[0007] In one aspect, the present disclosure provides a memory cell having an array of ferroelectric diodes, optionally comprising aluminum scandium nitride (AlScN) or hafnium zirconium oxide (HfZrO2), characterized in that the ferroelectric diodes are non-volatile and field programmable via pulsing to an analog state that is dependent on a number of pulses.

[0008] Also provided is an array of memory cells having a plurality of instances of a memory cell of the present disclosure (e.g., according to any of aspects 1-8), the array arranged for a V / 2 scheme used to read and program the ferroelectric diodes.

[0009] Further provided is a ternary content addressable memory (TCAM) having a memory cell according to the present disclosure (eg, according to any one of aspects 1-8).

[0010] Further disclosed is a neural network having an array of multi-bit diode synapses, each diode synapse optionally having a ferroelectric diode, e.g., having Aluminum Scandium Nitride (AiScN), each diode being non-volatile and field programmable via pulsing to an analog state that is dependent on the number of pulses.

[0011] This Summary is provided to introduce in a simplified form some of the concepts that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. Moreover, the claimed subject matter is not limited to limitations that solve any or all of the disadvantages noted in any part of this Summary. [Brief description of the drawings]

[0012] A more detailed understanding may be had from the following description, given by way of example in conjunction with the accompanying drawings, in which: [Figure 1] FIG. 1 shows various potential applications of ferrodiode arrays for memory, in-memory search, and neural networks. [Figure 2A] FIG. 2A is a vertical cross-sectional view of an exemplary ferrodiode. [Figure 2B] FIG. 2B is a TEM image of a vertical cross section of an exemplary ferrodiode. [Diagram 3] 3A and 3B are IV curves of an exemplary ferrodiode in positive and negative forward polarization states, respectively. [Figure 4] The implementation of the accumulation mode is shown in Figure 4. The high on / off and self-rectification ratios allow the V / 2 scheme to be applied to reading and programming 0-T RAMs. [Diagram 5] FIG. 5 shows two IV curves of a ferrodiode in different polarization states. [Figure 6] 6A-6D are electrical schematics of a single-cell TCAM implementation. [Figure 6A] FIG. 6A shows a typical TCAM connection. [Figure 6B] FIG. 6B shows a 16T CMOS TCAM. [Figure 6C] FIG. 6C shows a 2T-2R TCAM. [Figure 6D] Figure 6D shows a 0T-2R TCAM. [Figure 7] FIG. 7 is a chart of voltage modes and encodings for various values ​​of stored states, search voltages, and search results. [Figure 8] 8A-8D show the use of a ferrodiode array for a search mode, the implementation of which may include a high sense margin of match line resistance that may be achieved by a high on / off ratio and self-rectification. [Figure 9]Figure 9 shows two graphs of the search line voltage and match line voltage over time for a ferrodiode 0T-2R TCAM cell. The waveforms were generated in SPICE for the condition where state "0" is stored and searched for by two sense voltages. See Y.LeCun et al.,Proceedings of the IEEE, Volume 86, Issue 11, Nov, 1998. [Figure 10A] Figure 10A is a schematic diagram of LeNet-5. See Y. LeCun et al. [Figure 10B] FIG. 10B shows a ferrodiode 0T-1R crossbar array for direct mapping of pre-trained CNN architectures. [Figure 11A] 11A is a graph of conductance versus the number of sequentially applied positive and negative pulse trains. The ferrodiode is bipolar and capable of analog state modulation dependent on the number of pulses. [Figure 11B] Figure 11B plots the benchmarked inference accuracy of LeNet-5 against the number of bits per weight. It shows an inference accuracy of about 97.5% on the MNIST dataset on current machines, approaching the ideal software-level inference. [Figure 12A] FIG. 12A shows a field programmable ferroelectric diode reconfigurable CIM. [Figure 12B] FIG. 12B shows the room temperature electrical characteristics of the AlScN / MoS2 FE-FET. [Figure 13] FIG. 13 shows a 2-FeD TCAM cell for a search operation. [Figure 14] FIG. 14 shows a neural network based on FeD. [Figure 15] FIG. 15 shows three methods of electron transport through a potential barrier. [Figure 16] Figure 16 shows a comparison of the IV curves using the WKB approximation and the new voltage shift model of a ferroelectric diode for an arbitrary ferroelectric. [Figure 17]FIG. 17 shows the shift of the HRS IV curve with the change in the precoded oxide capacitance image. [Figure 18] FIG. 18 shows the shift of the HRS IV curve with the change in the remnant polarization image. [Figure 19] FIG. 19 shows the shift in the IV curve with the change in the coercive field line image results. [Figure 20] FIG. 20 shows the Log(I) vs V of the measured current I as a DC voltage sweep is applied to 16 different conditions. [Figure 21] FIG. 21 shows current versus images for 16 different conditions. [Figure 22] Figure 22 shows an image of the digit “5” input from the MNIST dataset and its plot after mapping. [Figure 23] FIG. 23 shows a measurement of the current at the output when a coded voltage is applied to a ferroelectric diode device in response to the original input. [Figure 24] FIG. 24 shows the normalized conductance. [Diagram 25] FIG. 25 shows a signal sequence for PUND measurement. [Figure 26] FIG. 26 shows the dynamic current response in 45 nm AlScN. [Figure 27] FIG. 27 shows the TCAM cell structure. [Figure 28] FIG. 28 shows a metal / oxide / A10.64Sc0.36N / metal memristor device. [Figure 29] FIG. 29 shows the current-voltage characteristics of a ferroelectric memristor. [Diagram 30] FIG. 30 shows the characteristics of the MIM device. [Diagram 31] FIG. 31 shows cycle IV curves over manual DC switching cycles and holding low and high current / resistance states. [Diagram 32] FIG. 32 shows a pulse sequence for measuring PUND. [Diagram 33] FIG. 33 shows a ferroelectric (FE) AlScN metal-insulator-metal device. [Diagram 34] FIG. 34 shows the IV characteristics of an in-situ deposited MIM Al(30 nm) / A10.68 Sc0.32N(45 nm) / Al(85 nm) ferrodiode device. [Diagram 35] FIG. 35 shows the on-state sweep of current density versus voltage for three circular Pt / native oxide / A10.64Sc0.36N / Pt MIM devices. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] There is growing interest in new technologies and computing paradigms that enable faster and more energy-efficient information processing. The background to this is the difficulty of scaling according to Moore's law and the associated performance degradation. Driven by applications such as big data, the Internet of Things, and artificial intelligence (AI), in-memory computing (IMC) technologies based on non-volatile memories are developing rapidly. These applications require the "distance" between computing and data to be reduced. See Ielmini et al., Nature Electron. 1 p. 333 (2018).

[0014] However, AI computational tasks that leverage big data typically require multiple IMC architectures on the same chip, i.e., on-chip storage, content search, and matrix multiplication engines, to process information sequentially. This has been challenging until now. In this paper, we present a strategy to leverage the unique properties of ferroelectric diodes made from a ferroelectric material (AlScN) to build reconfigurable circuits and architectures with significantly improved both areal density and speed for multiple data-intensive applications. See Wang et al.,.IEEE EDL,41,pp1747(2020). 0T-1R for storage, 0T-2R for search, and a crossbar for neural networks (Figure 1).

[0015] Field programmable ferrodiode A schematic diagram and cross-sectional TEM image of the ferrodiode are shown in Figure 2. A 20 nm AlScN film was co-sputtered at 350 degrees Celsius on top of the Pt electrode, followed by a Pt (100 nm) metal top electrode. Figure 3 shows the IV curves of the positive and negative forward diodes, with the two polarized states reversed. Storage Figure 5 shows typical IV characteristics of a field programmable ferrodiode. The device has a self-rectification ratio of over 104 and suppresses leakage current without additional access transistors or selectors. See Ielmini et al., Nature Electron. 1 p. 333 (2018). The diode achieves a large on / off ratio of over 104 at a read bias voltage of ~2V, which is at least two orders of magnitude higher than the on / off ratio previously reported for hafnia-based memory cells. See K.Ota,et al.,in IEDM Tech.Dig.,pp.6.2.1-6.2.4 (2019). See further, Berdan, R ai., Nature Electron. 3, p. 259 (2020).

[0016] Based on the high on / off ratio and self-correction ratio, the well-known V / 2 scheme can be applied to read and program the 0-T resistive crossbar. See further Serb, et ai, IEEE Trans. Circuits Syst. I 63, pp. 827-835 (2016).

[0017] search The cell structure of TCAM can be greatly simplified by using two ferrodiodes (Fig. 6) connected in parallel, but polarized in opposite directions. The basic principle is as follows: ML discharge occurs only when the ferrodiode is programmed in positive forward direction and the read voltage is higher than the turn-on voltage. The operation of an OT-1R ferrodiode TCAM cell is summarized in Fig. 7. During the cell operation, the two ferrodiodes are first programmed with complementary states. If the search data matches the stored information, the ML remains high, otherwise the ML discharges. In a SPICE simulation example (Fig. 9), a logic "0" state is written to the TCAM cell by setting the up / down ferrodiodes to positive forward / negative forward states, respectively. Then, a logic 0 is searched for by applying low / high pulse amplitudes to the up / down ferrodiodes. In the case of "Match", the ML resistance is R1 / R2, and in the case of "Mismatch", the ML resistance is R1 / R3=R3, as shown in Fig. 8. That is, the sense margin is approximately expressed as (R1 / R2) / R3. In other words, it is essential to achieve high on / off ratio and high self-correction ratio simultaneously in the design of OT-2R TCAM. Due to the absence of transistors, the SPICE simulations verify that the proposed TCAM has a very compact design compared to the previous architectures based on transistors, with a search delay of less than 100ps for a 4x8 TCAM array. See Li, J. et al., IEEE J. Solid-State Circuits 49, pp. 896-907 (2014). See also K. Pagiamtzis et al., IEEE Journal of Solid-State Circuits 41, pp. 712 (2016).

[0018] Neural Networks The reported highly linear and symmetric neuromorphic synaptic behavior of the ferrodiodes also supports their application in deep neural network acceleration. See Qlangfel Xia et al., Nature Materials.18,pp.309,(2019). An example pulse response is shown in Figure 11, where alternating polarity pulse trains are applied in sequence, demonstrating that the ferrodiodes are bipolar and capable of pulse-number-dependent analog state modulation. We also experimentally observed a 4-bit ferrodiode synapse with highly linear and symmetric enhancement / decay characteristics, enabling applications in high-precision, low-latency neural network inference. We note that the highly linear and symmetric weights are programmable simply by using pulse trains with uniform height and width, which greatly simplifies the programming of this memo-resistive crossbar. This design is benchmarked against experimental ferrodiode data and the LeNet-5 architecture in the PyTorch framework, demonstrating an inference accuracy of ~97.5% on the MNST dataset, approaching ideal software-level inference, as shown in Figure 11B.

[0019] side The following aspects are illustrative, and not limiting of the scope of the disclosure or the appended claims.

[0020] Aspect 1. A memory cell including an array of ferroelectric diodes, the ferroelectric diodes optionally comprising aluminum scandium nitride (AlScN) or hafnium zirconium oxide (HfZrO2), the ferroelectric diodes being non-volatile and field programmable via pulsing to an analog state that is dependent on a number of pulses.

[0021] Aspect 2. The memory cell of aspect 1, wherein the diode has an on / off ratio greater than 2, 5, 10, 25, 50, 75, 100, 500, 1,000, 5,000, or 10,000.

[0022] Aspect 3. The memory cell of aspect 1, wherein the diode has a self-rectifying ratio greater than 25, 50, 75, 100, 200, 500, 1,000, 10,000, 50,000, or 100,000.

[0023] Aspect 4. The memory cell of aspect 1, wherein the cell is compatible with CMOS back-end-of-the-line (BEOL) processing.

[0024] Aspect 5. The memory cell of aspect 1, further comprising a ferroelectric material comprising aluminum scandium nitride (AlScN) or hafnium zirconium oxide (HfZrO2), the ferroelectric material having a deposition temperature less than 400 degrees Celsius.

[0025] Aspect 6. The memory cell of aspect 1, wherein the ferroelectric diode is bipolar pulse programmable.

[0026] Aspect 7. The memory cell of aspect 6, wherein the ferroelectric diode is pulse programmable with 4 bits of state resolution.

[0027] Aspect 8. In the memory cell of aspect 1, the diode comprises AlScN or HfZrO2 having a thickness less than about 100 nm, less than about 75 nm, less than about 50 nm, or less than about 25 nm.

[0028] Aspect 9. An array of memory cells having a plurality of instances of the memory cell of any one of aspects 1-8, the array arranged for a V / 2 scheme to be used to read and program the ferroelectric diodes.

[0029] Aspect 10. A ternary content addressable memory (TCAM) having a memory cell according to any one of aspects 1 to 8.

[0030] Aspect 11. In the TCAM of aspect 10, a search delay of the TCAM is about 1 μs or less, about 500 ns or less, or about 100 ns, 50 ns, 10 ns, 1 ns, 100 ps or less.

[0031] Aspect 12. In the TCAM of aspects 9-11, each memory cell has two diodes of opposite polarity.

[0032] Aspect 13. A neural network having an array of multi-bit diode synapses, each diode synapse optionally having a ferroelectric diode having aluminum scandium nitride (AlScN) or hafnium zirconium oxide (HfZrO2), each diode being non-volatile and field programmable via pulsing to an analog state that depends on a number of pulses.

[0033] Phase 14. In the neural network of Phase 13, the multi-bit diode synapse is deployed in the LeNet-5 architecture of the PyTorch framework.

[0034] Aspect 15. The neural network of any of aspects 13 or 14, wherein the neural network exhibits an inference accuracy of at least about 90%, at least about 95%, or at least about 97% on the MNIST dataset.

[0035] Example: Reconfigurable Compute-in-Memory on Field-Programmable Ferroelectric Diodes The proliferation of sensors and data-generating devices is driving a paradigm shift in modern computing from computation-logic-centric to data-centric processing. At the hardware level, there is an urgent need to integrate high-density, high-performance, and low-power memory units into SI logic processor units. However, data-intensive problems such as search and pattern matching also require paradigm-changing innovations at the circuit and architecture levels to realize compute-in-memory (CIM) operations. CIM architectures that combine data storage with low latency and small footprints at the same time are highly sought after but have yet to be realized. Here, we present an aluminum scandium nitride (AlScN) ferroelectric diode (FeD) memristor device. Our device can be directly integrated on top of SI processors in a scalable back-end-of-line process. Leveraging the field programmability, non-volatility, and non-linearity of FeDs, we achieve search latency <0.1ns and cell footprint <0.12μm. 2 We have demonstrated a circuit block that supports search operations in in-situ memory. Furthermore, we have demonstrated matrix multiplication operations with 4-bit operations on the FeD. These results highlight that the FeD is a promising candidate for a fast and efficient multi-function CIM platform.

[0036] The convergence of big data and artificial intelligence (AI) has led to the emergence of several new technologies in various computing applications. As sensors and edge / IoT devices become more ubiquitous, a flood of data is emerging, exposing a significant efficiency gap in computer hardware, from mobile and edge devices to data centers and cloud computing hardware. In addition, the slowdown in the scaling of silicon-based complementary metal oxide semiconductor (CMOS) devices further highlights the gap in resource requirements based on traditional von Neumann computer hardware architectures, specifically central processing units (CPUs), graphics processing units (GPUs), and field programmable arrays (FPGAs). Moreover, it is well-known that for many data-centric tasks in such von Neumann architectures, the majority of energy and time is consumed in memory access and data movement, rather than in the actual computation. To mitigate and overcome this bottleneck, several solutions have been proposed, most notably by placing memory and logic units in close physical proximity. While significant progress has been made along this line, both at the material and device levels, an innovative approach is to use in-situ memories to perform computational functions. This is commonly known as Compute-in-Memory (CIM). The overarching goal of CIM is to fundamentally transform computer architectures by completing computations where the data is stored, rather than redesigning traditional von Neumann architectures with individual optimizations such as memory bandwidth, new non-volatile memory (NVM) technologies, and data parallelism. Although there have been several demonstrations of CIM architectures using NVM, the majority of the efforts have been limited to a single type of computational task. For example, matrix multiplication accelerators have typically been realized using memristive crossbar arrays.However, AI computational tasks that utilize “big data” require multiple data-intensive computations on the same chip, preferably processing information in a pipeline using the same architecture. There are three most important functions or operations: 1) on-chip storage, 2) parallel search, and 3) matrix multiplication. A key challenge in building CIM architectures is the conflicting trade-off between performance and flexibility required to realize these three functions. As a result, while CIM accelerators have been demonstrated to achieve high performance in matrix multiplication acceleration, they are fundamentally unsuitable for other big data operations such as parallel search. It is therefore important to conceptualize and develop reconfigurable and operationally flexible hardware for CIM to simultaneously support essential data operations such as on-chip memory, parallel search, and matrix multiplication acceleration.

[0037] In this work, we leverage the unique properties of aluminum scandium nitride (AlScN) ferroelectric diode (FeD) devices, particularly their field programmability, non-volatility, and non-linearity, to demonstrate circuit blocks based on FeD elements that support multiple essential fundamental data manipulation in-situ memories in a transistor-free design (Figure 12A). Specifically, we first demonstrate FeD elements that are non-volatile and compatible with CMOS back-end-of-line (BEOL) processing and exhibit self-correcting behavior with non-linearity >106, high on / off ratio >102, endurance >104 cycles, and field programming speed >500 ns. We then leverage these unique properties to demonstrate a non-volatile ternary content addressable memory (TCAM) using 0-transistor / 2-FeD cells, which will serve as key building blocks in the hardware implementation of in-memory computing for parallel search processing in big data applications. This transistor-free approach is a key benefit of our device and memory cell design. As a result, the 2-FeD TCAM is the most compact design (0.12 μm at 45 nm node). 2 / cell), which significantly reduces the search latency (<0.1ns at 45nm node) compared to TCAM cells based on 2 transistors / 2 resistors (2T-2R). Finally, we also show that the FeD element can be programmed by electrical pulsing into 4-bit distinct conductive states with excellent linearity and symmetry. We leverage this programmable multi-bit property of the ferrodiode to demonstrate a hardware implementation of neural network computation in the form of analog voltage amplitude matrix multiplication, a key kernel of neural network computation. We demonstrate accuracy approaching that of an ideal software-based neural network. The matrix multiplication operation is benchmarked by mapping neural network weights to experimental FeD conductance states in a convolutional neural network architecture for both inference and the in situ learning tasks, showing that our accuracy approaches that of an ideal software-level simulation on the MNIST dataset. The results demonstrate that the AlSCN-based field-programmable non-volatile FeD offers a unique opportunity to build reconfigurable CIM architectures with a good balance of performance and flexibility.

[0038] Field-programmable AlScN FeD for memory applications Our FeD element is a sputter-deposited 45 nm thick ferroelectric AlScN layer sandwiched between top and bottom aluminum electrodes. This forms a metal-insulator-metal (MIM) structure, as shown in the left panel of Fig. 12Ba. AlScN is a recently discovered ferroelectric with a nearly ideal ferroelectric hysteresis loop, record remanent polarization values, and composition-tunable coercive field. Furthermore, it can be directly integrated into CMOS BEOL compatible process technologies on 8-inch wafers. It has also been shown that AlScN films are one of the most promising candidates for high-performance ferroelectric memory devices and are scalable to thicknesses of less than 10 nm. The AlScN films were electrically characterized and showed a large coercive field (EC) of 2-4.5 MV / cm. This is important for scaling to thinner ferroelectric layers while maintaining a large memory window, high on / off ratio, and good retention. The measured high remanent polarization (Pr is 80-150 μC / cm 2 ), leading to a pronounced tunneling electroresistance effect based on the strong tunnel barrier modulation and thus a high on / off ratio. For details on film deposition, characterization, and device fabrication, see Methods and Supplementary Information. Figure 12B(a) shows a representative cross-sectional transmission electron microscopy (TEM) image of an MLM FeD element consisting of an AlScN film and an Al top electrode deposited on an Al / AlScN / Si substrate. An atomic resolution TEM image of the AlScN film is shown in Figure 12B(b1). Figure 12B(b2) shows the ∼2 nm thick interfacial layer at the AlScN / bottom Al interface.

[0039] Figure 12A shows a reconfigurable CIM of field programmable ferroelectric diodes. a) Schematic diagram of FeD elements in a crossbar structure with up-down polarization of ferroelectric AlScN. The field programmability, non-volatility, and nonlinearity of these devices can be exploited for multiple primitive data operations such as storage, retrieval, and neural networks without the need for additional transistors, as shown in b-d. b) The two-terminal FeD elements exhibit a diode-like self-rectifying behavior with an on / off ratio of over 102 and endurance of over 104 cycles, while at the same time a nonlinearity of over 106, placing FeD elements well in memory hierarchy for storage. Furthermore, the high nonlinearity allows the suppression of sneak currents without the need for additional access transistors or selectors. c) It serves as a building block in hardware implementation of in-memory computing for parallel retrieval in big data applications. d) For neural networks, FeD elements can provide programmability to distinguish multiple conductive states with high linearity with respect to the number of electrical pulses. This allows the matrix multiplication operation, a key kernel of neural network computations, to be mapped to reading the accumulated current at each bit line of the FeD element by encoding the input vector into an analog voltage amplitude and the matrix elements into the conductance of an array of FeD elements.

[0040] The ferroelectric response of 45 nm AlScN thin films was characterized by positive-up, negative-down (PUND) measurements using a square wave with a delay of 2 μs and a pulse width of 400 ns on a circular metal / ferroelectric / metal capacitor with a radius of 25 μm (see Figure 25). PUND tests are preferred over polarization-field hysteresis loop (PE loop) measurements because the PE loops of 45 nm AlScN exhibit polarization-dependent leakage, which prevents the observation of polarization saturation upon application of a positive field that switches the material to the metallic polar state. The PUND results show a remanent polarization of ∼150 μC / cm, as shown in Figure 12Bc. 2, which is consistent with the previous observations. To further verify the ferroelectric switching, a dynamic current response was performed, and a peak corresponding to the ferroelectric switching was observed. See Fig. 26. To further evaluate the memory effect and reliability, a durability test was performed between positive and negative polarity states, as shown in Fig. 12Bd. Fig. 12Bd shows the residual positive and negative polarization extracted from 20,000 PUND cycles. Repeated set / reset operation of the same AlScN FeD element shows that both the positive and negative polarity states are stable and can be rewritten for a significant number of cycles. The FeD element was repeatedly set / reset between low resistance state (LRS) and high resistance state (HRS) by applying negative / positive voltages to the top electrode while the bottom electrode is grounded, as shown in Fig. 12Be, using a pseudo DC voltage sweep for 100 cycles. The FeD element exhibits ultra-low operating current and self-rectifying operation with nonlinearity exceeding 106 between 9V and 0V, thereby suppressing leakage current without additional access transistors or selectors. The distribution of resistance values ​​of LRS and HRS is summarized in FIG. 12Bf, and a strict distribution is observed in the cycle-to-cycle variation of the ratio of LRS to HRS.

[0041] Figure 12B. Electrical properties of AlScN / MoS2 FE-FT at room temperature. a) 3D schematic diagram of AlScN FeD element and cross-sectional TEM image of AlScN FeD showing 45 nm AlScN as ferroelectric switching layer. b) The high-resolution phase-contrast TEM images obtained from regions (1) and (2) in (a). c) PUND results of 45 nm AlScN thin film with pulse width of 400 ns and inter-pulse delay of 2 μs. The PUND test shows a saturated remnant polarization of 150 μC / cm 2 d) Remanent polarization extracted from PUND measurements during endurance testing of AlScN films with a pulse width of 1.5 μs and amplitude of 26 V. e) 100 program and erase cycles measured on a 45 nm AlScN based FeD. f) Resistance distribution of the HRS and LRS in e during programming and erasing.

[0042] 2-FeD TCAM cell for search We next focus on the CIM circuit architecture and computer applications with the above FeDs acting as non-volatile memories. First, we demonstrate the implementation of TCAM using our FeDs. TCAMs are a key component in the hardware implementation of CIMs that realize fast and energy-efficient parallel searches in big data applications. TCAMs perform the search function by comparing the input data with the stored data in the memory array in parallel and returning the data address if a match is found. Such parallel search allows TCAMs to perform a look-up table function in one clock cycle. Unlike binary content-addressable memory cells that store bit values ​​of either "0" or "1", TCAM cells can additionally store an "X" ("don't care") bit, which is in a match state regardless of the input search data, making TCAMs more powerful in search applications. However, in conventional Si CMOS architectures, multiple transistors (~16) are required to configure one TCAM cell in static RAM (SRAM) (Figure 13a). This configuration results in a large footprint and high power consumption due to the charging and discharging of the transistors and the parasitic capacitance of the wiring. This limits the use of this configuration in high-speed, large-scale, and power-constrained systems. Non-volatile memory (NVM) is a promising choice for implementing TCAM because it is area- and energy-efficient, forming a single TCAM cell in a more compact architecture and retaining the stored information even when power is removed. TCAMs based on resistive RAM (PRAM), magnetic tunnel junction (MTJ) RAM, floating gate transistor memory (FLASH), and phase change memory (PCM) have already been demonstrated. However, all of these architectures are built on top of front-end-of-line transistors, and none of them are fully BEOL compatible.

[0043] In this study, the large nonlinearity of the FeD makes it unnecessary to incorporate transistors, and the cell structure of the TCAM can be greatly simplified by using only two FeDs (Fig. 13a). The operation of the single FeD TCAM cell is shown in Fig. 13b. From this cell structure, it is natural to use an FeD crossbar memory array for the demonstration of the TCAM, where the signal lines connecting the anode and cathode are parallel in bit search, as shown in Supplementary Fig. 17. First, we explain how the FeD-based TCAM stores and searches a "0" or "1" bit (Fig. 13b). During the cell operation, complementary states are first written to the two FeDs, and if the search data biased on the search lines (SL and SL) matches the stored information, the match line (ML) remains high, otherwise the ML is pulled down. As shown earlier, the FeD element is highly self-rectifying and maintains a high on / off ratio. Therefore, discharging to the ML can only occur if the FeD is programmed to a low resistance state and the read voltage is higher than the turn-on voltage of the FeD.

[0044] As shown in FIG. 13b, a logic "1" state is written to the FeD TCAM cell by setting the left / right FeDs to a low / high resistance state, respectively. During the search operation, the match line is biased by a read voltage Vs that is higher than the turn-on voltage of the FeDs. The high / low voltages are then applied to the left / right FeDs, respectively, to search for a logic "1" and the high / low voltages are applied to the left / right FeDs, respectively, to search for a logic "0". In this context, "high voltage" refers to the read voltage Vs that is higher than the turn-on voltage of the FeDs and lower than the write voltage. Conversely, "low voltage" refers to a read voltage that is close to zero and much lower than the turn-on voltage of the FeDs. Since the left FeD is in parallel with the right FeD, a match state is observed only when both the FeDs in a cell are cut off (FIG. 13b, left panel). Based on these write and search methods, when the stored data and the search data match (as shown in the left diagram of Fig. 13b, the storage bit is logic "1" and the search bit is logic "1"), the FeD in the low resistance state is turned off because the voltage drop between its anode and cathode is close to zero, which is lower than the turn-on voltage. Furthermore, the current passing through the FeD in the high resistance state is naturally small, so the FeD in the high resistance state is also cut off. Therefore, the discharge currents of the two channels are both at a minimum, and the ML is kept at a high level. However, when the search data does not match the stored data, the right FeD in the high resistance state remains cut off, but the left FeD is not cut off. The left FeD in the low resistance state turns on because the voltage drop between its anode and cathode is VS, which is higher than the turn-on voltage. Therefore, the discharge current is large and the volatilization amount of the ML is low (Fig. 13b, center panel). We also show a ternary “don’t care” state in the TCAM based on the two FeDs. As shown in the right panel of Fig. 13b, a logical “don’t care” state is written to the FeD TCAM cell by forcing both the left and right FeDs into a high-resistance state.With the above write scheme and the same search scheme for logic “1” and logic “0”, no matter what signal arrives at the two FeDs, both the FeDs are always disconnected since they are in the high resistance state. Figure 13c shows repeated pseudo-DC reads of the resistance of the TCAM cell based on the two FeDs for both match and mismatch states of the search data and stored data bit “1” with a moderate search voltage of 7V applied to the FeDs. Figure 13d shows repeated pseudo-DC reads of the resistance of the two FeD TCAM cell for the stored data bit “don’t care” with both query bits “1” and “0”. This shows that for both queries, the ML resistance of the TCAM based on the two FeDs remains high and thus no discharge occurs through either of the two FeDs. Thus, the TCAM cell with the two FeDs is fully functional in all three states. The complete lookup table of the TCAM cell based on the two FeDs is summarized in Table 1 of the Supplementary Information.

[0045] Traditional two-terminal NVM (memristor) is always paired with a front-end transistor to construct a TCAM cell. This is because a transistor is connected in series with the two-terminal NVM, and therefore a transistor is required to block the channel. The FeD-based design benefits from a high self-rectification ratio that blocks the channel without the need for any transistor. In other words, the FeD conceptualizes the function of the transistor in its self-rectification operation. The absence of a transistor results in a smaller footprint and area efficiency, which in turn improves the search speed of the FeD-based TCAM. Using SPICE simulation, we verified that the search delay of the FeD-based TCAM is reduced compared to the preceding TCAM architecture based on 2-transistor-2-resistor (2T-2R). A benchmark comparison chart of the lateral footprint and search delay of various TCAM cells is shown in Figure 13e. It is clear that our two FeD-based TCAMs outperform CMOS SRAM and other transistor+NVM element based architectures.

[0046] The sensing margin of our FeD-based TCAM is a function of both the self-rectification ratio and the on / off conductance (or current) ratio. Our detailed compact model (see Supplementary Note 1) shows that the on / off ratio of the FeD can be further improved by integrating a non-ferroelectric insulator on top of the ferroelectric layer and engineering both the thickness ratio of the ferroelectric layer to the non-ferroelectric insulator layer and the coercive field of the ferroelectric layer. Future work will focus on further improving the sensing margin by engineering these variables.

[0047] Figure 13 2-FeD TCAM cell for search operation, a) Box schematic of a TCAM cell with match line (ML), search line (SL) and search line (SL bar) electrodes (left). Schematic of a single 16-transistor (16T) TCAM cell based on CMOS voltage static RAM (SRAM) technology and a 2-transistor 2-resistor (2T2R) TCAM based on resistive memory elements such as PCM and RRAM (center). The TCAM cell with two ferrodiodes proposed in this work (right) greatly simplifies the design of the TCAM by using two FeDs connected in parallel but with opposite polarization. b) The operation of a TCAM cell consisting of two FeDs has "Match", "Mismatch" and "Don't care" states. c) The resistance of the two FeD TCAM cells was repeatedly subjected to pseudo DC reads in both cases where the search data and the stored data bits "1" matched and mismatched, showing a difference of more than 100 times compared to the ML ratio. d) Repeated pseudo DC reads of the resistance of the two ferrodiode TCAM cells for the stored data bit "don't care" using both query bits "1" and "0" reveal that the ML resistance of the two FeD TCAMs is high for both queries and therefore does not discharge through either of the two FeDs. e) Benchmark comparison chart of TCAM cell lateral footprint and search latency for various memory technologies. For this estimate, 0.0081μm 2 A single FeD area of ​​100m2 is assumed.

[0048] Neural Networks We next focus on the application of our FeD element array to deep neural network (DNN) inference, which involves repeated matrix multiplication / accumulation (MMAC) operations. MMAC operations and DNNs are typically implemented at the software level. However, software implementations are particularly challenging to deploy in power- and resource-constrained devices and environments. This is again largely due to the traditional von Neumann computer hardware approach, which is memory-access intensive and difficult to parallelize. Performing the MMAC operation in the analog domain offers a promising alternative. Memristors with analog capacitors have been shown to be an excellent hardware medium for performing MMAC operations. By leveraging the high parallelism of the Kirchhoff Current Law (KCL), we can significantly reduce the MMAC operation and read out the accumulated current in each bit line of the memristor in a single clock. This is achieved by encoding the input vector into an analog voltage amplitude and the matrix elements into the conductance of the memristor array.

[0049] An ideal memristive element suitable for MMAC should have a linear arrangement of conductance values ​​across electrical programming, a linear dependence of current on driving voltage, and a high resistance to suppress the amount of current. Previous work in this area has focused mainly on memristive elements that exhibit good ohmic behavior and a large number of conductance states, such as PRAM and PCM. In the context of DNN inference accuracy, a linear relationship between current and voltage is required to minimize distortion of the input data, and a large number of conductances minimizes precision loss in the weight matrix, which are essential to perform high-precision inference tasks. However, from the perspective of power and area efficiency, good ohmic behavior and a large number of conductance states undermine the architectural metrics that achieve power efficiency and low latency per computation. There are several reasons for this. First, memristive elements with good ohmic behavior come at the cost of high element conductance. Second, the corresponding need for a large number of conductances necessitates high-precision analog-to-digital converters (ADCs). It is already known from previous studies that in memristor array systems, the power and area costs at the circuit level are dominated by the ADC. Therefore, in a DNN inference engine, the more conductance states there are, the higher the power overhead at the architecture level. Thus, there is a clear trade-off between the inference accuracy of the DNN and the power and area efficiency. Here, we show that an optimal trade-off between these metrics can be achieved by using FeD memristors. First, to achieve the trade-off on the conductance of the element, it is important to reduce the operational conductance of the memristor element while maintaining its linear behavior. The former condition is easily met for devices with high self-rectification, which is an inherent property of the FeD. The latter condition can be met by applying an encoder to the input voltage amplitude to linearize the current-voltage relationship (see Supplementary Note 2). Second, to mitigate the trade-off on the number of conductance states, a small number of sparsely linearly arranged conductance states are required.This approach can achieve comparable inference accuracy compared to approaches that implement multiple conductance states.

[0050] FIG. 14A shows the sequential switching of the FeD by stepped voltage pulse modulation. The FeD cell is sequentially programmed to 16 different conductance states using stepped voltage pulses. These conductance states show high linearity with respect to the number of programming pulses as described below. The figure (left) shows a sequence of programming operations in which the stepped voltage pulses (ranging from 16V to 19V) are applied to the top electrode of the FeD, followed by an erase operation each time. The callout window (right) shows the conductance vs. pulse number for a representative cycle. FIG. 4d shows that the FeD element is capable of analog bipolar switching with voltage pulses (ranging from 116V to 19V, left). The callout window (right) shows one cycle of sequential programming and sequential erase. The FeD element showed better linearity (R2 score of 0.9997 for linear fit) over the 16 different conductance states than bidirectional modulation. The conductance retention for 16 different conductance states is shown in Figure 14c, with no obvious degradation. Figure 4d shows the conductance state distribution of five separate FeD elements subjected to an identical sequence of 16 program pulses (pulse width 2 μs) with interleaved readout (8 V). The results indicate that element-to-element variation is negligible among these FeD elements. Note that the conductance range of the FeD elements used to program these states (~25-250 nS) is much smaller compared to the conductance range used for TCAM operation (~2-250 nS). This is primarily because linearity of operation is better achieved over the smaller conductance range. Furthermore, the DNN inference application does not necessarily require a high range of conductance modulation. The performance of an array composed of such FeD elements is simulated in a practical application using a trained convolutional neural network (CNN) for computer vision. A CNN (containing two convolutional layers and one fully connected layer) is trained on the MNIST dataset (MNIST, a modified National Institute of Standards and Technology database) and subsequently transfers the pre-trained weights to the FeD conductance range.A diagram of the network is shown in Fig. 14e. A coefficient of variation A, a measure of nonlinearity, was added to analyze the accuracy degradation due to weight movement to low-precision conductance values. The relationship between the A factor and the nonlinearity is detailed in Supplementary Note 3. Thus, the weights of the fully trained network are quantized to the number of conductance states (varies from 1 to 9 bits). Then, the accuracy of the network on the MNIST test dataset is re-evaluated. As can be seen in Fig. 14f, the convolutional neural network is robust to low-precision weight movement with low nonlinearity (A>0.5), where a 97.5% full-precision test accuracy in single-precision floating-point format (FP32) is recovered with only 3 bits of weight precision for low-precision weight movement variations. For high nonlinearity (A>0.35), 1 or 2 bits of weight precision are required to recover full-precision test accuracy on FP32, indicating that a sparse but linear arrangement of highly linear conductance states can replace a large number of conductance states and perform comparable inference accuracy. Furthermore, we trained the same convolutional neural network and simulated an in-memory implementation of in-situ training on an FeD array, where weight updates are directly mapped to the realistic conductance states of the FeD after each backpropagation. As shown in Figure 14g, for the individual conductance states of the FeD element 16 demonstrated in Figure 14a, the accuracy of the in-situ training is ~2% lower than that learned on FP32. However, with more advanced low-precision training techniques and model compression techniques in software, this number can be significantly reduced, and we believe that performing low-precision weight transfer on FeD elements during the training phase will cause little accuracy degradation.

[0051] Thus, the AlScN-based ferrodiode element is a BEOL-compatible platform for multifunctional CIM in transistor-free architectures. Experimental demonstration of search functionality is achieved by TCAM circuits with lateral cell footprint and search latency that outperform existing and experimental NVM technologies. Finally, we demonstrate a stable pulse-programmable 4-bit memory with ferrodiode elements combined with a hardware implementation of a convolutional neural network with inference accuracy comparable to software. Our work therefore opens new possibilities for CIM platforms by enabling architectures using new ferroelectric materials and diode elements based on them.

[0052] Fig. 14. FeD-based neural network. a) Sequential switching of a ferrodiode (FeD) with stepped voltage modulation pulses. The FeD cells are sequentially programmed to different conductance states using stepped voltage pulses. The left panel shows a sequence of programming operations in which the stepped voltage pulses are biased to the top electrode of the FeD, followed by an erase operation each time. The call-out window (right panel) shows the conductance vs. pulse number for a representative cycle. b) The FeD is demonstrated to be capable of analog bipolar switching with voltage pulses (left). The call-out window (right) shows one cycle of sequential programming and sequential erasure. The FeD element shows excellent linearity over 16 different states. c) Resistance retention for 16 different resistance states. d) Resistance state distribution of five separate FeDs sequenced with 16 program pulses (pulse width 2 μs) with interleaved readout (8 V). e) Diagram of a CNN trained on the MNIST dataset. A hardware implementation of a neural network using ferroelectric diode arrays for matrix multiplication can operate in a fully analog mode without surrounding analog-to-digital converters. f) Simulation results of the inference effect of the network in e). The simulation involves an inaccurate weight mapping of the network, which is composed of FeD elements with an analog weight layer and trained on MNIST using FP32 calculations. The simulation in f) shows that for A<0.5, even with a weight precision as low as 3 bits, the degradation of the inference accuracy of the network is less than 1%. g) Simulation of the network in e) trained in-situ with the FeD elements with an analog weight layer. Leveraging the excellent linearity in sequential programming of the FeD, the analog weight layer with 16 resistance states is simulated to operate with inference accuracy equivalent to the FP32 calculation baseline.

[0053] Fabrication of the element FeD is Si / Al 0.8 Sc 0.2 On a N (85 nm) substrate, Al (80 nm) / Al0.68 Sc 0.32 The layer structure is a 6-inch Si substrate. <100> On top of the wafer, an 85 nm thick Al 0.80 Sc 0.20 The AlN template layer is deposited by sputtering. 0.8 Sc 0.2 N is a single alloy of Al 0.8 Sc 0.2 Pulsed DC reactive sputter deposition of N target was used, target power 5kw, pressure 7.47x10 -3 The films were deposited in a N2 atmosphere at 3756°C and 1000 mbar. The first layer of 85 nm of Al0.8Sc0.2N served to orient the subsequent 80 nm thick Al layer in the {111} direction. This Al (80 nm thick) layer was the Al ferroelectric layer used in this device. 0.68 Sc 0.32 The second layer of ferroelectric AlN (45 nm thick) serves as the bottom electrode. 0.68 Sc 0.32 N films were co-sputtered from separate 4 inch Al and Sc targets in an Ecatec CLUSTERLINE® 200 two-pulse DC physical deposition system. The Al and Sc targets were operated at 1250W and 695W, respectively, with a chuck temperature of 350 degrees Celsius, and Ar gas flows of 10 sccm and N2 gas flows of 25 sccm. The chamber pressure was ~1.45x10 -3 The pressure in the vacuum chamber was kept at 1000 psi (mbar). Under these sputtering conditions, the deposition rate was 0.3 nm / sec. The highly oriented {111}Al layer promoted the growth of AlScN with its

[0001] axis perpendicular to the substrate, resulting in a highly textured FE film. Then, without breaking the vacuum, a 30 nm Al layer was deposited as the top electrode and a ferroelectric Al 0.68 Sc 0.32 It was sputtered as a capping layer to prevent N oxidation.

[0054] Element characteristic evaluation Current-voltage measurements were performed at ambient temperature in air using a Keithley 4200A semiconductor characterization system. PE hysteresis loop and PUND measurements of ferroelectric AlScN were performed using a Keithley 4200A semiconductor characterization system and a Radiant Precision Premier2 test platform. TEM cross-section samples were prepared using the in-situ lift-out technique on an FEI Helios Nanolab 6000 focused ion beam (FIB) system. The samples were coated with a thin carbonaceous protective layer by scribing the surface with a Sharpie® marker. Subsequent deposition of a platinum protective layer by electron and ion beam was performed to prevent charging and heating effects during FIB milling. In the final cleaning step, a low-energy Ga+ ion beam (5 keV) was used to reduce FIB-induced damage. TEM characterization and image acquisition were performed using a JEOL F200 operating at an accelerating voltage of 200 kV. The samples were imaged oriented along the axis of the

[0001] zone. All the TEM images were collected using Digital Micrograph software.

[0055] A compact model for evaluating the on / off ratio of ferroelectric diodes General method for evaluating on / off ratio In order to evaluate the on / off ratio of the ferroelectric diode (FeD) and understand the four characteristics, it is necessary to understand the electron transport in the ferroelectric diode. There are three main ways of electron transport in the ferroelectric diode: direct tunneling, Fowler-Nordheim tunneling, and thermionic emission. The band diagram showing the effect of each is shown in Figure 15. Using the Wenzel-Kramers-Brillouin (WKB) approximation, all three methods can be encompassed by one equation. In this approximation, the tunneling probability is given by

[0056]

number

[0057] where m* is the effective mass of the electron, E c is the coercive field of the ferroelectric, V(x) is the voltage across the ferroelectric, and E is the applied magnetic field. The integral of the density of states is

[0058]

number

[0059] where KBT is the Boltzmann constant multiplied by temperature, E f,1 and E f,2 are the left and right Fermi levels of the ferroelectric. Using these equations, we can define the current density J as

[0060]

number

[0061] This current density multiplied by the area of ​​the ferroelectric film is the tunneling current through the device. Although this model effectively captures the IV characteristics of a ferroelectric diode, it lacks efficiency.

[0062] Figure 15 shows three methods of electron transport through a potential barrier: (a) direct tunneling, (b) Fowler-Nordheim tunneling, and (c) thermionic emission.

[0063] Voltage shift model and its verification Voltage Shift Model In our analysis, we propose a new compact shift model to describe the IV characteristics of the FeD. In the FeD, the change in the IV curve of the diode from low resistance state (LRS) to high resistance state (HRS) can be treated as the IV curve shifts from left to right by ΔV as it transforms from LRS to HRS. In other words, to generate the same current as in LRS, more voltage is required to offset the ΔV voltage in HRS. The shifted voltage ΔV can be derived as follows:

[0064]

number

[0065] where t is the thickness of the ferroelectric layer, E dp is the depolarizing magnetic field of the ferroelectric material, and it has been found that the depolarizing magnetic field can be expressed as

[0066]

number

[0067] Here, E C is the coercive field of the ferroelectric layer, P r is the remanent polarization, ε is the dielectric constant of the ferroelectric, and β is the oxide capacitance C ox and the ferroelectric capacitance C fe This is a parameter related to

[0068]

number

[0069] Comparison of voltage shift model and WKB approximation The voltage shift model has been verified to provide results in relative agreement with the IV characteristics of the ferroelectric diode modeled with the WKB approximation shown in FIG. 16. Furthermore, the voltage shift model is more efficient since it utilizes analytical equations rather than numerical integration as in the WKB approximation. Furthermore, the hyperbolic function of the new model provides a better understanding of the depolarization electric field E dp is the coercive field E in the model C This helps to focus on the read voltage region of the IV curve.

[0070] Figure 16. Comparison of the four curves for an arbitrary ferroelectric using the WKB approximation (green) and the new voltage shift model for ferroelectric diodes (blue). The purple curve shows the base curve in the high resistance state modeled with the WKB approximation.

[0071] IV curves and on / off ratios associated with the voltage shift model After validation of this compact model, it was used to determine the overall trends of the on / off ratio of the ferroelectric diode versus parameters such as oxidation capacitance, remanent polarization, and coercive field.

[0072] Changes in IV curves and on / off ratio with oxide capacitance First, the I-V curves of the FeD shift under different insulator capacitances are plotted. β is varied between 0 and 1. By selecting appropriate values ​​of remanent polarization and coercivity, the simulated I-V curves of the HRS shift are shown in Figure 17(a)). And the on / off ratio with varying β is shown in Figure 17(b).

[0073] Figure 17 shows (a) a plot of the IV curve shift of the HRS versus the change in pre-coded oxide capacitance β, where β is exponentially varied from 0.01 to 0.54 to better see the trend of the IV curve shift. (b) On / Off ratio versus β, where the on / off ratio is the current ratio between the LRS and the corresponding shift curve at a voltage of 7V in (a).

[0074] IV curve and on / off ratio change with remanent polarization Next, the appropriate insulator capacitance C ox and coercive field E C Using the above, the remnant polarization P r 1~135μC / cm 2 The IV characteristics obtained are shown in Fig. 18(a) and Fig. 18(b) show the on / off ratio under different remanent polarization.

[0075] FIG. 18 is a plot of the shift of the IV curve of HRS due to the change in the remanent polarization Pr. r 1~135μC / cm 2 (b) shows the on / off ratio vs. P rwhere the on / off ratio is the current.

[0076] Changes in IV curves and on / off ratio with coercive field Finally, the coercive field E of 0.12 to 3.12 MV / cm C The IV curve shift plot versus the coercive field is shown in Figure 19(a), and the corresponding plot of the on / off ratio of the FeD under different coercive fields is shown in Figure 19(b).

[0077] Figure 19. The coercive field E C The plot of the IV curve shift of HRS due to the change in E is shown in (a). C The on / off ratio was linearly changed from 0.12 to 3.12 MV / cm. (b) shows the on / off ratio versus EC, where the on / off ratio is the current ratio between the LRS at a voltage of 7 V in (a) and the corresponding shifted curve.

[0078] The IV curves in Figures 17-19 show that the HRS curve shifts further when the coding insulator capacitance β, the remnant polarization Pr, or the coercive field EC increases. And, from both Equation 5 and Figures 17-19, it can be seen that the hyperbolic function of Equation 5 limits the influence of the remnant polarization Pr and the oxide capacitance on the shift of the IV curve. On the other hand, when the coercive field EC increases, the on / off ratio increases rapidly and is not limited by the hyperbolic function.

[0079] Linearization of the current-voltage relationship of ferroelectric diodes. In the log I-V characteristics of the device shown in FIG. 20, the log I has excellent linearity with the applied voltage, and the slope of the plot for the 16 states of the element is consistent in fitting.

[0080] Figure 20. Log(I) vs. V. Current I measured by applying a DC voltage sweep to 16 different conditions.

[0081] To linearize the IV characteristic of a ferroelectric diode:

[0082]

number

[0083] Here, Gi is a parameter related to the conductance of the diode.

[0084] The constant slope α can be estimated by linear regression for 16 different logI-V characteristics of the ferroelectric diode element.

[0085] Figure 21. Current I vs. exp(αV) for 16 states. From Figure 21, we can see that the I-exp(αV) characteristics of the ferroelectric diode for 16 states show good linearity and cross at the origin, which is the same as the IV characteristics of an ohmic resistor. The different slopes of all 16 states are proportional to the conductance of the 16 states, which also behaves linearly.

[0086] Due to the linear characteristic between the current I and the voltage function f(V)=exp(αV), the input can be linearly associated with f(V). For example, assuming that there are inputs ranging from 0 to 1, the input 1 can be associated with the maximum (exp(αV)) and the input 0 with the minimum (exp(αV), and the inputs between 0 and 1 are evenly distributed between min(exp(αV)) and max(exp(αV)). Therefore, to associate each input with the corresponding f(V) and decode f(V) to obtain the corresponding voltage V, the following can be done.

[0087]

number

[0088] Figure 22. (a) An image of the digit "5" input from the MNIST dataset. (b) Plot after encoding the input signal by mapping it to a realistic voltage V. The function remains after transforming the input signal into the voltages applied to the elements.

[0089] Figure 22(b) shows the MNIST input shown in Figure 22(a) converted to an encoding of the voltage amplitude applied to the element, with the intensity as the input signal. In this way, the AlScN ferroelectric diode can be used as a simple resistor in neural network computations by simply encoding the input V into a function f(V), and obtaining a measured current I as the output, as shown below:

[0090]

number

[0091] To verify the encoding scheme on a realistic device, a series of inputs in the range [0,1] are encoded into a read voltage range [4V,8V]. The encoded voltages are then applied directly to the ferroelectric diode device and the current in response to the original input is measured as the output.

[0092] Figure 23. Measurement of the output current upon application of the encoded voltage to the ferroelectric diode element in response to the original input.

[0093] As shown in Figure 23, the output current exhibited excellent linearity with respect to the input, with an R score of 0.9998 for the linear fit, verifying that the AlScN ferroelectric diode can be used as a simple resistor in neural network computations simply by using this linearization encoding method.

[0094] Nonlinear weight updating of ferroelectric diodes. A linear quantization sequence is typically used to map pre-trained weights to memristors, so ideally, the weight increment and decrement should be linearly proportional to the number of write pulses. However, realistic elements reported in the literature do not follow such an ideal trajectory, and the conductance usually changes rapidly at the beginning and then gradually saturates. This is one of the main reasons that inhibit high-precision hardware matrix multiplication. Such nonlinear weight updates for realistic elements can be evaluated by the coefficient A.

[0095]

number

[0096] Here, G min and G max are the minimum and maximum conductance values ​​measured by the element, N is the number of pulses applied, and N0 is the maximum number to apply. From the above equation, we can conclude that as A becomes smaller, the element will perform a worse nonlinear weight update.

[0097] Figure 24. (a) Normalized conductance with nonlinear weight update varying coefficient A. (b) The normalized conductance measured with the realistic FeD element.

[0098] As shown in Figure 24(b), the normalized conductance measured for our demonstrated FeD element shows an A of over 10 relative to the ideal value and an R2 score of 0.9997, indicating a near-ideal weight update.

[0099] Table 1 in the Appendix shows the voltage mode and encoding table for the storage states, search voltages, and search results for various values ​​of the demonstrated TCAM.

[0100] Figure 25. a) Schematic of the signal sequence of the PUND measurement to distinguish the ferroelectric and non-ferroelectric contributions to the polarization, b) PUND current density showing ferroelectric switching within 400ns of the start of the voltage switching pulse.

[0101] Figure 26. Dynamic current response in 45 nm AlScN. a) Schematic of the signal sequence for dynamic current response measurement to observe the ferroelectric switching induced current response. b) Current-voltage hysteresis loop for 45 nm thick AlScN corresponding to the signal sequence shown in a). The plot shows a positive coercive field of +4.62 MV / cm and a negative coercive field of -3.79 MV / cm. Optimization of leakage of the ferroelectric film is an ongoing task.

[0102] Figure 27. The TCAM cell structure makes it natural to use the FeD crossbar memory array, in which the signal lines connecting the anode and cathode are parallel, for bit search in the TCAM demonstration.

[0103] Example: CMOS-compatible aluminum-scandium-nitride based ferroelectric diode memory element CMOS Back-End-of-Line (BEOL), Complementary Metal-Oxide-Semiconductor (CMOS) compatible Al 0.64 Sc 0.36 N-based ferroelectric diodes exhibit polarization-dependent hysteresis in their leakage current. Our devices are fabricated using a metal / insulator / ferroelectric / metal structure (Pt / native oxide / Al) compatible with BEOL temperatures (~350°C) grown on 4-inch silicon wafers. 0.64 Sc 0.36 The device is constructed of a 100-V CMOS transistor (Cu / N / Pt). The device exhibits self-selecting behavior as a diode with a rectification ratio of over 105 (at 5 V). Leakage current can be suppressed without additional access transistors or selectors. Furthermore, considering the polarization-dependent leakage current, the current-voltage sweep of the diode is similar to that of a memristor with an on / off ratio between low and high resistance states of ~50,000. Our device also exhibits stable programmed resistance states during DC cycling and has a retention time longer than 1,000 s at 300 K. These results indicate that this system has great potential as a future high-performance post-CMOS compatible non-volatile memory technology.

[0104] Emerging device applications such as Internet of Things (IoT) devices, non-von Neumann computing architectures, and artificial intelligence (AI) computational algorithms are creating a strong demand for low-power, high-density non-volatile memory (NVM) solutions. Among various emerging NVM technologies, ferroelectric random access memory (FeRAM) is attractive due to its fast access, high endurance, extremely low write energy and current, and good retention. However, the incorporation of FeRAM into commercial-scale semiconductor applications has stalled at the 130 nm node. There are three main challenges that have hindered the rapid development of ferroelectric (FE) memory and challenged classical charge-based memories and other NVM technologies: 1) Conventional one-transistor, one-ferroelectric capacitor (1T1C) structures are subject to destructive reads and have a large footprint; 2) Conventional ferroelectrics are not compatible with standard BEOL, CMOS processes; and 3) perovskite FE materials such as lead zirconate titanate (PZT) and barium titanate (BTO) exhibit degradation in ferroelectric properties as they are scaled down to thinner layers.

[0105] To address these issues, various new technologies have been developed in the past decade. Two-terminal elements such as ferroelectric diodes and ferroelectric tunnel junctions (FTJs), which use polarization-dependent leakage or tunneling currents and rectification for resistive switching (similar to memristors), are promising alternatives to 1T1C cells. This is because they have the advantage of being compact, two-terminal devices with non-destructive readout. In recent years, FTJ memristors based on doped HfO2 have attracted much attention for compact non-volatile memory applications. However, many reports have shown that the high annealing temperatures (>400 degrees Celsius) required for doped HfO2 to acquire ferroelectricity make them unsuitable for integration in CMOS BEOL processes. A high on / off ratio is essential not only to enable low-power in-memory computing, but also to maintain strong immunity to noise and variations when used in new applications such as multi-bit memory elements for neuromorphic computing.

[0106] Sc-doped AlN, a recently discovered ferroelectric, offers a promising route to the realization of practical two-terminal ferroelectric nonvolatile memory devices. AlN alloyed with Sc has a large coercive field E of 2-4.5 MV / cm. c This allows scaling to thinner ferroelectric layers while maintaining a large memory window. 2 High remanent polarization P r Combined with, this leads to large resistive switching with strong tunnel barrier modulation and therefore high on / off ratios.Recently reported ferroelectric switching at low deposition temperatures (below 350 degrees Celsius) in sub-20 nm Sc-doped AlN enables the direct integration of these devices into CMOS, BEOL compatible processes.

[0107] Here, we fabricated an Al substrate using a full BEOL, CMOS-compatible process on a 4-inch Si wafer. 0.64 Sc 0.36 We demonstrate a ferroelectric diode based on N.Al with a thickness of 20 nm.0.64 Sc 0.36 Ferroelectric capacitors using N as the ferroelectric layer and a thin native oxide barrier layer exhibit polarization-dependent leakage current hysteresis and can be used for up to 10 5 We have achieved a large self-rectification ratio of over 100, a high on / off ratio of over 50,000, stable programmed states under DC cycling, and a retention time of over 1,000 seconds at 300 K. These results are promising for future high-performance CMOS BEOL compatible NVM.

[0108] Figure 28(a) shows Pt / native oxide / Al 0.64 Sc 0.36 A schematic diagram of an N / Pt element. A Pt (100 nm) bottom electrode (BE) was formed on a Si substrate by sputtering. Next, a 20 nm Al 0.64 Sc 0.36 The N films were co-sputtered from two separate 4 inch Al (1000 W) and Sc (655 W) targets in an Evatec CLUSTERLINE® 200 two-pulse DC physical vapor deposition system. The deposition was performed at 350 degrees Celsius with a N gas flow of 20 sccm. The top electrode (TE) area was then patterned using standard photolithography, followed by deposition of a Pt (100 nm) metal top electrode and a lift-off process, as shown in Figure 28(c). Figure 28(b) shows the Al on PtBE. 0.64 Sc 0.36 The cross-sectional transmission electron microscope (TEM) of the AlN film. In the inset of Fig. 28(b), a high-resolution TEM image of the area enclosed in a red box shows the AlN film. 0.64 Sc 0.36 The device shows a textured epitaxial growth of a N film and a ~4 nm native oxide on the ferroelectric surface due to exposure to air. Energy dispersive X-ray spectroscopy (EDS) analysis map of the device cross section suggests that the oxide has similar Al and Sc concentrations as the nitride. Note that the presence of an oxide is not necessary to demonstrate the polarization dependent leakage, which is the most fundamental and defining characteristic of this device. 0.64 Sc 0.36The Schottky barrier between N and Pt introduces an asymmetry into the device structure. Modulation of this Schottky barrier by ferroelectric polarization switching results in a large difference in leakage current between sweeps combined with the rectifying function of the device (similar to a diode), hence the name ferroelectric diode. There are several other examples in the literature based on other ferroelectric materials that show the same device concept, functionality and are referred to by the same name. Here we demonstrate this concept with a ferroelectric material based on AlScN.

[0109] The leakage of this device is polarization dependent and asymmetric, so that the ferroelectric polarization during switching is convoluted by the leakage in typical polarization-electric field (PE) loop measurements. To overcome this problem, we suppress the leakage and use Al 0.64 Sc 0.36 To clarify the FE characteristics of N, we performed positive-up, negative-down (PUND) measurements at low temperature (120 K) and relatively high frequency (10 kHz). For details of the PE hysteresis measurements at room temperature, please refer to our previous work. Figure 28(c) shows the Al FE characteristic extracted from the PUND measurements. 0.64 Sc 0.36 The typical PE hysteresis loop of an N-type device is shown. The pulse circuit diagram for the PUND measurement is shown in Supplementary Information Fig. 32, as in our previous work. The measurement results were obtained with a coercive field of 6.5 MV / cm and a hysteresis loop of 25 μC / cm. 2The coercive field is observed to be slightly larger than that observed in our DC measurements. This is speculated to be because the coercive field has been reported to increase significantly with decreasing temperature and increasing measurement frequency. The relatively low remnant polarization is likely due to the partial ferroelectric switching occurring during the PUND measurements at low temperatures. Furthermore, the CV curve of the device measured at 1 MHz at room temperature (Figure 28(d)) shows a butterfly-shaped loop suggestive of a nonlinear capacitor with decreasing capacitance with increasing applied voltage, indicating ferroelectric polarization switching. Similar CV curves have been reported for FTJ or ferroelectric diode devices based on other FE materials. In addition, a clear ferroelectric switching induced peak was observed during the first CV sweep, which disappeared upon repeated CV measurement sweeps (see Supplementary Information Figure 33), further suggesting the ferroelectric nature of the switching.

[0110] FIG. 29 shows the Al 0.64 Sc 0.36 The IV characteristics of a N ferroelectric diode are shown in semi-logarithmic and linear scales. The blue plot shows the nonlinear diode-like IV curve with TE polarization after applying a negative program voltage, and the orange plot shows the IV curve with BE polarization after applying a positive program voltage. After being programmed with a positive voltage, the resistance changes from high to low and the memristor polarity changes from a negative forward diode (blue line) to a positive forward diode (orange line). Similarly, with a negative voltage sweep, it can be observed that the memristor polarity changes from a positive forward diode to a negative forward diode. The Al 0.64 Sc 0.36Due to the presence of a Schottky barrier between N and the metal electrode (Pt), the device exhibits self-selecting behavior as a diode with a rectification ratio of over 205 at 5 V, which may suppress leakage current without additional access transistors or selectors when used in crossbar arrays. A large on / off current ratio of 50,000 is obtained between forward and reverse voltage sweeps at a read bias voltage of ∼2.5 V, which exceeds the on / off ratios reported so far for hafnia-based FTJs and ferroelectric diodes. A summary of key characteristics of ferroelectric memristive devices from the literature is provided in Table 2 of the Supplementary Information, focusing on the CMOS compatibility, on / off ratio, and ferroelectric layer thickness. It is noteworthy that the Al0.64Sc0.36N-based ferroelectric diode we reported is one of only two demonstrated examples that simultaneously exhibit high on / off ratios while being compatible with CMOS BEOL processes. It should be noted that although the presence of a surface oxide may be important to obtain a large on / off current ratio, the oxide layer is neither necessary nor important to exhibit the ferroelectric effect in our devices. 0.68 Sc 0.32 This is also evident from the fact that in-situ deposited MIM ferrodiodes of N (45 nm) / Al (85 nm) showed a similar effect with an on / off ratio of ∼100 (see Supporting Information S3).

[0111] Furthermore, these Al 0.64 Sc 0.36 We have investigated the effect of polarization on the band diagram and electron transport in N FTJs. 0.64 Sc 0.36The N thin film is sputter deposited and contains many point and line defects, resulting in multiple trap states in the band gap. Therefore, current conduction through the MIM ferroelectric diode device with a 20 nm thick ferroelectric insulator must account for some trap-assisted transport / conduction mechanism as a means to explain the μA level currents observed in the forward bias measurements. The forward current through the diode was then fitted with the well-known trap-assisted conduction and leakage current model, i.e., Poole-Frenkei (PF) tunneling model, versus applied voltage. Furthermore, we sought to compare Fowler-Nordheim or direct wave mechanism tunneling of electrons through a modulated triangular barrier. The polarization charge effect of the ferroelectric induces an asymmetric modulation of the electronic band diagram. As shown in Figure 30, when P is flipped, the steepness of the electronic band diagram changes depending on whether the direction of P is the same or opposite to the applied electric field. As shown in Figure 30, when a positive voltage is applied to the TE, the barrier height is, on average, higher when P points to the TE than when P points to the BE. The electronic band diagrams of the high resistance state (HRS) and low resistance state (LRS) of the ferroelectric diode at positive bias are shown in Figure 30(a) and (b). With the thickness of the ferroelectric insulator layer being ~20 nm, direct wave mechanism tunneling is expected to be negligible since the tunneling probability decays exponentially with the barrier width. Thus, the current-voltage data is best fitted to the PF tunneling model, as shown in Figure 30(c). The dielectric constant of the ferroelectric layer extracted from the PF model, ~16, is close to the independent capacitance measurements, 14-15. Note that in our device, the applied electric field causes polarization switching of the ferroelectric, and this polarization switching changes the electric field profile and thus the leakage through the 20 nm thick ferroelectric layer. To explain this leakage mechanism, we use trap-assisted Poole-Frenkel tunneling. It is also worth noting that a similar mechanism has been used to describe the conduction through FTJ devices, where the ferroelectric layer thickness is much smaller.In the case of the LRS, the applied electric field follows the polarization direction of the ferroelectric. The injected electrons hop from highly occupied traps to empty traps, resulting in a large current. Conversely, when the applied electric field is opposite to the ferroelectric polarization direction, the electron hopping rate drops significantly due to fewer occupied electrons. This leads to empty traps, breaking the total number of conduction paths, and resulting in a smaller current through the diode. A complete and compact IV model of this device is an important and ongoing research topic that is beyond the scope of the present manuscript and will be reported in a future work. Finally, we would like to point out that based on the area-dependent current density scaling of the MIM device, conductive bridge formation can be ruled out as a resistive switching in the device. The ferroelectric nature of the resistive switching was further verified by the linear scaling of the on-current with respect to the area of ​​the MIM device (see Supplementary Information S4).

[0112] Preliminary reliability testing of the ferroelectric diode was also performed. Figure 31(a) shows data from 10 manual DC cycles. Cyclic IV curves from the same device show that the current-voltage characteristics are stable and reproducible. Furthermore, the two different polarization states of the ferroelectric, and therefore the resistance (current) states of the memristor, can be programmed as two non-volatile memory states. Readout with various delay times was performed to determine retention (Figure 31(b)). The low and high current / resistance states can be retained at room temperature for at least 1,000 seconds without any obvious degradation. Given that the switching of our ferroelectric diode is a purely electronic mechanism, it is subject to the same voltage-time dilemma as all other ferroelectric memory elements. However, this voltage-time dilemma can be minimized by making the ferroelectric layer thin and by having a near-ideal (square-shaped) hysteresis loop at the same time as a high coercive field, which is characteristic of AlScN material.

[0113] This Al0.64Sc0.36N-based ferroelectric diode exhibits a large difference in leakage current as a function of ferroelectric polarization, resulting in a hysteretic current-voltage loop similar to a memristor. Our devices are fabricated in a fully BEOL, CMOS-compatible process on 4-inch Si wafers. Using 20-nm-thick Al0.64Sc0.36N as the ferroelectric layer, the resulting ferroelectric diode exhibits high performance, with a large self-rectification ratio of over 105, a high on / off ratio of over 50,000, stable programmed states under DC cycling, and a retention time of over 1,000 seconds at 300 K. These results indicate that this system has great potential as a future high-performance CMOS BEOL-compatible nonvolatile memory technology.

[0114] Figure 28. (a) Metal / oxide / Al 0.64 Sc 0.36 (b) Schematic of the N / metal memristor element. (b) Pt bottom electrode grown on the Si wafer substrate and the Al 0.64 Sc 0.36 Cross-sectional transmission electron microscope image of the device showing the N ferroelectric. Inset shows high-resolution TEM image and elemental mapping by EDS of the area enclosed in the red box. (c) Al measured at 120 K. 0.64 Sc 0.36 Measurement results of N PUND. (d) A typical CV curve of the device measured at room temperature and 1 MHz, showing a typical butterfly loop.

[0115] Figure 29. (a) Semi-logarithmic and linear current-voltage characteristics of the ferroelectric memristor. The blue plot shows the nonlinear I-V curve after applying a negative programming voltage, and the orange plot shows the I-V sweep where the resistance state is programmed by a positive voltage.

[0116] Figure 30. (a) HRS and LRS electronic band diagrams of the MIM device. Note that the slope of the lines is a measure of the E field, and the trap levels are assumed to be at mid-gap. (c) Fit of the experimental current-voltage data to the Poole-Frenkel tunneling model. We extract a dielectric constant for the insulator of ∼16, showing a good fit in agreement with independent capacitance measurements.

[0117] Figure 31. (a) Cyclic 4 curves over manual DC switching cycles showing the stability and repeatability of the FTJ. (b) Retention of the low and high current / resistance states for ∼1,000 s with readout at 5 V.

[0118] Figure 32. Schematic of the pulse sequence for PUND measurements. The ferroelectric response of AlScN thin films was characterized by PUND measurements using five unipolar triangular signals with a 1 ms delay between two pulses.

[0119] Figure 33. (a) Schematic cross-section of a ferroelectric (FE)AlScN metal-insulator-metal device. Arrows indicate the polarization directions at the initial and final states of the voltage sweep for capacitance-voltage (CV) measurements. The voltage sweep numbers are indicated by arrows. (b) CV data for each sweep number indicated in (a). The first sweep shows a clear rise in capacitance up to ~7.5 V, followed by a sharp drop characteristic of ferroelectric polarization switching. The remaining sweeps show no capacitance rise, indicating that the polarization is maintained and does not switch over the same sign and magnitude range of the applied voltage.

[0120] Figure 34. The 20 nm thick Al shown in this paper. 0.68 Sc 0.32 In-situ MIM Al(30nm) / Al showing qualitatively similar IV characteristics to N-type devices 0.68 Sc 0.32 IV characteristics of a N(45nm) / Al(85nm) ferrodiode element. The element shown above was grown in-situ without breaking vacuum, so there is no oxide layer on the element, and it shows the switching behavior of a ferrodiode with an on / off ratio of ~100.

[0121] Figure 35. Three circular Pt / native oxide / Al with different top electrode diameters. 0.64 Sc 0.36 On-state sweep of current density versus voltage for N / Pt MIM devices. The on-state current density (current normalized by cross-sectional area) overlaps for all three devices, suggesting that the conductance or current increases linearly with cross-sectional area. If the devices formed a conductive bridge, the current density curves should not overlap. Thus, conductive bridge formation is ruled out as a switching mechanism.

[0122] Supplementary Information

[0123] [Table 1]

[0124] [Table 2]

Claims

1. A memory cell having an array of ferroelectric diodes, A memory cell, the ferroelectric diode comprising doped aluminum nitride (AIN), the ferroelectric diode being non-volatile and field programmable via pulsing to an analog state that is dependent on a number of pulses.

2. 2. The memory cell of claim 1, wherein the ferroelectric diode comprises scandium doped aluminum nitride (AlScN), yttrium doped aluminum nitride (AlYN), magnesium and hafnium doped aluminum nitride (AlMgHfN), magnesium and zirconium doped aluminum nitride (AlMgZrN), magnesium and titanium doped aluminum nitride (AlMgTiN), boron doped aluminum nitride (AlBN), or ytterbium doped aluminum nitride (AlYbN).

3. 3. The memory cell of claim 1 or claim 2, wherein the ferroelectric diode has an on / off ratio greater than 2, 5, 10, 25, 50, 75, 100, 500, 1,000, 5,000, or 10,000.

4. 3. The memory cell of claim 1 or claim 2, wherein the ferroelectric diode has a self-rectifying ratio greater than 25, 50, 75, 100, 200, 500, 1,000, 10,000, 50,000, or 100,000.

5. 3. The memory cell of claim 1 or 2, wherein the cell is compatible with CMOS back-end-of-the-line (BEOL) processing.

6. 3. The memory cell of claim 2, wherein the deposition temperature of the doped aluminum nitride is less than 400 degrees Celsius.

7. 3. The memory cell of claim 1 or 2, wherein the ferroelectric diode is bipolar pulse programmable.

8. 7. The memory cell of claim 6, wherein said ferroelectric diode is pulse programmable with 4-bit state resolution.

9. 3. The memory cell of claim 1 or 2, wherein the ferroelectric diode has the doped aluminum nitride layer having a thickness of less than about 100 nm, less than about 75 nm, less than about 50 nm, or less than about 25 nm.

10. 10. An array of memory cells having a plurality of instances of the memory cell of any one of claims 1 to 9, the array being arranged for a V / 2 scheme to be used to read and program the ferroelectric diodes.

11. A ternary content addressable memory (TCAM) comprising a memory cell according to any one of claims 1 to 9.

12. 12. The TCAM of claim 11, wherein the search delay of the TCAM is about 1 μs or less, about 500 ns or less, or about 100 ns, 50 ns, 10 ns, 1 ns, 100 ps or less.

13. 13. The TCAM according to claim 11, wherein each memory cell has two diodes of opposite polarity.

14. A ternary content addressable memory (TCAM) having an array of ferroelectric diodes, the ferroelectric diodes comprising hafnium zirconium oxide (HfZrO2), the ferroelectric diodes being non-volatile and field programmable via pulsing to an analog state that is dependent on a number of pulses.

15. 15. The TCAM of claim 14, wherein the search delay of the TCAM is about 1 μs or less, about 500 ns or less, or about 100 ns, 50 ns, 10 ns, 1 ns, 100 ps or less.

16. 16. The TCAM according to claim 14, wherein each memory cell has two diodes of opposite polarity.

17. A neural network having an array of multi-bit diode synapses, each diode synapse having a ferroelectric diode having doped aluminum nitride (AIN), each ferroelectric diode being non-volatile and field programmable via pulsing to an analog state that is dependent on a number of pulses.

18. 20. The neural network of claim 17, wherein each ferroelectric diode comprises scandium doped aluminum nitride (AIN) (AlScN), yttrium doped aluminum nitride (AlYN), magnesium and hafnium doped aluminum nitride (AlMgHfN), magnesium and zirconium doped aluminum nitride (AlMgZrN), magnesium and titanium doped aluminum nitride (AlMgTIN), boron doped aluminum nitride (AlBN), or ytterbium doped aluminum nitride (AlYbN).

19. 19. The neural network of claim 17 or 18, wherein the multi-bit diode synapses are arranged in the LeNet-5 architecture of the PyTorch framework.

20. 20. The neural network of claim 17, wherein the neural network exhibits an inference accuracy of at least about 90%, at least about 95%, or at least about 97% on the MNIST dataset.

21. 1. A method for forming an array of ferroelectric diodes on a top surface of a semiconductor wafer and an array of circuit contacts on said top surface of said wafer, comprising the steps of: depositing a bottom conductor layer on top of the wafer; depositing a layer of ferroelectric material over the lower metal layer; removing excess portions of the ferroelectric material layer and the lower metal layer; forming an oxide over the layer of ferromagnetic material, the excess portion not overlapping the circuit contact; depositing a top conductor layer on top of the wafer; patterning the upper conductor layer; The method comprising:

22. 22. The method of claim 21 , wherein the ferroelectric material layer comprises aluminum nitride (AIN) doped with scandium (AlScN), yttrium (AlYN), magnesium hafnium (AlMgHfN), magnesium zirconium (AlMgZrN), magnesium titanium (AlMgTIN), boron (AlBN), or ytterbium (AlYbN).

23. The method according to any one of claims 21 to 22, further comprising: A method comprising forming an oxide by exposing a ferromagnetic material to air.

24. 1. A method for forming an array of ferroelectric diodes on a top surface of a semiconductor wafer and an array of circuit contacts on said top surface of said wafer, comprising the steps of: depositing a bottom conductor layer on an upper surface of the wafer; forming an oxide layer on the lower conductor layer; depositing a layer of ferroelectric material over the oxide layer; removing excess portions of the ferroelectric material layer and the lower metal layer away from the circuit contacts; depositing a top conductor layer on top of the wafer; patterning the upper conductor layer; The method comprising:

25. 25. The method of claim 24, wherein the ferroelectric material layer comprises aluminum nitride (AIN) doped with scandium (AlScN), yttrium (AlYN), magnesium hafnium (AlMgHfN), magnesium zirconium (AlMgZrN), magnesium titanium (AlMgTIN), boron (AlBN), or ytterbium (AlYbN).

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