Three-dimensional (3D) vertical spiral inductors and transformers

Abstract

An apparatus is disclosed that includes a vertical spiral inductor. The vertical spiral inductor may include a plurality of dielectric layers formed on a substrate, a plurality of conductive layers, each of the plurality of conductive layers disposed on each of the plurality of dielectric layers, and a plurality of insulating layers, each of the plurality of insulating layers disposed on each of the plurality of conductive layers, each of the plurality of insulating layers separating each of the plurality of dielectric layers. A first spiral coil is disposed in a first plane perpendicular to the substrate, the first spiral coil being formed from a first portion of the plurality of conductive layers and a first set of vias of the plurality of vias configured to connect the first portion of the plurality of conductive layers.

Description

[Technical field]

[0001] The present disclosure relates generally to semiconductor devices, and more particularly, but not exclusively, to 3D spiral inductors and transformer devices including these spiral inductors and methods for their manufacture. [Background technology]

[0002] Integrated circuit and packaging technology has made great strides in increasing computing power and decreasing power consumption through miniaturization and scaling of active elements. The present disclosure generally relates to high quality factor (Q) inductor structures having planar spiral inductor configurations and device packaging structures that can accommodate the spiral inductors. These spiral inductors can also be coupled in a manner via respective input and output taps to form a transformer configuration.

[0003] Inductors are impedance devices, which may also include transformers and other inductive reactors. Inductors are used in many important circuit applications, such as filters, power conditioning, and impedance matching circuits.

[0004] Inductor structures are used in semiconductor devices, which are generally fabricated from a core and a semiconductor substrate, upon which various patterns and shapes of conductor layers are formed, connected and separated by dielectric, metal and other insulating layers, respectively.

[0005] Various inductors are shaped as coils that are then wound onto various core materials, such as ferrite. The cores are typically shaped as rods, cylinders, or toroids. Generally, the more windings a coil has, the higher its impedance value. Summary of the Invention [Problem to be solved by the invention]

[0006] Thus, there is a need for devices and methods that overcome the deficiencies of conventional approaches as provided and described in this disclosure. [Means for solving the problem]

[0007] The following presents a simplified summary of one or more aspects and / or examples related to the apparatus and methods disclosed herein. As such, the following summary should not be considered an extensive overview of all contemplated aspects and / or examples, nor should the following summary be considered to identify key or critical elements of all contemplated aspects and / or examples or to delineate the scope related to any particular aspect and / or example. As such, the following summary is intended only to present certain concepts related to one or more aspects and / or examples related to the apparatus and methods disclosed herein in a simplified form prior to the detailed description presented below.

[0008] In accordance with various aspects disclosed herein, at least one aspect includes an apparatus having a spiral inductor including a plurality of dielectric layers formed on a substrate, a plurality of conductive layers, each of the plurality of conductive layers disposed on a respective one of the plurality of dielectric layers, a plurality of insulating layers, each of the plurality of insulating layers disposed on each of the plurality of conductive layers and configured to separate each of the plurality of dielectric layers, a plurality of vias, and a first spiral coil disposed in a first plane perpendicular to the substrate, the first spiral coil being formed from a first portion of the plurality of conductive layers and a first set of the plurality of vias configured to connect the first portion of the plurality of conductive layers.

[0009] In accordance with various aspects disclosed herein, at least one aspect may include a method for manufacturing a spiral inductor, the method may include depositing a plurality of dielectric layers on a substrate; depositing a plurality of conductive layers, each of the plurality of conductive layers disposed on each of the plurality of dielectric layers; depositing a plurality of insulating layers, each of the plurality of insulating layers disposed on each of the plurality of conductive layers and each of the plurality of insulating layers separating each of the plurality of dielectric layers; forming a plurality of vias; and forming a first spiral coil in a first plane perpendicular to the substrate, the first spiral coil being formed from a first portion of the plurality of conductive layers and a first set of the plurality of vias configured to connect the first portion of the plurality of conductive layers.

[0010] Other features and advantages associated with the apparatus and methods disclosed herein will become apparent to one with skill in the art based on the following drawings and detailed description.

[0011] A more complete understanding of the various aspects of the present disclosure and many of the associated technical advantages will be readily appreciated by reference to the following detailed description when considered in conjunction with the accompanying drawings, which are provided for purposes of illustration only and are not intended to limit the disclosure. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 is a partial cross-sectional view of a conventional horizontally oriented planar spiral inductor. [Diagram 2] FIG. 2 is a partial cross-sectional view of a vertically oriented 3D spiral inductor according to at least one embodiment of the present disclosure. [Diagram 3] 1A-1D are partial cross-sectional views of vertical 3D spiral inductors connected in series, according to at least one embodiment of the present disclosure. [Figure 4] 1 is a partial cross-sectional view of a vertical 3D spiral inductor according to at least one embodiment of the present disclosure. [Diagram 5]1 is a partial cross-sectional view of a vertical 3D spiral inductor according to at least one embodiment of the present disclosure. [Figure 6] FIG. 13 illustrates another partial cross-sectional view of a vertical 3D spiral inductor including two nested coils disposed in one plane, according to at least one embodiment of the present disclosure. [Figure 7] 1 is a partial cross-sectional view of a vertical 3D spiral inductor according to at least one embodiment of the present disclosure. [Figure 8] 1 is a partial cross-sectional view of a vertical 3D spiral inductor according to at least one embodiment of the present disclosure. [Figure 9] 1A-1D are partial cross-sectional views of parallel-connected vertical 3D spiral inductors according to at least one embodiment of the present disclosure. [Figure 10] 1 is a partial cross-sectional view of a vertical 3D spiral inductor according to at least one embodiment of the present disclosure. [Figure 11] 1 is a partial cross-sectional view of a vertical 3D spiral inductor according to at least one embodiment of the present disclosure. [Figure 12] 1 is a partial cross-sectional view of a vertical 3D spiral inductor according to at least one embodiment of the present disclosure. [Figure 13] 1 is a partial cross-sectional view of a vertical 3D spiral inductor according to at least one embodiment of the present disclosure. [Figure 14] FIG. 2 is a partial cross-sectional view of a vertical 3D spiral transformer according to at least one embodiment of the present disclosure. [Figure 15] FIG. 1 illustrates an exemplary method for manufacturing a package, according to at least one aspect of the present disclosure. [Figure 16] FIG. 1 illustrates a mobile device in accordance with at least one aspect of the present disclosure. [Figure 17] 1A-1C illustrate various electronic devices that may be integrated with any of the 3D spiral inductors disclosed herein, according to some examples of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] In accordance with common practice, features illustrated in the drawings may not be drawn to scale. Thus, dimensions of illustrated features may be arbitrarily expanded or reduced for clarity. In accordance with common practice, some of the drawings have been simplified for clarity. Thus, the drawings may not depict all components of a particular apparatus or method. Moreover, like reference numerals denote like features throughout the specification and figures.

[0014] Aspects of the present disclosure are illustrated in the following description and related drawings directed to specific aspects. Alternative aspects or embodiments may be devised without departing from the scope of the teachings herein. In addition, well-known elements of exemplary aspects of the present disclosure may not be described in detail or may be omitted so as not to obscure the relevant details of the teachings in the present disclosure.

[0015] In some described exemplary implementations, examples are made clear in which some of the various component structures and operations are derived from known conventional techniques and configured in accordance with one or more exemplary aspects. In such examples, some internal details of the known conventional component structures and / or operations may be omitted to help avoid potential ambiguity of the concepts illustrated in the exemplary aspects disclosed herein.

[0016] The terms used herein are merely for the purpose of describing particular aspects and are not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural unless the context clearly indicates otherwise. It is further understood that the terms "comprises", "comprising", "includes" and / or "including" as used herein specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0017] Aspects of the present disclosure describe spiral inductor and transformer structures used for high quality factor (Q) inductors and transformers. The structures include multiple spiral traces supported by multiple respective substrates. These spiral structures have a spiral design implemented on a single plane, with the spiral including one or more turns within the plane of the inductor.

[0018] The inductance value of an inductor is proportional to the length of metal used to form the inductor. The inductance value can also be affected by many factors, such as the width of the metal forming the turns of the inductor, the space found between the turns, the dimensions (e.g., diameter) of the metal conductor, and the number of turns in the spiral. This type of spiral inductor can have more or fewer loops or spiral turns depending on the desired circuit application and its associated inductance requirements.

[0019] A spiral trace is a semiconductor representation or implementation of what is also known in the relevant art as an inductor, coil, or winding.

[0020] For simplicity, the term spiral inductor will be used to refer to both spiral inductors and transformers. A transformer is formed using a spiral inductor where the spiral inductor is magnetically coupled and electrically connected using at least one input tap and at least one output tap selected for the particular transformer application desired.

[0021] 1 shows a conventional horizontal planar spiral inductor showing two spiral structures (102 and 104) in a planar configuration parallel to one another and electrically connected or coupled to one another (the connection or coupling is shown at 106). This conventional inductor configuration requires a bottom wafer substrate shield of polysilicon or some other suitable material (e.g., metal) to provide the necessary shielding (shielding not shown) to reduce the adverse effects of magnetic flux and currents on the silicon substrate for eddy current losses.

[0022] Shielding is necessary to prevent adverse effects from the diverging inductor from propagating to sensitive electronic components or signal / electrical routing paths located below the inductor. These adverse effects are illustrated by the energy flow and field lines that run through the spiral inductor (108). These adverse effects lead to design constraints and requirements to establish keep-out zones (KOZ) to the side and below the inductor structure to prevent this interference from occurring in the conventional configuration shown in FIG.

[0023] In the prior art, grill-like structures (similar to Faraday cages) are sometimes used to provide the conventional shielding structure required for this horizontal spiral inductor configuration to prevent the generated electric and magnetic flux fields from tunneling through the entire substrate structure. It is known from physics and device material properties that these electric and magnetic flux fields can generate eddy currents (also called Foucault currents). They are loops of current induced in a conductor by a changing, fluctuating, or flowing magnetic field within the conductor that operates according to Faraday's law of induction. Eddy currents generally flow in closed loops within the conductor as well as in planes perpendicular to the magnetic field.

[0024] These eddy currents can cause undesirable types of interference and degraded operating characteristics within the device. Therefore, various shielding structures (e.g., in the form of molding compounds) are required on the bottom surface of the package and may also be required on the top surface to mitigate the detrimental effects of these electric and magnetic fields.

[0025] At least one technical advantage of various embodiments of the present disclosure is a device that reduces or prevents these adverse events from occurring and eliminates the requirements for shielding and KOZ used in conventional designs.

[0026] FIG. 2 illustrates a vertically oriented 3D spiral inductor 200 configuration showing three spiral conductive structures (e.g., coil 202, coil 204, and coil 206) parallel to one another and coupled in series with one another using conductors 208 and 210. Electric flux lines 212 flowing through the three spiral conductive structures are also shown in FIG. 2. The 3D spiral inductor 200 is disposed in a vertically oriented plane. It will be appreciated that the various disclosed aspects are not limited to the illustrated configuration. For example, in some aspects, coils 202, 204, and 206 may be coupled in parallel, or in other aspects, coils 202, 204, and 206 may be configured to form a transformer or a portion of a transformer.

[0027] According to various aspects disclosed herein and described below, a back-end interconnect (BEOL) process may include forming one or more intermetal dielectric (IMD) layers, where the IMD may have one or more metal layers (e.g., Mx, Mx-1, Mx-2, etc.) and one or more vias used to form the various coils, inductors, and transformers described herein. In some aspects, the metal layers may be formed from any highly conductive material, such as copper (Cu), aluminum (AL), silver (Ag), gold (Au), cobalt (Co), ruthenium (Ru), tungsten (W), or other conductive materials, alloys, or combinations thereof. In some aspects, the IMD layers may be formed from materials such as doped silicon dioxide (SiO2), or fluorine-doped and carbon-doped forms thereof, as well as spin-on organic polymer dielectrics, such as polyimide (PI), polynorbornene, benzocyclobutene (BCB), polytetrafluoroethylene (PTFE), and / or silicone-based polymer dielectrics.

[0028] Those skilled in the art will appreciate that the number of spiral trace layers and how tightly the spiral is wound or helically wound within the IMD can allow for higher or lower inductance values ​​depending on the final design parameters and inductance value used for a given circuit application.

[0029] Additionally, those skilled in the art will appreciate that other geometric shapes for the spiral pattern shown in Figure 2 may also be used without departing from the spirit and scope of the present invention. For example, some other shapes that may be implemented include (but are not limited to) triangles, rectangles, squares, circles, ellipses, and other polygons of higher or lower order.

[0030] 3 shows another implementation of a vertical 3D spiral inductor 300 configuration showing three spiral conductive structures (e.g., spiral coils 302, 304, and 306) coupled to each other using conductors 310 and 312 in a parallel configuration, parallel to each other, and arranged in a vertical orientation perpendicular to a substrate layer (not shown). The arrangement of the spiral conductive structures relative to their orientation on multiple metal layers is shown as Mx, Mx-1, Mx-2, Mx-3, and Mx-4. These metal layers are presented for illustrative purposes, and more or fewer metal layers may be used in accordance with various disclosed aspects. The various disclosed aspects allow for a higher Q value as well as a lower resistance (R) compared to conventional designs. In some embodiments, the substrate may include one or more of the active elements, passive elements, and / or metal routing located under one or more of the spiral coils (e.g., spiral coils 302, 304, and 306), which in conventional designs would require a protective layer of shielding as well as the associated KOZ previously described. In contrast to the prior art, in the illustrated embodiment, there are three parallel spiral coils 302, 304, and 306, which may be considered as one spiral inductor or individual spiral inductors, and there is no need to use a bottom shield above the substrate.

[0031] FIG. 4 illustrates a partial cross-sectional view of a vertical 3D spiral inductor along the X-X′ reference line of FIG. 3 of the inductor 300 according to various aspects of the present disclosure. Again, exemplary metal layers are indicated as Mx, Mx-1, Mx-2, Mx-3, and Mx-4. Dielectric insulating layers (e.g., IMD) are indicated as 402, 404, 406, 408, and 410. Insulating layers 411, 413, 415, 417, and 419 may be disposed on the respective dielectric layers (402, 404, 406, 408, and 410). Insulating layers 411, 413, 415, 417, and 419 may also serve as a diffusion barrier layer to cover the top of the metal layers, and may be, for example, silicon carbonitride (SiCN). Insulating layers 411, 413, 415, 417, and 419 may also serve as a contact etch stop layer. Again, as previously described in FIG. 3, the solid unbroken lines of the connectors and vias shown at 312 are shown as such to indicate the spiral inductors connected in a parallel configuration.

[0032] In FIG. 4, a first portion 451 of the first spiral coil 302 in a given metal layer is represented in cross section. Other similarly shaped and sized second portion 452 for the second spiral coil 304 and third portion 453 for the third spiral coil 306 are also shown in FIG. 4, but each of those portions is not labeled with a unique reference number. The various portions (e.g., 451, 452, and 453) may be formed by patterning and etching the various metal layers (e.g., Mx, Mx-1, Mx-2, Mx-3, and Mx-4) to form the various inductor portions and interconnect the various coils (e.g., 312 and 310). These metal layer portions (e.g., 451, 452, and 453) are coupled by vias to form the vertical coils (e.g., 302, 304, and 306). It will be appreciated that the various portions, interconnects, and vias may be fabricated in a BEOL stack during conventional back-end interconnect (BEOL) processing.

[0033] 5 shows another view of a vertical 3D spiral inductor 300 in the Y-Y' reference frame, as described by the Y-Y' reference line in FIG. 3, according to various embodiments of the present disclosure. In the embodiment shown, the cross-sectional view of the spiral coil 302 includes cross-sectional views of the metal layers Mx, Mx-1, Mx-2, Mx-3 and Mx-4 as well as the dielectric layers 402, 404, 406, 408 and 410 and the insulating layers 411, 413, 415, 417 and 419. The spiral coil 302 is formed from Mx, Mx-1, Mx-2, Mx-3 and Mx-4 and a first set 505 of a plurality of vias, which are configured to couple various portions of the metal layers Mx, Mx-1, Mx-2, Mx-3 and Mx-4 to form the spiral coil 302 configured as only one continuous coil. Vias 505 penetrate the dielectric and insulating layers (e.g., 402 and 413) to couple various portions of the metal layers (e.g., Mx and Mx-1). The ends of the spiral coil 302 are coupled to the conductors 310 and 312, which are coupled to other spiral coils in parallel connections. For brevity, each via 505 and associated couplings will not be described in detail herein. Furthermore, it will be appreciated that each spiral coil will have a set of vias to couple various metal layer portions forming the spiral coil. For example, a first set of vias 505 may couple a first portion 451 of the metal layers (layers Mx, Mx-1, Mx-2, Mx-3, and Mx-4) in the first spiral coil 302. A second set of vias may couple a second portion 452 of the metal layers (layers Mx, Mx-1, Mx-2, Mx-3, and Mx-4) in the second spiral coil 304. A third set of vias may couple a third portion 453 of the metal layers (layers Mx, Mx-1, Mx-2, Mx-3, and Mx-4) in the third spiral coil 306. It will be appreciated that the terms "first," "second," and "third" are used for convenience only and do not necessarily affect the order, and should not be considered as limiting various aspects to the configurations shown.

[0034] From the disclosure herein, it will be appreciated that various aspects may include an apparatus including a spiral inductor (e.g., 300) having a plurality of dielectric layers (e.g., 402, 404, 406, 408, and 410) formed on a substrate. A plurality of conductive layers (e.g., Mx, Mx-1, Mx-2, Mx-3, and Mx-4) may be provided, each of the plurality of conductive layers disposed on each of the plurality of dielectric layers. A plurality of insulating layers (e.g., 411, 413, 415, 417, and 419) are provided, each disposed on each of the conductive layers and configured to separate each of the dielectric layers. A plurality of vias (e.g., 505) are provided. A first spiral coil (e.g., 302) is disposed in a first plane perpendicular to the substrate. The first spiral coil (e.g., 302) is formed from a first portion (e.g., 451) of the plurality of conductive layers and a first set (e.g., 505) of the plurality of vias configured to couple the first portion (e.g., Mx, Mx-1, Mx-2, Mx-3, and Mx-4) of the plurality of conductive layers. As described above, the 3D vertical inductor configuration provides at least the technical advantage of reduced electromagnetic interference to device layers above and / or below the 3D vertical inductor, which reduces or eliminates the need for a KOZ adjacent to the inductor. It will be appreciated that the illustrated configurations provided herein are merely to provide examples and facilitate the description of the various aspects disclosed. However, the various aspects disclosed are not limited to the particular illustrated configurations.

[0035] FIG. 6 illustrates another configuration of a vertical 3D spiral inductor 600 according to various embodiments of the present disclosure. It will be appreciated that the vertical 3D spiral inductor 600 may be similar to the inductor 300, and that the coils 620 and 630 may be illustrated in a similar Y-Y′ reference frame, similar to the coil 302 illustrated with the Y-Y′ reference line in FIG. 3. FIG. 6 may also be referred to as a vertically stacked inductor configuration or a vertically stacked transformer configuration. In the illustrated embodiment, the cross-sectional view of the spiral coils 620 and 630 includes cross-sectional views of the metal layers Mx, Mx-1, Mx-2, Mx-3, and Mx-4, as well as the dielectric layers 602, 604, 606, 608, and 610 and the insulating layers 611, 613, 615, 617, and 619. The spiral coils 620 and 630 are formed from Mx, Mx-1, Mx-2, Mx-3, and Mx-4 and vias 605 that are coupled to various portions of the metal layers Mx, Mx-1, Mx-2, Mx-3, and Mx-4 to form the spiral coils 620 and 630 configured as two interleaved continuous coils. The vias 605 penetrate the dielectric and insulating layers (e.g., 602 and 613) to couple various portions of the metal layers (e.g., Mx and Mx-1). For brevity, each via 605 and associated couplings will not be described in detail herein. The spiral coil 620 has a first end 621 and a second end 622, which in some aspects may be configured as an input tap or an output tap. The spiral coil 630 has a first end 631 and a second end 632, which in some embodiments may be configured as an input tap or an output tap. The spiral coils shown in FIG. 6 are shown in a parallel connection or open-ended configuration. In some embodiments, the coils 620 and 630 are in a vertically stacked transformer configuration. In other embodiments, the ends may be connected such that the coils 620 and 630 are in a series configuration. In further embodiments, it will be appreciated that the ends (e.g., 621, 622, 631, 632) may be connected to other coils (not shown) in either a series or parallel configuration based on various design concepts. Thus, it will be appreciated that the various disclosed embodiments are not limited to the configurations shown.

[0036] FIG. 7 illustrates a partial cross-sectional view of a vertical 3D spiral inductor 700 according to at least one embodiment of the present disclosure. The cross-sectional view of the inductor 700 is in an X-X′ reference frame similar to that shown in connection with the inductor of FIG. 3. In FIG. 7, various metal layers are shown, such as metal layers Mx, Mx-1, Mx-2, Mx-3, and Mx-4. For ease of illustration, metal portions are not shown in layers Mx and Mx-4. However, it will be appreciated that these layers may be used for additional electrical routing and connections. Also shown are dielectric layers 721, 723, 725, 727, and 729, as well as insulating layers 711, 713, 715, 717, and 719. In the illustrated embodiment, three coils 702, 704, and 706 are shown in the X-X′ reference frame.

[0037] As before, for ease of illustration in FIG. 7, 707 refers to how the spiral conductor element looks in cross section. Other similarly shaped and sized spiral conductor elements are also shown in FIG. 7, but they are not labeled with unique reference numbers. Also shown is conductor 712, which connects coils 702, 704, and 706 in parallel. It will be appreciated that in the configuration shown, only three metal layers (Mx-1, Mx-2, and Mx-3) are used to form the inductor. While reducing inductance, this illustrates that the various disclosed aspects may use more than two of the metal layers, which allows additional routing flexibility for unused metal layers. In addition, it will be appreciated that the metal layers used may be any combination of metal layers (e.g., (Mx, Mx-1, and Mx-2), (Mx-2, Mx-3, and Mx-4), (Mx, Mx-2, and Mx-4), etc.). Thus, the various disclosed aspects are not limited to the configuration shown.

[0038] FIG. 8 illustrates a partial cross-sectional view of a vertical 3D spiral inductor 700 according to at least one embodiment of the present disclosure. The cross-sectional view of the inductor 700 is in the same Y-Y′ reference frame including the coil 702, which is a similar reference frame to the coil 302 shown in connection with the inductor 300 of FIG. 3. In the embodiment shown, there are five metal layers Mx, Mx-1, Mx-2, Mx-3, and Mx-4. For ease of illustration, no metal portions are shown in layers Mx and Mx-4. However, it will be appreciated that these layers may be used for additional electrical routing and connections. Also shown are dielectric layers 721, 723, 725, 727, and 729, and insulating layers 711, 713, 715, 717, and 719. The coil 702 is formed from three metal layers (Mx-1, Mx-2, and Mx-3 as shown). A conductor 712 is shown in cross section, connecting the coils 702, 704 and 706 in parallel at a first end, as is a conductor 714, connecting the coils 702, 704 and 706 in parallel at a second end of the inductor, but only the connection to the inductor 702 is shown.

[0039] 9 illustrates a partial cross-sectional view of a vertical 3D spiral inductor 900 according to at least one embodiment of the present disclosure. Three spiral structure coils 902, 904, and 906 are arranged in a vertical orientation and, in this configuration, are connected in series with each other by conductors 903 and 905. A first end 908 and a second end 909 of the inductor 900 are also shown. The ends 908 and 909 may be used to couple the inductor to other components and / or additional coils.

[0040] FIG. 10 illustrates a partial cross-sectional view of a vertical 3D spiral inductor 900 in the X-X′ reference frame illustrated in FIG. 9 according to at least one embodiment of the present disclosure. Again, cross-sectional views of metal layers Mx, Mx-1, Mx-2, Mx-3, and Mx-4 are shown, as well as dielectric layers 1002, 1004, 1006, 1008, and 1010 and insulating layers 1011, 1013, 1015, 1017, and 1019. As described above, coils 902, 904, and 906 are connected in a series-coupled configuration. Specifically, a first conductor 903 couples coil 902 to coil 904. A second conductor 905 couples coil 904 to coil 906. The first conductor 903 and second conductor 905 are formed from vias 1005 and portions of metal layers (e.g., Mx, Mx-1, and Mx-2) disposed between the respective coupled coils. For example, as shown, a first conductor 903 is disposed between coils 902 and 904, and a second conductor 905 is disposed between coils 904 and 906. Additionally, as shown, a first end 908 is coupled to coil 902 to provide an external coupling point. For ease of illustration in FIG. 10, 1003 refers to the portion where the spiral conductor element is seen in a cross-sectional view. Other similarly shaped and sized spiral conductor elements are also shown in FIG. 10, but they are not labeled with unique reference numbers. It will be appreciated that the illustrated embodiment is provided only as an example, and that the various disclosed embodiments are not limited to the illustrated configuration. For example, conductors 903 and 905 may be placed in different layers, and the coupling of the coils may be achieved at other locations. It will be appreciated, therefore, that the various disclosed embodiments are not limited to the illustrated configuration.

[0041] FIG. 11 illustrates a partial top view of a vertical 3D spiral inductor 900 in a Y-Y′ reference frame according to at least one embodiment of the present disclosure. Again, cross-sectional views of metal layers Mx, Mx-1, Mx-2, Mx-3, and Mx-4 are shown, as well as dielectric layers 1002, 1004, 1006, 1008, and 1010 and insulating layers 1011, 1013, 1015, 1017, and 1019. As discussed above, coils 902, 904, and 906 are connected in a series-coupled configuration, but in this view, only coil 902 is shown. As shown, a first conductor 903 is coupled to the top of coil 902 in metal layer Mx, which forms part of the connection to coil 904 (not shown). Additionally, as shown, a first end 908 is coupled to coil 902 in metal layer Mx-2 toward the center of the coil to provide the external coupling point discussed above. Again, it will be appreciated that the illustrations are provided for purposes of explanation only and not as limitations of various aspects disclosed.

[0042] FIG. 12 illustrates a partial cross-sectional view of a vertical parallel 3D spiral inductor 1200 in an X-X′ reference frame according to at least one embodiment of the present disclosure. The cross-sectional view of the inductor 1200 is in an X-X′ reference frame similar to that shown in connection with the inductor of FIG. 9. In FIG. 12, various metal layers are shown, such as metal layers Mx, Mx-1, Mx-2, Mx-3, and Mx-4. For ease of illustration, metal portions are not shown in layers Mx and Mx-4. However, it will be appreciated that these layers may be used for additional electrical routing and connections. Also shown are dielectric layers 1202, 1204, 1206, 1208, and 1210, and insulating layers 1211, 1213, 1215, 1217, and 1219. In the illustrated embodiment, three coils 1202, 1204, and 1206 are shown in the X-X′ reference frame.

[0043] Also, as shown, 1202, 1204, and 1206 are connected in a series coupling configuration. Specifically, a first conductor 1203 couples coil 1202 to coil 1204. A second conductor 1205 couples coil 1204 to coil 1206. The first conductor 1203 and the second conductor 1205 are formed from vias and portions of metal layers (e.g., Mx-2 and Mx-3) disposed between the respective coupled coils. For example, as shown, the first conductor 1203 is disposed between coils 1202 and 1204, and the second conductor 1205 is disposed between coils 1204 and 1206. Additionally, as shown, a first end 1201 is coupled to coil 1202 to provide an external coupling point. While reducing the inductance of the coil with fewer turns, this configuration illustrates that the various disclosed embodiments may use more than two of the metal layers, which allows additional routing flexibility for unused metal layers. In addition, it will be appreciated that the metal layers used may be any combination of metal layers (e.g., (Mx, Mx-1 and Mx-2), (Mx-2, Mx-3 and Mx-4), (Mx, Mx-2 and Mx-4), etc.). Thus, the various disclosed embodiments are not limited to the configuration shown.

[0044] FIG. 13 illustrates a partial cross-sectional view of a vertical 3D spiral inductor 1200 according to at least one embodiment of the present disclosure. The cross-sectional view of the inductor 1200 is in the same Y-Y′ reference frame including the coil 1202, which is a similar reference frame to the coil 902 shown in connection with the inductor 900 of FIG. 9. In the embodiment shown, there are five metal layers Mx, Mx-1, Mx-2, Mx-3, and Mx-4. For ease of illustration, metal portions are not shown in layers Mx and Mx-4. However, it will be appreciated that these layers may be used for additional electrical routing and connections. Also shown are dielectric layers 1202, 1204, 1206, 1208, and 1210, and insulating layers 1211, 1213, 1215, 1217, and 1219. The coil 1202 is formed from three metal layers (Mx-1, Mx-2, and Mx-3 as shown). A first end 1201 that connects coil 1202 to an external component is shown in cross section. Also shown in cross section is conductor 1203 that couples coils 1202 and 1204 in series, but only the connection to inductor 1202 is shown.

[0045] FIG. 14 illustrates a partial cross-sectional view of a vertical 3D spiral transformer 1400 according to at least one embodiment of the present disclosure. In this embodiment, spiral windings 1402, 1404, and 1406 are connected into a transformer configuration. Specifically, windings 1402 and 1406 are coupled together to form a first coil (coil 1) of the transformer 1400. Spiral winding 1404 forms a second coil (coil 2) of the transformer 1400. The arrangement of spiral windings 1402, 1404, and 1406 is formed vertically using metal layers, as shown at Mx, Mx-1, Mx-2, Mx-3, and Mx-4. Various input and output taps can be selected to form a desired transformer configuration (not shown). Additionally, additional windings can be added to the first coil and / or the second coil. Thus, the various disclosed embodiments are not limited to the configurations shown.

[0046] FIG. 15 illustrates an exemplary method 1500 of fabricating a spiral inductor according to an embodiment of the disclosure. Other fabrication methods are possible, and the described fabrication method is presented merely as an aid to understanding the various embodiments disclosed herein. The method 1500 begins at block 1502 by depositing a plurality of dielectric layers on a substrate. The method proceeds to block 1504, depositing a plurality of conductive layers, each of the plurality of conductive layers disposed on each of the plurality of dielectric layers. The method proceeds to block 1506, depositing a plurality of insulating layers, each of the plurality of insulating layers disposed on each of the plurality of conductive layers, each of the plurality of insulating layers separating each of the plurality of dielectric layers. The method proceeds to block 1508, forming a plurality of vias. The method proceeds to block 1510, forming a first spiral coil in a first plane perpendicular to the substrate, the first spiral coil being formed from a first portion of the plurality of conductive layers and a first set of the plurality of vias configured to couple the first portion of the plurality of conductive layers.

[0047] It will be appreciated that the foregoing manufacturing processes are provided merely as general illustrations of some of the aspects of the present disclosure, and are not intended to limit the scope of the present disclosure or the appended claims. Furthermore, many details of the manufacturing processes known to those skilled in the art have been omitted or combined into summary process sections to facilitate understanding of the various aspects disclosed, without describing in detail each and / or every possible process variation.

[0048] The foregoing devices described or variations and other aspects thereof may be incorporated into an apparatus selected from the group including music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed location terminals, tablet computers, computers, wearable devices, Internet of Things (IoT) devices, laptop computers, servers, and devices in automotive vehicles.

[0049] FIG. 16 illustrates an exemplary mobile device according to some examples of the present disclosure. Referring now to FIG. 16, a block diagram of a mobile device configured according to an exemplary aspect is depicted, generally designated as a mobile device 1600. In some aspects, the mobile device 1600 may be configured as a wireless communication device. As shown, the mobile device 1600 includes a processor 1601. The processor 1601 is shown to comprise an instruction pipeline 1612, a buffer processing unit (BPU) 1608, a branch instruction queue (BIQ) 1611, and a throttler 1610, as known in the art. Other well-known details of these blocks (e.g., counters, entries, confidence fields, weighted sums, comparators, etc.) are omitted from this view of the processor 1601 for clarity of illustration. The processor 1601 is communicatively coupled to a memory 1632 via a link, which may be an inter-die link or an inter-chip link. The mobile device 1600 also includes a display 1628 and a display controller 1626 coupled to the processor 1601 and the display 1628 .

[0050] In some aspects, FIG. 16 may include a coder / decoder (codec) 1634 (e.g., an audio and / or voice codec) coupled to the processor 1601, a speaker 1636 and a microphone 1638 coupled to the codec 1634, and a wireless antenna 1642 and wireless circuitry 1640 (which may include a modem, RF circuitry, filters, etc., and may use various 3D spiral inductors and / or transformers disclosed herein) coupled to the processor 1601.

[0051] In certain aspects where one or more of the above-mentioned blocks are present, the processor 1601, the display controller 1626, the memory 1632, the codec 1634, and the wireless circuitry 1640 can be included in a system-in-package or system-on-chip device 1622. The input device 1630 (e.g., a physical or virtual keyboard), the power source 1644 (e.g., a battery), the display 1628, the input device 1630, the speaker 1636, the microphone 1638, the wireless antenna 1642, and the power source 1644 may be external to the system-on-chip device 1622 or may be coupled to components of the system-on-chip device 1622, such as an interface or a power management controller. Various 3D spiral inductors disclosed herein may be used in portions of the power coupling circuitry.

[0052] It should be noted that although FIG. 16 shows a mobile device, the processor 1601 and memory 1632 may also be incorporated into a set-top box, a music player, a video player, an entertainment unit, a navigation device, a personal digital assistant (PDA), a fixed location data unit, a computer, a laptop, a tablet, a communications device, a mobile phone, or other similar device.

[0053] FIG. 17 illustrates various electronic devices that may be integrated with any of the above transistor cells, according to some examples of the present disclosure. For example, a mobile phone device 1702, a laptop computer device 1704, and a fixed location terminal device 1706 may include a semiconductor device 1700 including various 3D spiral inductors and / or transformers (e.g., 200, 300, 600, 700, 900, 1200, 1400) as described herein. The semiconductor device 1700 may be, for example, an integrated circuit, a die, an integrated device, an integrated device package, an integrated circuit device, a package, an integrated circuit package, or a package-on-package device. The devices 1702, 1704, and 1706 illustrated in FIG. 17 are merely examples. Other electronic devices may also feature semiconductor device 1700, including, but not limited to, a group of devices (e.g., electronic devices) including mobile devices, handheld personal communications system (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communications devices, smartphones, tablet computers, computers, wearable devices, servers, routers, electronic devices implemented within automotive vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0054] The devices and functions disclosed above may be designed and configured in computer files (e.g., Register Transfer Level (RTL), Geometric Data Stream (GDS) Gerber, etc.) stored on a computer-readable medium. Some or all of such files may be provided to a manufacturer who produces devices based on such files. The resulting products may include semiconductor wafers, which are then cut into semiconductor dies and packaged into semiconductor packages, integrated devices, system-on-chip devices, etc., which may then be used in the various devices described herein.

[0055] It will be appreciated that the various aspects disclosed herein may be described as functional equivalents of structures, materials, and / or devices described and / or recognized by those skilled in the art. For example, in one aspect, an apparatus may comprise means for performing the various functions described above. It will be appreciated that the foregoing aspects are provided by way of example only, and that the various aspects claimed are not limited to the specific content and / or figures cited as examples.

[0056] One or more of the components, processes, features, and / or functions shown in FIGS. 2-17 may be rearranged and / or combined as a single component, process, feature, or function, or may be incorporated as several components, processes, or functions. Additional elements, components, processes, and / or functions may be further added without departing from this disclosure. It is also noted that FIGS. 1-16 and corresponding descriptions within this disclosure are not limited to dies and / or ICs. In some implementations, FIGS. 2-17 and corresponding descriptions may be used to manufacture, make, provide, and / or produce an integrated device. In some implementations, the device may include a die, an integrated device, a die package, an integrated circuit (IC), a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, and / or an interposer.

[0057] As used herein, the terms "user equipment" (or "UE"), "user device," "user terminal," "client device," "communication device," "wireless device," "wireless communication device," "handheld device," "mobile device," "mobile terminal," "mobile station," "handset," "access terminal," "subscriber device," "subscriber terminal," "subscriber station," "terminal," and variations thereof may interchangeably refer to any suitable mobile or fixed device capable of receiving wireless communication and / or navigation signals. These terms include, but are not limited to, music players, video players, entertainment units, navigation devices, communication devices, smartphones, personal digital assistants, fixed location terminals, tablet computers, computers, wearable devices, laptop computers, servers, automotive devices in automotive vehicles, and / or other types of portable electronic devices that are typically carried by a person and / or have communication capabilities (e.g., wireless, cellular, infrared, short range radio, etc.). These terms are also intended to include a device that communicates with another device that can receive wireless communication and / or navigation signals by a short-range wireless connection, an infrared connection, a wired connection, or other connection, etc., regardless of whether the satellite signal reception, assistance data reception, and / or location-related processing is performed on that device or on another device. Furthermore, these terms are intended to include all devices, including wireless and wired communication devices, that can communicate with a core network via a radio access network (RAN), through which the UE can connect to external networks, such as the Internet, and to other UEs. Of course, other mechanisms for connecting to a core network and / or the Internet are also possible for a UE, such as via a wired access network, a wireless local area network (WLAN) (e.g., based on IEEE 802.11, etc.), etc.A UE may be embodied by any of several types of devices, including, but not limited to, a printed circuit (PC) card, a CompactFlash device, an external or internal modem, a wireless or wired phone, a smartphone, a tablet, a tracking device, an asset tag, etc.

[0058] Wireless communications between electronic devices may be based on various technologies, such as Code Division Multiple Access (CDMA), W-CDMA, Time Division Multiple Access (TDMA), Frequency Division Multiple Access (FDMA), Orthogonal Frequency Division Multiplexing (OFDM), Global System for Mobile Communications (GSM), 3GPP® Long Term Evolution (LTE), 5G New Radio, Bluetooth (BT), Bluetooth Low Energy (BLE), IEEE 802.11 (WiFi), and IEEE 802.15.4 (Zigbee / Thread) or other protocols that may be used within a wireless or data communications network.

[0059] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any detail described herein as "exemplary" should not be construed as advantageous over other examples. Likewise, the term "example" does not imply that all examples include the described feature, advantage or mode of operation. Furthermore, particular features and / or structures may be combined with one or more other features and / or structures. Moreover, at least a portion of the apparatus described herein may be configured to perform at least a portion of the methods described herein.

[0060] It should be noted that the terms "connected" and "coupled," or any variation thereof, mean any direct or indirect connection or coupling between elements, unless that connection is expressly disclosed as being directly connected, and may encompass the presence of intermediate elements between two elements that are "connected" or "coupled" together through intermediary elements.

[0061] Any reference herein to an element using a designation such as "first," "second," etc. is not intended to limit the quantity and / or order of those elements. Rather, these designations are used as a convenient method of distinguishing between two or more elements and / or instances of an element. Also, unless otherwise stated, a set of elements can comprise one or more elements.

[0062] In the above detailed description, it is seen that various features are grouped together in the examples. This manner of disclosure should not be understood as an intention that the exemplary clauses have more features than are expressly stated in each clause. Rather, various aspects of the disclosure may include fewer than all features of each disclosed exemplary clause. Thus, the following clauses should be considered as incorporated in the description, and each clause may stand alone as a separate example. Although each dependent clause may refer to a specific combination with one of the other clauses in the following clauses, the aspects of that dependent clause are not limited to that specific combination. It will be understood that other exemplary clauses may also include combinations of aspects of the dependent clause with the subject matter of any other dependent clause or independent clause, or combinations of any features with other dependent clauses and independent clauses. Unless a specific combination is not intended (e.g., conflicting aspects such as defining an element as both an insulator and a conductor) is expressly expressed or can be easily inferred, the various aspects disclosed herein expressly include these combinations. It is further contemplated that aspects of a clause may be included in any other independent clause, even if the clause is not directly dependent on an independent clause.

[0063] Example implementations are described in the following numbered clauses.

[0064] Clause 1. An apparatus including a spiral inductor, the spiral inductor including a plurality of dielectric layers formed on a substrate, a plurality of conductive layers, each of the plurality of conductive layers disposed on a respective one of the plurality of dielectric layers, a plurality of insulating layers, each of the plurality of insulating layers disposed on each of the plurality of conductive layers and configured to separate each of the plurality of dielectric layers, a plurality of vias, and a first spiral coil disposed in a first plane perpendicular to the substrate, the first spiral coil being formed from a first portion of the plurality of conductive layers and a first set of vias of the plurality of vias configured to connect the first portion of the plurality of conductive layers.

[0065] Clause 2. The apparatus of clause 1, further comprising a second spiral coil disposed in a second plane perpendicular to the substrate, the second spiral coil formed from a second portion of the plurality of conductive layers and a second set of vias of the plurality of vias configured to connect the second portion of the plurality of conductive layers.

[0066] Clause 3. The apparatus of clause 2, wherein the first spiral coil is electrically coupled to the second spiral coil.

[0067] Clause 4. The apparatus of clause 2 or 3, wherein the first spiral coil and the second spiral coil are coupled in series.

[0068] Clause 5. The apparatus of clause 2 or 3, wherein the first spiral coil and the second spiral coil are coupled in parallel.

[0069] Clause 6. The apparatus of any one of clauses 2 to 5, wherein the first spiral coil is magnetically coupled to the second spiral coil.

[0070] Clause 7. The apparatus of clause 6, wherein the first spiral coil and the second spiral coil are arranged in a transformer configuration and include at least one input tap and one output tap.

[0071] Clause 8. The apparatus of any one of clauses 2-7, further comprising a third spiral coil disposed in a third plane perpendicular to the substrate, the third spiral coil formed from a third portion of the plurality of conductive layers and a third set of vias of the plurality of vias configured to connect the third portion of the plurality of conductive layers.

[0072] Clause 9. The apparatus of clause 8, wherein the third spiral coil and the second spiral coil are magnetically coupled to each other, and the first spiral coil and the third spiral coil are electrically coupled to each other.

[0073] Clause 10. The apparatus of clauses 8 or 9, wherein the first spiral coil, the second spiral coil, and the third spiral coil are electrically coupled.

[0074] Clause 11. The apparatus of clause 10, wherein the first spiral coil, the second spiral coil, and the third spiral coil are coupled in series.

[0075] Clause 12. The apparatus of clause 10, wherein the first spiral coil, the second spiral coil, and the third spiral coil are coupled in parallel.

[0076] Clause 13. The apparatus of any one of clauses 2 to 12, wherein the first spiral coil and the second spiral coil are arranged on the same plane in a nested coil configuration.

[0077] Clause 14. The apparatus of clause 13, wherein the first spiral coil is magnetically coupled to the second spiral coil in a transformer configuration.

[0078] Clause 15. The apparatus of clause 13 or 14, wherein the first spiral coil is electrically coupled to the second spiral coil.

[0079] Clause 16. The apparatus of any one of clauses 1 to 15, wherein the substrate includes at least one of an active element, a passive element, or metal routing located below the first spiral coil.

[0080] Clause 17. The apparatus of any one of clauses 1 to 16, wherein the first spiral coil is formed in a back-end interconnect (BEOL) stack.

[0081] Clause 18. The apparatus of any one of clauses 1 to 17, wherein the apparatus is selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and a device in an automotive vehicle.

[0082] Clause 19. A method for manufacturing a spiral inductor, comprising: depositing a plurality of dielectric layers on a substrate; depositing a plurality of conductive layers, each of the plurality of conductive layers disposed on each of the plurality of dielectric layers; depositing a plurality of insulating layers, each of the plurality of insulating layers disposed on each of the plurality of conductive layers, each of the plurality of insulating layers separating each of the plurality of dielectric layers; forming a plurality of vias; and forming a first spiral coil in a first plane perpendicular to the substrate, the first spiral coil being formed from a first portion of the plurality of conductive layers and a first set of the plurality of vias configured to connect the first portion of the plurality of conductive layers.

[0083] Clause 20. The method of clause 19, further comprising forming a second spiral coil in a second plane perpendicular to the substrate, the second spiral coil being formed from a second portion of the plurality of conductive layers and a second set of vias of the plurality of vias configured to connect the second portion of the plurality of conductive layers.

[0084] Clause 21. The method of clause 20, further comprising electrically coupling the first spiral coil to the second spiral coil.

[0085] Clause 22. The method of clause 20 or 21, further comprising electrically coupling the first spiral coil and the second spiral coil in series.

[0086] Clause 23. The method of clause 20 or 21, further comprising electrically coupling the first spiral coil and the second spiral coil in parallel.

[0087] Clause 24. The method of any one of clauses 20 to 23, wherein the first spiral coil is magnetically coupled to the second spiral coil.

[0088] Clause 25. The method of any one of clauses 20-24, further comprising forming a third spiral coil in a third plane perpendicular to the substrate, the third spiral coil being formed from a third portion of the plurality of conductive layers and a third set of vias of the plurality of vias configured to connect the third portion of the plurality of conductive layers.

[0089] Clause 26. The method of clause 25, wherein the third spiral coil is magnetically coupled to the second spiral coil, and the first spiral coil and the third spiral coil are electrically coupled to each other.

[0090] Clause 27. The method of clause 25 or 26, wherein the first spiral coil, the second spiral coil, and the third spiral coil are arranged in a transformer configuration and include at least one input tap and one output tap.

[0091] Clause 28. The method of any one of clauses 25 to 27, further comprising electrically coupling the first spiral coil, the second spiral coil, and the third spiral coil.

[0092] Clause 29. The method of clause 28, further comprising electrically coupling the first spiral coil, the second spiral coil, and the third spiral coil in series.

[0093] Clause 30. The method of clause 28, further comprising electrically coupling the first spiral coil, the second spiral coil, and the third spiral coil in parallel.

[0094] Clause 31. The method of any one of clauses 20 to 30, wherein the first spiral coil and the second spiral coil are arranged in a coplanar manner in a nested coil configuration.

[0095] Clause 32. The method of clause 31, wherein the first spiral coil is magnetically coupled to a second spiral coil in a transformer configuration.

[0096] Clause 33. The method of clause 31 or 32, further comprising electrically coupling the first spiral coil to the second spiral coil.

[0097] Clause 34. The method of any one of clauses 19 to 33, wherein the substrate includes at least one of an active element, a passive element, or metal routing located below the first spiral coil.

[0098] Clause 35. The method of any one of clauses 19 to 34, wherein the first spiral coil is formed in a back-end interconnect (BEOL) stack.

[0099] Clause 36. The method of any one of clauses 19 to 35, wherein the spiral inductor is integrated into an apparatus, and the apparatus is selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and a device in a motor vehicle.

[0100] Those skilled in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For example, the data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0101] Nothing described or illustrated or shown in this application is intended to confer upon the public any element, action, feature, benefit, advantage, or equivalent, whether or not that element, action, feature, benefit, advantage, or equivalent is recited in a claim.

[0102] Moreover, those skilled in the art will appreciate that the various example logical blocks, modules, circuits, and algorithmic actions described in connection with the examples disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability of hardware and software, the various example components, blocks, modules, circuits, and actions have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the particular application and design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0103] Although some aspects have been described with respect to devices, it will be appreciated that these aspects also constitute a description of the corresponding methods, and thus blocks or components of the devices should also be understood as corresponding method actions or features of method actions. Similarly, aspects described with respect to or as method actions also constitute a description of corresponding blocks, or details or features of the corresponding devices. Some or all of the method actions may be performed by (or using) a hardware apparatus, such as, for example, a microprocessor, a programmable computer, or an electronic circuit. In some examples, some or more of the most important method actions may be performed by such an apparatus.

[0104] In the above detailed description, it can be seen that various features are grouped together in the examples. This method of disclosure should not be understood as the claimed examples having more features than are expressly recited in each claim. Rather, the disclosure may include fewer than all features of each disclosed example. Thus, the following claims should be considered as incorporated into this description, with each claim standing alone as a separate example. It should be noted that, although each claim standing alone as a separate example, a dependent claim may refer to a specific combination with one or more claims within the scope of the claim, while other examples may include a combination of said dependent claim with the subject matter of any other dependent claim, or may include a combination of any feature with other dependent claims and independent claims. Such combinations are proposed herein unless it is expressly stated that a specific combination is not intended. It is further intended that a feature of a claim may be included in an independent claim even if said claim is not directly dependent on any other independent claim.

[0105] It is further noted that the methods, systems and apparatus disclosed in the present description or claims may be implemented by a device comprising means for performing each action and / or function of the disclosed methods.

[0106] Additionally, in some examples, an individual action may be subdivided into or include multiple sub-actions, and such sub-actions may be included in and become part of the disclosure of the individual action.

[0107] Although the above disclosure illustrates examples of the present disclosure, it should be noted that various changes and modifications can be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions and / or actions of the method claims according to the examples of the present disclosure described herein need not be performed in any particular order. In addition, well-known elements may not be described in detail or may be omitted so as not to obscure the relevant details of the aspects and examples disclosed herein. Furthermore, although elements of the present disclosure may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated. [Explanation of symbols]

[0108] 102 Spiral Structure 104 Spiral Structure 106 Electrical Connections or Couplings 108 Spiral Inductor 200 3D Spiral Inductor 202 Coil 204 Coil 206 Coil 208 Conductor 210 Conductor 212 Electric Field Lines 300 3D Spiral Inductor 302 First spiral coil 304 Spiral Coil 306 Spiral Coil 310 Conductor 312 Conductor 402 Dielectric insulating layer, dielectric layer 404 Dielectric insulating layer, dielectric layer 406 Dielectric insulating layer, dielectric layer 408 Dielectric insulating layer, dielectric layer 410 Dielectric insulating layer, dielectric layer 411 Insulating layer 413 Insulating Layer 415 Insulating layer 417 Insulating Layer 419 Insulating Layer 451 First Part 452 Second Part 453 Third Part 505 Beer 600 3D Spiral Inductor 602 Dielectric layer 604 Dielectric layer 605 Via 606 Dielectric layer 608 Dielectric layer 610 Dielectric layer 611 Insulating layer 613 Insulating Layer 615 Insulating Layer 617 Insulating Layer 619 Insulating Layer 620 Spiral Coil 621 First End 622 Second End 630 Spiral Coil 631 First End 632 Second End 700 3D Spiral Inductor 702 Coils, inductors 704 Coil 706 Coil 707 Cross-section of a spiral conductor element 711 Insulating layer 712 Conductor 713 Insulating layer 714 Conductor 715 Insulating layer 717 Insulating Layer 719 Insulating layer 721 Dielectric Layer 723 Dielectric Layer 725 Dielectric Layer 727 Dielectric Layer 729 Dielectric Layer 900 3D Spiral Inductor 902 Spiral structure coil 903 Conductor 904 Spiral structure coil 905 Conductor 906 Spiral structure coil 908 First End 909 Second End 1002 Dielectric layer 1003 Cross-sectional view of a portion of a spiral conductor element 1004 Dielectric layer 1005 Via 1006 Dielectric layer 1008 Dielectric layer 1010 Dielectric layer 1011 Insulation layer 1013 Insulation layer 1015 Insulation layer 1017 Insulating layer 1019 Insulating layer 1200 3D Spiral Inductor 1201 First end 1202 Dielectric layer, coil 1203 First Conductor 1204 Dielectric layer, coil 1205 Second Conductor 1206 Dielectric layer, coil 1208 Dielectric layer 1210 Dielectric layer 1211 Insulating layer 1213 Insulating layer 1215 Insulating layer 1217 Insulating layer 1219 Insulating layer 1400 3D Spiral Transformer 1402 Spiral Winding 1404 Spiral Winding 1406 Spiral Winding 1600 Mobile Devices 1601 Processor 1608 Buffer Processing Unit (BPU) 1610 Throttle 1611 Branch Instruction Queue (BIQ) 1612 instruction pipeline 1622 System on Chip Device 1626 Display Controller 1628 Display 1630 Input Devices 1632 memory 1634 Codec 1636 Speakers 1638 Microphone 1640 Wireless Circuit 1642 Wireless Antenna 1644 Power supply 1700 Semiconductor Devices 1702 Mobile Phone Devices 1704 Laptop Computer Device 1706 Fixed Location Terminal

Claims

1. 1. An apparatus including a spiral inductor, the spiral inductor comprising: a plurality of dielectric layers formed on a substrate; a plurality of conductive layers, each of the plurality of conductive layers disposed on a respective one of the plurality of dielectric layers; a plurality of insulating layers, each of the plurality of insulating layers disposed on each of the plurality of conductive layers and configured to separate each of the plurality of dielectric layers; A plurality of vias; a first spiral coil disposed in a first plane perpendicular to the substrate, the first spiral coil being formed from a first portion of the plurality of conductive layers and a first set of vias of the plurality of vias configured to connect the first portion of the plurality of conductive layers; a second spiral coil disposed in the first plane, the second spiral coil being formed from a second portion of the plurality of conductive layers and a second set of vias of the plurality of vias configured to connect the second portion of the plurality of conductive layers; Including, The apparatus, wherein the first spiral coil and the second spiral coil are arranged in a nested coil configuration.

2. The apparatus of claim 1 , wherein the first spiral coil is electrically coupled to the second spiral coil.

3. the first spiral coil and the second spiral coil are coupled in series; or The apparatus of claim 2 , wherein the first spiral coil and the second spiral coil are coupled in parallel.

4. the first spiral coil is magnetically coupled to the second spiral coil; The apparatus of claim 1 , wherein the first spiral coil and the second spiral coil are arranged in a transformer configuration and include at least one input tap and one output tap.

5. 13. The apparatus of claim 1, further comprising a third spiral coil disposed in a second plane perpendicular to the substrate, the third spiral coil being formed from a third portion of the plurality of conductive layers and a third set of vias of the plurality of vias configured to connect the third portion of the plurality of conductive layers.

6. The apparatus of claim 5 , wherein the third spiral coil and the second spiral coil are magnetically coupled to each other, and the first spiral coil and the third spiral coil are electrically coupled to each other.

7. The apparatus of claim 5 , wherein the first spiral coil, the second spiral coil, and the third spiral coil are electrically coupled.

8. the first spiral coil, the second spiral coil, and the third spiral coil are coupled in series; or The apparatus of claim 7 , wherein the first spiral coil, the second spiral coil, and the third spiral coil are coupled in parallel.

9. The apparatus of claim 1 , wherein the first spiral coil is magnetically coupled to the second spiral coil in a transformer configuration.

10. The apparatus of claim 1 , wherein the substrate includes at least one of an active element, a passive element, or metal routing located under the first spiral coil.

11. The apparatus of claim 1 , wherein the first spiral coil is formed in a back-end-of-line (BEOL) stack.

12. 10. The device of claim 1, wherein the device is selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and a device in an automotive vehicle.

13. 1. A method for manufacturing a spiral inductor, comprising the steps of: depositing a plurality of dielectric layers over a substrate; depositing a plurality of conductive layers, each of the plurality of conductive layers being disposed on a respective one of the plurality of dielectric layers; depositing a plurality of insulating layers, each of the plurality of insulating layers disposed on each of the plurality of conductive layers, each of the plurality of insulating layers separating each of the plurality of dielectric layers; forming a plurality of vias; forming a first spiral coil in a first plane perpendicular to the substrate, the first spiral coil being formed from a first portion of the plurality of conductive layers and a first set of vias of the plurality of vias configured to connect the first portion of the plurality of conductive layers; forming a second spiral coil in the first plane, the second spiral coil being formed from a second portion of the plurality of conductive layers and a second set of vias of the plurality of vias configured to connect the second portion of the plurality of conductive layers; Including, The method, wherein the first spiral coil and the second spiral coil are arranged in a nested coil configuration.

14. electrically coupling the first spiral coil to the second spiral coil; and electrically coupling the first spiral coil and the second spiral coil in series; or The method of claim 13 , further comprising electrically coupling the first spiral coil and the second spiral coil in parallel.

15. forming a third spiral coil in a second plane perpendicular to the substrate, the third spiral coil being formed from a third portion of the plurality of conductive layers and a third set of vias of the plurality of vias configured to connect the third portion of the plurality of conductive layers; the third spiral coil is magnetically coupled to the second spiral coil, and the first spiral coil and the third spiral coil are electrically coupled to each other; or The method of claim 13 , wherein the first spiral coil, the second spiral coil, and the third spiral coil are arranged in a transformer configuration and include at least one input tap and one output tap.

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