Processes and Applications for Catalytically Influenced Chemical Etching

Abstract

A system for assembling fields onto a second substrate from a source substrate, the source substrate including the fields, the system further including a transfer chuck, the transfer chuck being used to pick in parallel from the source substrate at least four of the fields to be transferred to the second substrate, the relative positions of the at least four of the fields being predetermined.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Provisional Patent Application No. 63 / 167,462, entitled “Systems and Processes for Nano-Precise Pick-and-Place Assembly of Semiconductor Sub-Circuits,” filed March 29, 2021, which is incorporated by reference in its entirety herein.

[0002] This application further claims priority to U.S. Provisional Patent Application No. 63 / 174,128, entitled "Processes and Applications for Catalyst Influenced Chemical Etching," filed April 13, 2021, which is incorporated by reference herein in its entirety.

[0003] This application additionally claims priority to U.S. Provisional Patent Application No. 63 / 215,807, entitled "Tool and Processes for Pick-and-Place Assembly," filed June 28, 2021, which is incorporated by reference herein in its entirety.

[0004] The present invention relates generally to etching, and more specifically to equipment and process techniques for catalytically influenced chemical etching. [Background technology]

[0005] In semiconductor device fabrication, etching refers to any technique that selectively removes material from a thin film over a substrate (with or without prior structures on its surface), resulting in the creation of a pattern of that material on the substrate. The pattern can be defined by a mask that is resistant to the etching process. With the mask in place, etching of the material not protected by the mask can occur by either wet chemical or "dry" physical methods.

[0006] One type of etching is Catalyst Influenced Chemical Etching (CICE), which is a catalyst-based etching method that can be used to fabricate features in semiconductors (e.g., silicon, germanium, etc.) where such features have high aspect ratios, low sidewall taper, low sidewall roughness, and / or controllable porosity. This method is used to produce higher density and higher performance static random access memories (SRAMs) as well as low loss waveguides.

[0007] Unfortunately, there are currently limitations to using CICE to fabricate features in semiconductors. [Prior art documents] [Non-patent literature]

[0008] [Non-Patent Document 1] Ward et al., "Design of Tool for Exfoliation of Monocrystalline Micro-Scale Silicon Films," Journal of Micro and Nano-Manufacturing, April 5, 2019. [Non-Patent Document 2] Rouhani et al., "In-Situ Thermal Stability Analysis of Amorphous Carbon Films with Different Sp3 Content," Carbon, Vol. 130, April 1, 2018, pp. 401-409 Summary of the Invention [Means for solving the problem]

[0009] In one embodiment of the invention, a system for assembling fields onto a second substrate from a source substrate includes a source substrate including a plurality of fields, the system further including a transfer chuck used to pick in parallel from the source substrate at least four of the plurality of fields to be transferred to the second substrate, the relative positions of the at least four of the plurality of fields being predetermined.

[0010] In another embodiment of the invention, the transfer chuck includes a rectangular array of adaptive chucking modules, and further includes a variable pitch mechanism configured to vary at least one of an X-pitch or a Y-pitch of the rectangular array of adaptive chucking modules.

[0011] In a further embodiment of the invention, the transfer substrate includes a field that was previously picked from a source substrate using a transfer chuck, and the transfer substrate further includes an embedded structure that is compliant in the Z direction.

[0012] In another embodiment of the present invention, a method for generating alignment marks in a field during singulation includes generating alignment marks in the field during singulation using an etching technique, the etching technique including catalytically influenced chemical etching or deep reactive ion etching.

[0013] Moreover, in another embodiment of the present invention, a method for preventing catalyst wandering during catalytically influenced chemical etching (CICE) includes providing a semiconductor material. The method further includes patterning a catalyst on a surface of the semiconductor material, the catalyst including one or more isolated features, the one or more isolated features including a predetermined hole. The method additionally includes exposing the patterned catalyst to an etchant, the patterned catalyst and the etchant causing etching of the semiconductor material to form a buttress corresponding to the predetermined hole, the buttress preventing catalyst wandering during CICE.

[0014] Additionally, in another embodiment of the present invention, a method for fabricating nanostructures includes performing a chemically influencing chemical etch on a polysilicon layer to generate a silicon structure. The method further includes depositing one or more structural materials on the silicon structure, the one or more structural materials being selected to enhance desired device characteristics. The method additionally includes generating access to the silicon structure. Moreover, the method includes selectively removing the silicon structure, thereby leaving the one or more structural materials substantially the same.

[0015] In another embodiment of the invention, the fluidic device comprises a multilayer stack of silicon micro- and nano-pillar arrays, where the silicon micro- and nano-pillar arrays are fabricated using catalytically influenced chemical etching, the multilayer stack being fabricated by depositing a film including a polysilicon film and by etching the polysilicon film using catalytically influenced chemical etching.

[0016] In a further embodiment of the invention, a method for curving one or more image sensors into a spherical shape includes compressing a front side of the one or more image sensors using a transfer chuck to create a curvature in the one or more image sensors.

[0017] The foregoing has outlined rather generally the features and technical advantages of one or more embodiments of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter, which may form the subject of the claims of the invention.

[0018] A better understanding of the invention can be obtained when the following detailed description is considered in conjunction with the following drawings. [Brief description of the drawings]

[0019] [Figure 1] FIG. 1 illustrates an exemplary tool for pick-and-place assembly, in accordance with an embodiment of the present invention. [Diagram 2] 2A and 2B are diagrams illustrating an exemplary design for a source / product / intermediate substrate chuck in accordance with an embodiment of the present invention. [Diagram 3] FIG. 1 illustrates an exemplary design for a source substrate chuck with an ultraviolet (UV) light emitting diode (LED) array for field release, in accordance with an embodiment of the present invention. [Figure 4-1] 4A and 4B are diagrams illustrating a transfer chuck with an attached field according to an embodiment of the present invention, and a cross-sectional view of the transfer chuck according to an embodiment of the present invention. [Figure 4-2] Figure 4C is a top view of an xy actuator layer, Figure 4D is a top view of a pneumatic valve layer, and Figure 4E is an alternative top view of a pneumatic valve layer, according to an embodiment of the present invention. [Diagram 5] Figure 5A is an exemplary illustration of a transfer chuck (TC) containing custom fabricated layers for each new field type, according to an embodiment of the present invention. Figure 5B is an expanded view of a transfer chuck containing custom fabricated layers for each new field type, according to an embodiment of the present invention. [Figure 6] Figure 6A illustrates an exemplary transfer chuck (TC) constructed from compliant pins, in accordance with an embodiment of the present invention. Figure 6B is a close-up view of a portion of the top metal layer of the transfer chuck, in accordance with an embodiment of the present invention. Figure 6C is a close-up view of a thin skin positioned over a bottom portion of the top metal layer of the transfer chuck as shown in Figure 6B, in accordance with an embodiment of the present invention. [Figure 7] FIG. 1 illustrates an exemplary labeling of a field within a rectangular bounding region that can be assembled using an actuator grid using nine labels (nine assembly steps), according to an embodiment of the present invention. [Figure 8] 1A-1C illustrate an exemplary process showing intermediate substrates used for assembly, in accordance with an embodiment of the present invention. [Figure 9] FIG. 1 illustrates an exemplary illustration of multiple TCs being used during assembly, according to an embodiment of the present invention. [Figure 10] FIG. 2 illustrates an exemplary reconfigurable grid TC according to an embodiment of the present invention. [Figure 11] 11A and 11B are diagrams illustrating an exemplary TC with closed boundary vacuum and / or pressure regions, according to an embodiment of the present invention. [Figure 12] 12A and 12B are diagrams illustrating alternative embodiments of an exemplary TC with closed boundary vacuum and / or pressure regions, in accordance with embodiments of the present invention. [Figure 13]11 is a further alternative embodiment of an exemplary TC with a closed boundary vacuum and / or pressure region, according to an embodiment of the present invention. [Figure 14] 1 illustrates an exemplary sensor arrangement for an exemplary weighing module, in accordance with an embodiment of the present invention. [Figure 15] 14A-14D illustrate alternative exemplary sensor arrangements for an exemplary weigh module, in accordance with an embodiment of the present invention. [Figure 16] 1 illustrates an exemplary reconfiguration grid sensor arrangement for an exemplary weighing module, in accordance with an embodiment of the present invention. [Figure 17] FIG. 17 illustrates the reconstructed grid sensor arrangement shown in FIG. 16 enlarged to capture a 30 mm×3 mm field in accordance with an embodiment of the present invention. [Figure 18] 18A-18D are diagrams illustrating an exemplary alignment metrology framework for an exemplary metrology module, in accordance with an embodiment of the present invention. [Figure 19] 19A-19C are diagrams illustrating an alternative exemplary alignment metrology framework for an exemplary metrology module, in accordance with an embodiment of the present invention. [Figure 20] 20A-20C are diagrams illustrating details regarding an exemplary weighing module, according to an embodiment of the present invention. [Figure 21] FIG. 1 illustrates an exemplary metering framework, according to an embodiment of the present invention. [Figure 22] FIG. 2 illustrates an exemplary field containing a 2×2 array of dies, in accordance with an embodiment of the present invention. [Diagram 23] FIG. 1 illustrates an exemplary metering framework, according to an embodiment of the present invention. [Figure 24] FIG. 2 illustrates another embodiment of an exemplary metering framework, in accordance with embodiments of the present invention. [Diagram 25] FIG. 1 illustrates a further embodiment of an exemplary metering framework, in accordance with an embodiment of the present invention. [Figure 26] 26A and 26B are diagrams illustrating an exemplary Known Bad Die Replacement Chuck (KRC), in accordance with an embodiment of the present invention. [Figure 27] 27A-27C are diagrams illustrating exemplary source substrate types, according to embodiments of the present invention. [Figure 28] 28A and 28B are diagrams illustrating an example field with an example multi-layer encapsulation, in accordance with an embodiment of the present invention. [Figure 29] 29A and 29B are diagrams illustrating exemplary face-to-back (F2B) and face-to-face (F2F) device stacks, in accordance with an embodiment of the present invention. [Diagram 30] FIG. 2 illustrates an exemplary assembly of a static random access memory (SRAM) above a logic field in accordance with an embodiment of the present invention. [Diagram 31] FIG. 2 illustrates an exemplary assembly of multiple stacked static random access memories (SRAMs) above a logic field in accordance with an embodiment of the present invention. [Diagram 32] FIG. 1 illustrates an exemplary assembly of a static random access memory (SRAM) above a logic field with an error correction interposer in between, in accordance with an embodiment of the present invention. [Diagram 33] 1A-1C illustrate an exemplary sequence for pick-and-place assembly in accordance with an embodiment of the present invention. [Diagram 34] 10A-10C illustrate an alternative exemplary sequence for pick-and-place assembly in accordance with an embodiment of the present invention. [Diagram 35] 13A-13C illustrate further alternative exemplary sequences for pick-and-place assembly in accordance with an embodiment of the present invention. [Diagram 36] 36A and 36B are diagrams illustrating an exemplary transfer chuck in accordance with an embodiment of the present invention. [Figure 37-1]37A-37F and 37I illustrate alternative exemplary transfer chucks, according to embodiments of the present invention. [Figure 37-2] 37G, 37H, and 37J-O illustrate alternative exemplary transfer chucks, according to embodiments of the present invention. [Figure 38] 38A-38C are diagrams illustrating an exemplary reconfigured transfer chuck (TC), in accordance with an embodiment of the present invention. [Figure 39] 39A-39C illustrate an exemplary transfer chuck, showing an array of adaptive chucking modules (ACMs) that are movable relative to one another using a variable pitch mechanism (VPM), in accordance with an embodiment of the present invention. [Diagram 40] 40A and 40B illustrate an alternative exemplary transfer chuck, showing an array of elongated adaptive chucking modules (ACMs) that are movable relative to one another using a variable pitch mechanism (VPM), in accordance with an embodiment of the present invention. [Diagram 41] FIG. 1 illustrates a further alternative exemplary transfer chuck, showing an array of elongated adaptive chucking modules (ACMs) movable relative to one another using a variable pitch mechanism (VPM) in accordance with an embodiment of the present invention. [Diagram 42] 42A and 42B are diagrams illustrating an exemplary adaptive chucking module (ACM), in accordance with an embodiment of the present invention. [Diagram 43] 43A-43C illustrate an additional exemplary transfer chuck, showing an array of adaptive chucking modules (ACMs) that are movable relative to one another using a variable pitch mechanism (VPM), in accordance with an embodiment of the present invention. [Diagram 44] 44A-44F are diagrams illustrating an exemplary transfer substrate, according to an embodiment of the present invention. [Diagram 45]1 illustrates an alternative exemplary transfer substrate, according to an embodiment of the present invention. [Figure 46] 46A and 46B are diagrams illustrating an exemplary interference prevention method (during field assembly onto a transfer substrate) according to an embodiment of the present invention. [Figure 47] 47A-47E are diagrams illustrating an exemplary source substrate according to an embodiment of the present invention. [Figure 48] 4 is a flow chart of a method for generating a source substrate for assembly from a substrate with a sacrificial layer in accordance with an embodiment of the present invention. [Figure 49] 49A-49F are cross-sectional views for generating a source substrate for assembly from a substrate with a sacrificial layer using the steps described in FIG. 48 according to an embodiment of the invention. [Figure 50] 50A-50C are diagrams illustrating an exemplary yield management flow according to an embodiment of the present invention. [Figure 51] 51A-51D are diagrams illustrating an exemplary method for dicing and alignment mark creation, according to an embodiment of the present invention. [Figure 52] 52A and 52B are diagrams illustrating aligning a picked field on a transfer chuck to a stable reference grid, in accordance with an embodiment of the present invention, and aligning the position of an ACM relative to the stable reference grid, in accordance with an embodiment of the present invention. [Diagram 53] 53A and 53B are diagrams illustrating an exemplary approach for Metal-Assisted Catalytic Etching (MACE) based dicing using an inkjetted catalyst, according to an embodiment of the present invention. [Figure 54] 54A and 54B are diagrams illustrating an alternative exemplary approach for MACE-based dicing using inkjetted catalyst, according to an embodiment of the present invention. [Figure 55]55A and 55B illustrate an exemplary method for substrate dicing after backgrinding, in accordance with an embodiment of the present invention. [Figure 56] 1A-1C illustrate an exemplary method for producing diced cuts in a source substrate prior to backgrinding, in accordance with an embodiment of the present invention. [Figure 57] 4 is a flow chart of a method for creating a metal break for substrate dicing using metal-assisted chemical etching, in accordance with an embodiment of the present invention. [Figure 58] 58A-58C are cross-sectional views for creating metal breaks for substrate dicing using metal-assisted chemical etching using the steps described in FIG. 57, according to an embodiment of the invention. [Figure 59] 1 is a flowchart of a method for patterning a catalyst using selective atomic layer deposition (ALD) such that the catalyst is part of a “collapse avoidance cap” in accordance with an embodiment of the present invention. [Figure 60] 60A-60E are cross-sectional views for patterning a catalyst using selective atomic layer deposition (ALD) such that the catalyst is part of a “collapse avoidance cap” using the steps described in FIG. 59 according to an embodiment of the invention. [Figure 61] 1 is a flow chart of a method for producing a collapse avoidance cap and catalyst patterning by directional deposition of catalyst and atomic layer etching in accordance with an embodiment of the present invention. [Figure 62] 62A-62D are cross-sectional views for producing a collapse avoidance cap and catalyst patterning by directional deposition of catalyst and atomic layer etching using the steps described in FIG. 61 according to an embodiment of the present invention. [Figure 63] 63A-63D are diagrams illustrating wandering of an isolated catalyst during a CICE, according to an embodiment of the present invention. [Figure 64]64A-64D are diagrams illustrating exemplary geometries for stabilization patterns or support structures, according to embodiments of the present invention. [Figure 65] 1 is a flowchart of a method for fabricating isolated catalytic dots with circular catalytic buttresses having Ru as a catalyst according to an embodiment of the present invention. [Figure 66] 66A-66E are cross-sectional views for fabricating isolated catalyst dots with circular catalytic buttresses having Ru as a catalyst using the steps described in FIG. 65 according to an embodiment of the present invention. [Figure 67] 67A-67E are top views for fabricating isolated catalyst dots with circular catalytic buttresses having Ru as a catalyst using the steps described in FIG. 65 according to an embodiment of the present invention. [Figure 68] Figure 68A illustrates a catalyst with nanostructures composed of porous silicon and Figure 68B illustrates a catalyst with nanostructures composed of alternating layers of porous and non-porous silicon, according to an embodiment of the invention. [Figure 69] 69A-69D illustrate the removal of silicon buttresses ("stabilization patterns") after CICE using an isolated catalyst with buttresses to prevent wandering ("catalyst buttresses") in accordance with an embodiment of the present invention. [Figure 70] 70A-70C are diagrams illustrating designing collapsed pillars to deterministically collapse in a particular direction, such as by placing a buttress pattern towards one side of an etch, in accordance with an embodiment of the present invention. [Figure 71] 4 is a flowchart of a method for fabricating a line / space pattern with lithographic links using a CICE in accordance with an embodiment of the present invention. [Figure 72]FIG. 72 is a top view of a desired line / space pattern using the steps described in FIG. 71 in accordance with an embodiment of the present invention. [Figure 73] 73A-73C are cross-sectional views for fabricating a line / space pattern with lithographic links using CICE using the steps described in FIG. 71 according to an embodiment of the present invention. [Figure 74] 74A and 74B show exemplary polysilicon nanowire arrays fabricated using CICE with gold as a catalyst, according to an embodiment of the present invention. [Figure 75] FIG. 1 illustrates an exemplary geometry for converting silicon fins to holes using atomic layer deposition (ALD) of silicon oxide, according to an embodiment of the invention. [Figure 76] 4 is a flowchart of a method for a tone-reversal process by CICE according to an embodiment of the present invention. [Figure 77] 77A-77D are top views for a CICE tone reversal process using the steps described in FIG. 76 according to an embodiment of the present invention. [Figure 78] 78A-78D are cross-sectional views for a CICE tone reversal process using the steps described in FIG. 76 according to an embodiment of the present invention. [Figure 79] 1 is a flow chart of a method for performing a polysilicon CICE tone reversal process including catalyst removal using selective chemical etching in accordance with an embodiment of the present invention. [Figure 80] 80A-80D are top views of performing a polysilicon CICE tone reversal process, including catalyst removal using selective chemical etching, using the steps described in FIG. 79, in accordance with an embodiment of the present invention. [Figure 81]81A-81F are cross-sectional views for performing a polysilicon CICE tone reversal process, including catalyst removal using selective chemical etching, using the steps described in FIG. 79 according to an embodiment of the present invention. [Figure 82] 1 is a flow chart of a method for performing a polysilicon CICE tone reversal process including catalyst removal using selective chemical etching, where the etch stop layer is removed in the final device, in accordance with an embodiment of the present invention. [Figure 83] 83A-83D are top views of performing a polysilicon CICE tone reversal process, including catalyst removal using selective chemical etching using the steps described in FIG. 82, in accordance with an embodiment of the present invention, with the etch stop layer being removed in the final device. [Figure 84] 84A-84G are cross-sectional views for performing a polysilicon CICE tone reversal process using the steps described in FIG. 82 according to an embodiment of the invention, including catalyst removal using selective chemical etching, with the etch stop layer being removed in the final device. [Figure 85] 4 is a flow chart of a method for fabricating metal interconnects and vias using a polysilicon CICE tone reversal process in accordance with an embodiment of the present invention. [Figure 86] 86A-86F are top views of fabricating metal interconnects and vias using a polysilicon CICE tone reversal process using the steps described in FIG. 85 according to an embodiment of the present invention. [Figure 87] 87A-87L are cross-sectional views for fabricating metal interconnects and vias using a polysilicon CICE tone reversal process using the steps described in FIG. 85 according to an embodiment of the invention. [Figure 88]1 is a flow chart of a method for forming a superlattice by tone reversal CICE and selective growth in accordance with an embodiment of the present invention. [Figure 89] 89A-89D are top views of forming a superlattice by tone reversal CICE and selective growth using the steps described in FIG. 88 according to an embodiment of the present invention. [Figure 90] 90A-D are cross-sectional views for forming a superlattice by tone-reversal CICE and selective growth using the steps described in FIG. 88 according to an embodiment of the present invention. [Figure 91] 1 is a flowchart of a method for Deterministic Lateral Displacement (DLD) device fabrication using CICE and silicon wafer detachment in accordance with an embodiment of the present invention. [Figure 92] 92A-92G are cross-sectional views for DLD device fabrication using CICE and silicon wafer detachment using the steps of FIG. 91 according to an embodiment of the present invention. [Figure 93] 1 is a flowchart of a method for bonding a cover plate to a DLD pillar to produce a DLD device after CICE without causing pillar collapse, according to an embodiment of the present invention. [Figure 94] 94A-94E are cross-sectional views for bonding a cover plate to a DLD pillar to produce a DLD device after CICE without causing pillar collapse, using the steps of FIG. 93, according to an embodiment of the present invention. [Figure 95] 4 is a flow chart of a method for improving pillar height using a porous stabilizing material, according to an embodiment of the present invention. [Figure 96] 96A-96C are cross-sectional views for improving pillar height using a porous stabilizing material using the steps of FIG. 95, according to an embodiment of the present invention. [Figure 97]1 is a flowchart of a method for bonding a cover plate for a DLD device after CICE without causing pillar collapse, in accordance with an embodiment of the present invention. [Figure 98] 98A-98D are cross-sectional views for bonding a cover plate for a DLD device after CICE without causing pillar collapse using the steps of FIG. 97 according to an embodiment of the present invention. [Figure 99] 1 is a flow chart of a method for improving thin pillar collapse by reducing pillar size starting with thick pillars after cover plate bonding in accordance with an embodiment of the present invention. [Figure 100] 100A-100D are cross-sectional views for improving collapse of thin pillars by starting with the thick pillars and reducing the pillar size after cover plate bonding using the steps of FIG. 99 according to an embodiment of the present invention. [Figure 101] 1 is a flowchart of a method for multi-stack DLD device fabrication using polysilicon CICE according to an embodiment of the present invention. [Figure 102] 102A-102F are cross-sectional views for multi-stack DLD device fabrication using polysilicon CICE using the steps of FIG. 101 according to an embodiment of the present invention. [Figure 103] FIG. 1 illustrates a cross-section of a multi-stack DLD device in a nanoscale area to improve overall throughput, according to an embodiment of the present invention. [Figure 104] FIG. 1 illustrates a metasurface comprising four arrays of pillars for focusing of light of various wavelengths using silicon nanopillars fabricated by CICE and oxidized porous silicon nanopillars in accordance with an embodiment of the invention. [Figure 105] FIG. 1 illustrates an exemplary 3D stacked image sensor, in accordance with an embodiment of the present invention. [Figure 106] 1 illustrates an exemplary petal-shaped imager die, according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] As discussed in the Background section, in semiconductor device fabrication, etching refers to any technique that selectively removes material from a thin film over a substrate (with or without prior structures on its surface), resulting in the creation of a pattern of that material on the substrate. The pattern can be defined by a mask that is resistant to the etching process. With the mask in place, etching of the material not protected by the mask can occur by either wet chemical or "dry" physical methods.

[0021] One type of etching is catalytically influenced chemical etching (CICE), which is a catalyst-based etching method that can be used to fabricate features in semiconductors (e.g., silicon, germanium, etc.) where such features have high aspect ratios, low sidewall taper, low sidewall roughness, and / or controllable porosity. This method is used to produce higher density and higher performance static random access memories (SRAMs) as well as low loss waveguides.

[0022] Unfortunately, there are currently limitations to using CICE to fabricate features in semiconductors.

[0023] The principles of the present invention provide a means for utilizing the CICE process to efficiently fabricate features in semiconductors using the equipment and process techniques for catalytically influenced chemical etching of the present invention.

[0024] Referring now in detail to the figures, FIG. 1 illustrates an exemplary tool 100 for pick-and-place assembly, in accordance with an embodiment of the present invention.

[0025] As shown in FIG. 1, tool 100 includes a nanoprocessing xy stage 101 for supporting a source substrate chuck 102 (used to hold a source substrate 103) and a product substrate chuck 104 (used to hold a product substrate 105).

[0026] Tool 100 further includes a precision pick and place module frame 106 that supports a short stroke xy stage 107. Additionally, as shown in FIG. 1, tool 100 includes an optional metrology module 108 on top of the short stroke xy stage 107. Additionally, tool 100 includes a voice coil 109 and plasma unit 110 along with a transfer chuck (TC) 111 where a subset of fields 112 are picked up by the transfer chuck 111 from the source substrate 103, as shown in FIG.

[0027] Additionally, as shown in FIG. 1, singulated field 113 remains on source substrate 103 where field 114 contains known bad die.

[0028] Additionally, as shown in FIG. 1, layer 1 (element 115) with field 1 of product substrate 105 has already been assembled.

[0029] Moreover, FIG. 1 illustrates, among other things, an exemplary tool 100 for pick-and-place assembly of fields from one or more source substrates 103 to a product substrate 105. A "field," as used herein, refers to the largest contiguous portion of a substrate produced after substrate singulation. A field can contain one or more dies, chiplets, or devices. In one embodiment, the source substrates 103 each contain a single type of field. In another embodiment, the source substrates 103 contain multiple types of fields. In one embodiment, the fields in the source substrates 103 can range in size from 0.5 mm on a side to up to 200 mm on a side.

[0030] In one embodiment, a tool 100 for pick-and-place assembly incorporates one or more of the following components: a source substrate chuck 102, a product substrate chuck 104, an intermediate substrate chuck (holding the intermediate substrate) (not shown in FIG. 1), a transfer chuck (TC) 111, a plasma unit 110 for pre-bonding surface activation, and a metrology module (MM) 108.

[0031] 2A-2B and 3 in conjunction with FIG 1, FIG 2A-2B illustrate exemplary designs for source / product / intermediate chucks in accordance with embodiments of the present invention. FIG 3 illustrates an exemplary design for a source substrate chuck (such as source substrate chuck 102) with an ultraviolet (UV) light emitting diode (LED) array for field release in accordance with embodiments of the present invention.

[0032] 2A, a transparent source / product / intermediate substrate 201 touches a portion of a chuck 202 (representing a source substrate chuck 102 or a product substrate chuck 104 or an intermediate substrate chuck). In one embodiment, such a substrate 201 includes chiplets 203.

[0033] In one embodiment, source / product / intermediate substrate chuck 202 includes an optional light source 204 for field release (e.g., fiber-based) via optical path 205. Additionally, in one embodiment, source / product / intermediate substrate chuck 202 includes an optional imager 206 for in situ metrology. Additionally, in one embodiment, source / product / intermediate substrate chuck 202 includes an optional light source 207 for thermal actuation, a DMD assembly 208, and another optional light source 209 for field release (e.g., fiber-based).

[0034] Additionally, in one embodiment, the source / product / intermediate substrate chuck 202 includes an optional projector 210 for projecting an optical signal and another optional imager 211 for in-situ metrology.

[0035] Additionally, in one embodiment, the source / product / intermediate substrate chuck 202 includes an optional grouping of a thermoelectric cooler 212, an optional transparent thermally conductive printed circuit board (PCB) 213, and an optional cooling assembly 214 with a transparent coating.

[0036] As shown in Figure 2B, Figure 2B illustrates a top view of an exemplary optional photonic waveguide substrate 215. Such substrate 215 includes an outcoupling grating 216 and an incoupling grating 217. Additionally, Figure 2B illustrates that the photonic waveguide substrate 215 includes a two-dimensional photonic crystal passage 218 for in-plane light transmission.

[0037] Additionally, as shown in FIG. 3, the source substrate chuck 102 includes an optional addressable ultraviolet (UV) light emitting diode (LED) array 301 along with an optional cooling system assembly 302 .

[0038] Further discussion of Figures 2A-2B and 3, in conjunction with Figure 1, is provided below.

[0039] In one embodiment, the primary function of the substrate chuck 202 is to hold the source / product / intermediate substrate, respectively, in a thermo-mechanically stable state during field assembly and (when required) to change the thermo-mechanical state of the substrate in a controlled manner.

[0040] In one embodiment, the substrate chuck 202 is constructed using one or more of the following: silicon carbide (SiC), sapphire, fused silica, glass, silicon, a flexible substrate (e.g., polycarbonate, etc.). In one embodiment, the surface of the chuck that contacts the substrate is coated with a hard material (e.g., one or more of the following: silicon nitride (SiN), silicon carbide (SiC), etc.).

[0041] In one embodiment, one or more of the substrate chucks 202 have transparent portions. The transparent portions (with respect to the relevant spectrum) can allow light transmission through the chuck to facilitate field release / temporary bonding to / from the substrate and / or metrology through the chuck. Light-based field release solutions are commercially available. Light is incident from the bottom surface of the substrate chuck 202, or alternatively from the side, or a combination of the two. In one embodiment, a waveguide-based solution is used to direct light from the side of the substrate chuck 202 (where the light is incident) to the bottom surface of the substrate. If the minimum feature size required in the waveguide substrate is larger than 100 nm, direct write methods can be used for substrate patterning (e.g., laser direct write). If the minimum feature size is smaller than 100 nm, nanoimprint lithography (NIL) can be used for patterning with a limited number of standardized NIL templates. Standard templates can be constructed from quantized pattern pieces (e.g., 1 mm vertical waveguide channel, 1 mm horizontal waveguide channel, +90° waveguide channel, -90° waveguide channel, etc.). These can be used to pattern custom waveguide paths from any outcoupling grating 216 to the incoupling grating 217. In one embodiment, the incoupling grating 217 is placed at a location on the periphery that satisfies the quantized X and Y separation constraints imposed by the quantized waveguide pieces. In another embodiment, an addressable UV LED array is used for field release from the source substrate 103.

[0042] In one embodiment, one or more of the substrate chucks 202 incorporate a weigh module (eg, weigh module 108) to enable in-situ metrology.

[0043] In one embodiment, one or more of the substrate chucks 202 have thermal actuators (embedded or otherwise). The thermal actuators can be used to control one or more of the following: temperature, field distortion, and field topography on the source / product / intermediate substrate. In one embodiment, thermal actuation can be implemented using an array of thermoelectric coolers (TECs). A heat exchanger can be utilized to exchange heat with the thermal actuators. In one embodiment, the heat exchanger uses a liquid (e.g., water, etc.) as the actuation fluid. In one embodiment, the thermal actuators are mounted on a thermally conductive printed circuit board 213. In one embodiment, the printed circuit board 213 is transparent.

[0044] In another embodiment, thermal actuation is performed using spatially modulated incident radiation that is absorbed by the source / product / intermediate substrate, for example, using one or more digital micromirror devices (DMDs). The radiation can incorporate one or more of the following: Short Wavelength Infrared Radiation (SWIR), Middle Wavelength Infrared Radiation (MWIR), and Long Wavelength Infrared Radiation (LWIR).

[0045] In one embodiment, one or more of the substrate chucks 202 are inert to the source substrate sacrificial layer etchant, hi another embodiment, one or more of the chucks 202 can be coated with a material that is inert to the sacrificial layer etchant (e.g., PTFE, high density polyethylene (HDPE), etc.).

[0046] In one embodiment, one or more of the source substrate chucks 102 are mounted on a motion stage that moves independently of other stages in an n-MASC tool (a tool for nanometer-scale modular assembly of semiconductor chiplets).

[0047] In one embodiment, the n-MASC tool incorporates multiple substrate chucks 202, each of which may be independently movable, for simultaneous handling and / or processing of multiple source / product / intermediate substrates.

[0048] 4A-4E, which illustrate details regarding an exemplary transfer chuck (TC) 111.

[0049] As shown in FIG. 4A, FIG. 4A illustrates a transfer chuck (TC) 111 with an attached field 401 in accordance with an embodiment of the present invention.

[0050] A cross-sectional view of transfer chuck (TC) 111 is shown in FIG. 4B, in accordance with an embodiment of the present invention.

[0051] 4B, the TC 111 includes optional micromachined pins 402, for example made of silicon, to connect the stationary thermal actuator layer to the movable thermal actuator arm. In one embodiment, such micromachined pins 402 have a diameter of 2 μm with a height of 10 μm.

[0052] In one embodiment, the TC111 includes a heat exchanger fluid 403 and a thermally conductive printed circuit board 404. Additionally, in one embodiment, the TC111 includes a heat exchanger layer 405 and a thermal actuator layer 406, which can contain a thermoelectric cooler 407. Additionally, in one embodiment, the TC111 includes an xy actuator layer 408. In one embodiment, the xy actuator layer 408 is constructed of stainless steel. In one embodiment, the xy actuator layer 408 has a thickness of 5 mm. A top view of such an xy actuator layer 408 is shown in FIG. 4C, in accordance with an embodiment of the present invention.

[0053] Referring to FIG. 4C, the xy actuator layer 408 includes an xy flexure 409 , a stationary portion 410 , and a movable portion 411 .

[0054] Returning to Figure 4B, the TC 111 further includes a pneumatic valve layer and an xy flexure layer 412. Such layer 412 includes an optional flexible layer 413 (e.g., a polymer) that creates a valve seal within the pneumatic valve layer 412. Additionally, such layer 412 includes a flow valve 414, which can be electrostatically actuated, for example.

[0055] An illustration of a top view of pneumatic valve layer 412 is shown in Figure 4D, in accordance with an embodiment of the present invention. As shown in Figure 4D, pneumatic valve layer 412 includes a stationary portion 415 and a movable portion 416. Additionally, as shown in Figure 4D, pneumatic valve layer 412 includes an xy flexure 417. In one embodiment, such an xy flexure 417 can be used to induce vacuum and pressure from stationary portion 415 to movable portion 416.

[0056] A further illustration of an alternative top view of pneumatic valve layer 412 is shown in FIG. 4E, in accordance with an embodiment of the present invention. As shown in FIG. 4E, pneumatic valve layer 412 includes an example actuation grid 418, optional pressure line 419, optional vacuum source 420 at the layer edge, optional pressure source 421, and optional vacuum line 422. As shown in FIG. 4E, pneumatic valve layer 412 can include vacuum and pressure distribution lines from the edge of the layer to each actuation unit. In one embodiment, pressure and vacuum are provided through channels etched into the layer substrate. In one embodiment, the pressure and vacuum distribution lines are on different sides of the same substrate.

[0057] Returning to FIG. 4B, in one embodiment, the TC 111 includes a z-flexure layer 423 (two bonded layers to create an internal fluid channel). In one embodiment, each layer of the internal fluid channel has a thickness of 0.25 mm. In one embodiment, the z-flexure layer 423 includes a z-flexure 424.

[0058] Additionally, in one embodiment, the TC 111 includes a pressure manifold layer 425 for field bowing. In one embodiment, layer 425 has a thickness of 0.3 mm. In one embodiment, pressure manifold layer 425 includes optional pressure lines 426.

[0059] Additionally, in one embodiment, the TC 111 includes a vacuum suction layer 427. In one embodiment, the vacuum suction layer 427 has a thickness of 0.3 mm.

[0060] Additionally, Figure 4B illustrates field contact pins 428. In one embodiment, such pins can be optionally coated with a hard material (e.g., SiN, SiC, etc.). Moreover, Figure 4B illustrates field 401 and optional vacuum line 429. Finally, Figure 4B illustrates gap 430 between the actuation unit boundary and the xy-movable layer.

[0061] Moreover, as shown in FIG. 4B, in one embodiment, the lighter shaded regions can be filled with a sacrificial material (e.g., SiO2, etc.) during TC fabrication. In one embodiment, these regions can provide structural stability during operation (e.g., TC pin grinding, etc.), but can be etched away, for example, using vapor HF, once the TC 111 is fabricated.

[0062] Additionally, as shown in FIG. 4B, in one embodiment, the darker shaded areas may be made of silicon.

[0063] Reference is now made to FIG. 5A, which illustrates an example illustration of a transfer chuck (TC) 111 containing custom fabricated layers for each new field type, in accordance with an embodiment of the present invention.

[0064] As shown in Figure 5A, the TC 111 can optionally include a vacuum supply 501 to the TC vacuum manifold. Additionally, as shown in Figure 5A, the TC 111 is optionally secured to the frame 106 using an annular contact 502 at its periphery.

[0065] FIG. 5B illustrates a close-up view of transfer chuck 111 containing custom-fabricated layers for each new field type, in accordance with an embodiment of the present invention.

[0066] 5B, transfer chuck 111 contains a primary vacuum manifold 503 and a secondary vacuum manifold 504. In one embodiment, the primary and secondary vacuum manifolds 503, 504 are optionally coupled together (e.g., such as shown at element 505).

[0067] In one embodiment, the TC 111 does not have a vacuum supply in areas where the field is not to be assembled (eg, such as that shown in element 506).

[0068] In one embodiment, the primary and secondary vacuum manifolds 503, 504 are optionally designed in such a way that the pins do not interfere with the waveguide multilayer memory (WMM) beam path (e.g., such as shown in element 507).

[0069] Additionally, in one embodiment, the TC 111 includes a vacuum section 508 in a secondary vacuum manifold 504 that holds the field to the manifold pins.

[0070] Additionally, FIG. 5B illustrates an example air flow direction 509.

[0071] In one embodiment, the secondary vacuum manifold 504 is fabricated from a standard silicon substrate. In one embodiment, the primary vacuum manifold 503 is fabricated using a thick silicon substrate to provide additional structural strength against sagging due to gravity.

[0072] Reference is now made to FIG. 6A, which illustrates an exemplary transfer chuck (TC) 111 constructed from compliant pins, in accordance with an embodiment of the present invention.

[0073] As shown in Fig. 6A, the TC111 includes a top metal layer 601 and a back transistor layer 602, with a nMASC field 603 (multi-layer Al2O3-SiO2 combination) between layers 601 and 602. Moreover, as shown in Fig. 6A, an exemplary particle 604 is positioned on the surface of the top metal layer 601.

[0074] An enlarged view of a portion of the top metal layer 601 is shown in Figure 6B in accordance with an embodiment of the present invention. Figure 6C illustrates an enlarged view of a thin skin 605 positioned over a bottom portion of the top metal layer 601 as shown in Figure 6B in accordance with an embodiment of the present invention.

[0075] A discussion regarding Figures 4A-4E, 5A-5B, and 6A-6C is provided below.

[0076] The primary function of TC111 is to pick up one or more fields from or place one or more fields on a source / product / intermediate substrate in a thermo-mechanically stable manner, and (if required) change the thermo-mechanical state of the fields in a controlled manner.

[0077] In one embodiment, one or more of the TCs 111 are constructed using one or more of the following: silicon carbide (SiC), sapphire, fused silica, glass, silicon, flexible substrates (e.g., polycarbonate, etc.). In one embodiment, the substrate-contacting surfaces of one or more of the TCs 111 are coated with a hard material (e.g., silicon nitride (SiN), silicon carbide (SiC), etc.).

[0078] In one embodiment, one or more of the TCs 111 have transparent portions. The transparent portions (with respect to the relevant spectrum) can allow light transmission through the TC and facilitate field release / temporary coupling to / from the substrate and / or metrology through the TC. Light is incident from the underside of the substrate chuck, or alternatively from the side, or a combination of the two. In one embodiment, a waveguide-based solution is used to direct light from the side of the substrate chuck (where the light is incident) to the underside of the substrate.

[0079] In one embodiment, the chuck (e.g., TC111, etc.) incorporates one or more metal layers (e.g., metal layer 601, etc.). The metal layers (e.g., metal layer 601, etc.) can be used to provide structural stability to TC111. The metal layers (e.g., metal layer 601, etc.) can be machined using macromachining techniques (e.g., computer numerical control (CNC) machining). In one embodiment, the metal layers (e.g., metal layer 601, etc.) are made from a high thermal expansion material. In one embodiment, the metal layers (e.g., metal layer 601, etc.) are made from a low thermal conductivity material. In one embodiment, the metal layers (e.g., metal layer 601, etc.) are made using stainless steel.

[0080] In one embodiment, the TC111 incorporates a thick substrate (e.g., thick silicon, thick sapphire) having a thickness of 0.775 mm or greater. A thick substrate can be used to provide structural stability to the TC111.

[0081] In one embodiment, TC111 incorporates layers to promote bonding of the various TC layers (eg, chrome thin films, polymer films, adhesive polymer films, etc.).

[0082] In one embodiment, the TC 111 incorporates a layer to prevent contamination of the n-MASC tool components (including the TC subcomponents) by sacrificial layer etchants (e.g., thin chromium films, polymer films, adhesive polymer films, etc.).

[0083] In one embodiment, the multiple layers that make up TC111 are bonded together using one or more of the following: anodic bonding, fusion bonding, hybrid bonding, pneumatic suction, adhesives, and the like.

[0084] In one embodiment, the TC111 utilizes vacuum suction to hold the field 401. In one embodiment, the TC111 incorporates an integrated valve assembly for turning on and off the vacuum suction for each picked field. The TC111 can also incorporate an integrated valve assembly for turning on and off a pressure source corresponding to each picked field. The pressure source can be utilized to generate a thin fluid lubrication layer immediately prior to field pick-up or field bonding. The holes and recesses required to enable the supply of vacuum and pressure to the picked fields can be generated using a deep etching process (e.g., metal-assisted chemical etching (MACE), deep reactive ion etching (DRIE), etc.). Moreover, the TC111 utilizes a flexure mechanism machined into one or more of the TC layers to supply pressure and vacuum from the movable parts of the TC111 to the fixed parts of the TC111.

[0085] In one embodiment, the valve assembly (for turning on and off pressure / vacuum) consists of a hole in TC111, a flexible membrane (e.g., made from a polymer), a membrane actuation mechanism (e.g., a voice coil with a magnetically sensitive material deposited or attached to the flexible membrane), and a relay (e.g., using a transistor) for turning the actuation mechanism on and off. In one embodiment, the actuation mechanism utilizes thermal expansion.

[0086] In one embodiment, the TC111 incorporates a porous layer to create a vacuum suction over the field 401. In one embodiment, the TC111 incorporates a layer with a hybrid porous and non-porous structure to create a vacuum suction over the field 401.

[0087] In one embodiment, the TC 111 uses electrostatic forces to hold the fields 401. In one embodiment, the TC 111 uses Johnsen-Rahbek type electrostatic chucking, holding the fields 401 only where they contact the TC 111. In one embodiment, the chucking mechanism incorporates an array of switches for modulating the electrostatic holding force. In one embodiment, the array of switches is addressed using multiplexer electronics.

[0088] In one embodiment, the TC 111 utilizes an adhesive to hold the field 401. In one embodiment, the TC 111 utilizes a UV release glue to hold the field 401.

[0089] In one embodiment, the TC 111 contacts the field 401 using an array of pins (such as, for example, pin 428). The pins can be in the shape of a truncated cone. The pins can have one or more holes, and the vacuum or pressure is applied through the one or more holes. In another embodiment, the TC 111 contacts the field 401 using an array of rings. The ring area can include one or more holes for applying the vacuum or pressure.

[0090] In one embodiment, the pins (such as, for example, pin 428) are compliant in the z-axis.

[0091] In one embodiment, the TC contact surface is polished after assembly of the TC 111. Any recesses in the TC layer can be filled with a fluid-etchable layer (such as silicon oxide, for example), which can be etched using vapor HF. The fluid-etchable layer can be etched away after polishing.

[0092] In one embodiment, the TC111 incorporates integrated mechanical actuators (e.g., one or more piezoelectric actuators, thermal actuators, electrostatic actuators, etc.) to perform actuation in the X-axis, Y-axis, and / or θ-axis for one or more of the picked fields 401. In one embodiment, the TC111 incorporates a flexure layer to facilitate in-plane motion of the fields 401, as well as certain portions of the TC111. In one embodiment, thermal actuators are used to perform said in-plane motion by appropriate heating and cooling of the flexure arms. Thermal actuation of the flexure arms can be created using an array of thermoelectric elements. In one embodiment, the thermoelectric elements are used to transfer heat to the flexures using an array of flexible pillars. Alternatively, the thermoelectric elements are used to transfer heat to the flexures using a thin, low-friction coefficient material (e.g., a thin film of polytetrafluoroethylene (PTFE), a thin film of thermally conductive paste, etc.). In another embodiment, thermal actuation of the flexure arm is performed using spatially modulated radiation that is absorbed by the flexure arm (e.g., such as by using one or more digital micromirror devices (DMDs)). In one embodiment, the piezoelectric transducers are areally placed around the field 401 (where they are arranged in a checkerboard configuration) to perform actuation in the plane of the field 401. In one embodiment, thermal actuation is performed in a timed manner, where actuation occurs at a specific time t after the initiation of thermal actuation. a and for duration Δt a The desired control is maintained throughout.

[0093] In one embodiment, an integrated mechanical actuator (described above) is used to correct one or more components of first order overlay error. In one embodiment, an integrated mechanical actuator (described above) is used to correct one or more components of higher order overlay error.

[0094] In one embodiment, the TC 111 incorporates a pressurizable region to create an arc in the field 401 immediately prior to binding. In one embodiment, the TC 111 incorporates a pressurizable region to actuate the field 401 in the z-axis.

[0095] In one embodiment, the TC111 incorporates one or more heat exchanger layers (such as, for example, heat exchanger layer 405) to transport excess heat or cold away from the TC111.

[0096] In one embodiment, the TC111 incorporates one or more layers incorporating flexures that are constrained to move in the z-axis. The flexures can have a range of motion of 10 μm or more. In one embodiment, the flexures are actuated using thermal, piezoelectric, and / or pneumatic actuators.

[0097] In one embodiment, the thickness change of the field 401 is actively sensed. In one embodiment, the thickness change of the field 401 is sensed using an air gauge.

[0098] In one embodiment, the TC 111 has an optically clear passageway to allow in situ metrology through the TC 111. In one embodiment, the TC 111 has an optically clear passageway for infrared radiation.

[0099] In one embodiment, one or more custom TCs 111 are used for every new field design, with the TC actuator grid (defined by an array of repeating actuator groups, where each actuator group is used to actuate a single field of default dimensions) matched to the field dimensions. In one embodiment, the custom TCs 111 can be replaced using a robotic arm and lift pins.

[0100] In one embodiment, the TC 111 with a fixed grid (corresponding to the default field dimensions) is adapted to assemble fields of various dimensions. An algorithm to achieve this is described below. Bounding region W∈R 2 is defined, which is the diameter d substrate It is possible that the circular a. Two tilings are defined: ○ T actuator is a set of tiles, each of which has a size (width actuator ,height actuator ) and T actuator tessellates W. T actuator The tiles in are translatable in X and Y as a group. ○ T field is a set of tiles, each of which has a size (width field ,height field ) and T field is supposed to tessellate W. For a given set of labels n, T field All tiles in the set of tiles that share a label are assigned to each field and T actuator The center-to-center distance between the tiles in the actuator -width field ) / 2, and along the Y axis (heightactuator -height field ) / 2. Such a labeling is field By first generating m0 random assignments of n labels to tiles in actuator ,height actuator The best label assignment is found by checking across all labels the maximum center-to-center distance for all fields belonging to the label by sliding the actuator tile a small fixed amount in the X and Y axes until an area of ​​100 kb is covered. A better label assignment is then produced using a heuristic optimizer (e.g., a genetic algorithm type minimizer), where label assignments are crossed over, mutated, and selected for the smallest of maximum center-to-center distances. A comprehensive heuristic optimizer is run, which minimizes the set of labels n.

[0101] One such labeling is shown in FIG. 7, which is discussed below.

[0102] FIG. 7 illustrates an exemplary labeling of a field 401 within a rectangular bounding area 701 that can be assembled using an actuator grid 702 using nine labels (nine assembly steps), according to an embodiment of the present invention.

[0103] In one embodiment, TC111 is held using a structural member in the form of a thin ring that contacts TC111 at an annular area that is etched into the side of TC111.

[0104] In one embodiment, the sacrificial layer etchant is delivered through TC111 through holes in etchant inactive parts of TC111. In one embodiment, the sacrificial layer etchant is delivered through parts of TC111 that are made from silicon.

[0105] The following discussion is based on Figure 8, which illustrates an exemplary process showing intermediate substrates used for assembly, according to an embodiment of the present invention. In one embodiment, a cascade of TCs 111 are used to transfer a field 401 from one source / intermediate / product substrate 103 / 801 / 105 to a different source / intermediate product substrate 103 / 801 / 105.

[0106] In one embodiment, a cascade of TCs 111 are used to transfer the fields from the source substrate 103 to the product substrate 105. One or more TCs 111 pick up a subset of the fields 401 from the source substrate 103 and transfer them (e.g., in a field-by-field manner) to the intermediate substrate 801 while ensuring that the pitch of the fields along the X-axis and the pitch of the fields along the Y-axis match the corresponding X-pitch and Y-pitch of the fields 401 in the product substrate 105. In one embodiment, one or more TCs 111 are used to flip the orientation of the subset of the fields 401 from the source substrate 103 or from one of the intermediate substrates 801 so that the correct side required for bonding faces the product substrate 105. In one embodiment, one or more TCs 111 perform overlay control and hybrid bonding for the subset of the fields 401 being assembled on the product substrate 105.

[0107] In another embodiment, a cascade of TCs 111 are used to transfer the fields 401 from the source substrate 103 to the product substrate 105. One or more TCs 111 pick up a subset of the fields 401 from the source substrate 103 and transfer them to the intermediate substrate 801 in a row-by-row manner, while ensuring that the pitch of the fields along the X-axis matches the pitch of the fields 401 on the product substrate 105. In one embodiment, one or more TCs 111 pick up a subset of the fields 401 from the intermediate substrate 801 and transfer them to a different intermediate substrate 801 in a row-by-row manner, while ensuring that the pitch of the fields along the Y-axis matches the pitch of the fields 401 on the product substrate 105. In one embodiment, one or more TCs 111 are used to flip the orientation of the subset of the fields 401 from the source substrate 103 or from one of the intermediate substrates 801 so that the correct side required for bonding faces the product substrate 105. In one embodiment, one or more TCs 111 perform overlay control and hybrid bonding for a subset of the fields 401 that are fabricated on the product substrate 105 .

[0108] In one embodiment, intermediate substrate 801 is made of silicon, silicon oxide, glass, polymer (such as polycarbonate), and / or sapphire. In one embodiment, intermediate substrate 801 has metrology marks embedded inside. In one embodiment, the metrology marks in intermediate substrate 801 are utilized to align the fields to a known, precise grid.

[0109] In one embodiment, the source substrate 103 is comprised of singulated fields on a dicing tape frame. In one embodiment, the intermediate substrate 801 is comprised of a glass substrate with embedded alignment marks. In one embodiment, the temporary bonding onto the intermediate substrate 801 is performed using an inkjetted UV-curable adhesive. Moreover, in one embodiment, the final bonding is performed between the fields 401 and the product substrate 105, which are attached to the intermediate substrate 801.

[0110] In one embodiment, the TC 111 is geometrically bounded by a cylinder having a diameter of 300 mm. In another embodiment, the TC 111 is geometrically bounded by a rectangular solid. In one embodiment, the TC 111 is geometrically bounded by a rectangular solid, two sides of which are greater than 300 mm.

[0111] 8, source substrate 103 (identified as "source substrate 2") includes fields 401 facing downward. Such fields 401 are transferred to intermediate substrate 801 by TC 111. In one embodiment, there is an embedded alignment grid 802 to help ensure that the pitch of the fields along the X-axis and the pitch of the fields along the Y-axis match the corresponding X-pitch and Y-pitch of the fields 401 in product substrate 105. In one embodiment, there is an optional variable density glue 803 dispensed to compensate for field thickness variations.

[0112] Additionally, Figure 8 illustrates an exemplary field 401 from a source substrate 103 (identified as "Source Substrate 1") that has already been assembled onto a product substrate 105, as shown via element 804. Moreover, Figure 8 illustrates that the product substrate 105 has optionally been plasma treated, such as, for example, immediately prior to assembly.

[0113] 8 illustrates an exemplary field 401 from a source substrate 103 (identified as "Source Substrate 2") above a product substrate 105 that is optionally being plasma processed, as shown via element 805. It is noted that field 401 faces upwards above the product substrate 105.

[0114] Such fields 401 of product substrate 105 are combined to form assembled product substrate 105, as shown via element 806.

[0115] Reference is now made to FIG. 9, which illustrates an exemplary illustration of multiple TCs 111 being used during assembly, according to an embodiment of the present invention.

[0116] 9, multiple TCs 111 are used in parallel to assemble a field represented as dies 901 on a source wafer 902. In one embodiment, each TC 111 is configured to pick up and assemble a single die 901. It is noted that each TC 111 can be actuated in the X-axis, Y-axis, and / or Z-axis and can have independently controllable pressure and vacuum supplies.

[0117] In one embodiment, multiple TCs 111 are used in parallel to assemble the field 401 (e.g., die 901), where each TC 111 is capable of picking up, overlapping, and bonding one or more fields 401. In one embodiment, multiple TCs 111 are used in parallel to assemble the field 401, where each TC 111 is capable of picking up, overlapping, and bonding one field.

[0118] Reference is now made to FIG. 10, which illustrates an exemplary reconfigurable grid TC111 (eg, 300 mm×300 mm) in accordance with an embodiment of the present invention.

[0119] As shown in FIG. 10, there is a pair of superimposed "base plates" 1001. These base plates 1001 are optionally unconnected, which facilitates independent X and Y extension. Additionally, as shown in FIG. 10, there is optionally a monolithically fabricated Y reconstruction array 1002. Links 1003 (shaded darker) lie in a different plane compared to lighter shaded links 1004. The X reconstruction array (not shown in FIG. 10) can be fabricated separately and optionally superimposed on top of the Y reconstruction array 1002.

[0120] Moreover, Figure 10 illustrates an example location 1005 for application of force to reconfigure the TC X-grid. Additionally, Figure 10 illustrates an example location 1006 for application of force to reconfigure the TC Y-grid.

[0121] Additionally, FIG. 10 illustrates a single actuation unit 1007 and also illustrates that a defective actuation unit 1008 can be individually replaced.

[0122] In one embodiment, a TC 111 with a reconfiguration actuation grid is used. In one embodiment, the reconfiguration mechanism is fabricated monolithically. In one embodiment, the reconfiguration arrangement is built by stacking one or more layers, each of which is fabricated monolithically. In one embodiment, the reconfiguration mechanism is fabricated using bulk metals, bulk polymers, thin coatings, etc., or any combination thereof. In one embodiment, the reconfiguration mechanism is fabricated using steel, stainless steel, chrome, etc., or any combination thereof. In one embodiment, the reconfiguration mechanism is composed of flexure elements. In one embodiment, the flexure elements are arranged to form a scissor mechanism between each pair of actuation units 1007. In one embodiment, separate reconfiguration mechanisms are utilized for expansion along the X and Y directions. These mechanisms can be stacked on top of each other. Each mechanism is actuable in one direction while being free to move in the orthogonal direction. In one embodiment, actuation of the reconfiguration mechanism is produced using actuators (e.g., voice coil motors, piezoelectric actuators, thermal actuators, etc.) located at one or more locations on or within the periphery of the reconfiguration mechanism. In one embodiment, the actuators are located on the axis of symmetry of the reconfiguration mechanism. In one embodiment, each actuation unit 1007 is moved in X and / or Y using one or more dedicated actuators. In one embodiment, a group of one or more actuation units is moved in X and / or Y using one or more groups of actuators. In one embodiment, the reconfiguration mechanism rests on fluid bearings. In one embodiment, the reconfiguration mechanism can be stepped and / or scanned across the associated substrate. In one embodiment, the reconfiguration grid is rectangular in shape, the shorter arm of which is smaller than the size of the source / product / intermediate substrate.In one embodiment, the reconstruction grid is in the shape of a single horizontal or vertical line of actuation units.

[0123] In one embodiment, the TC actuation units 1007 are mounted on a plate such that the pitch of the actuation units 1007 is an integer multiple of the field pitch on the source / product / intermediate substrate 103 / 105 / 801. The plate can be custom-made for each new field layout. The plate can have recesses (or slots) for positioning the actuation units 1007. In one embodiment, the plate can be mounted on the X-axis, Y-axis, Z-axis, θ X axis, θ Y axis and / or θ Z It has alignment features (e.g., pins) for aligning the actuation unit 1007 in the axis. In one embodiment, the actuation unit 1007 is attached to the plate using adhesive, a flexure-based snap-in mechanism, magnets, electromagnets, vacuum, etc., or any combination thereof.

[0124] 11A-11B, which illustrate an exemplary TC 111 with closed boundary vacuum and / or pressure regions, in accordance with an embodiment of the present invention. FIGURES 12A-12B illustrate an alternative embodiment of the exemplary TC 111 with closed boundary vacuum and / or pressure regions, in accordance with an embodiment of the present invention. FIGURES 13A-13C illustrate a further alternative embodiment of the exemplary TC 111 with closed boundary vacuum and / or pressure regions, in accordance with an embodiment of the present invention.

[0125] As shown in Figure 11A, there is a grid of TCs 111 represented by a TC assembly 1101 (identified as "ATC"). As further shown in Figure 11A, there is an optional porous filter membrane 1102 for filtering particles in the air stream so that they do not reach the ATC (TC assembly) field interface. Additionally, as shown in Figure 11A, there are holes 1103 in the filter membrane 1102 for vacuum and / or pressure.

[0126] Additionally, as shown in Figure 11A, there are pins 1104 that are used to hold the field 401. In one embodiment, such pins 1104 can optionally be tapered at their base to reduce the contact area with the field 401.

[0127] Figure 11B illustrates the actual contact edges between the ATC 1101 and the field 401 at element 1105. Additionally, Figure 11B illustrates an optional material 1106 for plugging the vacuum holes. For example, such material 1106 can be inkjetted.

[0128] As shown in Figure 12A, there is an optional porous filter membrane 1102 to filter particles in the air stream so that they do not reach the ATC (assembly of the TC) field interface. Additionally, as shown in Figure 12A, there are holes 1103 in the filter membrane 1102 for vacuum and / or pressure to run through the thickness of the ATC 1101.

[0129] 12A, there are pins 1104 that are used to hold the field 401. In one embodiment, such pins 1104 can optionally be tapered at their base to reduce the contact area with the field 401.

[0130] Additionally, as shown in Figure 12A, a plugging material 1201 is dispensed and / or deposited on the ATC 1101. This can prevent contamination of the ATC field interface by such plugging material 1201.

[0131] Moreover, as shown in FIG. 12A, the ATC subcomponents 1202 (eg, thermal actuators, X / Y / Z flexures, valve units, etc.) are positioned on the periphery of the vacuum / pressure hole 1103.

[0132] FIG. 12B illustrates the actual contact edge between the ATC 1101 and the field 401 at element 1105.

[0133] As shown in FIG. 13A, the top part 1301 of TC111, in one embodiment, can be attached to the bottom part using vacuum suction and can be detached to cover the holes using an inkjet.

[0134] In one embodiment, the bottom part 1302 of the TC 111 (in contact with the picked die) remains fixed. Moreover, Figure 13A illustrates holes 1103 for the vacuum and pins 1104 for holding the field 401. In one embodiment, such pins 1104 can optionally be tapered at their base to reduce the contact area with the field 401.

[0135] Additionally, Figure 13A illustrates an optional porous filter membrane 1303 for filtering particles in the air stream so that they do not reach the TC field interface. In one embodiment, the porous filter membrane 1303 is fabricated from porous silicon with sub-100 nm pore sizes, making it act as an effective medium. Alternatively, an array of normally closed silicon cantilevers can be used to fabricate the porous filter membrane 1303.

[0136] In one embodiment, the top part 1301 of the TC 111 can be returned to its default unclogged state using piranha cleaning, UV-based cleaning, etc. If the cleaning process is slow, multiple TCs 111 can be used.

[0137] 13B illustrates an inkjet 1304 dispensing UV-curable adhesive into a cone-shaped hole 1103. In one embodiment, the droplet is allowed to rest steadily on the top of the cone to minimize surface area.

[0138] FIG. 13C illustrates that the vacuum holes 1103 have been plugged, as shown at element 1305.

[0139] 11A-11B, 12A-12B, and 13A-13C, in one embodiment, the TC 1101 has a closed boundary vacuum and / or pressure region (as opposed to the conventional open boundary vacuum region in a semiconductor pin chuck). The pin 1104 can have a tapered cross section to reduce the contact area between the TC 111 and the picked field 401. The tapering can be created using an etching technique including crystallographic etching, isotropic etching, anisotropic etching (e.g., reactive ion etching), etc., and any combination thereof. In one embodiment, the vacuum and / or pressure in the closed boundary regions are switched on and off by plugging them with the plugging material 1201. The plugging can be performed using an inkjet. Alternatively, a masked plasma-based deposition process can be used to deposit the plugging material 1201. In one embodiment, the plugging is performed using a mixture of a volatile liquid and an oxide of the SiLK type. The pore size of the porous oxide (left after evaporation of the volatile components) can be optimized to minimize air flow through the oxide. The plugging material 1201 can be subsequently removed by a plasma jet, a chemical etchant (e.g., vapor HF), heating the TC111 back to its default state (evaporating the plugging material), and the like, and any combination thereof. In one embodiment, the field size (X and / or Y) is constrained to be an integer multiple of the pitch of the TC pins 1104. In one embodiment, the plugging material dispenser is part of the pick-and-place tool. The TC111 can also contain an optional porous membrane 1102, as shown in FIG. 11A and FIG. 12A, to limit particle contamination from one part of the TC111 to another.In one embodiment, the porous membrane 1102 can be made of transparent (e.g., in IR radiation), porous polymer, porous silicon, etc., or any combination thereof. The pore size of the porous membrane 1102 can be optimized to minimize airflow restriction while contaminants are filtered out. Alternatively, normally closed arrays of micromachined cantilevers placed above each vacuum / pressure hole 1103 can be used for contaminant filtration. These can be made of silicon, silicon oxide, transparent polymer, etc., or any combination thereof. Optionally, the vacuum and / or pressure holes 1103 can have (partially or entirely) a cone-shaped geometry, such that the adhesive dispensed is in a suitable stationary spot at the apex of the cone-shaped geometry. For example, the cone-shaped geometry can be constructed using crystallographic etching.

[0140] In one embodiment, the suction generating layer on top of the TC 111 (that touches the picked fields) can be custom fabricated to match the grid of the picked fields 401. The custom suction generating layer can be attached to the rest of the TC 111 using vacuum suction, adhesive, electrostatic forces, magnetic forces, electromagnetic forces, etc., or any combination thereof.

[0141] In one embodiment, a plasma producing unit (such as, for example, plasma unit 110) is utilized to clean the bonding surfaces immediately prior to bonding.

[0142] In one embodiment, the plasma production units (such as, for example, plasma unit 110) operate at atmospheric pressure. In one embodiment, such plasma production units are produced by Surfx® technology.

[0143] In one embodiment, a plasma unit (such as, for example, plasma unit 110) covers the entire area of ​​the source / product / intermediate substrate 103 / 105, 801.

[0144] In one embodiment, a plasma unit (such as, for example, plasma unit 110) is scanned across an area of ​​the source / product / intermediate substrate 103 / 105 / 801. The plasma unit (such as, for example, plasma unit 110) can be mounted on a motion stage that can progress along the X-axis, the Y-axis, and / or the Z-axis. In one embodiment, the plasma unit (such as, for example, plasma unit 110) is mounted on a retractable plate that retracts out of the way of field 401 once plasma processing is completed.

[0145] In one embodiment, the plasma unit (such as, for example, plasma unit 110) faces upwards to treat a downward field 401.

[0146] In one embodiment, the plasma unit (such as, for example, plasma unit 110) faces downward to treat an upwardly directed field 401.

[0147] In one embodiment, the upward and downward plasma heads are synchronized such that the downward unit processes the upward field 401 when the upward unit processes the downward field 401.

[0148] In one embodiment, multiple source / product / intermediate substrates 103 / 105 / 801 are plasma processed in separate chambers of an n-MASC tool.

[0149] Reference is now made to FIG. 14, which illustrates an exemplary sensor arrangement for an exemplary weigh module 108, in accordance with an embodiment of the present invention.

[0150] 14, the metering module 108 includes an exemplary single interchangeable unit of imager 1401. In one embodiment, the metering module 108 has a total of about 30 such units. In one embodiment, the image sensor 1401 can have non-photosensitive areas surrounding a photosensitive area.

[0151] Moreover, as shown in Figure 14, the weighing module 108 has an exemplary single "line" of imagers 1402. In one embodiment, the weighing module 108 has approximately 2.5 total lines of imagers. Additionally, Figure 14 illustrates an exemplary scanning-based approach for acquiring X and Y alignment data for every field 401 picked by the TC 111.

[0152] In one embodiment, the metrology module 108 accommodates a full reconfigurable array of imagers 1401, which is 300 mm by 300 mm.

[0153] In one embodiment, the exemplary field 401 has a horizontal length of 25 mm and a vertical length of 30 mm. In one embodiment, the field 401 has up to eight total alignment marks (four for X alignment and four for Y alignment). Additionally, the field 401 can have alignment marks at layer 0 or at the half-kerf.

[0154] In one embodiment, the imager 1401 consists of a short wave infrared (SWIR) sensor (e.g., Sony® IMX990-AABJ-C). In one embodiment, there are approximately 130 such sensors in the weighing module 108.

[0155] In one embodiment, an exemplary Y scan for the weigh module 108 travels approximately 300 mm. In one embodiment, an exemplary X scan for the weigh module 108 travels approximately 190 mm.

[0156] Reference is now made to FIG. 15, which illustrates an alternative exemplary sensor arrangement for an exemplary weigh module 108, in accordance with an embodiment of the present invention.

[0157] 15, the weighing module 108 includes an exemplary single interchangeable unit of an imager 1401. In one embodiment, the weighing module 108 has a total of about 12 such units.

[0158] Moreover, as shown in Figure 15, the weighing module 108 has an exemplary single "line" of imagers 1402. In one embodiment, the weighing module 108 has only one line of imagers.

[0159] In one embodiment, an exemplary Y-scan for the weigh module 108 travels approximately 500 mm. In one embodiment, an exemplary X-scan for the weigh module 108 travels approximately 3×190 mm (i.e., performing an X-scan of the weigh module 108 traveling 190 mm in three separate instances).

[0160] FIG. 16 illustrates an exemplary reconfiguration grid sensor arrangement for an exemplary weighing module 108, in accordance with an embodiment of the present invention.

[0161] 16, there is optionally a pair of stacked "base plates" 1601. These base plates 1601 are optionally unconnected, which facilitates independent X and Y expansion.

[0162] Additionally, as shown in Fig. 16, there is optionally a monolithically fabricated Y reconstruction array 1602. Links 1603 (shaded darker) lie in a different plane compared to lighter shaded links 1604. An X reconstruction array (not shown in Fig. 16) can be fabricated separately and optionally overlaid on top of the Y reconstruction array 1602.

[0163] Moreover, Figure 16 illustrates an example location 1605 for application of a force to reconfigure the imager X-grid. Additionally, Figure 16 illustrates an example location 1606 for application of a force to reconfigure the imager Y-grid.

[0164] Additionally, FIG. 16 illustrates that defective imagers 1401 can be individually replaced.

[0165] In one embodiment, the exemplary field 401 has a horizontal length of 20 mm and a vertical length of 20 mm. In one embodiment, the field 401 has a maximum of eight total alignment marks (four for X alignment and four for Y alignment).

[0166] In one embodiment, the imager 1401 consists of a short wave infrared (SWIR) sensor (e.g., Sony® IMX990-AABJ-C). In one embodiment, there are about 20 such sensors in the weighing module 108.

[0167] In one embodiment, the metrology module 108 accommodates a full reconfigurable array of imagers 1401, which is 300 mm by 300 mm.

[0168] Reference is now made to FIG. 17, which illustrates the reconstructed grid sensor arrangement shown in FIG. 16 enlarged to capture a 30 mm×3 mm field, in accordance with an embodiment of the present invention.

[0169] Figure 17 illustrates an exemplary location 1701 for application of force to reconfigure the imager X-grid. Additionally, Figure 17 illustrates an exemplary location 1702 for application of force to reconfigure the imager Y-grid.

[0170] Additionally, FIG. 17 illustrates an X reconstruction array 1703 superimposed on a Y reconstruction array (not shown in FIG. 17).

[0171] 18A-18D, which illustrate an exemplary alignment metrology framework for an exemplary metrology module 108, in accordance with an embodiment of the present invention.

[0172] As shown in Figure 18A, such a framework includes a top view of a SWIR imager subassembly 1801 that includes the photosensitive area 1802 of a SWIR sensor. In one embodiment, both coarse (box-in-box type) and fine (moire) alignment marks are captured by the same imager and optics. In one embodiment, 1x magnification optics are implemented. In one embodiment, reflective moire is utilized.

[0173] Additionally, telecentric focusing optics 1803 are utilized. In one embodiment, such optics 1803 includes a numerical aperture of about 0.2, a resolution at 1.4 μm of about 4.2 μm, a depth of field at 1.4 μm of about 20 μm, and a magnification of 1×.

[0174] Additionally, FIG. 18A illustrates a staggered sensor design 1804, which ensures that back-reflected light from the 0th and 1st orders does not end up contaminating neighboring imagers.

[0175] FIG. 18B illustrates a cross-sectional view of a staggered sensor design, such as a portion of ATC 1101 containing alignment marks and a portion of field 401 containing alignment marks.

[0176] Figure 18C illustrates a top view of a staggered sensor design composed of two counter-propagating moire marks 1805. In one embodiment, the total height is approximately 20 μm.

[0177] Additionally, FIG. 18C illustrates an imaging-based mark 1806 (e.g., in a picked field 1807) and also illustrates an improved kerf (approximately 5 μm) at 1808, where the standard kerf is approximately 60 μm at 1809.

[0178] If the alignment marks are patterned on layer 0 or in the inter-die kerf (in the case where an entire field consisting of multiple dies is being picked up), the full kerf width could potentially be available to generate the alignment marks.

[0179] Alternatively, MAC-based dicing techniques can be used to produce thick micrometer-scale kerf cuts with sharp corners, which can allow most of the previously unavailable kerf area to be used for alignment mark placement.

[0180] FIG. 18D illustrates a normally-back-diffracting moiré metric. As shown in FIG. 18D, incident light 1810 is reflected off a moiré grating 1811. To ensure that the first order returns along the grating normal towards the SWIR sensor, the following grating equation is satisfied: sin(θ1) = sin(2θ i ) = sin(θ i ) + λ / ρ.

[0181] The detection precision using imaging-based marks (assuming 5 μm SWIR pixel pitch and 1 / 10 sub-pixel detection) is approximately 0.5 μm. However, the detection precision using moire marks (ρ1, ρ2 = 3, 3.05 μm, assuming 1 / 10 sub-pixel detection) is approximately 8 nm. Moreover, the moire phase-unambiguous capture range is approximately 1.5 μm.

[0182] 19A-19C illustrate an alternative exemplary alignment metrology framework for an exemplary metrology module 108, according to an embodiment of the present invention.

[0183] 19A illustrates a top view of the SWIR imager subassembly 1901, including the SWIR sensor photosensitive area 1902. In one embodiment, 1× magnification optics are implemented. In one embodiment, reflective imaging is utilized.

[0184] Additionally, Figure 19A illustrates focusing optics 1903. In one embodiment, such optics 1903 includes a numerical aperture of about 0.5, a resolution at 1.4 μm of about 1.8 μm, a depth of field at 1.4 μm of about 3.6 μm, and a magnification of 1×.

[0185] Additionally, FIG. 19A illustrates that focusing optics 1903 includes an IR LED and focusing optics 1904 .

[0186] FIG. 19B illustrates a cross section of the metrology plane, which includes a portion of the ATC 1101 containing alignment marks and a portion of the field 401 containing alignment marks.

[0187] FIG. 19C illustrates a top view of a metrology plane composed of two counter-propagating moiré marks 1905.

[0188] Additionally, FIG. 19C illustrates an imaging-based mark 1906 (e.g., in a picked field 1907) and also illustrates an improved kerf (approximately 5 μm) at 1908, where the standard kerf is approximately 60 μm at 1909.

[0189] If the alignment marks are patterned on layer 0 or in the inter-die kerf (in the case where an entire field consisting of multiple dies is being picked up), the full kerf width could potentially be available to generate the alignment marks.

[0190] Alternatively, MAC-based dicing techniques can be used to produce thick micrometer-scale kerf cuts with sharp corners, which can allow most of the previously unavailable kerf area to be used for alignment mark placement.

[0191] Moreover, in such an embodiment, the detection precision using imaging-based marks (assuming 1 μm SWIR pixel pitch and 1 / 20 sub-pixel detection) is approximately 90 nm.

[0192] 20A-20C illustrate details regarding an exemplary weighing module 108, according to an embodiment of the present invention.

[0193] Fig. 20A illustrates a flow-based cooler 2001 for the SWIR sensor and LEDs. Additionally, Fig. 20A illustrates a custom 300 mm thermally conductive PCB substrate 213 for the IR sensor and LED array. Additionally, Fig. 20A illustrates the PCB traces and heat exchanger fluid harness 2002.

[0194] FIG. 20B illustrates that the SWIR LED 2003 and SWIR sensor 2004 are integrated directly onto a custom PCB 213. Additionally, FIG. 20B illustrates a machined metal frame 2005, which acts as an LED / sensor enclosure. Additionally, FIG. 20B illustrates a flat lens 2006 forming a magnifying telecentric pair micromachined onto a 300 mm glass substrate. Additionally, FIG. 20B illustrates off-axis LED focusing optics 2007 and a moiré plane 2008.

[0195] FIG. 20C illustrates a close-up view of the ATC 1101 along the moiré plane 2008. As shown in FIG. 20C, the incident light 2009 is reflected off of the moiré grating 2010. In order for the first order to return along the grating normal towards the SWIR sensor, the following grating equation will be satisfied: sin(θ1) = sin(2θ i ) = sin(θ i For example, for an incident wavelength of 1.4 μm and a grating pitch of 5 μm, the incident angle θ that satisfies the above condition is approximately 18 degrees.

[0196] FIG. 21 illustrates an exemplary metering framework, according to an embodiment of the present invention.

[0197] Referring to Fig. 21, Fig. 21 illustrates alignment measurement between ATC 1101 and picked field (using MM 108) via element 2101. Moreover, Fig. 21 illustrates global alignment 2102 between ATC 1101 and product wafer 105. Additionally, Fig. 21 illustrates product substrate 105 with layer 1 already assembled and product substrate chuck 104 for holding product substrate 105.

[0198] Moreover, FIG. 21 illustrates that the alignment of field 401 on product wafer 105 may potentially be pre-characterized outside of MM tool 108 (see element 2103).

[0199] It is noted that Figure 21 merely shows a bounding box for the MM 108. The actual MM assembly may be within this bounding box.

[0200] Figure 22 illustrates an exemplary field 401 containing a 2x2 array of dies 2201, in accordance with an embodiment of the present invention. Additionally, Figure 22 illustrates alignment mark locations 2202.

[0201] FIG. 23 illustrates an exemplary metering framework, according to an embodiment of the present invention.

[0202] As shown in Fig. 23, the imager 2301 (e.g., a SWIR sensor) includes a reflective blazed grating 2302. Additionally, as shown in Fig. 23, the metrology framework can include focusing optics 2303 for focusing light from a light source 2304 (e.g., an LED) onto an opaque enclosure wall 2305 on the transparent PCB 213.

[0203] Additionally, as shown in FIG. 26, a Littrow angle 2306 is formed from the reflected light at the Moire plane 2008.

[0204] FIG. 24 illustrates another embodiment of an exemplary metering framework, in accordance with an embodiment of the present invention.

[0205] As shown in FIG. 24, the integer assembly 2401 consists of a light source 2402 (eg, an LED) with focusing optics 2403 for focusing the light emanating from the light source 2402 onto the ATC 1101 .

[0206] In one embodiment, diffractive elements at locations identified by elements 2404 couple light into and out of the light guide at specific angles. Photonic light guide 2405 patterned into ATC1101 can be fabricated into a custom layer that is attached to the rest of the ATC1101 using adhesives, vacuum, electromagnetic forces, magnetic forces, electrostatic forces, etc., or any combination thereof.

[0207] In one embodiment, the photonic light guide 2405 guides light onto a picked field 2406 above the ATC 1101 in the moiré plane 2008 .

[0208] FIG. 25 illustrates a further embodiment of an exemplary metering framework, in accordance with an embodiment of the present invention.

[0209] Referring to FIG. 25, FIG. 25 illustrates a series of diffractive elements 2501 for guiding light from a light source to an alignment mark.

[0210] 14-17, 18A-18D, 19A-19C, 20A-20C, and 21-25, in one embodiment, the metrology module 108 is used to measure overlay, alignment, in-plane, and / or out-of-plane distortion errors of picked fields 401, TC 111, source substrate 103, intermediate substrate 801, and / or product substrate 105. In one embodiment, the metrology module 108 is used to measure overlay of the fields 401 immediately prior to assembly onto the product substrate 105. In one embodiment, the metrology module 108 is used to measure in-plane distortion of one or more fields 401 on the source substrate 103, intermediate substrate 801, and / or product substrate 105.

[0211] In one embodiment, the weighing module 108 performs measurements for all fields 401 on the TC 111 simultaneously.

[0212] In one embodiment, the metering module 108 incorporates one or more imager units 1401. In one embodiment, the imager units 1401 are sensitive to visible radiation, infrared radiation, short-wave infrared radiation (SWIR), or the like.

[0213] In one embodiment, one or more light sources 2402 are used to illuminate the metrology target. In one embodiment, the light sources 2402 incorporate light emitting diodes (LEDs), laser diodes, fiber guided light sources, vertical-cavity surface-emitting lasers (VCSELs), etc., or any combination thereof. Alternatively, edge lighting can be used as the light source 2402 for metrology, where light is injected from the side of the edge lighting substrate and transported to the relevant area using, for example, photonic crystal based light guiding. In one embodiment, the light source 2402 is mounted on a printed circuit board. In one embodiment, the light source 2402 is mounted adjacent to the imager unit 1401. In one embodiment, the light source 2402 directs light towards the metrology target at a predefined angle using an off-axis lens. Alternatively, the light source 2402 directs light towards the metrology target at a predefined angle using one or more mirrors. The mirror assembly can be constructed using a reflective blazed grating. The blazed grating can be coated with a metal. The blazed grating can be fabricated on silicon, sapphire, silicon oxide, glass, and / or polymer substrates. In one embodiment, the light from the light source 2402 is incident at a Littrow angle 2306. In another embodiment, the light from the light source 2402 is incident at an angle such that one of the first diffracted orders from the metrology mark is directed back toward the imager 1401 along the field normal direction.

[0214] In one embodiment, the imager unit 1401 is mounted on a printed circuit board. In one embodiment, the light source 2402 is mounted on the printed circuit board. In one embodiment, the imager unit 1401 and the light source 2402 are mounted together on the printed circuit board. In one embodiment, the light source 2402 and the imager unit 1401, which are mounted on the printed circuit board, are optically isolated using a dark machined frame. In one embodiment, the printed circuit board is thermally conductive.

[0215] In one embodiment, an array of lenses patterned on a silicon, sapphire, glass, silicon oxide, and / or polymer substrate is utilized to direct light from the light source 2402 onto the metrology marks and focus the light from the metrology marks onto the imager array. In one embodiment, the lens array incorporates annular lenticular regions etched into the lens array substrate. In one embodiment, the lens array incorporates a group of concentric metal annuli. Alternatively, the lens array incorporates a metalens, which is made from an etched substrate, a metal, and a high refractive index material (such as titanium oxide). In one embodiment, the lens array forms a telecentric couple to focus the light onto the imager array.

[0216] In one embodiment, the metrology scheme is based on the principle of moiré-based spatial phase sensing. In one embodiment, the metrology scheme is based on on-axis moiré metrology. In one embodiment, the metrology scheme is based on circular moiré metrology. In one embodiment, a purely imaging-based metrology is utilized (e.g., box-in-box alignment mark metrology). In one embodiment, a focus variation system is utilized to maintain focus in two or more different planes during metrology. The focus variation can be achieved, for example, using a zoom lens. In one embodiment, one or more of the methods described in this paragraph are utilized simultaneously.

[0217] In one embodiment, metrology is performed in reflection mode, where the light source 2402 is on the same side of the metrology mark as the imager unit 1401. In another embodiment, metrology is performed in transmission mode, where the light source 2402 is on the opposite side of the imager unit 1401.

[0218] In one embodiment, the metering scheme uses visible light. In one embodiment, the metering scheme uses infrared light.

[0219] In one embodiment, non-magnifying optics are used to view substrate areas larger than the size of the imager unit 1401. In another embodiment, magnifying optics are used to view substrate areas smaller than the size of the imager unit 1401. In one embodiment, a sub-pixel edge detection technique is used to detect edges in the metrology signal.

[0220] In one embodiment, the weighing module 108 is mounted on a motion stage that moves in the X, Y, and / or Z axes. In one embodiment, the weighing module 108 captures information from all fields currently being constructed by stepping and / or scanning an appropriate amount along the X, Y, and / or Z axes.

[0221] In one embodiment, the metrology marks are located near one or more corners of the field 401 being assembled. The field 401 can be free of circuit elements in layers above and below the metrology marks. In one embodiment, the metrology marks are located in a kerf area of ​​the field 401. In one embodiment, the field 401 is comprised of two or more dies, each of which is separated from one another by a kerf area, with the inter-die kerf area containing one or more alignment marks.

[0222] In one embodiment, metrology is performed in real-time as the field 401 is being bonded onto the product substrate 105. In another embodiment, metrology is performed before bonding occurs. In one embodiment, a feed-forward model is utilized to correct for repeatable components of the field distortion.

[0223] In one embodiment, the metrology module 108 measures the alignment between the fields 401 picked up by the TC 111, where the TC 111 has embedded alignment marks that match the field grid. The metrology module 108 can then align the TC 111 to the product substrate 105 using metrology marks installed near the edge and / or kerf regions of the TC 111 and the product substrate 105. In one embodiment, real-time topography mapping of the picked fields 401 and the product substrate 105 is performed, and predicted errors are compensated for by overlay control actuators (e.g., thermal actuators). In one embodiment, a single topography measurement is performed for each field 401. The topography mapping can be performed using (for example) air gauges. An array of air gauges can be mounted next to the PCB 213, for example. Also, if the PCB 213 heats the product board 105 and picked field 401 too much, air curtains can be used to cool them.

[0224] In one embodiment, an on-axis alignment method is used in the weighing module 108.

[0225] In one embodiment, the TC 111 has a grating mounted and / or patterned on it to track XY displacement with high precision.

[0226] In one embodiment, the alignment marks are placed in the half kerf region above field 401 (as shown in Figures 18C and 19C). As an alternative to patterning the alignment marks inside half the kerf (or half kerf), a MACE-based dicing process can be used to allow for alignment marks in the full kerf region. In one embodiment, the alignment marks are placed in the metal 0 (M0) layer above field 401.

[0227] In one embodiment, a very large sensor is used for alignment detection in the weigh module 108.

[0228] In one embodiment, photonic crystal based light guiding techniques are used to illuminate the alignment marks at the correct angle and location.

[0229] In one embodiment, local data processors are associated with and located in close proximity to one or more of the image sensors 1401. These data processors can be used to perform sensor local image processing. In one embodiment, the data processing is fabricated as part of the image sensor 1401 (in-sensor computer).

[0230] In one embodiment, a fixed grid of image sensors 1401 is used. In one embodiment, the image sensors 1401 are arranged in a linear array, a staircase type array, or a combination of the two. In one embodiment, the image sensors 1401 are arranged such that the area of ​​the substrate captured by one of the sensors overlaps with the area of ​​the substrate captured by the next closest image sensor 1401, such that the entire array of sensors captures a continuous and uninterrupted wide area of ​​the substrate. In one embodiment, the image sensor 1401 contains a photosensitive area surrounding a non-photosensitive area. In one embodiment, the light source 2402 is mounted in this non-photosensitive area, at an angle if required, and is enclosed on the sides in an opaque covering (to prevent contamination of the sensor by stray light). Light from the light source 2402 is passed through focusing optics 2303 and incident towards the metrology plane. The light source 2402 is designed such that the beam depth (along the Z axis) is the same as the depth of the image sensor 1401. When the incident light lands on the superimposed metrology marks, the light is reflected towards the image sensor 1401 in a direction normal to the substrate. The light incident towards the image sensor 1401 from the metrology mark plane is focused onto the sensor using low numerical aperture optics with a magnification of 1×. The sensor array is scanned in the X direction (see FIGS. 14 and 15) to collect (for example) Y overlay data for the entire substrate. A second sensor array (that is orthogonal to the first sensor array) is used to collect (for example) X overlay data for the entire substrate. Alternatively, the same sensor array, when used for Y overlay data collection, can be used to collect X overlay data as well, by scanning in a serpentine manner, by stepping to a new location, and by scanning in a serpentine manner again (see FIGS. 14 and 15).

[0231] In one embodiment, a reconfiguration arrangement of the image sensor 1401 is used. In one embodiment, the reconfiguration arrangement is monolithically fabricated. In one embodiment, the reconfiguration arrangement is constructed by stacking one or more layers, each of which is monolithically fabricated. In one embodiment, the reconfiguration arrangement is fabricated using bulk metals, bulk polymers, thin coatings, etc. In one embodiment, the reconfiguration arrangement is fabricated using steel, stainless steel, chrome, etc. In one embodiment, the reconfiguration arrangement is composed of flexure elements. In one embodiment, the flexure elements are arranged to form a scissor mechanism between each pair of image sensors. In one embodiment, separate reconfiguration arrangements are utilized for reconfiguration along the X and Y directions. These arrangements can be stacked on top of each other. Each arrangement is actuable in one direction while being free to move in the orthogonal direction. In one embodiment, actuation of the reconfiguration arrangement is produced using actuators (e.g., voice coil motors, piezoelectric actuators, thermal actuators, etc.) located at one or more locations on or within the periphery of the reconfiguration arrangement. In one embodiment, the actuators are placed on the axis of symmetry of the reconfiguration arrangement. In one embodiment, each sensor is moved in the X and / or Y directions using one or more dedicated actuators. In one embodiment, groups of sensors are moved in the X and / or Y directions using groups of actuators. In one embodiment, the reconfiguration arrangement rests on a fluid bearing. In one embodiment, the reconfiguration arrangement can be stepped and / or scanned across the TC 111. In one embodiment, the reconfiguration arrangement is in the shape of a rectangle whose shorter arm is smaller than the size of the source / product / intermediate substrate 103 / 105 / 801. In one embodiment, the reconfiguration arrangement is in the shape of a single horizontal or vertical line of sensors.

[0232] In one embodiment, the image sensor 1401 is mounted on a plate such that the pitch of the image sensor 1401 is an integer multiple of the field pitch on the TC / source / product / intermediate substrate (111 / 103 / 105 / 801). The plate can be custom-made for each new field layout. The plate can have recesses (or slots) to position the image sensor 1401. The plate can be aligned along the X, Y, Z, θ axes. X axis, θ Y axis and / or θ Z It may have alignment features (e.g., pins 1104) to align the image sensor 1401 in axis. The image sensor 1401 is attached to the plate using adhesive, a flexure-based snap-in mechanism, magnets, electromagnets, vacuum, etc.

[0233] In one embodiment, the weigh module 108 is separated from the rest of the pick and place tool using a transparent window. In one embodiment, the weigh module 108 is installed behind a transparent window such that there is no mass transfer between the weigh module 108 and the rest of the pick and place tool. In one embodiment, the weigh module 108 is installed in a sealed chamber with a transparent window facing the TC 111. In one embodiment, the sealed chamber has a door to remove and / or insert the weigh module 108.

[0234] In one embodiment, the topography (and alignment of the field 401 to a known grid) on the product substrate 105 is measured prior to attachment of the picked field 401 onto one or more intermediate substrates. In one embodiment, the topography (and alignment of the picked field 401 to a known grid) of the picked field 401 on the TC 111 is measured prior to attachment of the field 401 onto one or more intermediate substrates. In one embodiment, the measured topography and alignment information for the picked field 401 on the product substrate 105 and the TC 111 is utilized to actuate the picked field 401 to partially or fully compensate for the overlay error that would result if the final bonding step (bonding from intermediate substrate to product substrate) onto the product substrate 105 was not compensated. Prediction of the overlay error based on the topography and alignment data can be performed using mechanical modeling techniques. In one embodiment, the temperature of the field 401 above the TC 111 and the temperature of the product substrate 105 are maintained within a small window (e.g., 10 mK). In one embodiment, a single topography measurement is performed for each field 401 above the TC 111 and the product substrate 105. Topography mapping can be performed using (for example) an air gauge.

[0235] In one embodiment, a group of image sensors 1401 (consisting of one or more image sensors 1401) uses a dedicated and / or local data processor to process all or a portion of an image processing pipeline used to determine metrology outputs (e.g., overlay, alignment, topography, etc.) from the captured images. In one embodiment, the data processor is a single board computer.

[0236] In one embodiment, a custom light path (that transports the light incident from the light source 2402 to an ideal location for projection onto the alignment marks) is patterned into the TC111. In one embodiment, the light path is created in a custom layer that is attached to the rest of the TC111. In one embodiment, the attachment is performed using adhesives, vacuum, electromagnetic forces, magnetic forces, electrostatic forces, etc. In one embodiment, the light path is composed of only transmissive and reflective diffractive structures. In one embodiment, the light path is generated using nanoimprint lithography (NIL). In one embodiment, the light path is composed of repeating standardized sections that can be patterned using a limited number of fixed masks or reticles.

[0237] A bulk HF etcher is used to generate tethers in the sacrificial layer of one or more source substrates.

[0238] In one embodiment, the substrates are positioned horizontally on a multi-substrate chuck, while in another embodiment, the substrates are positioned vertically on a multi-substrate rack.

[0239] In one embodiment, in situ metrology for endpoint and uniformity measurements is performed for one or more of the substrates being etched.

[0240] A stocker unit can be used to store multiple (fully and partially populated) source / product / intermediate substrates 103 / 105 / 801. The stocker unit can be used to store TC units 111 and metering units 108 as well. In one embodiment, the TCs 111 can have fields 401 attached to them. In one embodiment, the stocker unit has a dedicated vacuum source with emergency power backup to provide vacuum to the stored TCs 111.

[0241] In one embodiment, the storage unit has temperature and humidity control.

[0242] In one embodiment, a single or multiple robot handler units may be used to move individual substrates, groups of substrates, TC111, metrology unit 108, etc. between various parts of the n-MASC tool.

[0243] 26A-B, which illustrate an exemplary known-bad-die replacement chuck (KRC) 2601, in accordance with an embodiment of the present invention.

[0244] As shown in FIG. 26A, a buffer substrate 2602 is populated with known good die 2603, where the buffer substrate 2602 is held by a buffer substrate chuck 2604.

[0245] Moreover, as shown in FIG. 26A, known bad die 2605 is replaced with a known good die (such as, for example, known good die 2603) on the source substrate 103.

[0246] 26B is a close-up view of a cross section of the precision module frame 106, illustrating an exemplary manner of loading and unloading the KRC 2601 using a robotic arm 2606 that mounts on the periphery of the KRC 2601. It is noted that the TC 111 can be loaded and unloaded in the same manner.

[0247] Additionally, FIG. 26B illustrates a voice coil post 2607 (a post to the voice coil 109) and a pin lift 2608.

[0248] Further discussion regarding Figures 26A-26B is provided below.

[0249] A known bad die replacement chuck (KRC) 2601 is used to replace a known bad die (KBD) 2605 with a known good die (KGD) 2603. One or more buffer substrates 2604 are used as a source of KGD 2603. The KRC 2601 can replace the KBD 2605 on one or more of the source / intermediate / product substrates 103 / 108 / 105. The design of the KRC 2601 can be similar to the TC 111 in its ability to chuck the field 401, its ability to sense and correct overlay, its ability to maintain thermal stability, etc.

[0250] In one embodiment, the KRC 2601 replaces the KBDs 2605 on the source substrate 103. The KBDs 2605 are selectively released from the source substrate 103 using, for example, localized UV exposure of a UV release adhesive, and replaced by KGDs 2603 using the KRC 2601. In one embodiment, the TC 111 picks up a group of two or more die from the source substrate 103 that has had one or more or all of its KBDs 2605 replaced with KGDs 2603, and proceeds to assembly onto the product substrate 105.

[0251] In one embodiment, the KRC 2601 assembles the KGD 2603 on the product substrate 105. The KBD 2605 is either directly removed from the TC 111 after picking up from the source substrate 103, or alternatively, the TC 111 avoids picking up the KBD 2605 from the source substrate 103. The space above the product substrate 105 that would have been occupied by the KBD 2605 is filled by the KGD 2603 picked from the buffer substrate 2602 and assembled on the product substrate 105 using the KRC 2601.

[0252] In one embodiment, the KRC 2601 assembles the KGD 2603 on the intermediate substrate (not shown in Figures 26A-26B). The KBD 2605 is either directly removed from the TC 111 after picking up from the source substrate 103, or alternatively, the TC 111 avoids picking up the KBD 2605 from the source substrate 103. The space above the intermediate substrate that would have been occupied by the KBD 2605 is filled by the KGD 2603 picked from the buffer substrate 2602 and assembled onto the intermediate substrate using the KRC 2601.

[0253] In one embodiment, the dies (e.g., die 2603) on the buffer substrate 2602 are height mapped so that the KRC 2601 can pick up the KGD 2603 at the correct height for placement on the source / intermediate / product substrate 103 / 801 / 105. Height mapping can be performed using a variety of methods (e.g., air gauges, confocal laser sensors, etc.).

[0254] In one embodiment, the KRC2601 is attached to the n-MASC tool using a z-actuation assembly that is separate from the z-actuation assembly for the TC111. In another embodiment, the KRC2601 is mounted on the same z-actuation assembly as the TC111 (with the TC111 temporarily unloaded from the z-actuation assembly).

[0255] Pick and place assembly tools can be designed to operate in various regimes of throughput, overlay, and yield. Exemplary throughput options are as follows: 1. At the high end of the throughput spectrum: (a) full substrate assembly (all fields 401 are assembled in parallel), (b) half-checkerboard assembly (half of the fields 401 on the source substrate 103 are assembled in parallel, where the fields 401 are arranged in the form of a checkerboard pattern that contains half of the fields 401 on the source substrate 103 and / or the product substrate 105. In the case of any 3×3 array of dies that are contiguous on the source substrate 103 and / or the product substrate 105. (a) a half-checkerboard, which is composed of five fields that share no edges, or alternatively, composed of the four fields that also do not share edges but are closest to the center of the 3×3 array); (b) a quarter-checkerboard assembly, in which a quarter of all the fields 401 on the source substrate 103 are assembled in parallel, where the fields 401 are arranged in the form of a checkerboard pattern containing a quarter of all the fields 401 on the source substrate 103 and / or product substrate 105. 2. At the low end of the throughput spectrum: (a) 9-field assembly, (b) 4-field assembly, (c) assembly by field, (d) 6-field assembly, (e) 8-field assembly, (f) 12-field assembly, (g) 14-field assembly, (h) 16-field assembly, (i) 18-field assembly, (j) 20-field assembly, (k) 24-field assembly, (l) 25-field assembly, (m) 36-field assembly, (n) 50-field assembly, and (o) 64-field assembly. Exemplary overlay options are as follows: 1. At the fine end of the overlay spectrum: (a) sub-10 nm (3σ) overlay control above production substrates; (b) sub-50 nm (3σ) overlay control above production substrates; (c) sub-100 nm (3σ) overlay control above production substrates. 2. At the lower precision end of the overlay spectrum: (a) sub-200 nm (3σ) overlay control above the production substrate; (b) sub-500 nm (3σ) overlay control above the production substrate; (c) sub-1 μm (3σ) overlay control above the production substrate. Exemplary yield options are as follows: 1. Full Replacement: Replace all known bad die 2605 with known good die 2603 using KRC 2601. 2. Half-replacement: Replace approximately half of the known bad die 2605 with known good die 2603 using KRC 2601. 3. Quarter Replacement: Replace approximately one-quarter of the known bad die 2605 with known good die 2603 using KRC 2601. 4. No Replacement: Do not replace any of the known bad die 2605.

[0256] [Table 1]

[0257] Reference is now made to Figures 27A-27C, which illustrate exemplary source substrate types, according to embodiments of the present invention.

[0258] Referring to FIG. 27A, FIG. 27A illustrates a "source substrate type 1", which is composed of a bulk silicon layer 2701, a buried oxide layer 2702 (corresponding to a sacrificial layer for assembly) present on the bulk silicon 2701, a silicon (Si) layer 2703 present on the buried oxide layer 2702, a buried oxide layer 2704 (for device function) present on the silicon layer 2703, and a silicon layer 2705 for the device present on the buried oxide layer 2704.

[0259] FIG. 27B illustrates a “source substrate type 2”, which consists of a layer 2706 of bulk silicon, a layer of heavily doped p-type material (p++) for creating a buried sacrificial layer 2707, a layer 2708 of very lightly doped n-type material (n−) on top of layer 2707, a layer 2709 of heavily doped p-type material (p++) for device functionality on top of layer 2708, and a layer of silicon 2710 for the device on top of layer 2709.

[0260] FIG. 27C illustrates a “source substrate type 3”, which consists of a layer 2711 of heavily doped (p++) bulk silicon, a layer 2712 of very lightly doped n-type material (n−) on top of layer 2711, a layer 2713 of heavily doped p-type material (p++) for device function on top of layer 2712, and a layer 2714 of silicon for the device on top of layer 2713.

[0261] 28A-B illustrate an example field 401 with an example multi-layer encapsulation, according to an embodiment of the present invention.

[0262] As shown in Figure 28A, Figure 28A illustrates an enlarged version of a cross section of field 401 including device stack 2801 overlying crystalline silicon 2802. In one embodiment, the width of field 401 is approximately 30 mm. In one embodiment, the width of device stack 2801 is approximately 3 μm. In one embodiment, the width of crystalline silicon 2802 is approximately 1 μm.

[0263] FIG. 28B illustrates field 401 with a multi-layer encapsulation including a thin chemical barrier layer 2803 (eg, chemical vapor deposition of carbon) and a structural stability layer 2804 (eg, chemical vapor deposition of silicon dioxide).

[0264] Moreover, as shown in Figure 28B, the encapsulation layer in region 1 2805 only needs to match compliance with the thin underlying silicon layer and therefore can have a low effective stiffness. It is noted that the patterning for region 1 2805 can be performed in the same manner (e.g., lithography) used to create the access holes to the buried sacrificial layer.

[0265] Additionally, as shown in FIG. 28B, a harder encapsulation layer (region 2 2806) may be needed to compensate for the greater tendency to bend.

[0266] 29A-B illustrate exemplary face-to-back (F2B) and face-to-face (F2F) device stacks, according to an embodiment of the present invention.

[0267] As shown in FIG. 29A, a typical F2B stack includes device layers 2901A-2901N (identified as “device layer 1” 2901A, identified as “device layer 2” 2901B, identified as “device layer 3” 2901C, and identified as “device layer N” 2901N as shown in FIG. 29A), where such device layers are connected in a face-to-back manner via vertical electrical connections 2902 (through silicon vias (TSVs)). Device layers 2901A-2901N may be referred to collectively or individually as device layers 2901 or device layers 2901, respectively.

[0268] As shown in FIG. 29B, a typical F2F stack includes device layers 2903A-2903N (2903A identified as “device layer 1”, 2903B identified as “device layer 2”, 2903C identified as “device layer 3”, 2903N-1 identified as “device layer N-1”, and 2903N identified as “device layer N” as shown in FIG. 29B), where such device layers are connected in a face-to-face manner via vertical electrical connections 2904 (through silicon vias (TSVs)). Device layers 2903A-2903N may be referred to collectively or individually as device layers 2903 or device layers 2903, respectively.

[0269] FIG. 30 illustrates an exemplary assembly of a static random access memory (SRAM) above a logic field in accordance with an embodiment of the present invention.

[0270] As shown in FIG. 30, logic field 3001 and SRAM field 3002 with sacrificial layer 3003 are assembled via F2B using n-MASC equipment 3004 to form an assembled product 3005 consisting of SRAM 3002 residing on top of logic field 3001.

[0271] TSV formation and package connection are then performed to form device 3006 which includes connection 3007 to the package and TSV 3008 .

[0272] Reference is now made to FIG. 31, which illustrates an exemplary assembly of multiple stacked static random access memories (SRAMs) above a logic field in accordance with an embodiment of the present invention.

[0273] 31, device 3006 now includes multiple SRAMs 3101 stacked above logic field 3001. Further discussion regarding stacking SRAMs is provided below.

[0274] Reference is now made to FIG. 32, which illustrates an exemplary assembly of static random access memory (SRAM) above a logic field with an error correction interposer in between, in accordance with an embodiment of the present invention.

[0275] 32, interposer field 3201 is used to determine good bit cells of logic field 3001 and SRAM field 3002 and to fabricate custom error correction procedures (e.g., electrical connectivity, heat dissipation, etc.). Interposer field 3201 can then be between logic field 3001 and SRAM field 3002 after being assembled (F2B) by n-MASC equipment 3004.

[0276] The following discussion is based on Figures 27A-27C, 28A-28B, 29A-29B, and 30-32.

[0277] In one embodiment, the source substrate 103 contains a buried sacrificial layer 2702, 2707. In one embodiment, the sacrificial layer 2702, 2707 is silicon oxide. In one embodiment, the starting substrate for the sacrificial layer-containing source substrate is composed of a lightly doped n-type layer (abbreviated to N-) 2708, 2712 and a highly doped p-type layer (abbreviated to P++) 2709, 2713. The highly doped p-type layer 2709, 2713 can first be converted to porous silicon (e.g., using silicon anodization) and then oxidized to produce a buried sacrificial layer of silicon oxide. The lightly doped n-type layer 2708, 2712 remains unaffected during anodization, limiting the anodization to only the highly doped layer. In one embodiment, layers with low n-type and high p-type doping can be produced using epitaxial growth. In one embodiment, the bulk silicon itself is highly p-doped (eg, layer 2711).

[0278] In one embodiment, the source substrate 103 is comprised of a background device on a carrier substrate. The carrier substrate can be bulk silicon, a glass substrate, a tape frame, etc., depending on the process used for the generation of the background device and the desired device orientation. In one embodiment, the carrier substrate is transparent. In one embodiment, the carrier substrate is attached to the background field using a UV release adhesive. In one embodiment, the carrier substrate is attached to the background field using a sublimable polymer. In one embodiment, the backgrinding is performed using a MACE process.

[0279] In one embodiment, the background field is attached to a carrier substrate using a light-to-heat conversion (LTHC) adhesive layer. In one embodiment, after pick-up (by one or more TCs 111), the field 401 can be cleaned on the TCs 111 themselves using (for example) oxygen plasma, etchant vapor (e.g., vapor HF), and / or etchant liquid.

[0280] In one embodiment, distortion of the thin field 401 due to residual stress is controlled using a structural encapsulation layer of a thickness and material such that the rigidity of the encapsulation layer is close to or equal to the rigidity of the underlying field 401. In one embodiment, the encapsulation layer is composed of a chemical encapsulation layer 2803 (to protect against chemical damage) along with a structural encapsulation layer 2804 (to prevent distortion due to residual stress). In one embodiment, the structural encapsulation layer 2804 is patterned to counter various distortion trends across the area of ​​the field 401. In one embodiment, the residual distortion in the encapsulated field is sensed using a wavefront-based method, a laser-based raster scanning method, a capacitive method, or the like.

[0281] In one embodiment, for face-to-back assembly, the encapsulation layer over the picked field 401 is not removed prior to bonding. In one embodiment, a structural encapsulation layer that compensates for residual stresses is included within the device itself. In one embodiment, metal interconnects run through the structural encapsulation layer 2804.

[0282] In one embodiment, the encapsulation layer includes a compliant element to prevent field distortion due to embedded particles. In one embodiment, the compliant element is in the form of a compliant pin of a compliant pin chuck. In one embodiment, the encapsulation layer includes a compliant polymer layer to prevent field distortion due to embedded particles.

[0283] In one embodiment, the encapsulation layer contains a scratch resistant layer, which is made, for example, using a diamond-like layer or a hard coating (eg, aluminum oxide, etc.).

[0284] In one embodiment, the encapsulation layer is composed of three layers: carbon, silicon oxide, and carbon (with the silicon oxide sandwiched between two carbon layers).

[0285] In one embodiment, the patterning of the encapsulation layer is performed using nanoimprint lithography, photolithography, e-beam lithography, etc. In one embodiment, the patterning of the encapsulation layer is performed using the same lithography process used for the creation of the field access holes.

[0286] In one embodiment, the field 401 contains a nanowire forest at the bonding interface to facilitate electrical connection, hi one embodiment, the nanowire forest incorporates copper nanowires.

[0287] In one embodiment, the through silicon vias (TSVs) 2902, 2904 (formed after bonding to electrically connect the bonded fields 401) have a multi-shell structure that can include a metal connection (e.g., in the center of the TSV) along with a low-k dielectric in the form of an annulus around the metal connection.

[0288] In one embodiment, the assembled field 401 on the product substrate 105 is composed of a memory layer (e.g., 3002) and a logic layer (e.g., 3001). In one embodiment, the field 401 on the product substrate 105 contains an interposer (e.g., interposer field 3201) that can be used to create electrical connectivity, heat dissipation, etc.

[0289] In one embodiment, for face-to-back assembly, the field contact pins on the transfer chuck have a cross-sectional area larger than the size of the optional access holes in the field 401 .

[0290] In one embodiment, the starting substrate with the sacrificial layer is attached to a carrier substrate by adhesive and the sacrificial layer is peeled off so that the source substrate 103 consists of the field 401 on the carrier substrate.

[0291] The fields 401 on the incoming back-ground source substrate are first transferred to an intermediate substrate 801, then transferred to a second intermediate substrate 801 using a TC111, and then finally inverted onto the product substrate 105 and hybrid bonded to the product substrate 105. The incoming back-ground singulated fields can be on a transparent carrier (e.g., glass, quartz, sapphire, and / or polymer). The first intermediate substrate 801 can be a transparent substrate (e.g., glass, quartz, sapphire, and / or polymer). The second intermediate substrate 801 can be a transparent substrate (e.g., glass, quartz, sapphire, and / or polymer) or a non-transparent substrate (e.g., silicon) (in the visible spectrum). The adhesive that attaches the fields 401 to the carrier substrate in the source substrate 103 can be UV releasable, thermally releasable, etc. The adhesive used to attach the field 401 to the first intermediate substrate 801 in the source substrate 103 can be UV releasable, thermally releasable, etc. In one embodiment, the field 401 from the source substrate 103 is released by UV exposure of the UV release adhesive on the source substrate side after flipping and attachment onto the first intermediate substrate 801.

[0292] FIG. 33 illustrates an exemplary sequence for pick-and-place assembly, in accordance with an embodiment of the present invention.

[0293] 33, a series of pre-flip source wafers 3301A-3301N (it is noted that the terms "wafer" and "substrate" are used interchangeably herein) (3301A identified as "pre-flip source wafer 1," 3301B identified as "pre-flip source wafer 2," and 3301N identified as "pre-flip source wafer N") rest on carrier substrates 3302A-3302N, respectively. Pre-flip source wafers 3301A-3301N may be referred to collectively or individually as a plurality of pre-flip source wafers 3301 or pre-flip source wafers 3301, respectively. Carrier substrates 3302A-3302N may be referred to collectively or individually as a plurality of carrier substrates 3302 or carrier substrates 3302, respectively.

[0294] Moreover, as shown in FIG. 33, the metal structure (die) 3303 faces towards the adhesive 3304 .

[0295] In one embodiment, the wafer 3301 is flipped by temporary bonding and the pre-flip carrier 3302 is removed, such as by using a transfer chuck 111, thereby forming source wafers 3305A-3305N (3305A identified as "source wafer 1," 3305B identified as "source wafer 2," and 3305N identified as "source wafer N") as shown in Figure 33. Source wafers 3305A-3305N may be referred to collectively or individually as source wafers 3305 or source wafers 3305, respectively.

[0296] Next, as shown in FIG. 33, there can be a collective die transfer to intermediate wafers 3306A-3306N (3306A identified as "intermediate wafer 1", 3306B identified as "intermediate wafer 2", and 3306N identified as "intermediate wafer N"), potentially adjusting pitch in the X and / or Y directions using TC111. Intermediate wafers 3306A-3306N can be collectively or individually referred to as multiple intermediate wafers 3306 or intermediate wafers 3306, respectively. In one embodiment, the thickness of adhesive 3304 can be adjusted per die 3303 to compensate for height mismatch, as shown via element 3307. Additionally, FIG. 33 illustrates an exemplary adhesive island 3308, where a single die 3303 is adhesively bonded to intermediate wafer 3306.

[0297] Moreover, as shown in Figure 33, there can then be a collective transfer from all intermediate wafers 3306 to a transfer wafer 3309 using the TC 111. In one embodiment, overlay can be corrected during this step. Moreover, in one embodiment, during such a step the die grid pitch can be adjusted in the X and / or Y directions.

[0298] Additionally, as shown in FIG. 33, transfer wafer 3309 is bonded (eg, hybrid bonded) to product wafer 3310.

[0299] Reference is now made to FIG. 34, which illustrates an alternative exemplary sequence for pick-and-place assembly, in accordance with an embodiment of the present invention.

[0300] As shown in Fig. 34, compared to Fig. 33, there is a collective transfer using TC111 to a transfer wafer 3309 without the use of an intermediate wafer 3306. Moreover, as shown in Fig. 34, an exemplary adhesive island 3401 can be present on a source wafer 3305, where a single die 3303 is adhesively bonded to the source wafer 3305. Additionally, it is noted that the thickness of the adhesive 3304 can be adjusted per field 401 to compensate for field mismatch, as shown via element 3402.

[0301] Reference is now made to FIG. 35, which illustrates a further alternative exemplary sequence for pick-and-place assembly, in accordance with an embodiment of the present invention.

[0302] As shown in Figure 35 in comparison to Figures 33 and 34, the pre-flip source wafer 3301 is not flipped and there is no utilization of an intermediate wafer 3306. Instead, there is a collective transfer from all pre-flip source wafers 3301 to a transfer wafer 3309 using TC111. In one embodiment, overlay can be corrected during this step. Additionally, in one embodiment, the die grid pitch can be adjusted in the X and / or Y directions during such a step.

[0303] After transfer, the transfer wafer 3309 is inverted by temporary bonding and the carrier substrate 3302 is removed, such as by using the transfer chuck 111, thereby forming the structure 3501.

[0304] Moreover, as shown in FIG. 35, the exemplary adhesive islands 3502 can be present on a transfer wafer 3309, where a single die 3303 is adhesively bonded to the transfer wafer 3309.

[0305] 36A-B, which illustrate an exemplary transfer chuck 111, in accordance with an embodiment of the present invention.

[0306] As shown in FIG. 36A, the transfer chuck 111 can be composed of multiple mini TCs 3601.

[0307] Moreover, Fig. 36A illustrates an exemplary location 3602 for application of force to reconfigure the TC X-grid. Additionally, Fig. 36A illustrates an exemplary location 3603 for application of force to reconfigure the TC Y-grid.

[0308] Additionally, Figure 36A illustrates a Y reconstruction array 3604. An X reconstruction array (not shown in Figure 36A) can be fabricated separately and overlaid on top of the Y reconstruction array 3604.

[0309] In one embodiment, the TC111 contains a complete reconfigurable array of mini-TC3601s that are 300 mm by 300 mm. A magnified version of the cross section of a mini-TC3601 is shown in Figure 36B.

[0310] As shown in Fig. 36B, the mini-TC 3601 includes electrodes 3605 and a custom thin film transistor (TFT) backplane 3606. Additionally, as shown in Fig. 36B, a layer of dielectric 3607 between the mini-TC 3601 and the field 401 can be utilized, where the dielectric 3607 can optionally be leaky to create a Johnsen-Rahbek (JR) type chucking effect.

[0311] 37A-37O illustrate an alternative exemplary transfer chuck, according to an embodiment of the present invention.

[0312] Referring to Figure 37A, Figure 37A illustrates a magnified version of a cross section of a mini-TC 3601. As shown in Figure 37A, "Option 1" is to reuse a thin film transistor (TFT) backplane 3701 from a mini-LCD display. For example, the mini-TC 3601 would include a reused TFT backplane 3701. Additionally, the spaces 3702 between the electrodes 3703 are maintained at atmospheric pressure using an in-plane grid of channels 3704.

[0313] Additionally, Figure 37A illustrates a vacuum inlet 3705 where the vacuum is provided using an in-plane grid of vacuum channels (not shown in Figure 37A), and also illustrates a vacuum outlet 3706 to the field 401.

[0314] As shown in FIG. 37B, the structure of FIG. 37B includes a reused TFT backplane 3701 along with transistor leads 3707.

[0315] Referring now to Figure 37C, Figure 37C includes process steps for reusing a TFT backplane 3701 from a mini LCD display, including vacuum channel patterning 3708, metal deposition and patterning 3709 (for fixed electrodes), oxide deposition 3710, metal deposition and patterning 3711 (for movable electrodes), flexible film deposition 3712, TSV pattern and etching from the backside 3713, and bump creation 3714, resulting in the structure shown in Figure 37D.

[0316] As shown in FIG. 37D, the structure includes an electrode 3703 and a channel 3704.

[0317] Now referring to FIG. 37E, process steps for reusing the TFT backplane 3701 from a mini LCD display further include vacuum channel patterning 3715, oxide deposition 3716, TSV pattern and etch from the backside 3717, porous film deposition 3718, oxide deposition 3719, and pin polishing 3720, resulting in the structure 3721 shown in FIG. 37F.

[0318] Now referring to FIG. 37G, the structures shown in FIG. 37B, FIG. 37D, and FIG. 37F are bonded together by performing the process steps of bump bonding, fusion bonding, and oxide release using vHF (vapor phase hydrofluoric acid) (see element 3722), resulting in the structure 3723 shown in FIG. 37H.

[0319] Now referring to FIG. 37I, FIG. 37I illustrates a magnified version of the cross section of the mini-TC 3601. As shown in FIG. 37I, "Option 2" is to use a custom backplane 3724 at a TFT foundry. The mini-TC 3601 further includes a movable electrode 3725 and a fixed electrode 3726. In addition, as shown in FIG. 37I, there is an optional porous filter membrane 3727 to filter particles in the air stream so that they do not reach the TC field interface.

[0320] Referring now to Figure 37J, Figure 37J includes process steps for using a custom backplane 3724 at a TFT foundry, including TFT patterning 3728, vacuum channel patterning 3729, metal deposition and patterning 3730 (for fixed electrodes 3726), oxide deposition 3731, metal deposition and patterning 3732 (for movable electrodes 3725), and flexible film deposition 3733, resulting in the structure shown in Figure 37K.

[0321] As shown in FIG. 37K, the structure includes a custom backplane 3724 as well as moveable electrodes 3725 and fixed electrodes 3726 .

[0322] Referring now to Figure 37L, Figure 37L includes additional process steps for using a custom backplane 3724 at a TFT foundry, including vacuum channel patterning 3734, oxide deposition 3735, TSV pattern and etching from the backside 3736, porous film deposition 3737, oxide deposition 3738, and pin polishing 3739, resulting in the structure 3740 shown in Figure 37M.

[0323] Now referring to FIG. 37N, the structures shown in FIG. 37K and FIG. 37M are bonded together by performing the process steps of bump bonding, fusion bonding, and oxide release using vHF (vapor phase hydrofluoric acid) (see element 3741), resulting in the structure 3742 shown in FIG. 37O.

[0324] 38A-38C, which illustrate an exemplary reconfigured transfer chuck (TC) 111, in accordance with an embodiment of the present invention.

[0325] 38A illustrates an XZ plane cross-sectional view of the TC 111, depicting an optical electromagnetic actuator 3801. Additionally, the TC 111 includes a slider 3802 and an optional flexure system 3803, which is axially aligned in a θ x and θy, constraining the slider 3802. Additionally, the TC 111 includes an optional frictionless pivot 3804 between the flexure system 3803 and the optical electromagnetic actuator 3801.

[0326] In one embodiment, δ y , δ z , θ z , θ xis controllable. In one embodiment, the TC 111 includes an optional flexure bearing with an optional frictionless rotary bearing.

[0327] FIG. 38B illustrates a top view of TC 111.

[0328] FIG. 38C illustrates an enlarged view of a portion of the top view of TC 111.

[0329] As shown in Figures 38B and 38C, there is an optional pressure and / or vacuum 3805 to guide and / or secure the slider 3802 on the linear rail 3806. Additionally, Figure 38C illustrates an optional transparent core port 3807 in the slider 3802 to allow for metrology. Additionally, Figure 38C illustrates an optional encoder sensor 3808. Figure 38C further illustrates an optional permanent magnet / voice coil 3809.

[0330] Further discussion regarding Figures 33-35, 36A-36B, 37A-37O, and 38A-38C is provided below.

[0331] See below for a list of definitions of terms discussed herein. · SiP - System-in-Package, where separately manufactured die are integrated into a higher level assembly. Field - an individual die or a small cluster of dies arranged in a SiP. ·SPP-SiP Pitch On Product-SPP x and SPP y A wafer (SPP) comprising: · Transfer chuck - a system used to transfer fields and / or dies from one substrate to another while maintaining the thermo-mechanical stability of said fields and / or dies.

[0332] In one embodiment, the singulated fields on the source substrate 103 (obtained after back grinding) are first transferred to the intermediate substrate 801 using the transfer chuck 111 and then transferred to the transfer substrate 3309. In one embodiment, during the transfer from the source substrate 103 to the intermediate substrate 801, the fields 401 are displaced in the X-axis and / or Y-axis such that the field pitch matches the grid pitch on the product substrate 105 along the X-axis and / or Y-axis. In one embodiment, during the transfer from the intermediate substrate 801 to the transfer substrate 3309, the fields 401 are displaced in the X-axis and / or Y-axis such that the field pitch matches the grid pitch on the product substrate 105 along the X-axis and / or Y-axis. In one embodiment, during the transfer from the intermediate substrate 801 to the transfer substrate 3309, the predicted overlay error of the field on the product substrate 105 is fully or partially compensated by the TC 111 and / or actuators (thermal, mechanical) on the transfer substrate chuck. In one embodiment, the field 401 is transferred from the transfer substrate 3309 to the product substrate 105 in a whole substrate manner. In one embodiment, the transfer substrate 3309 is removed from the temporarily bonded field using heating (with a thermal release adhesive) or UV exposure (with a transparent or perforated substrate and a UV curable adhesive). In one embodiment, the transfer substrate 3309 is removed from the field 401 after temporary bonding onto the product substrate 105 (e.g., bonding is performed using room temperature hybrid bonding). After removal of the transfer substrate 3309, residual adhesive and / or UV curable planarization material is cleaned away using oxidative wet cleaning, O2 plasma ashing, etc. Cleaning can be performed after the temporary bond between the oxide surfaces and before the permanent bond, where the permanent bond is performed using thermal curing of the hybrid bonded surfaces.

[0333] One or more of the source / intermediate / transfer substrates 103 / 801 / 3309 can be composed of glass substrate, glass substrate in roll form, aluminum, aluminum in roll form, aluminum in foil form, polymer, polymer in roll form, stainless steel, and / or stainless steel in roll form. In one embodiment, one or more of the source / intermediate / transfer substrates 103 / 801 / 3309 have through-substrate perforations that act as light guides.

[0334] In one embodiment, the intermediate substrate 801 and the transfer substrate 3309 are composed of transparent substrates (e.g., silicon oxide, fused silica, glass, etc.), non-transparent substrates (e.g., silicon) and / or partially transparent substrates (e.g., silicon with perforations). Silicon substrates with perforations can be fabricated using deep etching processes (e.g., deep reactive ion etching (DRIE), metal assisted chemical etching (MACE), etc.).

[0335] In Figure 33, during field transfer from one or more source wafers 3305 to one or more intermediate wafers 3306, the pitch of the fields 401 can be changed along only a single axis (one of X or Y) using the ATC 1101. The fields 401 can then be transferred to a second set of intermediate wafers (not shown in Figure 33) where the field pitch is changed along a direction orthogonal to the previous step.

[0336] In one embodiment, the TC 111 is reconfigurable and contains optical elements (for focusing light from and onto the light source 2402 and light sensor on the MM 108) attached to every single or group of actuation units. In one embodiment, the TC contains one or more light sources attached to every single or group of actuation units 1007. In one embodiment, the optical elements and light sources 2402 associated with a single actuation unit 1007 can themselves be displaced in the X-axis, Y-axis, and / or Z-axis relative to the actuation unit 1007. Actuation can be performed using magnetic, electromagnetic (e.g., voice coil), thermal, piezoelectric, and / or pneumatic actuation modalities.

[0337] In one embodiment, an assembly of a turning mirror and single or multiple light sources 2402 is used to project light for metering onto the TC 111. In one embodiment, the turning mirror is comprised of a mirror with a predetermined reflectivity that starts at a predetermined amount and gradually increases and / or decreases as it progresses along the light path from the light source 2402. In one embodiment, the turning mirror is comprised of a transparent substrate coated with a patterned film of reflective material (with the pattern pitch varying to match the reflectivity requirements at a particular location).

[0338] In one embodiment, a laser-based method can be used to ablate and / or vaporize the plugging material 1201. The laser can be used to heat the portion of the TC 111 that immediately surrounds the plugging material 1201. In one embodiment, the laser operates in ultraviolet frequencies. In one embodiment, the laser has a wavelength of 257 nm. In one embodiment, the laser is a continuous wave laser, a pulsed laser, or an ultrashort pulsed laser. In one embodiment, wet cleaning is used to etch the plugging material 1201. The cleaning material can be dispensed only near where the plugging material 1201 is located.

[0339] In one embodiment, the plugging material 1201 is a transitional material. In one embodiment, the plugging material 1201 is an end-capped polyoxymethylene.

[0340] In one embodiment, two or more TCs 111 are used, where one of the TCs 111 is used for pick and place assembly and the rest of the TCs 111 are cleaned and returned to their default state for vacuum switching. In one embodiment, the TCs 111 are attached to an indexing mechanism. In one embodiment, the TCs 111 are attached to a mechanism that reverses their orientation and indexes them for cleaning.

[0341] In one embodiment, a thermally stable optical plate is used as a reference to measure alignment errors of fields on the source substrate 103, intermediate substrate 801, transfer substrate 3309, and / or product substrate 105. In one embodiment, the optical plate is custom made to measure alignment for different dies. In another embodiment, the optical plate is composed of a dense array of alignment marks that remain the same for each new type of die.

[0342] In one embodiment, the adhesive 3304 used to attach the field 401 to the source substrate 103, intermediate substrate 801, transfer substrate 3309, and / or product substrate 105 can be composed of two or more layers. The layers can be UV-curable adhesives, nanoparticle inks, heat-curable adhesives, pressure-sensitive adhesives, and / or transitional materials. In one embodiment, the nanoparticle inks absorb radiation in a narrow wavelength range. In one embodiment, the nanoparticle inks absorb radiation in a narrow wavelength range where one or more of the substrates and chucks in the n-MASC system show minimal or zero absorption. In one embodiment, one of the components of the adhesive 3304 is a transitional material that turns into a gas when heated. The heating can be created using radiative heat transfer (e.g., using a laser), convective heat transfer, or conductive heat transfer. In one embodiment, the transitional material contains polyoxymethylene. In one embodiment, adhesive 3304 is dispensed in adhesive islands (e.g., adhesive islands 3308, 3401, 3502) onto the source substrate 103, intermediate substrate 801, transfer substrate 3309, and / or product substrate 105. The adhesive islands (e.g., adhesive islands 3308, 3401, 3502) can vary in size from less than 10 μm in diameter to 300 mm in diameter.

[0343] In one embodiment, the source substrate 103, intermediate substrate 801, transfer substrate 3309, and / or product substrate 105 contain a fixed, high density grid of alignment marks that can be used, for example, as a fixed, stable reference to measure the misalignment of a field 401 picked onto a TC 111.

[0344] In one embodiment, the adhesive 3304 dispensed onto the source substrate 103, intermediate substrate 801, transfer substrate 3309, and / or product substrate 105 is performed outside of the n-MASC tool.

[0345] In one embodiment, a stock of one or more buffer source substrates of each type (required by the product substrates 105) is maintained in a stocker unit in the n-MASC tool. If the current stock of buffer substrates is all partially populated and does not contain all the dies required in the correct locations to create the required field layout on the product substrates 105, new buffer substrates can be added for a particular field type until a preset limit number of buffer substrates is reached, at which point die-by-die pick-and-place or pick-and-place of a small number of dies is implemented using one or already existing buffer substrates in the inventory.

[0346] In one embodiment, one or more of the encapsulation layers used during n-MASC contain a conductive element. In one embodiment, the conductive element is connected to a source of electrical potential to generate an electrostatic attraction between the transfer chuck 111 and the field 401 (where the encapsulation layer overlies the field 401). In one embodiment, one or more of the encapsulation layers is on an opposite side of the field 401 as the device structure.

[0347] In one embodiment, one or more mini TCs 3601 are used to pick and place one or more dies 901. The mini TCs 3601 rest on rails 3806 and can be actuated using electromagnetic attraction and / or repulsion between the rails 3806 and slider 3802. An exemplary system is shown in Figures 38A-38C. The rails 3806 and / or slider 3802 (on which the mini TCs 3601 are mounted) can be rotated along the X-axis, Y-axis, Z-axis, θ-axis, and θ-axis. x axis, θ y axis and / or θ zIt may have embedded electromagnets to generate controlled motion in the axes. In one embodiment, an orthogonal system of rails is utilized: one or more Y rails rest on and are guided on an orthogonal pair of X rails. One or more sliders 3802 may be guided on the Y rails. The sliders 3802 provide air-based and / or magnetic cushioning to control the X, Y, Z, θ axes. x axis, θ y axis and / or θ zThe slider 3802 and / or rail 3806 can be restrained in an axis. The slider 3802 and / or rail 3806 can contain holes and / or perforations to supply vacuum and / or pressure to create a cushioning effect. In one embodiment, the slider 3802 and / or rail 3806 can contain porous ceramic (e.g., porous SiC) to supply pressure and / or vacuum. In one embodiment, a flexible covering is utilized to cover the pressure and / or vacuum emanating from the holes and / or perforations in the slider 3802 and / or rail 3806. In one embodiment, a horizontal air curtain is generated across the face of the mini-TC 3601 and / or the substrate (from which the transfer is mounted). In one embodiment, the air curtain is used to reduce particle contamination. In one embodiment, pressure is only dispensed in two opposing directions (e.g., toward the top and bottom of the slider 3802 at the same time) to create a counter cushion for the slider restraint. In one embodiment, a combination of magnetic and air-based cushioning is utilized to constrain the slider 3802. The Y-rails can be constrained onto the X-rails using a mechanism similar to that used for the slider 3802. In one embodiment, vacuum preloading is utilized to constrain one or more of the slider 3802 and / or Y-rails. In one embodiment, the flexures are located either in a plane parallel to the TC111 and / or in a plane perpendicular to the TC111, and are aligned along the X, Y, Z, θ axes. x axis, θ y axis and / or θ zA slider restraint flexure can be used to restrain the Mini TC3601 in the axis. In one embodiment, an out-of-plane pantograph mechanism is used to provide the restraint. In one embodiment, a scissor mechanism is used per Y-rail for the restraint. In one embodiment, the cables (for slider 3802 and / or Mini TC3601 electrical and pneumatic connectivity) are supported by the slider restraint flexure.

[0348] In one embodiment, the TC reconfiguration can be feedback controlled. Global precision can be achieved using an encoder plate. In one embodiment, the encoder plate is used only at the beginning of the assembly of a particular source wafer set. The encoder plate is loaded onto the source wafer chuck 102, the TC 111 can be reconfigured, and then removed. Each mini TC 3601 can be referenced to a globally precise encoder plate. By incorporating an encoder plate into the source wafer chuck 102 or potentially the MM 108, real-time feedback can be implemented.

[0349] In one embodiment, the Mini TC3601 sits on a puck that slides over an electromagnetic plate, which in turn rotates along the X, Y, Z, θ axes. x axis, θ y axis and / or θ z The movement of the puck in the axis can be controlled. The mini TC3601 can face upwards and the die 901 and / or field 401 to be picked and placed can face downwards (such that the pick-up process separates the die and / or field from the substrate in a downward direction).

[0350] In one embodiment, the Mini TC 3601 rests on a chucking surface that is 300 mm or greater. In one embodiment, the Mini TC 3601 is attached to the chucking surface using vacuum, electromagnetic force, and / or chemical adhesion. During pick and place assembly, the Mini TC 3601 can be picked up from the chucking surface using the Mini TC picker mechanism and the SPP of the product substrate 105 prior to placement on the intermediate wafer 801, transfer wafer 3309, or product wafer 105. x or SPP y The picker mechanism can be expanded or contracted in the X-axis and / or Y-axis to match the position of the mini TC3601. The expansion can be performed in either one step or two steps. In the case of one-step expansion, the picker mechanism can contain a flexure mechanism, which is based on, for example, a scissor mechanism that can be expanded independently in both the X- and Y-directions. In the case of two-step expansion, the picker mechanism first expands the pitch of all the mini TC3601 in one direction. Thereafter, the mechanism is rotated by 90 degrees or a separate mechanism that is positioned orthogonally to the first mechanism is utilized to expand the pitch of the mini TC3601 in the orthogonal direction. The picker mechanism can expand the pitch of the mini TC3601 using a rail-type system or a scissor-type mechanism as described above, or a combination thereof.

[0351] 39A-39C, which illustrate an exemplary transfer chuck 111 showing an array of adaptive chucking modules (ACMs) that are movable relative to one another using a variable pitch mechanism (VPM), in accordance with an embodiment of the present invention.

[0352] As shown in Figure 39A, the TC 111 includes a flexure-based pivot 3901. A cross-sectional view of the TC 111 is provided in Figure 39B, which depicts an optional transparent window 3902, an ACM 3903 attached to the slider 3802, and an optional air bearing 3904.

[0353] Additionally, a top view of the TC111 is provided in FIG. 39C, which depicts the voice coil actuator 3905 and fixed central ACM 3903.

[0354] 40A-40B illustrate an alternative exemplary transfer chuck 111 showing an array of elongated adaptive chucking modules 3903 (ACMs) that are movable relative to one another using a variable pitch mechanism (VPM) in accordance with an embodiment of the present invention.

[0355] 40A, which illustrates a top view of transfer chuck 111 depicting X-rail 4001 and Y-rail 4002, and elongated ACM 3903 secured to Y-rail 4002. In one embodiment, the width of Y-rail 4002 is approximately 15 mm.

[0356] A close-up of a cross section of the Y-rail 4002 is depicted in FIG. 40B. As shown in FIG. 40B, the ends of the Y-rail 4002 are supported on the X-rail 4001 using air bearings 4003. In one embodiment, the ends of the Y-rail 4002 are made from porous silicon carbide. In another embodiment, the ends of the Y-rail 4002 are made from metal with holes to create the air bearings 4003. In one embodiment, actuation along the X-direction can be provided using an electromagnetic actuator system.

[0357] FIG. 41 illustrates a further alternative exemplary transfer chuck 111 showing an array of elongated adaptive chucking modules 3903 (ACMs) that are movable relative to one another using a variable pitch mechanism (VPM) in accordance with an embodiment of the present invention.

[0358] As shown in FIG. 41, the transfer chuck 111 includes an X-direction flexure 4101 .

[0359] 42A-42B illustrate an exemplary adaptive chucking module (ACM) 3903, in accordance with an embodiment of the present invention.

[0360] Referring to FIG. 42A, FIG. 42A illustrates a cross section of a bottom portion of ACM 3903. Among other things, FIG. 42A illustrates an exemplary connection 4201 to a switch, a fixed electrode 4202, a movable electrode 4203, and a 5 μm gap 4204 between such electrodes 4202, 4203. Additionally, FIG. 42A illustrates a location 4205 in the atmosphere and an ACM pin 4206 on the die 901. Additionally, FIG. 42A illustrates a pin pitch of about 100 μm. Additionally, FIG. 42A illustrates a dual seal 4207, a polysilicon membrane 4208, and a vacuum inlet 4209.

[0361] A top view of the ACM 3903 showing the routing of the vacuum inlet 4209 is depicted in FIG. 42B.

[0362] Further discussion regarding Figures 39A-C, 40A-B, 41, and 42A-B is provided below.

[0363] In one embodiment, the transfer chuck 111 can be comprised of an array of adaptive chucking modules (ACMs) 3903, each of which can be used to pick and place one or more fields 401 from one or more of the source / intermediate / product substrates 103 / 801 / 105. In one embodiment, the ACMs 3903 are comprised of an array of valve units. In one embodiment, an electrostatic actuation mechanism is utilized to actuate the valves. In one embodiment, a seal 4207, comprised of one or more chambers, is utilized to isolate the vacuum inlet portion 4209 from the outlet portion. In one embodiment, an air volume contained inside the seal 4207, comprised of one or more chambers, is utilized to cushion the impact of the membrane 4208 when it closes the valve.

[0364] The ACMs 3903 can be moved relative to each other using a variable pitch mechanism. The variable pitch mechanism can be composed of flexure, air, and electromagnetic bearings, as well as pneumatic and electromagnetic actuators. In one embodiment, the ACMs 3903 are mounted on planar motors that provide actuation along six axes. Some exemplary designs are shown in Figures 39A-C, 40A-B, and 41.

[0365] In one embodiment, the ACM3903 includes a mechanism for θ actuation of the ACM3903 to a variable pitch mechanism (VPM). In one embodiment, the θ actuation mechanism is flexure-based. In one embodiment, the θ actuation flexure is actuated using a thermal actuator that induces thermal expansion in the flexure arm. In one embodiment, the spacing between picked fields in the TC111 (or, equivalently, the pitch of the ACM3903) is increased to accommodate a larger length of the flexure to allow thermal actuation to create a larger θ displacement.

[0366] In one embodiment, one or more imagers 1401 are used to detect errors in field pick and place with the ACM 3903. In one embodiment, the imager 1401 is a visible light imager or an IR imager. In one embodiment, the imager 1401 observes a single ACM 3903 per imager, or observes multiple ACMs 3903 per imager. The image stream from the imager 1401 can be used by an automated fault detection algorithm to flag errors in the pick and place process. The fault detection algorithm can be based on an artificial neural network (ANN), a convolutional neural network (CNN), or the like.

[0367] 43A-43C illustrate an additional exemplary transfer chuck 111 showing an array of adaptive chucking modules 3903 (ACMs) that are movable relative to one another using a variable pitch mechanism (VPM) in accordance with an embodiment of the present invention.

[0368] Referring to FIG. 43A, the transfer chuck 111 includes a scissor-based mechanism 4301 for Y-expansion / contraction of the ACM3903.

[0369] FIG 43B is a close-up view of a cross section of the scissor-based mechanism 4301. As shown in FIG 43B, FIG 43B illustrates a fixation point 4303 on the VPM 4302. Additionally, the VPM 4302 includes an actuation arm 4304 coated with a light-to-heat conversion material (e.g., light absorbing nanoparticle links, a light-to-heat conversion release coating (LTHC) layer, etc.). Additionally, the VPM 4302 includes a thermally insulated connector 4305.

[0370] Figure 43C illustrates another close-up view of the cross section of the scissor-based mechanism 4301. As shown in Figure 43C, it illustrates an optional cantilever flexure 4306, which allows movement in the X, Y, and θ axes, but minimal movement in the Z plane.

[0371] FIG. 43C further illustrates an optional thermally insulating frame 4307 that is connected to the ACM 3903 using an optional thermally insulating adhesive.

[0372] 43A-43C, in one embodiment, the ACM 3903 is connected to the VPM 4302 using a mechanism capable of actuating one or more of the X, Y, and θ axes. In one embodiment, the range of X or Y displacement is at least 100 nm, while the range of θ is at least 10 microradians. In one embodiment, the actuation mechanism is connected to the fixed point 4303 of the VPM 4302 and the ACM 3903. In one embodiment, the connection of the mechanism with the fixed point 4303 of the VPM 4302 and the ACM 3903 is created using a thermally insulating material. In one embodiment, the thermally insulating connector also has a low overall thermal expansion (less than 25 nm, or even less than 10 nm). This low overall thermal expansion can be achieved by using a connector material with a low coefficient of thermal expansion (CTE), or by using thin (micrometer scale) connectors, or by using a low CTE and thin connector combination. These connector materials can include thermal insulating adhesives, polymer connectors with low overall thermal expansion, fused silica, or stainless steel. In one embodiment, the actuation arm 4304 is coated with a light-to-heat conversion material (e.g., light absorbing nanoparticle ink, LTHC layer). In one embodiment, heating of the actuation arm 4304 is performed by illuminating the actuation arm 4304 using one or more of the following: a scanning light source, a digital micromirror array, an array of LEDs, and an array of micro-LEDs. In one embodiment, a heat sink is used to maintain a stable reference temperature for the actuation arm 4304. The heat sink can be composed of a fluid flow (e.g., air) across the actuation arm 4304 and / or embedded fluid microchannels. In one embodiment, the variable pitch mechanism 4302 possesses a range of motion of at least 1 millimeter.

[0373] 44A-44F, which illustrate an exemplary transfer substrate 3309, according to an embodiment of the present invention.

[0374] As shown in FIG. 44A, FIG. 44A illustrates the transfer substrate 3309. FIG. 44B illustrates a close-up of a cross section of the transfer substrate 3309. FIG. 44B illustrates an optional mesa 4401 (area on top of the transfer substrate 3309 where the substrate 3309 is not etched away) for capillary pinning of the adhesive. In one embodiment, the mesa 4401 is made using a polymer and patterned (e.g., via photolithography, etc.). In one embodiment, the mesa 4401 is transparent to UV light (e.g., photoresist material). In one embodiment, the material of the mesa 4401 is index matched to the waveguide layer. The index of refraction of the mesa material can be adjusted to allow only a portion of the light in the waveguide to leak through the mesa 4401 into the adhesive (e.g., for UV curing).

[0375] Additionally, as shown in FIG. 44B, a small amount of source substrate adhesive 4402 can optionally be left on the underside of field 401 after pick-up from source substrate 103.

[0376] Moreover, Figure 44B illustrates two exemplary adjacent fields 401. In one embodiment, the fields 401 have their active sides facing upward (away from the transfer substrate 3309). Height variations in the fields 401 can be compensated for by z-compliant flexures, adhesive drop volume adjustments, and by cantilevering the fields 401 near the edges, as shown by element 4403.

[0377] Additionally, FIG. 44B illustrates a UV curable adhesive 4404.

[0378] Additionally, Figure 44B illustrates an optional waveguide layer 4405. The waveguide layer 4405 can be above and / or below the z-flexure structures. In one embodiment, the waveguide layer 4405 is made using SiO2, silicon nitride, and / or a UV-transparent polymer (e.g., acrylic).

[0379] Additionally, Figure 44B depicts incoupling gratings 4406 for coupling light (e.g., UV 4407) into the lateral waveguide structures 4405. These can be positioned near the periphery of the transfer substrate 3309 and / or in the kerf areas between the fields 401. These can optionally be patterned using Jet and Flash Imprint Lithography (J-FIL) on top of an imprint resist.

[0380] Additionally, Figure 44B illustrates a bulk portion 4408 (e.g., bulk silicon approximately 775 μm thick) of the transfer substrate 3309, which can be optionally perforated using an etching technique (e.g., catalytically influenced chemical etching (CICE) or deep reactive ion etching (DRIE), etc.) to allow UV exposure of the adhesive 4404 from the underside of the transfer substrate 3309.

[0381] Additionally, Figure 44B illustrates an optional encapsulation layer 4409 for the z-compliant structure 4410. In one embodiment, the encapsulation layer 4409 separates the internal structure of the z-compliant structure 4410 from the picked field 401. In one embodiment, the z-compliance of the encapsulation layer 4409 is varied by varying its thickness. In one embodiment, the encapsulation layer 4409 is made using silicon, polysilicon, silicon oxide, polymer, and / or metal (e.g., chromium).

[0382] Additionally, FIG. 44B illustrates an optional outcoupling grating 4411.

[0383]

[00101] Referring now to Fig. 44C, Fig. 44C is a close-up view of a z-compliant structure 4410. As shown in Fig. 44C, the z-compliant structure 4410 includes a flexure stem 4412. In one embodiment, the flexure stem 4412 is designed to buckle whenever the force on the field exceeds a certain value. Moreover, Fig. 44C illustrates a recess 4413 in the z-compliant structure 4410, which can be filled using an optional sacrificial material (e.g., silicon oxide, porous carbon, polyvinyl alcohol (PVA), etc.), which can be removed using an appropriate etchant at the end of fabrication.

[0384] Figure 44D is a close-up view of the top portion of the z-compliant structure 4410. As shown in Figure 44D, the secondary flexures 4414 allow bending of the central pad 4415 in the z direction while preventing substantial movement in the XY plane. In one embodiment, the mesa 4401 and adhesive 4404 can optionally sit above the central pad 4415.

[0385] Figure 44E is a close-up view of a central portion of the z-compliant structure 4410. As shown in Figure 44E, the flexure stem layer 4412 can be made of silicon (for example) and can be bonded to the remainder of the compliant layer using an appropriate bonding technique (e.g., covalent bonding).

[0386] Moreover, Fig. 44F is a close-up of a top view of the incoupling grating 4406 (e.g., for UV light). Additionally, Fig. 44F illustrates a top view of a cross section near the adhesive droplet 4416, showing drop staggering to allow the UV radiation being coupled into the waveguide layer 4405 to reach the maximum amount of the droplet before being absorbed or scattered.

[0387] FIG. 45 illustrates an alternative exemplary transfer substrate 3309, according to an embodiment of the present invention.

[0388] Referring to Fig. 45, Fig. 45 illustrates an optional mesa 4401 for capillary pinning of adhesive 4404. In one embodiment, mesa 4401 is made using a polymer and patterned using photolithography. In one embodiment, mesa 4401 is transparent to IR light 4501. Optionally, mesa 4401 can be embedded with nanoparticles that selectively absorb light at specific wavelengths (e.g., infrared light). These can be used to locally heat and cure two-part adhesive 4404.

[0389] FIG. 45 further illustrates an optional two-part adhesive 4404 (similar to the adhesive shown in FIG. 44B except that it is cured via IR radiation). In one embodiment, the adhesives 4404 are stored separately and dispensed together (e.g., using an inkjet) just prior to the field attachment step. In one embodiment, the adhesives 4404 can be optionally embedded with nanoparticles that selectively absorb light at specific wavelengths (e.g., infrared light 4501). These can be used to locally heat and cure the two-part adhesive 4404.

[0390] 44A-44F and 45, the transfer substrate 3309 is an intermediate substrate 801 on which the field 401 is temporarily assembled immediately prior to hybrid bonding (in an integration sequence) onto the product substrate 105. The field 401 is transferred from the transfer substrate 3309 to the product substrate 105, typically in a whole substrate fashion.

[0391] In one embodiment, the transfer substrate 3309 contains embedded structures that are selectively compliant in the Z direction while being rigid in the X and Y directions. Exemplary structures are shown in Figs. 44A-44F and 45. Such structures can be assembled by bonding together multiple 2D fabricated layers (using techniques such as laser machining, photolithography, etching, etc.). The recesses 4413 in the embedded structures can be filled with a sacrificial material (e.g., SiO2, water-soluble polyvinyl alcohol (PVA), porous carbon, etc.). The fill layer can be used to support the internal structure against collapse and damage, as well as any subsequent layers that may be grown on top of the already fabricated layers. The fill layer can be etched away at the end of the entire fabrication process using an appropriate etchant (e.g., HF for SiO2, water for PVA, etc.). The filler layer and internal structure may be coated with an encapsulation layer 4409 composed of SiO2, spin-on glass (SOG), metal, polymer, silicon, and / or polysilicon. In one embodiment, the encapsulation layer 4409 is capped with a metal layer that aids in the internal reflection of light within the light guide layer.

[0392] In one embodiment, the in-plane distortion of the transfer substrate 3309 is controlled using thermal actuation (e.g., Peltier cooler, infrared radiation based localized heating source) and mechanical actuation techniques. In one embodiment, thermal actuation is utilized to extract excess heat generated during adhesive curing using, for example, UV radiation. Optionally, a highly thermally conductive adhesive can be used to facilitate the heat transfer process.

[0393] In one embodiment, the transfer substrate 3309 is custom made for each new SiP. In one embodiment, the encapsulation layer 4409, the mesa layer 4401, and the incoupling lattice layer 4406 are custom patterned for each SiP.

[0394] In one embodiment, to prevent interference between the transfer substrate facing surface of the TC 111 (when placing the picked up field 401 on the transfer substrate 3309 by the TC 111) and the pre-existing field 401 on the transfer substrate 3309, a short plasma strip step can be used to reduce the thickness of the encapsulation layer 4409 above the pre-existing field 401. The plasma can be an atmospheric pressure plasma.

[0395] In one embodiment, to prevent interference between the transfer / source / intermediate substrate-facing surface of TC111 and the pre-existing field 401 on the transfer / source / intermediate substrate 3309 / 103 / 801 (when placing the picked up field 401 on the transfer / source / intermediate substrate 3309 / 103 / 801 by the TC111), a repulsive force can be created between the pre-existing field 41 on the transfer / source / intermediate substrate 3309 / 103 / 801 and the transfer / source / intermediate substrate-facing surface of TC111. This force can be created by pushing air out of the ACM 3903 (which is in the TC111) at the pre-existing field location to create a thin cushion of air that separates the pre-existing field 401 from the substrate-facing surface of TC111. Alternatively, this force can be created by charging the substrate-facing surface of the TC 111 and the TC-facing surface of the pre-existing field 401 with charges of like polarity to create an electrostatic repulsion between the surfaces. In one embodiment, the compliance of the z-flexure structure 4412 (also referred to as the "flexure stem") inside the transfer / source / middle substrate 3309 / 103 / 801 can be varied to aid in creating a gap between the TC and the field during the installation step.

[0396] In one embodiment, one or more of the mesa layer 4401, the waveguide layer 4405, the encapsulation layer 4409, and the z-compliant structure 4410 in the transfer substrate 3309 are fabricated using a material with high thermal conductivity (e.g., metal, silicon, high thermal conductivity composite polymer containing high thermal conductivity fillers) to enable vertical and lateral transport of heat away from the field 401 and towards the bulk of the transfer / source / intermediate substrate 3309 / 103 / 801 and the transfer chuck 111.

[0397] In one embodiment, the thickness of the mesa structure 4401 is increased to increase the local X,Y compliance of the transfer / source / intermediate substrate 3309 / 103 / 801. In one embodiment, the volume of the adhesive droplet 4416 is increased to increase the pinned height of the adhesive 4404 to increase the effective local X,Y compliance of the transfer / source / intermediate substrate 3309 / 103 / 801.

[0398] 46A-46B illustrate an exemplary interference prevention method (during field assembly onto a transfer substrate 3309) according to an embodiment of the present invention.

[0399] 46A, which illustrates an exemplary field 4601 already assembled on a transfer substrate 3309. The field 401 shown has a greater thickness (for example) compared to the assembled field 401. Without interference prevention methods, this would interfere with the ACM 3903 as it assembles the field 401 on the transfer substrate 3309.

[0400] Additionally, FIG. 46A illustrates field 4602 currently assembled on transfer substrate 3309.

[0401] Figure 46B is a close-up view of a portion of the transfer substrate 3309. As shown in Figure 46B, the local air pressure and / or electrostatic repulsion force 4603 generated by the ACM 3903 (at the location of the already assembled field 4601) prevents interference between the field and the TC / ACM 111 / 3903 during assembly.

[0402] Additionally, as shown in FIG. 46B, the flexure structure 4412 in the transfer substrate 3309 helps reduce interference.

[0403] 47A-47E, which illustrate an exemplary source substrate 103 according to an embodiment of the present invention.

[0404] As shown in FIG. 47A, FIG. 47A illustrates the source substrate 103. FIG. 47B illustrates a close-up of a cross-section of the source substrate 103. FIG. 47B illustrates an optional mesa 4701 (area above the source substrate 103 where the substrate 103 has not been etched away) for capillary pinning of the adhesive. In one embodiment, the mesa 4701 is made using a polymer and patterned (e.g., via photolithography, etc.). In one embodiment, the mesa 4701 is transparent to IR light. In one embodiment, the mesa 4701 can be embedded with nanoparticles that selectively absorb light (e.g., infrared light) at specific wavelengths. These can be used to locally heat and cure the two-part adhesive.

[0405] Additionally, as shown in FIG. 47B, a small amount of source substrate adhesive 4702 can optionally be left on the underside of field 401 after pick-up from source substrate 103.

[0406] Moreover, Figure 47B illustrates two exemplary adjacent fields 401. In one embodiment, the fields 401 have their active sides facing upwards (away from the source substrate 103). Height variations of the fields 401 can be compensated for by z-compliant flexures, adhesive drop volume adjustments, and by making the fields 401 cantilevered near the edges.

[0407] Additionally, FIG. 47B illustrates optional UV radiation 4703 for transient material activation.

[0408] Moreover, FIG. 47B illustrates a bulk portion 4704 of the source substrate 103 (eg, approximately 775 μm thick bulk silicon or silicon layer with perforations made using suitable etching techniques).

[0409] Additionally, FIG. 47B illustrates an optional encapsulation layer 4705 for the z-compliant structure 4706. In one embodiment, the encapsulation layer 4705 separates the internal structure of the z-compliant structure 4706 from the picked field 401. In one embodiment, the z-compliance of the encapsulation layer 4705 is varied by varying its thickness. In one embodiment, the encapsulation layer 4705 is made using silicon, polysilicon, silicon oxide, polymer, and / or metal (e.g., chromium).

[0410] Additionally, Figure 47B illustrates an optional transitional material (glue) 4707. In one embodiment, the transitional material 4707 is inkjetted onto the mesa layer 4701. A phase transition can be induced using, for example, heat or UV radiation. Optionally, the transitional material 4707 can be embedded with nanoparticles that selectively absorb light (e.g., infrared light) at specific wavelengths. These can be used to locally heat the material.

[0411] 47C, which is a close-up view of a z-compliant structure 4706. As shown in FIG. 47C, the z-compliant structure 4706 includes a flexure stem 4708. In one embodiment, the flexure stem 4708 is designed to buckle whenever the force on the field exceeds a certain value. Additionally, FIG. 47C illustrates a recess 4709 in the z-compliant structure 4706, which can be filled using an optional sacrificial material (e.g., silicon oxide, porous carbon, polyvinyl alcohol (PVA), etc.), which can be removed using an appropriate etchant at the end of fabrication.

[0412] Figure 47D is a close-up view of the top portion of the z-compliant structure 4706. As shown in Figure 47D, the secondary flexure 4710 allows bending of the central pad 4711 in the z direction while preventing substantial movement in the XY plane. In one embodiment, the mesa 4701 and adhesive 4707 can optionally sit above the central pad 4711.

[0413] Figure 47E is a close-up view of a central portion of the z-compliant structure 4706. As shown in Figure 47E, the flexure stem layer 4708 can be made of silicon (for example) and can be bonded to the remainder of the compliant layer using an appropriate bonding technique (e.g., covalent bonding).

[0414] In one embodiment, the source substrate 103 can consist of the field 401 attached to a transparent carrier substrate (e.g., glass, fused silica, sapphire) or tape frame carrier film using an adhesive (e.g., adhesive 4707). The adhesive can be a continuous film, the thickness of which varies to compensate for thickness variations in the field 401, or the adhesive is separated into islands, the X / Y extent and thickness of which vary to account for different X / Y extent and thickness of the field 401. In one embodiment, such a source substrate 103 is fabricated by starting with the field 401 on a substrate with a sacrificial layer (e.g., silicon-on-oxide (SOI), silicon-on-sapphire (SOS)), inverting and adhering a suitable carrier substrate to it in a whole substrate manner, and removing the bulk of the starting substrate using a suitable etchant. In one embodiment, the starting substrate consists of the field 401 fabricated on a silicon layer overlying a sacrificial silicon-germanium (SiGe) layer. Such SiGe layers can be grown using epitaxial deposition techniques. Etching of the sacrificial silicon-germanium layer can be performed using wet etching, plasma etching, atomic layer etching, and hybrid etching methods. In one embodiment, an etchant composed of vaporized HF, vaporized H2O2, and vaporized acetic acid is used.

[0415] Figure 48 is a flow chart of a method 4800 for generating a source substrate for assembly from a substrate with a sacrificial layer, according to an embodiment of the invention. Figures 49A-49F depict cross-sectional views for generating a source substrate for assembly from a substrate with a sacrificial layer using the steps described in Figure 48, according to an embodiment of the invention.

[0416] Referring to Figure 48 in conjunction with Figures 49A-49F, in step 4801, a partial etch of the sacrificial layer 4903 is performed to generate tethers as shown in Figures 49A-49B. Figure 49A illustrates singulated field 4901 with an active layer on top. Additionally, Figure 49A illustrates access holes 4902 for the sacrificial layer etchant, and sacrificial layer 4903 on top of bulk substrate 4904. Additionally, Figure 49A illustrates field kerf 4905.

[0417] As discussed above, in step 4801, a partial etch of sacrificial layer 4903 is performed to produce tethers 4906, as shown in Figure 49B.

[0418] In step 4802, as shown in Figure 49C, the bulk substrate 4904 is inverted and temporarily attached to an intermediate substrate 4907 via adhesive 4908. In one embodiment, the intermediate substrate 4907 is made using silicon, silicon carbide, silicon oxide, fused silica, sapphire, polymer films, and / or tape frames.

[0419] In step 4803, the bulk substrate 4904 is separated using a sacrificial layer etch, as shown in Figure 49D. In one embodiment, the bulk substrate 4904 (also referred to as a "carrier substrate") is always attached to a carrier substrate chuck. The carrier substrate chuck can optionally be sacrificial etchant resistant, for example, made using polytetrafluoroethylene (PTFE) and / or sapphire.

[0420] In step 4804, as shown in Figure 49E, the intermediate substrate 4907 is flipped over and temporarily attached to a source substrate 4909 for assembly (e.g., source substrate 103) using adhesive islands 4910. In one embodiment, the source substrate 4909 is fabricated using silicon, silicon carbide, silicon oxide, fused silica, sapphire, polymer film, and / or tape frame.

[0421] In step 4805, intermediate substrate 4907 (along with adhesive 4908) is removed (eg, via an etching technique, etc.), thereby leaving source substrate 4909 with fields 4901, as shown in FIG. 49F.

[0422] Further discussion regarding method 4800 is provided below.

[0423] In one embodiment, the field 401, 4901 contains access holes distributed throughout the area of ​​the field 401, 4901. Etchant for the sacrificial layer (e.g., sacrificial layer 4903) can be fed through the access holes 4902 in addition to feeding from the edge of the field 401, 4901 (during the tether formation etch and bulk substrate separation). In one embodiment, the XY pitch for the access holes 4902 is 20 μm. In one embodiment, the silicon layer above the sacrificial layer 4903 is about 300 nm thick. In one embodiment, the sacrificial layer 4903 (e.g., SiGe or SOI) is about 0.5 μm thick if a vapor etchant is used, or about 5 μm thick if a wet etchant is used with the value selected to allow sufficient lateral transport of the sacrificial layer etchant.

[0424] In one embodiment, the thickness of the mesa structure 4401 (shown in FIG. 45) is increased to increase the local X,Y compliance of the source substrate 103, 4909. In one embodiment, the volume of the adhesive droplet 4416 (see FIG. 44F) is increased to increase the pinned height of the adhesive 4404 and increase the effective local X,Y compliance of the source substrate 103, 4909.

[0425] In one embodiment, the thickness of the fields 401, 4901 can be modulated using one or more of subtractive methods (e.g., inkjet-based planarization) and additive methods (e.g., adding material to the backside using inkjet, chemical vapor deposition, spin coating, etc.) during backgrinding or during the source wafer generation process (on an intermediate carrier substrate) shown in Figures 47A-47E when the fields 401, 4901 are lying active side down. In one embodiment, the carrier substrate 4904 (which can be made of silicon, silicon oxide, sapphire, fused silica, etc.) is polished to be highly flat and is used as a reference for the fields 401, 4901 attached to the substrate. The field height above the carrier substrate 4904 can be measured using an appropriate topography measurement technique by measuring the change in topography between the kerf 4905 and the edge of the respective field 401, 4901. In one embodiment, an air gauge based thickness measurement method is used to measure the thickness of the fields 401, 4901.

[0426] Adhesives described herein can be used to attach the fields 401, 4901 to the source, intermediate, transfer, and carrier substrates 103, 801, 3309, 4904, as well as the transfer chuck (TC) 111. The adhesives can consist of UV release adhesives, thermal release adhesives, light-to-heat conversion (LTHC) coatings, liquid crystal (LC) based adhesives, UV phase switching LC based adhesives, etc.

[0427] In one embodiment, the adhesive layer is composed of one or more layers of a first light absorbing layer and a layer of a transitional material. The light absorbing layer can be a purely polymeric layer (e.g., LTHC coating manufactured by 3M®) or a composite of polymer and nanoparticles optimized for light absorption. In one embodiment, the fields 401, 4901 can be coated on their underside and / or in their entirety with an adhesive coating (e.g., VALMat) that adheres to the transitional material.

[0428] In one embodiment, the adhesive droplets 4416 are dispensed an appropriate distance away from the edges of the fields 401, 4901 such that the cantilevered fields (near the edges of the fields 401, 4901) bend to accommodate any residual height difference between adjacent fields 401, 4901 during hybrid bonding. Such bending does not necessarily lead to significant overlay errors if the thickness of the fields 401, 4901 is small.

[0429] In one embodiment, a light-to-heat conversion (LTHC) layer is used to locally heat and / or vaporize the adhesive. The LTHC layer can be comprised of one or more of the resonant absorber layers. In one embodiment, the LTHC contains embedded nanoparticles that are designed to absorb radiation in a narrow wavelength range (ideally at wavelengths where one or more of the TC111, source substrate 103, transfer substrate 3309 show minimal or zero optical absorption). In one embodiment, the adhesive is comprised of polyimide. In one embodiment, the adhesive is comprised of a polyimide-LTHC based release layer.

[0430] In one embodiment, the nanoparticles used for light absorption in the LTHC layer are made using gold, silicon, ruthenium, noble metals, titanium, and / or tungsten, hi one embodiment, the size of the nanoparticles is increased to increase their melting point (e.g., the melting point of gold nanoparticles decreases as the size of the nanoparticles decreases).

[0431] 50A-50C illustrate an exemplary yield management flow according to an embodiment of the present invention.

[0432] Referring now to FIG. 50A, FIG. 50A illustrates an example SIP 5001 on a transfer substrate 3309 and shows four example known bad die (KBD) 2605 that need to be replaced with known good die (KGD) 2603 from the buffer substrate.

[0433] 50B, which illustrates a known good die (KGD) 2603 on various active buffer substrates 5002A-5002N, where N is a positive integer (5002A identified as "active buffer substrate 1," 5002B identified as "active buffer substrate 2," and 5002N identified as "active buffer substrate N.") The active buffer substrates 5002A-5002N may be referred to collectively or individually as multiple active buffer substrates 5002 or active buffer substrates 5002, respectively.

[0434] At any one time, there are N (N is a positive integer) active buffer substrates 5002 being maintained. In one embodiment, these are maintained at all times to a low level of depletion such that the KBD exchange step for any given transfer wafer 3309 can be completed in at most one or two pick and place steps.

[0435] 50C illustrates a series of inactive buffer substrates 5003A-5003N, where N is a positive integer (5003A identified as "inactive buffer substrate 1," 5003B identified as "inactive buffer substrate 2," and 5003N identified as "inactive buffer substrate N.") Inactive buffer substrates 5003A-5003N may be referred to collectively or individually as multiple inactive buffer substrates 5003 or inactive buffer substrates 5003, respectively.

[0436] As shown in FIG. 50C, the die 901 from the most depleted inactive buffer substrate 5003 (e.g., inactive buffer substrate 5003N) is assembled in a die-by-die manner using one or more die-by-die transfer chucks to the least depleted inactive buffer substrate 5003 (e.g., inactive buffer substrate 5003A), as indicated by arrow 5004 in FIG. 50C.

[0437] Moreover, as shown in Figures 50B and 50C, the least depleted inactive buffer substrate 5003 (e.g., inactive buffer substrate 5003A) can be sent to the active set of buffer substrates 5002 when one of the active buffer substrates 5002 reaches a pre-specified threshold level of depletion, as indicated by arrow 5005.

[0438] 51A-51D illustrate an exemplary method for dicing and alignment mark creation, according to an embodiment of the present invention.

[0439] FIG. 51A illustrates an undiced field 5101 with the device layer facing towards the adhesive 5102 on the carrier substrate 3302.

[0440] Moreover, FIG. 51B is an enlarged view of the upper layers of the carrier substrate 3302 shown in FIG. 51A. As shown in FIG. 51B, FIG. 51B illustrates the device structure 5103 residing on the encapsulation layer 5104. Moreover, FIG. 51B illustrates the adhesive layer 5102, which can be an optional etch stop. Additionally, FIG. 51B illustrates a layer 5105 for creating metal breaks. Moreover, FIG. 51B illustrates an optional catalyst 5106 for creating alignment marks using CICE. Additionally, FIG. 51B illustrates the kerf region 5107, where an enlarged view of the kerf region 5107 is shown in FIG. 51C.

[0441] As shown in FIG. 51C, the kerf area 5107 includes alignment marks 5108.

[0442] Moreover, plasma etching for field dicing is shown in Fig. 51D. As shown in Fig. 51D, alignment marks 5109 are generated using CICE. As further shown in Fig. 51D, diced edges 5110 are generated using plasma etching.

[0443] In one embodiment, alignment marks 5108, 5109 are generated in the field during singulation.

[0444] In one embodiment, the alignment marks 5108, 5109 are generated on the backside of the field. For example, photolithography (PL) or nanoimprint lithography (NIL) can be used for patterning the marks 5108, 5109. In another example, deep reactive ion etching (DRIE) can be used for dry etching the marks 5108, 5109. In a further example, CICE can be used for etching the marks 5108, 5109. The marks 5108, 5109 can be located below the circuit pattern or near the kerf region 5107 away from the circuit area. In one embodiment, the marks 5108, 5109 can be etched all or part through the thickness of the field.

[0445] The singulation of the fields can be performed using a separate set of patterning and etching techniques (compared to the alignment mark generation step). Photolithography (PL) or nanoimprint lithography (NIL) can be used for patterning. Dry etching (e.g., DRIE) can be used for etching. Moreover, wet etching (e.g., CICE) can be used for etching. Alternatively, the singulation can be performed using laser-based methods (e.g., laser cutting, etc.) or stealth dicing.

[0446]

[00106] Referring now to Figure 52A, which illustrates aligning a picked field 401 on a TC 111 to a stable reference grid, in accordance with an embodiment of the present invention. In particular, Figure 52A illustrates an upward looking microscope 5201 for aligning the picked field 401 to the stable reference grid and / or to the TC 111.

[0447] FIG. 52A further illustrates that an optionally linked microscope resides on a separate VPM 5202, which can be calibrated against a stable reference grid.

[0448] Reference is now made to FIG. 52B, which illustrates aligning the position of the ACM 3903 relative to a stable reference grid 5203 (eg, a stable grid plate), in accordance with an embodiment of the present invention.

[0449] 52B, integrated light source and sensor pairs 5204A-5204B, 5204C-5204D are used to transmit the displacement of the ACM 3903 relative to a stable reference grid 5203 (e.g., a stable grid plate). The integrated light sources and sensors 5204A-5204D, collectively or individually, can be referred to as multiple integrated light sources and sensors 5204 or integrated light source and sensor 5204, respectively.

[0450] 52A-B, in one embodiment, a microscope 5201 facing up is used to measure the position of the field 401 relative to a global grid or alignment relative to the TC 111 at an alignment mark location on the field 401 when the field 401 is picked up on the TC 111. In one embodiment, the microscope 5201 facing up is mounted on a reconfigurable VPM (such as VPM 5202). In one embodiment, the position of the microscope 5201 facing up can be measured relative to a stable 2D grid and grid encoder attached to the microscope 5201. The position of the microscope 5201 on the VPM (such as VPM 5202) can be calibrated once, calibrated intermittently, or actively observed during every pick and place step. Alternatively, the position of the upward looking microscope 5201 can be measured using moiré based metrology, where one set of moiré marks is placed on the microscope 5201, another set of moiré marks is placed on a stable reference substrate, and a moiré microscope is used to observe the relative positions of the upward looking microscope 5201 and the corresponding set of marks on the reference substrate. In one embodiment, the source substrate 103 is used to assemble multiple transfer substrates 3309, such that the VPM (e.g., VPM 5202, etc.) for the upward looking microscope 5201 only has to be reconfigured when a new source substrate is loaded.

[0451] In one embodiment, the fields 401 from the source substrate 103 picked up by the TC 111 are sampled at a limited set of locations using an upward looking microscope 5201 to measure the positions of those fields 401 relative to a stable reference grid 5203 and / or relative to the TC 111. The remaining positions of the picked fields 401 above the TC 111 can be extrapolated using appropriate position extrapolation techniques.

[0452] The alignment marks on the field 401 can be viewed from the bottom side of the TC111, directly from above the TC111, or from above the TC111 with the alignment signals fed through incoupling gratings 4406 (which are used to send UV light in for adhesive curing). Interference of the alignment signals with circuit elements on the field 401 (for example) can be filtered out using computational methods or by designing the positions of the alignment marks to avoid them interfering with the structures.

[0453] In one embodiment, the position of the ACM3903 on a VPM (such as the VPM4302) can be directly observed with respect to a stable 2D grid. A compact grid encoder can be integrated onto the ACM3903 and used to view the 2D grid plate to measure the displacement of the ACM3903 in real time during assembly.

[0454] In one embodiment, the transfer substrate 3309 contains a grid of alignment marks. The grid of alignment marks can be optionally patterned on the mesas (e.g., mesa 4401) in the transfer substrate 3309 using the same technique (e.g., i-line lithography) used to fabricate the mesas (e.g., mesa 4401). In one embodiment, the incoming field 401 is aligned to the grid of alignment marks on the transfer substrate 3309. Incoming field position errors from the optional upward microscope 5201 and from an alignment microscope to measure the alignment between the transfer substrate 3309 and the field 401 can be corrected by a set of thermal actuators on the transfer substrate chuck.

[0455] In one embodiment, the zero layer for all fields 401 are fabricated on the same lithography tool (this includes fields of different types, not simply different fields of the same type).

[0456] In one embodiment, the field-facing surface of the TC 111 is polished to be highly flat to act as a reference flat for the picked and placed field 401. In one embodiment, the surface of the TC 111 is actively modulated in the z-direction to achieve a flat or desired non-flat profile.

[0457] In one embodiment, the production wafer chuck 104 contains actuators for planarizing the surface of the production wafer 105 prior to hybrid bonding. Sensing of the topography on the production wafer 105 can be performed using laser-based methods, air gauges, etc. Actuation of the wafer chuck can be performed using piezoelectric actuators, thermal actuators, and / or electromagnetic actuators.

[0458] Reference is now made to FIGS. 53A-B, which illustrate an exemplary approach for metal-assisted catalytic etching (MACE) based dicing using an inkjetted catalyst, in accordance with an embodiment of the present invention.

[0459] As shown in FIG. 53A, the kerf area 5107 includes alignment marks 5301, as well as optional diced edge stabilization structures 5302 and diced edges 5303.

[0460] Figure 53B is a close-up of the layers above adhesive layer 5102. As shown in Figure 53B, there is an optional shallow etched recess 5304 to improve etchant containment, a meniscus containing etchant droplets 5305, and inkjetted catalyst 5306. Additionally, Figure 53B illustrates that cut thickness 5307 can optionally be on the sub-micrometer scale.

[0461] Reference is now made to FIGS. 54A-B, which illustrate an alternative exemplary approach for MACE-based dicing using inkjetted catalyst, in accordance with an embodiment of the present invention.

[0462] As shown in Figure 54A, a knife edge dicer frame 5401 with a catalyst coated knife edge 5402 is used to dice the fields 401. A close-up of such a process is shown in Figure 54B.

[0463] As shown in Figure 54B, the knife edge dicer frame (e.g., silicon) can include an etchant inlet portion 5403 and an etchant outlet portion 5404. Additionally, as shown in Figure 54B, there is an optional protective layer 5405 (e.g., carbon) for the dicer frame 5401. Additionally, as shown in Figure 54B, there is a meniscus containing etchant droplets 5406 and a catalyst film 5407, where the cut thickness 5408 can optionally be on the sub-micrometer scale.

[0464] The following discussion is based on Figures 53A-53B and 54A-54B.

[0465] The MACE can be used to dice the substrate into fields 401 .

[0466] In one embodiment, the diced edges are straight. In another embodiment, the diced edges have one or more curved or angled elements (e.g., 90 ° It is possible for the grooves to have corners, etc.

[0467] In one embodiment, a MACE catalyst is dispensed onto the undiced substrate (e.g., undiced field 5101) using one or more inkjets. In one embodiment, the catalyst is gold. After dicing, the catalyst can be removed using an etchant (e.g., aqua regia for gold catalyst).

[0468] In another embodiment, the knife edge dicer frame 5401 is used to etch into a substrate (e.g., substrate 3302). In one embodiment, the knife edge 5402 is coated with a MACE catalyst. In one embodiment, the knife edge 5402 is coated with a protective layer (e.g., a carbon layer). In one embodiment, the knife edge 5402 has intermittent stabilization structures.

[0469] In one embodiment, the MACE etchant covers the entire substrate (e.g., substrate 3302). In one embodiment, the MACE etchant is dispensed using an inkjet near the kerf region 5107 of field 401. In one embodiment, the MACE etchant is contained near the kerf region 5107 using a recess etched prior to dicing. In one embodiment, the MACE etchant is contained near the kerf region 5107 using surface tension.

[0470] In one embodiment, the MACE etchant is circulated to prevent etch stagnation. In one embodiment, the etchant circulation is implemented within the vicinity of the kerf region 5107.

[0471] In one embodiment, field 401 is coated with a protective layer to protect against chemical damage during dicing and catalyst removal.

[0472] In one embodiment, the knife edge dicer frame 5401 has a flexure mechanism to provide compliance along the Z axis. In one embodiment, the knife edge dicer frame 5401 has a flexure mechanism to provide compliance along the Z axis for each field 401.

[0473] In one embodiment, the dicing edge has a cross-section that is optimized to reduce dishing and etch stagnation tendencies. In one embodiment, the dicing edge has a trapezoidal cross-section in the etched area. The trapezoidal cross-section can be produced using a crystallographic etch (e.g., a KOH-based etch).

[0474] In one embodiment, the dicing edge has orthogonal structures to provide mechanical support.

[0475] In one embodiment, an etch-based dicing technique (e.g., MACE-based dicing) is used to generate the non-straight field edges. In one embodiment, an etch-based dicing technique (e.g., MACE-based dicing) is used to singulate the field 401 such that the alignment marks 5301 over the kerf region 5107 are retained after dicing.

[0476] 55A-B, which illustrate an exemplary method for substrate dicing after backgrinding, according to an embodiment of the present invention.

[0477] As shown in FIG. 55A, the kerf area 5107 (e.g., 40 μm wide) includes a full-sized alignment mark 5301 (e.g., 38 μm wide) as well as optional diced edge stabilization structures 5302 and diced boundaries / edges 5303 (e.g., 1 μm).

[0478] Figure 55B is a close-up view of the layers above adhesive layer 5102. As shown in Figure 55B, catalyst 5501 is present at the dicing boundary.

[0479] Reference is now made to FIG. 56, which illustrates an exemplary method for creating dices in a source substrate 103 prior to backgrinding, according to an embodiment of the present invention.

[0480] In particular, Figure 56 is a close-up view of the layers above adhesive layer 5102. As shown in Figure 56, there is an encapsulation layer 5601 above device structure 5103, and there is also a catalyst 5501 at the dicing boundary, which is now located below device structure 5103, as opposed to being located at the same level as layer 5105 to create a metal break as shown in Figure 55B.

[0481]

[00106] Reference is now made to Fig. 57, which is a flow chart of a method 5700 for creating metal breaks for substrate dicing using metal-assisted chemical etching, according to an embodiment of the invention. Figs. 58A-C depict cross-sectional views for creating metal breaks for substrate dicing using metal-assisted chemical etching using the steps described in Fig. 57, according to an embodiment of the invention.

[0482] 58A-58C, in step 5701, ultraviolet (UV) curing is performed to cure catalyst break layer 5802, as shown in FIG. 58A-58B. As shown in FIG. 58A, a UV curable layer for catalyst break 5802 is present on substrate 5801 to be diced. Moreover, as shown in FIG. 58A, a template with mesas 5803 (such as mesa 5804) is present on catalyst break layer 5802. When UV curing is performed, catalyst break layer 5802 is cured, resulting in layer 5805 as shown in FIG. 58B.

[0483] Additionally, in step 5701, an optional plasma etch can be performed to improve the profile of catalyst break layer 5802, resulting in removal of template 5803, as shown in FIG. 58B.

[0484] In step 5702, a catalyst 5806 is deposited over the catalyst breaks 5805 and a UV curable layer for the substrate 5801, as shown in Figure 58C.

[0485] The following discusses Figures 55A-B, 56, 57, and 58A-C.

[0486] In one embodiment, the dicing process is performed from the front-side or the back-side of the source substrate 103. In one embodiment, the process is performed from the front-side of the source substrate 103 that is bonded to the carrier substrate 3302, or from the back-side of the source substrate 103 with the front-side bonded to the carrier substrate 3302. In one embodiment, the process is performed on a back-ground substrate that is attached to the carrier substrate 3302.

[0487] In one embodiment, the etching process for silicon-containing regions of the device stack is CICE. In one embodiment, the etching process for silicon components of the device stack is silicon electrochemical etching. In one embodiment, the etching process for non-silicon-containing regions of the device stack (e.g., silicon oxide, metal, non-silicon substrate (e.g., germanium, gallium arsenide, silicon carbide, etc.)) is a physical etching process, such as deep reactive ion etching (DRIE) or a wet etching process (e.g., etching using an etchant containing hydrofluoric acid in liquid or vapor form).

[0488] In one embodiment, the unetched parts of the device stack (e.g., metal lines that may remain unetched after exposure to (e.g.) HF etching) are etched last using a more aggressive cleaning etch (e.g., using aqua regia, nitric acid, etc.). In one embodiment, the unetched parts of the device stack containing copper are etched using ferric chloride, cupric chloride, alkaline etchants, mixtures of hydrogen peroxide and sulfuric acid, chromic sulfuric acid, sodium chlorate, citric acid, ammonium persulfate, etc. In one embodiment, the etchant for the unetched parts of the device stack is appropriately diluted so that it has reduced or no activity against device encapsulation layers, oxide layers, and other functional device layers. In one embodiment, the etchant is removed after etching using a spray of diluent (e.g., water).

[0489] In one embodiment, the device layers inside field 401 are protected during the etching process using an encapsulation layer (e.g., encapsulation layer 5601, etc.). In one embodiment, the encapsulation layer (e.g., encapsulation layer 5601, etc.) is composed of a precious metal, a non-precious metal, a non-metal, and / or a polymer. In one embodiment, the encapsulation layer (e.g., encapsulation layer 5601, etc.) is composed of CVD carbon. In one embodiment, the encapsulation layer (e.g., encapsulation layer 5601, etc.) is composed of parylene, a fluoropolymer (e.g., PTFE), and / or carbon (e.g., CVD deposited or spin coated). In one embodiment, the encapsulation layer (e.g., encapsulation layer 5601, etc.) is electrically insulating. In one embodiment, the encapsulation layer (e.g., encapsulation layer 5601, etc.) contains silicon oxide.

[0490] In one embodiment, the encapsulation layer (e.g., encapsulation layer 5601, etc.) is patterned using photolithography or nanoimprint lithography. In one embodiment, the encapsulation layer (e.g., encapsulation layer 5601, etc.) is deposited using inkjet. In one embodiment, the encapsulation layer (e.g., encapsulation layer 5601, etc.) is patterned using a discontinuous film generated by fluid pinning with a patterned template.

[0491] In one embodiment, the etchant for the chemical dicing process (e.g., using MACE) is dispensed (e.g., using an inkjet) only near the area to be etched or is held in a chamber to cover the entire substrate including the area to be etched. In one embodiment, an inkjet is used for etchant dispensing and all wetted areas of the inkjet are coated with an etchant inert layer (e.g., a fluoropolymer, e.g., PTFE, parylene, etc.).

[0492] With respect to MACE-based dicing, in one embodiment, the etch catalyst (e.g., catalyst 5106, etc.) is comprised of a precious metal, a non-precious metal, a non-metal, a polymer, and / or a ceramic. In one embodiment, the catalyst (e.g., catalyst 5106, etc.) is comprised of Au, Ag, Ru, Pt, Pd, C, Ta, W, Cu, Al, and / or Ni. In one embodiment, the catalyst (e.g., catalyst 5106, etc.) is a bilayer of gold and silver, with the silver underlaying and encapsulated by the gold. In one embodiment, the etch catalyst (e.g., catalyst 5106, etc.) is dispensed as a nanoparticle ink using an inkjet. In one embodiment, the etch catalyst (e.g., catalyst 5106, etc.) is electroplated. In one embodiment, the etch catalyst (e.g., catalyst 5106, etc.) is deposited using a physical vapor deposition technique (e.g., sputtering, e-beam deposition, etc.). In one embodiment, the etchant is deposited using techniques that create sidewalls with a line edge roughness (LER) below 10 nm (1σ, or 3σ), for example, using physical vapor deposition techniques (e.g., e-beam, focused ion beam, sputtering), electroplating, and / or electroless plating. In one embodiment, the catalyst (e.g., catalyst 5106, etc.) contains a thin film of silicon oxide underneath to improve etch uniformity. In one embodiment, the thickness of the silicon oxide film is between 10 nm and 100 nm. In one embodiment, the etch rate of the catalyst (e.g., catalyst 5106, etc.) is controlled by temperature, pH of the etchant solution (using a buffer solution, e.g., HF and NH4OH, or NHF), plasma treatment of the etchant, alloying the catalyst with a material (e.g., carbon) that has a lower activity for MACE using combinatorial sputtering.

[0493] In one embodiment, a catalyst (such as, for example, catalyst 5106) is dispensed onto a discontinuous polymer film created by fluid pinning (of a UV-curable polymer) with a patterned template and subsequent UV exposure (of a UV-curable polymer). In one embodiment, the catalyst (such as, for example, catalyst 5106) contains breaks at the edges between the polymer and the substrate (such as, for example, substrate 3302). In one embodiment, plasma-based cleaning is used to clean the edges of the polymer to create improved metal breaks.

[0494] In one embodiment, the MACE based dicing is stopped in a timed manner or, in cases where an adhesive film (such as, for example, adhesive film 5102) is available (where the substrate is attached to a carrier substrate), the adhesive film is used as an etch stop. In one embodiment, the adhesive film (such as, for example, adhesive film 5102) is coated with an etchant resistant material (such as, for example, carbon).

[0495] Once dicing is complete, the catalyst (e.g., catalyst 5106, etc.) is removed using a suitable etchant (e.g., an aqua domain for gold (or an etchant containing potassium iodide, cyanide, etc.)) or an atomic layer etching process, or, in certain cases where partial dicing is performed before backgrinding, the backgrinding process can also discard the catalyst by grinding it away.

[0496] In one embodiment, the diced edge geometry along the straight edge of field 401 is composed of curved and / or angled components. In one embodiment, the alignment marks (e.g., mark 5301, etc.) are contained within the curved portion of the diced edge 5303. In one embodiment, the diced edge 5303 contains support structures (e.g., structure 5302, etc.) to prevent wandering. Such support structures can be on the exterior or interior portions of the diced edge 5303. The alignment marks (e.g., mark 5301, etc.) contain recesses to accommodate the support structures (e.g., structure 5302, etc.). In one embodiment, image processing techniques are utilized to filter out loss of alignment signal due to recesses in the alignment marks (e.g., mark 5301, etc.). The recesses created in the alignment marks (such as, for example, mark 5301) can be filled after dicing using an appropriate material deposition technique (e.g., CVD (silicon, silicon oxide, etc.), ALD, etc.).

[0497] In one embodiment, a catalyst film (such as, for example, catalyst 5106) deposited on the metal break layer 5105 is used to create an electrostatic attraction between the die and the transfer chuck 111.

[0498] High aspect ratio, non-porous, non-tapered semiconductor nanostructures can be fabricated using CICE. CICE is also described as metal-assisted chemical etching (MACE). For CICE of silicon, a catalyst including one or more of Au, Pt, Pd, Ag, Ru, Ir, W, Cu, TiN, Ti, graphene, carbon, etc. (in alloy form, if necessary) catalyzes the reduction of H2O2 and injects the resulting electron holes into the silicon, thereby changing the oxidation state of the silicon. In one embodiment, HF selectively etches the silicon, and the catalyst sinks into the etched regions, continuing the local redox reaction, thereby creating silicon nanostructures in the catalyst-free areas. The quality of the resulting silicon nanostructures depends critically on the balance of reaction kinetics, charge transfer, etchant mass transfer, and catalyst movement. In one embodiment, the substrate for the CICE is comprised of one or more of the following: a single crystal bulk silicon wafer, a layer of polysilicon deposited on a substrate, a layer of amorphous silicon deposited on a substrate, an SOI (silicon-on-insulator) wafer, silicon-on-glass, silicon-on-sapphire, epitaxial silicon on a substrate, alternating layers of semiconductor material of varying doping levels and dopants, highly doped silicon and lightly doped silicon, undoped silicon and doped silicon or germanium, silicon and Si x Ge 1-x , differently doped silicon and / or Si x Ge 1-x , differently doped silicon and / or Ge, or Si and Ge.

[0499] In one embodiment, collapse of CICE etched nanostructures is delayed or eliminated by using a "collapse avoidance cap" or "collapse avoidance feature" on the tip of the nanostructure. In one embodiment, the collapse avoidance cap prevents collapse through electrostatic repulsion between the nanostructures.

[0500] FIG. 59 is a flow chart of a method 5900 for patterning a catalyst using selective atomic layer deposition (ALD) such that the catalyst is part of a "collapse avoidance cap" according to an embodiment of the invention. In this process, the catalyst does not grow on one part of the pattern mask. The ALD chemistries are listed in Table 2.

[0501] [Table 2A]

[0502] [Table 2B]

[0503] As mentioned above, Figure 59 is a flow chart of a method 5900 for patterning a catalyst using selective atomic layer deposition (ALD) such that the catalyst is part of a "collapse avoidance cap" according to an embodiment of the invention. Figures 60A-60E depict cross-sectional views for patterning a catalyst using selective atomic layer deposition (ALD) such that the catalyst is part of a "collapse avoidance cap" using the steps described in Figure 59 according to an embodiment of the invention.

[0504] In one embodiment, the catalyst is patterned using one or more of the following: nanoimprint lithography, photolithography, focused ion beam milling, electron beam lithography, laser interference lithography, nanosphere lithography, block copolymer lithography, and directed self-assembly. In another embodiment, CICE patterning includes using thermally stable carbon, etching into the carbon using a NIL (nanoimprint lithography) resist (such as photoresist), and stripping any polymer resist prior to catalyst deposition using a metal break.

[0505] Referring to FIG. 59 along with FIGS. 60A-60E, in step 5901, an ALD blocking material 6002 is deposited over a substrate 6001, as shown in FIG. 60A.

[0506] In step 5902, an ALD enhancing material 6003 is patterned over the ALD blocking material 6002, as shown in Figure 60B.

[0507] In step 5903, the ALD blocking material 6002 that is not covered by the ALD enhancing material 6003 and the portions of the substrate 6001 that are not covered by the ALD enhancing material 6003 are etched, as shown in FIG. 60C.

[0508] In step 5904, a catalyst 6004 is selectively deposited via ALD on the exposed substrate 6001 and the ALD enhancement material 6003, as shown in FIG. 60D.

[0509] In step 5905, CICE is performed to produce nanostructure 6005 with collapse avoidance cap 6006, where collapse avoidance cap 6006 is created by catalyst 6004 and ALD enhancing material 6003.

[0510] Reference is now made to Fig. 61, which is a flow chart of a method 6100 for producing a collapse avoidance cap and catalyst patterning by directional deposition of catalyst and atomic layer etching, according to an embodiment of the invention. Figs. 62A-62D depict cross-sectional views for producing a collapse avoidance cap and catalyst patterning by directional deposition of catalyst and atomic layer etching using the steps described in Fig. 61, according to an embodiment of the invention.

[0511] Referring to FIG. 61 in conjunction with FIGS. 62A-62D, in step 6101, a mask 6202 is patterned over a substrate 6201, as shown in FIG. 62A.

[0512] In step 6102, catalytic material 6203 is directionally deposited onto mask 6202 and exposed areas of substrate 6201 (i.e., those areas of substrate 6201 not covered by mask 6202), as shown in Figure 62B. In one embodiment, the directional deposition of catalytic material 6203 is performed using thermal evaporation, e-beam evaporation, physical vapor deposition, etc. In one embodiment, catalytic material 6203 is Ru.

[0513] In step 6103, the catalytic material 6203 is removed (e.g., via a dry etch, etc.) from the sidewalls of the mask 6202, as shown in Figure 62C. In one embodiment, an etch of the catalytic material 6203 (e.g., Ru, etc.) is used to remove a thinner metal that is deposited on the sidewalls of the mask 6202.

[0514] In step 6104 , CICE is performed to generate nanostructures 6204 with collapse avoidance caps 6205 , where the collapse avoidance caps 6205 are created by catalyst material 6203 and mask 6202 .

[0515] During the CICE process, isolated metal catalysts can wander and create undesirable non-vertical etch paths. Discontinuous catalyst features tend to wander during the CICE process and cause defects. CICE of holes with isolated catalysts can wander due to van der Waals forces above the catalyst and due to stochastic changes in applied forces due to changes in local etchant concentration or etch rate, as shown in Figures 63A-B.

[0516] 63A-63D illustrate wandering of an isolated catalyst during a CICE, according to an embodiment of the present invention.

[0517] Referring to Figures 63A-63D, Figure 63A illustrates an isolated catalyst 6301 wandering into a substrate 6302. Figure 63B illustrates a top view of the isolated catalyst 6301. Figure 63C illustrates a cross-sectional view of the isolated catalyst 6301. Additionally, Figure 63D illustrates the stochastic change in catalyst center etch rate.

[0518] To prevent wandering of the catalyst (such as catalyst 6301), stabilizing patterns can be inserted into the isolated catalyst, thereby providing a support structure for the catalyst during CICE. These stabilizing patterns can be predefined holes of different cross-sections that are patterned into the isolated catalyst structures. The support structures can be removed after CICE to achieve vertical wandering-free CICE. FIGS. 64A-64D show exemplary geometries for stabilizing patterns or support structures (referred to herein as "catalyst buttresses"), which can be holes of different cross-sections, according to embodiments of the invention.

[0519] Referring to Fig. 64A, Fig. 64A illustrates a top view of catalyst 6301 containing stabilization pattern 6401. Fig. 64B illustrates a cross-sectional view of catalyst 6301 containing stabilization pattern 6401. Fig. 64C illustrates a cross-sectional view of catalyst 6301, where stabilization pattern 6401 is removed after CICE is performed. Moreover, Fig. 64D illustrates various stabilization patterns 6401 to be inserted into catalyst 6301.

[0520] In one embodiment, patterning and fabrication of the catalytic buttress design shown in Figure 64D is performed using photolithography, imprint lithography, e-beam lithography, EUV lithography, self-aligned patterning, spacer patterning, etc.

[0521] Figure 65 is a flow chart of a method 6500 for making isolated catalytic dots with circular catalytic buttresses having Ru as a catalyst, according to an embodiment of the invention. Figures 66A-E depict cross-sectional views for making isolated catalytic dots with circular catalytic buttresses having Ru as a catalyst using the steps described in Figure 65, according to an embodiment of the invention. Figures 67A-E depict top views for making isolated catalytic dots with circular catalytic buttresses having Ru as a catalyst using the steps described in Figure 65, according to an embodiment of the invention.

[0522] 65 along with Figures 66A-66E and 67A-67E, in step 6501, a catalyst 6301 is deposited on a substrate 6601, as shown in Figures 66A and 67A. In one embodiment, the material of the catalyst 6301 is Ru.

[0523] In step 6502, a dot pattern 6602 is inserted into the catalyst 6301 via, for example, photolithography, imprint lithography, e-beam lithography, EUV lithography, self-aligned patterning, spacer patterning, etc., as shown in Figures 66B and 67B. In one embodiment, the dot pattern 6602 is an oxide material.

[0524] In step 6503, a spacer pattern 6603 is deposited surrounding the dot pattern 6602, as shown in Figure 66C and Figure 67C.

[0525] In step 6504, the dot pattern 6602 is removed, such as through various types of etching techniques, as shown in FIG. 66D and FIG. 67D. In one embodiment, the dot pattern 6602 is an oxide material, which is removed through etching. In one embodiment, the etchant used for etching includes one or more of the following: fluoride species, oxidizers, alcohols, and protic, aprotic, polar, and non-polar solvents. In one embodiment, the etchant includes two or more of the following: fluoride species containing chemicals HF or NH4F, oxidizers H2O2, KMnO4, or dissolved oxygen, alcohols ethanol, isopropyl alcohol, or ethylene glycol, protic, aprotic, polar, and non-polar solvents (such as, for example, DI water or dimethyl sulfoxide (DMSO)).

[0526] In step 6505, the spacer pattern 6603 and exposed portions of the catalyst 6301 (i.e., portions of the catalyst 6301 that are not covered by the spacer pattern 6603) are removed via etching (e.g., via various etching techniques (e.g., dry etching), etc.), thereby generating isolated dots, as shown in Figures 66E and 67E.

[0527] In one embodiment, the silicon nanostructures after CICE are porous. The porosity of silicon (Si) can enhance etchant diffusion and further prevent wandering of isolated catalyst 6301. In another embodiment, the silicon nanostructures are fabricated using silicon superlattice etching to produce alternating layers of porous and non-porous silicon nanostructures for an exemplary application in 3D NAND Flash, as shown in Figures 68A-B.

[0528] Figure 68A illustrates catalyst 6301 with nanostructures composed of porous silicon 6801, in accordance with an embodiment of the invention. Figure 68B illustrates catalyst 6301 with nanostructures composed of alternating layers of porous silicon 6801 and non-porous silicon 6802, in accordance with an embodiment of the invention.

[0529] 69A-69D illustrate the removal of silicon buttresses ("stabilizing patterns") ("catalyst buttresses") after CICE using isolated catalyst 6301 with buttresses (e.g., such as buttress 6401) to prevent wandering, according to an embodiment of the invention. In one embodiment, the buttresses (e.g., such as buttress 6401) collapse due to capillary and adhesion forces. To remove the collapsed silicon buttresses (e.g., such as buttress 6401), patterning of an etch mask and anisotropic plasma etching of silicon is used.

[0530] Referring to FIG. 69A, FIG. 69A illustrates a top view of several catalysts 6301 with buttress design 6401 (e.g., silicon buttresses). FIG. 69B illustrates a cross-sectional view of catalysts 6301 with buttress design 6401 (e.g., silicon buttresses). The buttress design 6401 (e.g., silicon pillars) is then removed, resulting in the structure shown in FIG. 69C and FIG. 69D. FIG. 69C illustrates a top view of the resulting structure after removal of buttress design 6401. FIG. 69D illustrates a cross-sectional view of the resulting structure after removal of buttress design 6401.

[0531] In one embodiment shown in Figures 70A-C, a collapsed pillar (such as collapsed buttress 6401 (e.g., a silicon buttress)) is designed to deterministically collapse in a particular direction in accordance with an embodiment of the present invention, such as by placing a buttress pattern towards one side of an etch. The collapsed buttress structure (such as buttress 6401) is removed using a plasma etch with an etch mask (whose geometry is biased to expose the collapsed regions).

[0532] Referring to Fig. 70A, Fig. 70A illustrates a collapsed silicon buttress 6401, where the collapsed silicon buttress 6401 is designed to deterministically collapse in a particular direction (e.g., toward one side of an etch), Fig. 70B illustrates the placement of an etch mask 7001, and Fig. 70C illustrates the removal of the collapsed silicon buttress 6401 with an etch mask 7001 whose geometry is biased to expose the collapsed regions.

[0533] Similar to etching holes by CICE, etching lines and spaces requires long isolated lines of catalyst, which tend to wander during the CICE process. In one embodiment, lithographic links between the lines and spaces are used to connect the isolated catalyst lines. The dimensions and location of the lithographic links are designed to ensure minimal disruption to the final device requirements. Deposition of filler material using a method (e.g., CVD, ALD, physical vapor deposition (PVD), etc.) is used to fill the gaps etched by CICE in the areas with the lithographic links. In one embodiment, the lithographic links are orthogonal to the direction of the desired line and space etching, and ALD of a low-k dielectric material (e.g., silicon oxide, etc.) is used to fill the gaps, as discussed below in connection with Figures 71, 72, and 73A-C.

[0534] Figure 71 is a flow chart of a method 7100 for fabricating a line / space pattern with lithographic links using CICE, according to an embodiment of the invention. Figure 72 illustrates a top view of a desired line / space pattern using the steps described in Figure 71, according to an embodiment of the invention. Figures 73A-73C depict cross-sectional views for fabricating a line / space pattern with lithographic links using CICE, using the steps described in Figure 71, according to an embodiment of the invention.

[0535] Referring to Fig. 72, Fig. 72 illustrates a top view of a desired line / space pattern 7201. Referring to Fig. 73A, Fig. 73A illustrates long isolated lines of catalyst 6301 with lithographic links 7301 to connect the isolated catalyst lines 6301 surrounding an area of ​​a substrate 6302.

[0536] Now referring to FIG. 71 in conjunction with FIGS. 73A-73C, in step 7101, CICE is performed to remove the lines of catalyst 6301 and lithographic links 7301 as shown in FIG. 73B.

[0537] In step 7102, a filler material is deposited (eg, via CVD, PVD, etc.) into the previously removed lines of catalyst 6301 and lithographic links 7301, as shown in Figure 73C.

[0538] Fabricating high aspect ratio structures in polysilicon using CICE enables applications such as stacked capacitors in DRAM, etc. Figures 74A-B show exemplary polysilicon nanowire arrays fabricated using CICE with gold as a catalyst, according to an embodiment of the invention.

[0539] CICE to generate high aspect ratio holes is difficult because isolated catalysts (such as isolated catalyst 6301) suffer from wandering. In one embodiment, the etched nanostructures can be used to change the tone of the feature from pillar to hole using atomic layer deposition (ALD) to partially fill the gap between the pillars. Figure 75 shows an exemplary geometry for converting silicon fins to holes using ALD of silicon oxide, according to an embodiment of the invention. In one embodiment, the silicon fin area is used to generate transistors and the hole area is used to generate capacitors for DRAM devices.

[0540] The tone reversal process by CICE can be further extended to include any material, where polysilicon or silicon structures are created by CICE and the gaps between the structures are filled with a structural material. In one embodiment, the material is an insulator. In one embodiment, the structural material is carbon, amorphous carbon, silicon dioxide, silicon nitride, metal oxide, tin oxide, and / or indium tin oxide. In one embodiment, the deposited material is one or more of the following: SiO2, TiO2, Al2O3, Pd, Pt, W, TiN, TaN, Cu, SiNx, SnOx, ZnOx, etc. Silicon is selectively removed to generate an inverse tone of the structure in the structural material. In one embodiment, the etched polysilicon and / or silicon structures are removed using selective wet etchants (e.g., KOH, TMAH, EDP), dry etchants (e.g., XeF2 vapor), plasma etching (e.g., species such as Cl2, SF6, BCl3 in a plasma). Optionally, a desired material can be deposited in the areas where the silicon was removed, thereby generating structures of any geometry with high aspect ratios in any material. Alternatively, the structural material can be a conductor and the desired material can be an insulator depending on the application requirements. Figures 76, 77A-77D, and 78A-78D discuss the process for tone reversal using CICE.

[0541] In one embodiment, the etch stop layer is selected such that it is not etched in the CICE process, as discussed in FIG. 79, FIG. 80A-80D, and FIG. 81A-81F. In another embodiment, the etch stop layer is removed during the tone reversal process, as discussed in FIG. 82, FIG. 83A-83D, and FIG. 84A-84G. The thickness of the etch stop layer is optimized to reduce the possibility of undercutting, as discussed in FIG. 82, FIG. 83A-83D, and FIG. 84A-84G. The thickness of the etch stop layer can be in the range of 1 nm to 100 nm. In one embodiment, the etch stop material includes carbon, Cr, chromium oxide, aluminum oxide, silicon nitride, silicon oxide, ruthenium, etc., or any combination thereof. In one embodiment, the etch of the etch stop layer is optimized to be anisotropic and selective (e.g., removal of the carbon layer using oxygen plasma etching, chemical etching with ozone, etc.).

[0542] Reference is now made to Fig. 76, which is a flow chart of a method 7600 for a CICE tone reversal process, in accordance with an embodiment of the present invention. Figs. 77A-77D depict top views for a CICE tone reversal process using the steps described in Fig. 76, in accordance with an embodiment of the present invention. Figs. 78A-78D depict cross-sectional views for a CICE tone reversal process using the steps described in Fig. 76, in accordance with an embodiment of the present invention.

[0543] Referring to Figure 76 along with Figures 77A-77D and Figures 78A-78D, in step 7601, CICE is performed, resulting in a structure having silicon pillars 7701 residing above a substrate 7702, as shown in Figures 77A and 78A.

[0544] In step 7602, deposition of oxide 7703 over silicon pillars 7701 and substrate 7702 is performed as shown in Figures 77B and 78B.

[0545] In step 7603, silicon pillars 7701 are removed (ie, etched) using various etching techniques (eg, CICE, etc.), as shown in Figures 77C and 78C.

[0546] In step 7604, a desired material 7704 is deposited, e.g., via CVD, PVD, ALD, etc., in the areas where silicon pillars 7701 were removed, thereby producing high aspect ratio, arbitrary geometric structures, as shown in Figures 77D and 78D.

[0547]

[00106] Referring now to Fig. 79, Fig. 79 is a flow chart of a method 7900 for performing a polysilicon CICE tone reversal process including catalyst removal using selective chemical etching, in accordance with an embodiment of the present invention. Figs. 80A-80D depict top views for performing a polysilicon CICE tone reversal process including catalyst removal using selective chemical etching, using the steps described in Fig. 79, in accordance with an embodiment of the present invention. Figs. 81A-81F depict cross-sectional views for performing a polysilicon CICE tone reversal process including catalyst removal using selective chemical etching, using the steps described in Fig. 79, in accordance with an embodiment of the present invention.

[0548] Referring to Figure 79 along with Figures 80A-80D and Figures 81A-81F, in step 7901, an etch stop layer 8101 and a layer of polysilicon 8102 are deposited over a desired device (e.g., a device including a layer 8103 of a desired material overlying a substrate 8104), as shown in Figures 81A-81B.

[0549] In step 7902, as shown in Figures 80A and 81C, CICE is performed to etch a portion of polysilicon 8102, leaving pillars of polysilicon 8105.

[0550] In step 7903, deposition of oxide 8106 over pillars 8105 and exposed areas of etch stop layer 8101 (i.e., those areas not covered by polysilicon pillars 8105) is performed, as shown in Figures 80B and 81D.

[0551] In step 7904, an etch back of oxide 8106 to the top level of pillars 8105 and removal of pillars 8105 is performed, for example via various etching techniques (e.g., ALE), as shown in Figures 80C and 81E.

[0552] In step 7905, a desired material 8107 is then deposited, for example via CVD, PVD, ALD, etc., in the areas previously occupied by the removed pillars 8105, as shown in Figures 80D and 81F.

[0553]

[00101] Referring now to Fig. 82, Fig. 82 is a flow chart of a method 8200 for performing a polysilicon CICE tone reversal process including catalyst removal using selective chemical etching and where the etch stop layer is removed in the final device, in accordance with an embodiment of the invention. Figs. 83A-83D depict top views for performing a polysilicon CICE tone reversal process including catalyst removal using selective chemical etching and where the etch stop layer is removed in the final device, in accordance with an embodiment of the invention. Figs. 84A-84G depict cross-sectional views for performing a polysilicon CICE tone reversal process including catalyst removal using selective chemical etching and where the etch stop layer is removed in the final device, in accordance with an embodiment of the invention, in accordance with an embodiment of the invention.

[0554] Referring to Figure 82, along with Figures 83A-83D and Figures 84A-84G, in step 8201, an etch stop layer 8401 and a layer of polysilicon 8402 are deposited over a desired device (e.g., a device including a layer 8403 of a desired material overlying a substrate 8404), as shown in Figures 84A-84B.

[0555] In step 8202, as shown in Figures 83A and 84C, CICE is performed to etch a portion of polysilicon 8402, leaving pillars of polysilicon 8405.

[0556] In step 8203, the exposed portions of the etch stop layer 8401 (i.e., those portions of the etch stop layer 8401 that are not covered by pillars 8405) are removed (i.e., etched) using various etching techniques (e.g., via ALE, etc.), as shown in FIG. 84D.

[0557] In step 8204, deposition of oxide 8406 is performed over pillars 8405 and exposed areas of the desired device (e.g., material 8403, etc.) (i.e., those areas not covered by etch stop layer 8401), as shown in Figures 83B and 84E.

[0558] In step 8205, as shown in Figures 83C and 84F, an etch back of oxide 8406 to the top level of pillars 8405 and removal of pillars 8405 and etch stop layer 8401 is performed, for example via various etching techniques (e.g., ALE).

[0559] In step 8206, a desired material 8407 is then deposited, e.g., via CVD, PVD, ALD, etc., in the areas previously occupied by the removed pillars 8405 and the removed etch stop layer 8401, as shown in Figures 83D and 84G.

[0560]

[00101] Referring now to Fig. 85, Fig. 85 is a flow chart of a method 8500 for fabricating metal interconnects and vias using a polysilicon CICE tone reversal process, in accordance with an embodiment of the invention. Figs. 86A-86F depict top views for fabricating metal interconnects and vias using a polysilicon CICE tone reversal process using the steps described in Fig. 85, in accordance with an embodiment of the invention. Figs. 87A-87L depict cross-sectional views for fabricating metal interconnects and vias using a polysilicon CICE tone reversal process using the steps described in Fig. 85, in accordance with an embodiment of the invention.

[0561] Referring to Figure 85, along with Figures 86A-86F and Figures 87A-87L, in step 8501, an etch stop layer 8701 and a layer of polysilicon 8702 are deposited over a desired device (e.g., a device including a layer 8703 of a desired material overlying a substrate 8704), as shown in Figures 87A-87B.

[0562] In step 8502, as shown in Figures 86A and 87C, a portion of polysilicon 8702 is etched (eg, via CICE, etc.) to leave pillars of polysilicon 8705.

[0563] In step 8503, a catalyst (e.g., Ru) 8706 is deposited on the exposed portions of the etch stop layer 8701 (i.e., those portions of the etch stop layer 8701 that are not covered by pillars 8705), such as via ALD, CVD, PVD, electroplating, or thermal evaporation, as shown in Figures 86A and 87C.

[0564] In step 8504, catalyst 8706 is removed, such as via various etching techniques (eg, dry etching, wet etching), as shown in FIG. 87D.

[0565] In step 8505, the exposed portions of the etch stop layer 8701 (i.e., those portions of the etch stop layer 8701 that are not covered by the pillars 8705) are removed, such as via an etching technique (e.g., ALE), as shown in FIG. 87E.

[0566] In step 8506, deposition of oxide 8707 is performed over pillars 8705 and exposed areas of the desired device (e.g., material 8703, etc.) (i.e., those areas not covered by etch stop layer 8701), as shown in Figures 86B and 87F.

[0567] In step 8507, as shown in Figures 86C and 87G, an etch back of oxide 8707 to the top level of pillars 8705 and removal of pillars 8705 and etch stop layer 8701 is performed, for example via various techniques (e.g., dry etching, wet etching), etc.

[0568] In step 8508, desired material 8708 is then deposited, e.g., via CVD, PVD, ALD, etc., in the areas previously occupied by the removed pillars 8705 and the removed etch stop layer 8701, as shown in Figures 86D and 87H.

[0569] In one embodiment, in step 8509, for a tone reversal CICE, step 8501 is repeated in which an etch stop layer 8709 and a layer of polysilicon 8710 are deposited over the device structure shown in Figures 86D and 87H, resulting in the structure shown in Figure 87I.

[0570] In step 8510, step 8502 is repeated where a portion of polysilicon 8710 is etched, such as via CICE, leaving pillars of polysilicon 8711, as shown in Figures 86E and 87J.

[0571] In step 8511, steps 8503-8507 are repeated, resulting in a structure with oxide 8712, as shown in Figure 87K.

[0572] In step 8512, step 8508 is repeated, in which desired material 8713 is then deposited, e.g., via CVD, PVD, ALD, etc., in the areas previously occupied by the removed pillars 8711 and the removed etch stop layer 8709 to form the structure shown in Figures 86F and 87L, in which the formed structure includes desired materials 8713, 8708 and oxides 8712, 8707.

[0573] Steps 8509-8512 can be continually repeated for as many metal and / or insulator layers as desired.

[0574] In one embodiment, method 8500 is used for a metal layer in an interconnect, where the structural material is a low-k dielectric (e.g., silicon oxide or silicon oxynitride, etc.) and the desired material is a conductor (e.g., Cu, Mo, W, Ru, TiN, TaN, Pd, etc.). In one embodiment, CICE is used for the fabrication of the metal interconnect, and the catalyst (e.g., catalyst 8706, etc.) for the CICE is Ru. In one embodiment, the catalyst (e.g., catalyst 8706, etc.) is not removed after CICE, and Ru is used as a seed layer for electroplating of Cu to produce Cu interconnects using a dual damascene process. Other metals that can be deposited for the interconnect include Ru, Co, Mo, TiN, Cu, W, TaN, etc. The metal can be deposited using ALD, CVD, PVD, electroplating, or thermal evaporation. In one embodiment, Cu is deposited using electroplating and polished using CMP.

[0575] Tone reversal CICE can be used to selectively grow superlattice structures in high aspect ratio holes, thereby enabling sidewall damage free vertically tapered superlattice nanostructures fabricated without the use of plasma etching for the superlattice material. The superlattice material can be deposited using selective atomic layer deposition, epitaxial growth, selective electrodeposition, etc., such that each layer grows only on the previous layer deposited and not on the structural material. Figures 88, 89A-89D, and 90A-90D illustrate an exemplary process for making these structures. In one embodiment, the alternating layers are Si and SiGe, which are grown epitaxially for application in nanosheet FETs, and the structural material is an insulator.

[0576] Figure 88 is a flow chart of a method 8800 for forming a superlattice by tone reversal CICE and selective growth, according to an embodiment of the invention. Figures 89A-89D depict top views for forming a superlattice by tone reversal CICE and selective growth using the steps described in Figure 88, according to an embodiment of the invention. Figures 90A-90D depict cross-sectional views for forming a superlattice by tone reversal CICE and selective growth using the steps described in Figure 88, according to an embodiment of the invention.

[0577] Referring to Figure 88 along with Figures 89A-89D and Figures 90A-90D, in step 8801, CICE is performed on a layer of polysilicon 8901 overlying a substrate 8902, resulting in polysilicon pillar shapes 8903, as shown in Figures 89A and 90A.

[0578] In step 8802, deposition of oxide 8904 over pillars 8903 and exposed areas of substrate 8902 is performed, as shown in Figures 89B and 90B.

[0579] In step 8803, an etch back of oxide 8904 to the top level of pillars 8903 and removal of pillars 8903 is performed, such as via various techniques (eg, ALE), as shown in Figures 89C and 90C.

[0580] In step 8804, a desired material 8905 is then deposited, for example via CVD, PVD, ALD, etc., in the areas previously occupied by the removed pillars 8903, as shown in Figures 89D and 90D.

[0581] A roll-to-roll (R2R) process can be used for the fabrication of silicon nanostructures using R2R deposition of silicon, R2R patterning, and R2R CICE. In one embodiment, polysilicon is deposited on a stainless steel roll and patterned using R2R nanoimprint lithography, followed by removal of the imprint resist residual layer thickness (RLT). Other substrates include metal and metal alloy foils, polymer films, and other flexible substrates. In another embodiment, a barrier layer is deposited between the roll substrate and the polysilicon. The barrier layer is chemically resistant to the CICE etchant solution and can act as an etch stop. Cr, carbon, and Al2O3 are examples of materials used for the barrier layer.

[0582] Thin films of adhesion layer material and catalyst material are deposited using e-beam evaporation, thermal evaporation, physical vapor deposition, chemical vapor deposition, etc. Examples of deposited thin films include Ti, Au, Pt, Pd, Ag, Ru, RuO2, Ir, IrO2, TiN, W, Cu, etc., or any combination thereof. The catalyst patterned on polysilicon on R2R substrate is then exposed to wet chemical etching for CICE. In one embodiment, the roll is placed in a vertical orientation and the etchant is sprayed on the patterned side of the roll. In another embodiment, the CICE process is carried out using a vapor phase etchant. In one embodiment, polysilicon nanowires are made using the R2R process for high density anodes in battery and ultracapacitor applications.

[0583] Deterministic lateral displacement (DLD) is a microfluidic technique that separates particles in a fluid medium based on their size using a specific arrangement of pillar arrays placed in a microfluidic channel. The gap between the pillars and the placement of the pillars determine the separation mechanism. The pillar arrays required for DLD can be fabricated using nanolithography (such as nanoimprint lithography combined with a catalytically influenced chemical etching (CICE) process). In one embodiment shown in Figure 91 and Figures 92A-92G, silicon pillars for DLD are created on a silicon wafer substrate. In another embodiment, the catalyst is not removed after CICE and the DLD device is encapsulated. A CICE etchant is flowed through the device inlet to further etch the pillars in the encapsulated DLD device.

[0584] In one embodiment, exfoliation is used to remove a thin layer of silicon from the silicon pillars, such that the remaining silicon substrate can be polished and reused. This process allows for reduced costs for DLD device fabrication and is discussed in Ward et al., "Design of Tool for Exfoliation of Monocrystalline Micro-Scale Silicon Films," Journal of Micro and Nano-Manufacturing, April 5, 2019, which is incorporated by reference in its entirety.

[0585] Referring to Fig. 91, Fig. 91 is a flow chart of a method 9100 for DLD device fabrication using a CICE and silicon wafer peeling, in accordance with an embodiment of the invention. Figs. 92A-92G depict cross-sectional views for DLD device fabrication using a CICE and silicon wafer peeling, in accordance with an embodiment of the invention, using the steps of Fig. 91.

[0586] Referring to Figure 91 in conjunction with Figures 92A-92G, in step 9101, a silicon wafer substrate 9201 is etched (e.g., via CICE, etc.) to form silicon nanowires (pillars) 9202 (also referred to herein as "silicon nanopillars"), as shown in Figure 92A.

[0587] In step 9102, support material 9203 is deposited in the recesses between the silicon nanowires 9202, as shown in Figure 92B.

[0588] In step 9103, nickel 9204 is deposited on the support material 9203 for release, as shown in Figure 92C.

[0589] In step 9104, at least a substantial portion of the silicon wafer substrate 9201 is peeled away, leaving a thin layer of silicon wafer substrate 9201, as shown in Figure 92D.

[0590] In step 9105, a support substrate 9205 is then bonded to the remainder of the silicon wafer substrate 9201, as shown in Figure 92E.

[0591] In step 9106, nickel 9204 and support material 9203 are removed, such as via an etching technique (eg, ALE), thereby forming a DLD device, as shown in FIG. 92F.

[0592] In step 9107, an encapsulation layer 9206 is deposited over the silicon nanowires 9202 of the DLD device, as shown in Figure 92G.

[0593] In one embodiment, the pillars (e.g., silicon nanowires 9202, etc.) in the encapsulated DLD device can be further etched (e.g., via CICE, etc.) to increase the pillar height. For example, a CICE etchant can be flowed through the device inlet to further etch the pillars (e.g., silicon nanowires 9202, etc.) in the encapsulated DLD device.

[0594] Collapse of silicon nanopillars (e.g., silicon nanopillar 9202, etc.) in the DLD array limits the maximum height of the pillars. In one embodiment, the pillar height is increased by creating a ceiling structure above the silicon nanopillars using deposition of a material that is chemically resistant to etchants (e.g., carbon, Cr, etc.), as discussed in Rouhani et al., "In-Situ Thermal Stability Analysis of Amorphous Carbon Films with Different Sp3 Content," Carbon, Vol. 130, April 1, 2018, pp. 401-409, which is incorporated herein by reference in its entirety.

[0595] In another embodiment, the ceiling structure (or stabilizing material) is made by co-sputtering an HF-resistant material with an HF-consuming material, thereby producing a porous mesh. In one embodiment, carbon and SiO2 are co-sputtered to produce the ceiling structure. When exposed to a CICE etchant, the SiO2 is etched away, resulting in a porous carbon mesh. The porous carbon mesh structurally stabilizes the silicon nanopillars, while the CICE etchant further increases their height.

[0596] Figure 93 is a flow chart of a method 9300 for bonding a cover plate to a DLD pillar to produce a DLD device after CICE without causing pillar collapse, according to an embodiment of the invention. Figures 94A-94E depict cross-sectional views for bonding a cover plate to a DLD pillar to produce a DLD device after CICE without causing pillar collapse, using the steps of Figure 93, according to an embodiment of the invention.

[0597] Referring to Figure 93 in conjunction with Figures 94A-94E, in step 9301, CICE is performed on a silicon wafer substrate 9401 to form DLD pillars 9402, as shown in Figure 94A.

[0598] In step 9302, a stabilizing material 9403 is deposited via various deposition techniques (eg, via CVD, PVD, ALD, etc.) on the DLD pillars 9402, as shown in FIG. 94B.

[0599] In step 9303, the stabilizing material 9403 is etched back to below the upper portions of the DLD pillars 9402 (referred to herein as "DLD pillar caps 9404"), as shown in Figure 94C.

[0600] In step 9304, the DLD pillar cap 9404 is removed, for example via various etching techniques (e.g., ALE), leaving a small portion of the DLD pillar 9402 (identified as element 9405) above the etched back stabilizing material 9403, as shown in FIG. 94D.

[0601] In step 9305, a cover plate 9406 is bonded to the remaining portion of the DLD pillar 9405 remaining after the DLD pillar cap 9404 is removed, as shown in Fig. 94E. Such bonding can be performed using anodic bonding, fusion bonding, hybrid bonding, pneumatic suction, adhesives, etc.

[0602] Figure 95 is a flow chart of a method 9500 for improving pillar height using a porous stabilizing material, according to an embodiment of the invention. Figures 96A-96C depict cross-sectional views for improving pillar height using a porous stabilizing material using the steps of Figure 95, according to an embodiment of the invention.

[0603] Referring to FIG. 95 in conjunction with FIGS. 96A-96C, in step 9501, CICE is performed on a silicon wafer substrate 9601 to form DLD pillars 9602.

[0604] In step 9502, DLD pillars 9602 are etched, such as via various etching techniques (eg, ALE), to reduce the height of DLD pillars 9602, as shown in FIG. 96A.

[0605] In step 9503, a layer 9603 with etchant-resistant and etchant-soluble components is deposited over the DLD pillars 9602 and exposed areas of the silicon wafer substrate 9601, as shown in Figure 96B.

[0606] In step 9504, further CICE is performed on the silicon wafer substrate 9601 below layer 9603 to extend the height of the DLD pillars, resulting in the structure shown in Figure 96C.

[0607] In step 9505, a porous resistant layer 9604 (e.g., a porous HF resistant layer, etc.) is optionally deposited over layer 9603 at approximately the mid-height level of pillars 9602 to stabilize pillars 9602, as shown in FIG. 96C.

[0608]

[00101] Figure 97 is a flow chart of a method 9700 for bonding a cover plate for a DLD device after a CICE without causing pillar collapse, according to an embodiment of the invention. Figures 98A-98D depict cross-sectional views for bonding a cover plate for a DLD device after a CICE without causing pillar collapse using the steps of Figure 97, according to an embodiment of the invention.

[0609] 98A-98D, in step 9701, CICE is performed on a silicon wafer substrate 9801 to form DLD pillars 9802, as shown in FIG. 98A. Such DLD pillars 9802 include DLD pillar caps 9803, which refer to the top portions of DLD pillars 9402.

[0610] In step 9702, a sacrificial material 9804 (eg, polyvinyl alcohol (PVA)) is deposited along the walls of the DLD pillars 9802, as shown in Figure 98B.

[0611] In step 9703, the DLD pillar caps 9803 are removed, such as via various etching techniques (eg, ALE), as shown in Figure 98C.

[0612] In step 9704, a cover plate 9805 with an etchant resist film 9806 is bonded to the remaining top portion of the DLD pillar 9802, as shown in Fig. 98C. Such bonding can be performed using anodic bonding, fusion bonding, hybrid bonding, pneumatic suction, adhesives, etc.

[0613] In step 9705, as shown in Fig. 98D, a sacrificial material etchant (e.g., deionized water) flow is performed to remove the sacrificial material 9804. Optionally, further CICE can be performed along with oxide growth and removal to create thinner wires.

[0614] Figure 99 is a flow chart of a method 9900 for improving collapse of thin pillars by reducing pillar size starting with the thick pillars after cover plate bonding, according to an embodiment of the invention. Figures 100A-100D depict cross-sectional views for improving collapse of thin pillars by reducing pillar size starting with the thick pillars after cover plate bonding using the steps of Figure 99, according to an embodiment of the invention.

[0615] 99 in conjunction with FIGS. 100A-100D, in step 9901, CICE is performed on a silicon wafer substrate 9801 to form DLD pillars 9802, as shown in FIG. 100A. Such DLD pillars 9802 include DLD pillar caps 9803, which refer to the top portions of DLD pillars 9402.

[0616] In step 9902, a sacrificial material 9804 (eg, polyvinyl alcohol (PVA)) is deposited along the walls of the DLD pillars 9802, as shown in FIG. 100B.

[0617] In step 9903, the DLD pillar caps 9803 are removed, such as via various etching techniques (eg, ALE), as shown in FIG. 100C.

[0618] In step 9904, a cover plate 9805 with an etchant resist film 9806 is bonded to the remaining top portion of the DLD pillar 9802, as shown in FIG. 100C. Such bonding can be performed using anodic bonding, fusion bonding, hybrid bonding, pneumatic suction, adhesives, etc.

[0619] In step 9905, an oxide etchant (eg, dilute hydrofluoric acid) flow is performed to remove portions of the sacrificial material 9804 and DLD pillars 9802, making them thinner, as shown in FIG. 100D.

[0620] In another embodiment, the layers of the DLD device are fabricated using polysilicon deposition and CICE, as discussed below in connection with FIG. 101, FIG. 102A-FIG. 102F, and FIG. 103. The polysilicon can be recrystallized using a laser recrystallization method. In one embodiment, the structural material is a water-soluble polymer (e.g., PVA, etc.), and the material is removed by running water through the device after fabrication. The encapsulation layer can be made of glass, Cr, polymer, silicon, oxide-coated polymer, etc. In another embodiment, multi-stack DLD pillars are fabricated in the nanoscale feature size DLD region, as shown in FIG. 103. This can allow for matching the flow resistance of fluid samples in the micrometer-scale and nanometer-scale areas of the DLD device. In one embodiment, the porous layer between the multi-layer stack is fabricated by co-sputtering an HF-resistant material with an HF-consuming material, thereby generating a porous mesh. In one embodiment, carbon and SiO2 are co-sputtered to produce a porous layer. When exposed to a CICE etchant, the SiO2 is etched away, resulting in a porous carbon mesh that structurally stabilizes the silicon nanopillars and allows for the transport of fluid samples through the different layers of the DLD device.

[0621] Figure 101 is a flow chart of a method 10100 for multi-stack DLD device fabrication using polysilicon CICE, according to an embodiment of the invention. Figures 102A-102F depict cross-sectional views for multi-stack DLD device fabrication using polysilicon CICE using the steps of Figure 101, according to an embodiment of the invention.

[0622] Referring to FIG. 101 in conjunction with FIGS. 102A-102F, in step 10101, CICE is performed on a silicon wafer substrate 10201 to form DLD pillars 10202, as shown in FIG. 102A.

[0623] In step 10102, a structural material 10203 is deposited in the recesses between the DLD pillars 10202, as shown in Figure 102B.

[0624] In step 10103, an encapsulation layer 10204 is deposited over the structural material 10203 and the DLD pillars 10202, as shown in Figure 102B.

[0625] In step 10104, a layer of polysilicon 10205 is deposited over the encapsulation layer 10204, as shown in Figure 102C.

[0626] In step 10105, CICE is performed, which etches a portion of polysilicon layer 10205 to form pillars 10206, as shown in Figure 102D.

[0627] In step 10106, a structural material 10207 is deposited into the recesses between the pillars 10206, as shown in Figure 102E.

[0628] In step 10107, an encapsulation layer 10208 is deposited over the structural material 10207 and pillars 10206, as shown in Figure 102E.

[0629] It is noted that steps 10104 to 10107 can be repeated to increase the number of DLD stacks.

[0630] In step 10108, the structural material 10207, 10203 is removed, such as via various etching techniques (eg, CICE), as shown in FIG. 102F.

[0631] FIG. 103 illustrates a cross-section of a multi-stack DLD device in a nanoscale area to improve overall throughput according to an embodiment of the present invention.

[0632] As shown in Fig. 103, the substrate 10301 includes micrometer-scale DLD pillars 10302 and nanometer-scale DLD pillars 10303. Additionally, as shown in Fig. 103, below the polysilicon layers 10306A-10306B there is a porous layer 10304 along with flow and etch stop layers 10305A-10305B, respectively. Additionally, Fig. 103 illustrates a cover plate 10307 located on top of the upper polysilicon layer 10306B, and the nanoscale DLD pillars 10303 positioned alongside the upper polysilicon layer 10306B.

[0633] In one embodiment, the particles separated by the DLD device can be detected on-chip using spectroscopic methods (such as surface enhanced Raman spectroscopy (SERS)). The SERS substrate is integrated into the DLD chip along with porous silicon for carrier fluid filtration, such that the particles to be detected are on top of the porous silicon. Particle detection can be enhanced by patterning SERS enhancing structures (such as gold nanostructures). In one embodiment, the porous silicon for the SERS detector is fabricated using CICE, where the areas with porous silicon are doped using ion implantation. Alternatively, the areas with porous silicon are patterned with a catalyst with higher CICE catalytic activity (such as Pt, Pd, or Ru), while the areas with the non-porous DLD pillar arrays are patterned with a catalyst with lower CICE catalytic activity (such as Au).

[0634] The ability to generate nanostructures with vertical sidewalls and vary critical dimensions and shapes can be used for applications such as metalenses and metasurfaces. In one embodiment, the metasurface includes an array of pillars with varying silicon nanopillar shapes and geometries such that the metasurface can focus light with specific wavelengths (e.g., near-IR and mid-IR). Additionally, the array can be made of oxidized porous silicon, which allows for focusing of visible wavelengths. FIG. 104 shows an exemplary pixel geometry, where one section of the pillar is oxidized silicon. In particular, FIG. 104 illustrates a metasurface including four arrays of pillars for focusing of various wavelengths of light using silicon nanopillars and oxidized porous silicon nanopillars produced by CICE, according to an embodiment of the invention. The porous silicon pillars can be made by intentionally increasing the doping concentration of silicon in desired areas of the pixel using lithography and ion implantation. The CICE process is optimized to produce porous silicon pillars in highly doped areas and non-porous silicon pillars in the lightly doped areas of the material to be etched. In one embodiment, the oxidation of the porous silicon nanopillars converts them completely into porous silicon oxide nanopillars, while a thin oxide shell is grown on top of the non-porous pillars.

[0635] In one embodiment, a 3D integration method (e.g., nMASC, etc.) is used for the integration of III-V detectors in the metasurface.

[0636] FIG. 105 illustrates an exemplary 3D stacked image sensor in accordance with an embodiment of the present invention.

[0637] FIG. 106 illustrates an exemplary petal-shaped imager die, according to an embodiment of the present invention.

[0638] The following discussion is based on Figures 105 and 106.

[0639] In one embodiment, a tool for pick and place assembly is used to assemble two or more fields, where at least one of the fields is a photosensitive pixel array, and at least one pair of the fields are stacked and assembled. In one embodiment, a tool for pick and place assembly is used to assemble two or more fields, where at least one of the fields is a photosensitive pixel array, and at least one of the fields is comprised of logic circuitry. In one embodiment, a tool for pick and place assembly is used to assemble two or more fields, where at least one of the fields is a photosensitive pixel array, and at least one of the fields is comprised of logic circuitry, and at least one of the fields is comprised of memory circuitry.

[0640] In one embodiment, the total thickness of the imager assembly is less than 25 μm. In one embodiment, groups of one or more pixels are addressed using logic circuitry that physically underlies the pixels.

[0641] In one embodiment, one or more image sensors are curved to a spherical shape. The imager curvature can be created by pressing the front side of the imager using a transfer chuck while the back side of the imager conforms to a spherical mold. The mold can be optionally transparent. In one embodiment, the mold has an adhesive thereon to secure the curved imager. The adhesive can be UV curable. The UV cure can be performed from the back side of the transparent mold. In one embodiment, the adhesive is inkjetted before the imager is curved. In one embodiment, multiple imagers are picked up from a source substrate (such as source substrate 103) and placed and curved simultaneously onto a group of molds. In one embodiment, the group of molds is fabricated as a single continuous part using a transparent polymer. In one embodiment, the edges of the imager die are fixed during the assembly process. In one embodiment, the edges of the imager die are not constrained during the assembly process. In one embodiment, the imager has petal type structures, in one embodiment, one or more edges of one or more petals lie behind an adjacent petal after the curvature process.

[0642] In one embodiment, the throughput of the DLD device can be improved by stacking multiple DLD devices and running samples in parallel. In one embodiment, the DLD devices are stacked using a 3D integration technique. In one embodiment, the 3D integration technique is n-MASC.

[0643] As a result of the foregoing, the principles of the present invention provide a means for utilizing the CICE process to efficiently fabricate features in semiconductors using the inventive catalytically influenced chemical etching equipment and process techniques.

[0644] The description of various embodiments of the present invention has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will become apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been selected to best explain the principles of the embodiments, practical applications, or technical improvements over the art found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein. [Explanation of symbols]

[0645] 100 Tools 101 Nano Procession xy Stage 102 Source Substrate Chuck 103 Source Board 104 Product Board Chuck 105 Product Board 106 Precision Pick and Place Module Frame 107 Short stroke xy stage 108 Weighing Module 109 Voice coil 110 Plasma Unit 111 Transfer Chuck (TC) 112 Field 113 Unified Fields 114 Field 115 Elements 201 Transparent source / product / intermediate substrate 202 Source / Product / Intermediate Board Chuck 203 Chiplet 204 Light source 205 Light Path 206 Imager 207 Light source 208 DMD Assembly 209 Light source 210 Projector 211 Imager 212 Thermoelectric cooler 213 Printed Circuit Board (PCB) 214 Cooling Assembly 215 Photonic Waveguide Substrate 216 Outcoupling lattice 217 Incoupling Lattice 218 Two-dimensional photonic crystal passage 301 Ultraviolet (UV) Light Emitting Diode (LED) Array 302 Cooling System Assembly 401 Field 402 Micromachined Pins 403 Heat exchanger fluid 404 Thermally Conductive Printed Circuit Board 405 Heat exchanger layer 406 Thermal Actuator Layer 407 Thermoelectric cooler 408 xy actuator layer 409 xy flexure 410 Stationary part 411 Moving parts 412 Pneumatic valve layer, xy flexure layer 413 Flexible Layer 414 Flow Valve 415 Stationary part 416 Moving parts 417 xy flexure 418 Activation Grid 419 Pressure Line 420 Vacuum source 421 Pressure Source 422 Vacuum Line 423 z-flexure layer 424 z-flexure 425 Pressure Manifold Layer 426 Pressure Line 427 Vacuum suction layer 428 Field Contact Pin 429 Vacuum Line 430 Gap 501 Vacuum supply section 502 Annular contact part 503 Primary Vacuum Manifold 504 Secondary Vacuum Manifold 505 Elements 506 Elements 507 Elements 508 Vacuum Section 509 Air Flow Direction 601 Upper metal layer 602 Back transistor layer 603 nMASC Field 604 particles 605 Thin Skin 701 Rectangular Bounding Area 702 Actuator Grid 801 Intermediate board 802 Alignment Grid 803 Various Density Glue 804 Elements 805 Element 806 Elements 901 Die 902 Source Wafer 1001 Base Plate 1002 Y-reconfigurable array 1003 Link 1004 Link Locations for exemplary force application to reconfigure the 1005 TC X-grid Locations for exemplary force application to reconfigure the 1006 TC Y-grid 1007 Single Actuating Unit 1008 Defective operating unit 1101 TC assembly, ATC 1102 Porous filter membrane Hole 1103 1104 Pin 1105 Element 1106 Optional material for plugging vacuum holes 1201 Plugging materials 1202 ATC Subcomponents 1301 TC111 upper part 1302 TC111 bottom part 1303 Porous filter membrane 1304 Inkjet 1305 Element 1401 Imager, Image Sensor 1402 Imager 1601 Base plate 1602 Y-reconfigurable array 1603 Link 1604 Link 1605 Location for Exemplary Force Application to Reconfigure Imager X-Grid 1606 Location for Exemplary Force Application to Reconfigure Imager Y-Grid 1701 Locations for Exemplary Force Application to Reconfigure Imager X-Grid 1702 Locations for Exemplary Force Application to Reconfigure Imager Y-Grid 1703X Reconfigurable Array 1801 SWIR Imager Subassembly 1802 SWIR sensor photosensitive area 1803 Telecentric Focusing Optics 1804 Staggered Sensor Design 1805 Moire Mark 1806 Imaging-based marks 1807 Field 1808 Improved Calf 1809 Standard Calf 1810 Incident light 1811 Moire grid 1901 SWIR Imager Subassembly 1902 SWIR sensor photosensitive area 1903 Focusing Optics 1904 Focusing Optics 1905 Moire Mark 1906 Imaging-based marks 1907 Field 1908 Improved Calf 1909 Standard Calf 2001 Flow-based Cooler 2002 PCB Wiring and Heat Exchanger Fluid Harness 2003 SWIR LED 2004 SWIR sensor 2005 Metal Frame 2006 Flat Lens 2007 Off-axis LED focusing optics 2008 Moire Plane 2009 Incident light 2010 Moire Grid 2101 Element 2102 Global Alignment 2103 Element 2201 Die 2202 Alignment mark location 2301 Imager 2302 Reflective blaze grating 2303 Focusing Optics 2304 Light source 2305 Opaque Enclosure Walls 2306 Littrow angle 2401 Integer Assembly 2402 Light source 2403 Focusing Optics 2404 Element 2405 Photonic Light Guide 2406 Field 2501 Diffractive Element 2601 Known Bad Die Replacement Chuck (KRC) 2602 Buffer Board 2603 Known Good Die 2604 Buffer Substrate Chuck 2605 Known Bad Dies 2606 Robot Arm 2607 Voice coil post 2608 Pin Lift 2701 Bulk Silicon Layer 2702 Buried Oxide Layer 2703 Silicon (Si) layer 2704 Buried Oxide Layer 2705 ​​Silicon Layer 2706 Bulk Silicon Layer 2707 Buried sacrificial layer 2708 A layer of very lightly doped n-type material (n-) 2709 A layer of heavily doped p-type material (p++) 2710 Silicon Layer 2711 A layer of heavily doped (p++) bulk silicon 2712 A layer of very lightly doped n-type material (n-) 2713 A layer of heavily doped p-type material (p++) 2714 Silicon Layer 2801 Device Stack 2802 Crystalline silicon 2803 Chemical protection layer 2804 Structural stability layer 2805 Area 1 2806 Area 2 2901A~2901N Device Layer 2902 Vertical Electrical Connection 2903A~2903N Device Layer 2904 Vertical Electrical Connection 3001 Logic Field 3002 SRAM Field 3003 Sacrificial Layer 3004 n-MASC equipment 3005 products 3006 Devices 3007 Connection 3008 TSV 3101 SRAM 3201 Interposer Field 3301A~3301N Pre-flip source wafers 3302A~3302N Carrier Board 3303 Metal structure (die) 3304 Adhesives 3305A~3305N Source Wafer 3306A~3306N Intermediate Wafer 3307 Element 3308 Adhesive Island 3309 Transfer Wafer 3310 Product Wafer 3401 Adhesive Island 3402 Element 3501 Structure 3502 Adhesive Island 3601 Mini TC 3602 Locations for Exemplary Force Application to Reconfigure the TC X-Grid 3603 Locations for Exemplary Force Application to Reconfigure the TC Y-Grid 3604 Y-reconfigurable array 3605 Electrode 3606 Custom Thin Film Transistor (TFT) Backplane 3607 Dielectric 3701 Thin Film Transistor (TFT) Backplane 3702 Space between electrodes 3703 3703 Electrode 3704 Channel 3705 Vacuum inlet 3706 Vacuum outlet section 3707 Transistor Lead 3721 Structure 3722 Elements 3723 Structure 3724 Custom Backplane 3725 Movable electrode 3726 Fixed electrode 3727 Porous filter membrane 3740 Structure 3741 Element 3742 Structure 3801 Optical electromagnetic actuator 3802 Slider 3803 Flexure System 3804 Pivot 3805 Pressure and / or Vacuum 3806 Linear Rail 3807 Transparent Core Port 3808 Encoder Sensor 3809 Permanent Magnet / Voice Coil 3901 Flexure-based pivot 3902 Transparent Window 3903 Adaptive Chucking Module (ACM) 3904 Air bearing 3905 Voice Coil Actuator 4001 X-Rail 4002 Y-rail 4003 Air Bearing 4101 X-direction flexure 4201 Connection 4202 Fixed electrode 4203 Movable electrode 4204 Gap 4205 Places in the atmosphere 4206 ACM Pin 4207 Dual Seal 4208 Polysilicon film 4209 Vacuum inlet 4301 Scissor-based mechanism 4302 Variable Pitch Mechanism (VPM) 4303 Fixed Point 4304 Actuating Arm 4305 Thermally Insulated Connector 4306 Cantilever Flexure 4307 Thermal insulation frame 4401 Mesa 4402 Source Board Adhesive 4403 Elements 4404 UV-curable adhesive 4405 Waveguide Layer 4406 Incoupling Lattice 4407 UV 4408 Bulk Part 4409 Encapsulation Layer 4410 z-Compliant Structure 4411 Outcoupling lattice 4412 Flexure stem, flexure stem layer 4413 Recess 4414 Secondary Flexure 4415 Center Pad 4416 Adhesive Droplet 4501 IR light 4601 Field 4602 Field 4603 Local air pressure and / or electrostatic repulsion 4701 Mesa 4702 Source Board Adhesive 4703 UV radiation 4704 Bulk part 4705 Encapsulation Layer 4706 z-Compliant Structure 4707 Transitional materials (adhesives) 4708 Flexure stem, flexure stem layer 4709 Recess 4710 Secondary Flexure 4711 Center Pad 4901 Field 4902 Access Hall 4903 Sacrificial Layer 4904 Bulk Substrate 4905 Field Calf 4906 Tether 4907 Intermediate board 4908 Adhesive 4909 Source Board 4910 Glue Island 5001 SIP 5002A~5002N Active Buffer Board 5003A~5003N Inactive Buffer Board 5004 Arrow 5005 Arrow 5101 Field 5102 Adhesives, adhesive layers, adhesive films 5103 Device Structure 5104 Encapsulation Layer 5105 Metal Break Layer 5106 Catalyst 5107 Kerf area 5108 Alignment Mark 5109 Alignment Mark 5110 Diced Edge 5201 Upward-facing microscope 5202 VPM 5203 Stable Reference Grid 5204A~5204D Integrated Light Source and Sensor Pairs 5301 Alignment mark 5302 Diced Edge Stabilization Structure 5303 Diced Edge 5304 Shallow Etched Recesses 5305 Meniscus containing etchant droplets 5306 Inkjet Catalyst 5307 Cutting thickness 5401 Knife Edge Dicer Frame 5402 Knife Edge 5403 Etchant inlet 5404 Etchant outlet 5405 Protective layer 5406 Meniscus containing etchant droplets 5407 Catalyst Film 5408 Cutting thickness 5501 Catalyst 5601 Encapsulation Layer 5801 Substrate 5802 Catalyst Break Layer 5803 Mesa 5804 Mesa 5805 Catalyst Break 5806 Catalyst 6001 Substrate 6002 ALD Blocking Materials 6003 ALD reinforced material 6004 Catalyst 6005 Nanostructures 6006 Collapse Prevention Cap 6201 Board 6202 Mask 6203 Catalyst materials 6204 Nanostructures 6205 Collapse Prevention Cap 6301 Isolated Catalyst 6302 Substrate 6401 Stabilization Pattern 6601 Board 6602 Dot Pattern 6603 Spacer Pattern 6801 Porous Silicon 6802 Non-porous silicone 7001 Etching mask 7201 Desired line / space pattern 7301 Lithographic Link 7701 Silicon pillar 7702 Board 7703 Oxide 7704 Desired material 8101 Etching stop layer 8102 Polysilicon layer 8103 Layer of desired material 8104 Substrate 8105 Polysilicon pillar 8106 Oxides 8107 Desired material 8401 Etching stop layer 8402 Polysilicon layer 8403 Layer of desired material 8404 Substrate 8405 Polysilicon pillar 8406 Oxide 8407 Desired material 8701 Etching stop layer 8702 Polysilicon layer 8703 Layer of desired material 8704 Substrate 8705 Polysilicon pillar 8706 Catalyst 8707 Oxides 8708 Desired material 8709 Etching stop layer 8710 Polysilicon layer 8711 Polysilicon pillar 8712 Oxide 8713 Desired material 8901 Polysilicon layer 8902 Board 8903 Pillar 8904 Oxides 8905 Desired material 9201 Silicon wafer substrate 9202 Silicon nanowire (pillar) 9203 Supporting material 9204 Nickel 9205 Support Board 9206 Encapsulation Layer 9401 Silicon wafer substrate 9402 DLD Pillar 9403 Stabilizing materials 9404 DLD Pillar Cap 9405 Element 9406 Cover Plate 9601 Silicon wafer substrate 9602 DLD Pillar 9603 Layers with etchant-resistant and etchant-soluble components 9604 Porous resistant layer 9801 Silicon wafer substrate 9802 DLD Pillar 9803 DLD Pillar Cap 9804 Sacrificial materials 9805 Cover Plate 9806 Etchant resist film 10201 Silicon wafer substrate 10202 DLD Pillar 10203 Structural materials 10204 Encapsulation Layer 10205 Polysilicon layer 10206 Pillar 10207 Structural materials 10208 Encapsulation Layer 10301 Substrate 10302 Micrometer-scale DLD pillars 10303 Nanometer-scale DLD pillars 10304 Porous layer 10305A-10305B Flow and Etch Stop Layers 10306A~10306B Polysilicon layer 10307 Cover plate

Claims

1. A method for assembling four or more dies on a target substrate, the method comprising: selectively picking the four or more dies from a source substrate by one or more chucking modules attached to the four or more dies; placing and bonding the selectively picked four or more dies onto the target substrate with a precise overlay, the precise overlay being enabled by a fluid disposed between the four or more dies and the target substrate, the precise overlay comprising a difference between a vector position of a point on the four or more dies and a vector position of a corresponding point on the target substrate; A method comprising:

2. The method of claim 1, wherein the assembly is performed to achieve an overlay precision between the four or more dies and the target substrate of one of the following: sub-10 nm, sub-50 nm, sub-100 nm, sub-200 nm, sub-500 nm, and sub-1 μm.

3. The method of claim 1, wherein the precision overlay between the four or more dies and the target substrate is achieved using a nanometer overlay metrology scheme.

4. The method of claim 1, wherein the precision overlay between the four or more dies and the target substrate is achieved using a moire metrology scheme.

5. The method of claim 1, wherein the precision overlay between the four or more dies and the target substrate is achieved using an infrared moire metrology scheme.

6. The method of claim 1, wherein the fluid comprises one or more of the following: IPA, water, adhesive, UV curable adhesive, photoswitchable adhesive, light-to-heat converting adhesive, and silicon low k dielectric.

7. The method of claim 1, wherein the target substrate is one or more of the following: product substrate, transfer substrate, intermediate substrate, carrier substrate, tape frame, dicing tape, tape, silicon wafer, glass wafer, transparent wafer, non-silicon wafer including GaN, GaAs, InP or SiC, and sapphire.

8. The method of claim 1, wherein the bonding comprises one or more of the following: direct bonding, SiO 2 -SiO 2 bonding, anodic bonding, fusion bonding, hybrid bonding, adhesive bonding, self-assembly, temporary bonding, and permanent bonding.

9. The method of claim 1, wherein the arrangement of the four or more dies is arbitrary.

10. The method of claim 1, wherein one or more of the X-pitch and Y-pitch of the four or more dies are changed after pick-up.

11. The method of claim 1, further comprising: picking the four or more dies from the source substrate; arranging the four or more dies on a tape, wherein a pitch along one or more of an X-axis and a Y-axis of the four or more dies matches a corresponding X-pitch and / or Y-pitch on a product substrate; The method of claim 1 further comprising:

12. The method of claim 11, wherein the source substrate is a tape or a dicing tape.

13. The one or more chucking modules include: a first set of chucking modules for picking the four or more dies from the source substrate; a second set of chucking modules that receive the four or more dies from the first set of chucking modules, the second set of chucking modules being used to position and bond the four or more dies onto the target substrate; and The method of claim 1 , comprising:

14. The method of claim 13, wherein the second set of chucking modules further includes an actuation module.

15. The method of claim 1, wherein the one or more chucking modules utilize one or more of the following: an electromagnetic actuator, an electrostatic actuator, a thermal actuator, and a piezoelectric actuator.

16. The method of claim 1, wherein the topography of the four or more dies changes during the positioning and bonding using the one or more chucking modules.

17. The method of claim 1, wherein distortion control of the four or more dies is utilized to enable the precision overlay.

18. The method of claim 17, wherein the strain control is enabled by a thermal actuator.

19. The method of claim 19, further comprising: dispensing the fluid between the four or more dies and the target substrate near edges of the four or more dies and dispensing air in areas not occupied by the fluid between the four or more dies and the target substrate, wherein the dispensing of the fluid and the air enables the precision overlay between the four or more dies and the target substrate. The method of claim 1 further comprising:

20. Subsequently, making a first contact between the four or more dies and the target substrate near a center of the four or more dies; then extending the contact area to cover the four or more dies; 20. The method of claim 19, further comprising:

21. The method of claim 1, wherein surface activation of the four or more dies is performed prior to the assembly to enable the assembly.

22. A system for assembling four or more dies on a target substrate utilizing the method of claim 1.

23. The system of claim 22, further comprising one or more of the following: a fluid dispensing system, a z-head assembly, a bridge, a wafer stage, and a metrology system.

24. The system of claim 23, wherein the one or more chucking modules are attached to the z-head assembly.

25. The system of claim 23, wherein the wafer stage includes one or more chuck assemblies for holding one or more source substrates and product substrates.

26. The system of claim 23, wherein the wafer stage includes one or more of the following: an air bearing stage and a roller bearing stage.

27. ​​The system of claim 22, wherein the one or more chucking modules utilize a thermal actuator.

28. The system described in claim 22, further comprising one or more of the following: a wet cleaning module and a plasma cleaning module.

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