Void-free contact trench filling in gate-all-around FET architectures

Abstract

A method of forming a contact trench structure in a semiconductor device, the method including: performing a first selective deposition process to form contacts on sidewalls of the trenches, each of the sidewalls of the trenches including a first cross section of a first material and a second cross section of a second material; performing a second selective deposition process to form a metal silicide layer on the contacts; performing a first metal fill process to form contact plugs in the trenches, the first metal fill process including depositing a contact plug metal material in the trenches; performing an etching process to form an opening in the trenches, the etching process including partially etching the contact plug metal material in the trenches; and performing a second metal fill process, the second metal fill process including depositing a contact plug metal material in the opening.

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE

[0002] Embodiments described herein relate generally to semiconductor device manufacturing, and more particularly to systems and methods for forming contact trench structures in gate-all-around field effect transistors (FETs). [Background technology]

[0002] Multi-gate metal oxide semiconductor field effect transistors (MOSFETs), e.g., double-gate field effect transistors (FinFETs), silicon-on-insulator (SOI) tri-gate MOSFETs, and gate-all-around (GAA) FETs, which are more scalable than traditional planar bulk MOSFETs because they incorporate multiple gates into a single device, pose production challenges due to their three-dimensional (3D) design and small size. In architectures for technology nodes below 10-15 nm, such as GAA FETs, where the gates are placed on two or all four sides of the silicon-based channel, parasitic or external resistances have a significant impact on device performance. To minimize such parasitic resistances, contacts are formed to interface the silicon-based channel with metal contact plugs. However, this structure poses additional challenges in forming the metal contact plugs, as existing metal filling processes often result in the formation of voids or cores in the contact plugs. The presence of voids in the contact plugs can significantly increase the contact resistance.

[0003] Thus, what is needed is a system and method that can fabricate FET devices with minimized parasitic resistance and void-free metal contact plugs. Summary of the Invention

[0004] An embodiment of the present disclosure provides a method for forming a contact trench structure in a semiconductor device, the method including: performing a first selective deposition process to form contacts on sidewalls of the trenches, each of the sidewalls of the trenches including a first cross-section of a first material and a second cross-section of a second material; performing a second selective deposition process to form a metal silicide layer on the contacts; performing a first metal fill process to form contact plugs in the trenches, the first metal fill process including depositing a contact plug metal material in the trenches; performing an etching process to form openings in the trenches, the etching process including partially etching the contact plug metal material in the trenches; and performing a second metal fill process, the second metal fill process including depositing a contact plug metal material in the openings. The first selective deposition process includes growing a silicide material on the sidewalls of the trench and etching a portion of the silicide material formed on the first cross section of the first material to selectively form a contact on the second cross section of the second material in the trench. The second selective deposition process includes growing a metal silicide material in the trench and on the contact and the first cross section of the first material and etching a portion of the metal silicide material formed on the first cross section of the first material to selectively form a metal silicide layer on the contact.

[0005] An embodiment of the present disclosure also provides a method of forming a void-free trench contact plug in a semiconductor device, the method including: performing a first metal fill process to form a contact plug in the trench, the first metal fill process including depositing a contact plug metal material in the trench, a sidewall of the trench including a first cross section of a first material on which an epitaxially grown contact is formed and a second cross section of a second material; performing an etching process to form an opening in the trench, the etching process including partially etching the contact plug metal material in the trench; and performing a second metal fill process, the second metal fill process including depositing the contact plug metal material in the opening.

[0006] An embodiment of the present disclosure further provides a semiconductor structure, the semiconductor structure including a stack of a first semiconductor layer and a second semiconductor layer, with a trench formed through the stack, a spacer formed at each end of the first semiconductor layer facing the trench, a contact epitaxially grown on each first cross section of the second semiconductor layer in the trench, a metal suicide layer grown on the contact, a barrier metal layer on the metal suicide layer in the trench, and a void-free metal contact plug in the trench.

[0007] So that the above-mentioned features of the present disclosure may be understood in detail, a more particular description of the present disclosure briefly summarized above may be had with reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only typical embodiments of the present disclosure and should not be considered as limiting the scope of the present disclosure, which may admit of other equally effective embodiments. [Brief description of the drawings]

[0008] [Figure 1]1 is a schematic top view of an exemplary multi-chamber processing system according to an embodiment. [Diagram 2] FIG. 2 is a process flow diagram of a method of forming a contact trench structure in a semiconductor structure according to one embodiment. [Figure 3A] FIG. 1 illustrates an isometric view of a semiconductor structure according to one embodiment. [Figure 3B] 1 is a cross-sectional view of a portion of a semiconductor structure according to one embodiment. [Figure 3C] 1 is a cross-sectional view of a portion of a semiconductor structure according to one embodiment. [Figure 3D] 1 is a cross-sectional view of a portion of a semiconductor structure according to one embodiment. [Figure 3E] 1 is a cross-sectional view of a portion of a semiconductor structure according to one embodiment. [Figure 3F] 1 is a cross-sectional view of a portion of a semiconductor structure according to one embodiment. [Figure 3G] 1 is a cross-sectional view of a portion of a semiconductor structure according to one embodiment. [Figure 3H] 1 is a cross-sectional view of a portion of a semiconductor structure according to one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] To facilitate understanding, the same reference symbols have been used, wherever possible, to designate identical elements common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further detail.

[0010] The embodiments described herein provide systems and methods for forming transistor devices for highly scaled processing nodes, such as gate-all-around (GAA) FETs, having metal contact plugs formed in trenches between adjacent device modules and contacts interfacing the contact plugs with silicon-based channels in the device modules. The contacts are formed by selective deposition processes to reduce parasitic resistance. The trenches are then filled with metal on the contacts to form metal contact plugs, which may form voids or cores. Thus, the contact plugs formed in the trenches are partially etched to form openings in the trenches, which are filled with metal to form void-free contact plugs, reducing contact resistance.

[0011] 1 is a schematic top view of an example of a multi-chamber processing system 100 according to some embodiments of the present disclosure. The processing system 100 generally includes a factory interface 102, load lock chambers 104, 106, transfer chambers 108, 110 with respective transfer robots 112, 114, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130. As detailed herein, wafers in the processing system 100 can be processed in and transferred between the various chambers without exposing the wafers to an ambient environment outside the processing system 100 (e.g., an ambient atmospheric environment that may exist in a foundry, etc.). For example, wafers can be processed in and transferred between the various chambers in a low pressure (e.g., about 300 Torr or less) or vacuum environment without breaking the low pressure or vacuum environment between the various processes performed on the wafers in the processing system 100. Therefore, the processing system 100 may provide an integrated solution for processing a portion of a wafer.

[0012] Examples of processing systems that may be suitably modified in accordance with the teachings provided herein include the Endura®, Producer®, or Centura® integrated processing systems or other suitable processing systems available from Applied Materials, Inc., Santa Clara, Calif. It is contemplated that other processing systems, including those from other manufacturers, may be adapted to benefit from the aspects described herein.

[0013] 1, the factory interface 102 includes a docking station 140 and a factory interface robot 142 to facilitate transfer of wafers. The docking station 140 is configured to receive one or more front opening unified pods (FOUPs) 144. In some examples, each factory interface robot 142 generally comprises a blade 148 disposed at one end of the corresponding factory interface robot 142 configured to transfer wafers from the factory interface 102 to the load lock chambers 104, 106.

[0014] The load lock chambers 104, 106 have respective ports 150, 152 coupled to the factory interface 102 and respective ports 154, 156 coupled to the transfer chamber 108. The transfer chamber 108 further has respective ports 158, 160 coupled to the holding chambers 116, 118 and respective ports 162, 164 coupled to the processing chambers 120, 122. Similarly, the transfer chamber 110 has respective ports 166, 168 coupled to the holding chambers 116, 118 and respective ports 170, 172, 174, 176 coupled to the processing chambers 124, 126, 128, 130. Ports 154, 156, 158, 160, 162, 164, 166, 168, 170, 172, 174, 176 may be, for example, slit valve openings having slit valves for transferring wafers by transfer robots 112, 114 and for providing a seal between each chamber to prevent gas passing between each chamber. Generally, any port is open for transferring wafers and is otherwise closed.

[0015] The load lock chambers 104, 106, the transfer chambers 108, 110, the holding chambers 116, 118, and the processing chambers 120, 122, 124, 126, 128, 130 may be fluidly coupled to a gas and pressure control system (not specifically shown). The gas and pressure control system may include one or more gas pumps (e.g., turbo pumps, cryopumps, roughing pumps), gas sources, various valves, and conduits fluidly coupled to the various chambers. In operation, the factory interface robot 142 transfers a wafer from the FOUP 144 through the port 150 or 152 to the load lock chamber 104 or 106. The gas and pressure control system pumps down the load lock chamber 104 or 106. The gas and pressure control system further maintains the transfer chambers 108, 110 and the holding chambers 116, 118 at an internal low pressure or vacuum environment (which may include an inert gas). Therefore, pumping down the load lock chambers 104 or 106 may facilitate the transfer of wafers between, for example, the atmospheric environment of the factory interface 102 and the low pressure or vacuum environment of the transfer chamber 108 .

[0016] With the wafer in the pumped down load lock chamber 104 or 106, the transfer robot 112 transfers the wafer from the load lock chamber 104 or 106 into the transfer chamber 108 through ports 154 or 156. The transfer robot 112 can then transfer the wafer to and / or between either of the processing chambers 120, 122 for processing through respective ports 162, 164 and the holding chambers 116, 118 for holding awaiting further transfer through respective ports 158, 160. Similarly, the transfer robot 114 can access wafers in the holding chambers 116 or 118 through ports 166 or 168 and can transfer wafers to and / or between any of the processing chambers 124, 126, 128, 130 for processing through respective ports 170, 172, 174, 176 and the holding chambers 116, 118 for holding awaiting further transfer through respective ports 166, 168. The transfer and holding of wafers in and between the various chambers can be performed in a low pressure or vacuum environment provided by a gas and pressure control system.

[0017] The processing chambers 120, 122, 124, 126, 128, 130 may be any suitable chambers for processing wafers. In some examples, the processing chamber 122 may be capable of performing a cleaning process, the processing chamber 120 may be capable of performing an etching process, and the processing chambers 124, 126, 128, 130 may be capable of performing respective epitaxial growth processes. The processing chamber 122 may be a SiCoNi™ Preclean chamber available from Applied Materials of Santa Clara, Calif. The processing chamber 120 may be a Selectra™ etch chamber available from Applied Materials of Santa Clara, Calif.

[0018] A system controller 190 is coupled to the processing system 100 to control the processing system 100 or components thereof. For example, the system controller 190 may control the operation of the processing system 100 using direct control of the chambers 104, 106, 108, 116, 118, 110, 120, 122, 124, 126, 128, 130 of the processing system 100 or by controlling controllers associated with the chambers 104, 106, 108, 116, 118, 110, 120, 122, 124, 126, 128, 130. During operation, the system controller 190 enables data collection and feedback from each chamber to regulate the performance of the processing system 100.

[0019] The system controller 190 generally includes a central processing unit (CPU) 192, a memory 194, and support circuits 196. The CPU 192 may be one of any form of general-purpose processor available in an industrial environment. The memory 194 or non-transitory computer-readable medium is accessible by the CPU 192 and may be one or more of memory such as random access memory (RAM), read-only memory (ROM), floppy disk, hard disk, or any other form of digital storage, local or remote. The support circuits 196 are coupled to the CPU 192 and may include cache, clock circuits, input / output subsystems, power supplies, and the like. The various methods disclosed herein may generally be performed under the control of the CPU 192 by the CPU 192 executing computer instruction codes stored in the memory 194 (or the memory of a particular process chamber) as, for example, software routines. When the computer instruction codes are executed by the CPU 192, the CPU 192 controls the chamber to perform processes according to the various methods.

[0020] Other processing systems may have other configurations. For example, more or fewer processing chambers may be coupled to the transfer apparatus. In the example shown, the transfer apparatus includes transfer chambers 108, 110 and holding chambers 116, 118. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chambers) may be implemented as the transfer apparatus in a processing system.

[0021] FIG. 2 illustrates a process flow diagram of a method 200 of forming a contact trench structure in a semiconductor structure 300 according to one or more implementations of the present disclosure. FIG. 3A illustrates an isometric view of the semiconductor structure 300. FIG. 3B, FIG. 3C, FIG. 3D, FIG. 3E, FIG. 3F, FIG. 3G, and FIG. 3H are cross-sectional views of a portion of the semiconductor structure 300 corresponding to various states of the method 200. It should be understood that FIG. 3A, FIG. 3B, FIG. 3C, FIG. 3D, FIG. 3E, FIG. 3F, FIG. 3G, and FIG. 3H illustrate only partial schematic views of the semiconductor structure 300, and that the semiconductor structure 300 may contain any number of transistor portions and additional materials having the aspects as shown in the figures. It should also be noted that while the method illustrated in FIG. 2 is described sequentially, other process sequences including one or more omitted and / or added operations and / or rearranged in another desired order are within the scope of the embodiments of the present disclosure provided herein.

[0022] 3A, 3B, 3C, 3D, 3E, 3F, 3G, and 3H, a semiconductor structure 300 may include a substrate 302 having a first gate-all-around field effect transistor (GAA FET) module TR1 and a second GAA FET module TR2. The second GAA FET module TR2 is not shown in FIG. 3A. The first GAA FET module TR1 and the second GAA FET module TR2 are separated by a trench 304.

[0023] The term "substrate" as used herein refers to a layer of material that serves as a base for subsequent processing operations and includes a surface to be cleaned. The substrate 302 may be a silicon-based material or any suitable insulating or conductive material, as appropriate. The substrate 302 may be crystalline silicon (e.g., Si <100> or Si <111> ), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers and patterned or unpatterned wafers, silicon-on-insulator (SOI), carbon doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, or sapphire.

[0024] Each of the GAA FET modules TR1 and TR2 includes a first semiconductor layer 306 and a second semiconductor layer 308 alternately and repeatedly stacked on a substrate 302. The first semiconductor layer 306 is formed of a first material having an etch selectivity with respect to a second material from which the second semiconductor layer 308 is formed (i.e., the etch rate of the first material is higher than the etch rate of the second material). The etch selectivity (i.e., the ratio of the etch rate of the first material to the etch rate of the second material) is about 10:1 to 200:1. Exemplary combinations of first and second materials include silicon germanium (SiG The stack of first semiconductor layer 306 and second semiconductor layer 308 is separated by trench 304 between the first GAA FET module TR1 and the second GAA FET module TR2, and is divided into separate pillars 310 in each of the first GAA FET module TR1 and the second GAA FET module TR2. The first semiconductor layer 306 may be selectively etched to form recesses at the ends of the first semiconductor layer 306 facing the trenches 304, each of which has a spacer 312 formed therein. These spacers 312 may be formed between source / drain regions (not shown) deposited next to the pillars in the first GAA FET module TR1 and the second GAA FET module TR2. The spacers 312 may be formed of a dielectric material such as silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), silicon oxycarbide (SiOC), boron-doped silicon oxycarbonitride (SiOCBN), aluminum oxide (Al2O3), or hafnium oxide (HfO2).

[0025] The second semiconductor layer 308 in the pillar can act as a channel having a width of several nanometers to several tens of nanometers.

[0026] The first semiconductor layer 306 and the second semiconductor layer 308 may be formed using any suitable deposition technique, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD), and the pillars 310 are formed by a patterning technique, such as a lithography and etching process. The first semiconductor layer 306 and the second semiconductor layer 308 may each have a thickness of about 6 nm to about 14 nm, for example about 10 nm. The selective etching of the first semiconductor layer 306 may be performed by any suitable etching process, such as a dry plasma etching process.

[0027] The method 200 begins with a first selective deposition process in block 210 to selectively form a contact 314 on an exposed cross-section 308S of the second semiconductor layer 308 in the trench 304, as shown in FIG. 3C. The contact 314 is formed as an interface between the second semiconductor layer 308 and a metal contact plug, as discussed below, to minimize parasitic resistance. The contact 314 is formed of a third material. Examples of the third material include silicon (Si), silicon carbide (SiC), and silicon germanium (SiGe) with a germanium (Ge) ratio ranging from 20% to 100%. The contact 314 is formed of a third material having a concentration of about 10, depending on the desired conductive properties of the contact 314. 20 cm -3 ~5·10 21 cm -3 The contact 314 may be doped with a p-type dopant, such as boron (B) or gallium (Ga), at a concentration of about 10 20 cm -3 ~5·10 21 cm -3 It may be doped with n-type dopants such as phosphorus (P) and antimony (Sb).

[0028] The first selective deposition process includes a first deposition process and a first etching process. The first deposition process is an epitaxial deposition process. The selectivity in the first selective deposition process may result from the difference in nucleation of a third material on the exposed cross section 308S of the second semiconductor layer 308 (e.g., silicon (Si) or silicon germanium (SiGe)) and the exposed cross section 312S of the spacer 312 (e.g., silicon dioxide (SiO2) or silicon nitride (Si3N4)) in the trench 304. Because nucleation may occur at a faster rate at the exposed cross-sections 308S of the second semiconductor layer 308 (e.g., silicon (Si) or silicon germanium (SiGe)) than at the exposed cross-sections 312S of the spacers 312 (e.g., silicon dioxide (SiO2) or silicon nitride (Si3N4)) (as shown in FIG. 3B), an epitaxial layer of a third material may be formed on the exposed cross-sections 308S of the second semiconductor layer 308 (e.g., silicon (Si) or silicon germanium (SiGe)), and an amorphous layer of a third material may be formed on the exposed cross-sections 312S of the spacers 312 (e.g., silicon dioxide (SiO2) or silicon nitride (Si3N4)) in the trench 304 when the sidewalls 304S of the trench 304 are exposed to a deposition gas containing a silicon source and a metal source in the first deposition process. In a subsequent first etching process, the amorphous layer of the third material formed on the exposed cross sections 312S of the spacers 312 can be etched by a suitable etching gas at a faster rate than the epitaxial layer of the third material formed on the exposed cross sections 308S of the second semiconductor layer 308. Thus, the first deposition process and the first etching process may be combined to generally result in epitaxial growth of the third material on the exposed cross sections 308S of the second semiconductor layer 308 in the trenches 304, while minimizing growth, if any, of the third material on the exposed cross sections 312S of the spacers 312.

[0029] In some embodiments, the silicon source in the deposition gas may include a silicon-containing precursor, such as, for example, silane (SiH4), dichlorosilane (SiH2Cl2), trichlorosilane (SiHCl3), tetrachlorosilane (SiCl4), disilane (Si2H6), and trisilane (Si3H8), or combinations thereof. The deposition gas may alternatively include a germanium source, including a germanium-containing precursor, such as germane (GeH4) and digermane (Ge2H6). The process gas may further include a dopant source. The dopant source may include, for example, carbon, phosphorus, boron, arsenic, gallium, or aluminum, depending on the desired conductive properties of the epitaxially deposited contact 314. The metal source in the deposition gas may include, for example, nickel (Ni), cobalt (Co), tungsten (W), titanium (Ti), and iron (Fe). The dopant source may include the precursor diborane (B2H6) for p-type doping and phosphorus (PH3) for n-type doping. The etching gas includes an etchant gas and a carrier gas. The etchant gas may include a halogen-containing gas, such as hydrogen chloride (HCI), chlorine (Cl2), or hydrogen fluoride (HF). The carrier gas may include nitrogen (N2), argon (Ar), helium (He), or hydrogen (H2).

[0030] The first deposition process and the first etch process in block 210 may each be performed in a processing chamber, such as processing chambers 120, 122, 124, 126, 128, or 130 shown in FIG. 1, at a temperature between about 300° C. and about 800° C. and a pressure between 5° Torr and 600° Torr.

[0031] The cycle of the first deposition process and the first etching process may be repeated as necessary to obtain a desired thickness of the contact 314 in the trench 304. The thickness of the contact 314 may be from about 5 Å to about 10 Å.

[0032] It should be noted that the epitaxially grown third material may show a clear crystal orientation relationship to the exposed cross-section 308S of the second semiconductor layer 308 because the epitaxially grown third material has a similar crystal structure and a small lattice mismatch to the exposed cross-section 308S of the second semiconductor layer 308. For example, nickel silicide (NiSi2) can be epitaxially grown on silicon single crystal (100) and (111), and the lattice match is good. Due to this crystal orientation relationship between the epitaxially grown third material and the exposed cross-section 308S of the second semiconductor layer 308, the epitaxially grown contact 314 may be ball-shaped or pyramid-shaped, depending on the conditions for the first deposition process and the first etching process, respectively.

[0033] 3D, a second selective deposition process is performed to deposit a metal silicide layer 316 on the contact 314. The metal silicide layer 316 applies to the contact 314 and provides and maintains an electrical connection between the contact plug in the trench 304 and the second semiconductor layer 308. The metal silicide layer 316 may be formed of a metal silicide material such as titanium silicide (Ti), cobalt silicide (Co), nickel silicide (Ni), molybdenum silicide (Mo), or tantalum silicide (Ta).

[0034] The second selective deposition process includes a second deposition process and a second etching process. The selectivity in the second selective deposition process may result from a difference in nucleation of metal silicide material on the contact 314 (e.g., silicon (Si) or silicon germanium (SiGe)) and the exposed cross section 312S of the spacer 312 (e.g., silicon dioxide (SiO2) or silicon nitride (Si3N4)) in the trench 304. Because nucleation may occur at a faster rate on the contacts 314 (e.g., silicon (Si) or silicon germanium (SiGe)) than on the exposed cross sections 312S of the spacers 312 (e.g., silicon dioxide (SiO2) or silicon nitride (Si3N4)), an epitaxial layer of metal silicide material may be formed on the contacts 314 (e.g., silicon (Si) or silicon germanium (SiGe)), and an amorphous layer of metal silicide material may be formed on the exposed cross sections 312S of the spacers 312 (e.g., silicon dioxide (SiO2) or silicon nitride (Si3N4)) in the trenches 304 when exposed to a deposition gas containing a metal silicide source in a second deposition process. In a subsequent second etching process, the amorphous layer of metal silicide material formed on the exposed cross sections 312S of the spacers 312 can be etched at a faster rate by a suitable etching gas than the epitaxial layer of metal silicide material formed on the contacts 314. Thus, the combination of the second deposition process and the second etching process may generally result in epitaxial growth of metal silicide material on the contacts 314 in the trenches 304, while minimizing the growth of metal silicide material, if any, on the exposed cross sections 312S of the spacers 312.

[0035] In some embodiments, the metal silicide source may include titanium (Ti), tantalum (Ta), or a combination thereof. The etching gas includes an etchant gas and a carrier gas. The etchant gas may include a chlorine-containing gas, such as hydrogen chloride (HCI), chlorine (Cl2), carbon tetrachloride (CCl4), chloroform (CHCl3), dichloromethane (CH2Cl2), or chloromethane (CH3Cl). The carrier gas may include nitrogen (N2), argon (Ar), helium (He), or hydrogen (H2). A carbon-containing gas, such as methane (CH4), ethane (C2H6), or ethylene (C2H4), may also be provided as a catalyst for etching the metal silicide layer 316.

[0036] The second deposition process and the second etching process in block 220 may each be performed in a processing chamber, such as processing chambers 120, 122, 124, 126, 128, or 130 shown in FIG. 1, at a temperature between about 300° C. and about 800° C. and a pressure between 1° Torr and 5° Torr.

[0037] The cycle of the second deposition process and the second etching process may be repeated as necessary to obtain the desired thickness of the metal suicide layer 316.

[0038] In block 230, a conformal deposition process is performed to form a barrier metal layer 318 on exposed surfaces of the trench 304, including the metal silicide layer 316, the exposed cross sections 312S of the spacers 312, the bottom surface 320 of the trench 304, and the top surfaces 322 of the first and second GAA FET modules TR1 and TR2, as shown in FIG. 3E. The barrier metal layer 318 protects the metal silicide layer 316 and enables nucleation and growth of the contact plugs 324 in the trench 304, as discussed below. The barrier metal layer 318 may be formed of a barrier metal material that is titanium nitride (TiN) or tantalum nitride (TaN).

[0039] The conformal deposition process in block 230 may include any suitable deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), spin-on, physical vapor deposition (PVD), etc., in a processing chamber, such as processing chambers 120, 122, 124, 126, 128, or 130 shown in FIG. 1, at a temperature between about 100° C. and about 300° C.

[0040] In block 240, a first metal filling process is performed to fill the trench 304 with a metal to form a contact plug 324, as shown in FIG. 3F. The contact plug 324 formed in the first metal filling process in block 240 may be formed of a contact plug metal material, such as tungsten (W), cobalt (Co), ruthenium (Ru), or molybdenum (Mo). The contact plug 324 may be p-type doped or n-type doped. The first metal filling process in block 240 may include a chemical vapor deposition (CVD) process using a tungsten-containing precursor, such as WF6, or a cobalt-containing precursor in a processing chamber, such as processing chamber 120, 122, 124, 126, 128, or 130 shown in FIG. 1.

[0041] The contact plug 324 deposited in the first metal fill process in block 240 may contain voids 326 in the trench 304 because the width of the trench 304 is narrowed by the contact 314, metal silicide layer 316, and second barrier metal layer 318 formed in blocks 210-230, thereby partially blocking the path for the metal fill deposition. The method 200 proceeds in blocks 240-250 to remove the voids 326 in the contact plug 324 in the trench 304.

[0042] In block 250, an etching process is performed to selectively etch the contact plug 324 in the trench 304 and form an opening 328, as shown in Figure 3G. The etching process in block 250 is performed in a processing chamber, such as processing chamber 120, 122, 124, 126, 128, or 130 shown in Figure 1, using an etching gas including an etchant gas and a carrier gas. The etchant gas may include a fluorine-containing gas, such as nitrogen trifluoride (NF3).

[0043] In block 260, a second metal process is performed to fill the opening 328 with a contact plug metal material to form a contact plug 330, as shown in FIG. 3H. The second metal filling process in block 260 is performed under the same conditions as the first metal filling process in block 240. The etching process in block 250 and the second metal filling process in block 260 may be repeated until the contact plug 330 is void-free. Such void-free quality of the contact plug 330 may be observed by a scanning electron microscope (SEM) or a tunneling microscope (TEM), and the resistance of the contact plug 314 may be reduced. In some embodiments, the etching process in block 250 and the second metal filling process in block 260 are repeated for about 10 cycles.

[0044] The embodiments described herein provide systems and methods for forming contact trench structures in transistor devices such as gate-all-around (GAA) FETs. The contact trench structures include metal contact plugs formed in trenches between adjacent device modules and contacts that interface the contact plugs with silicon-based channels in the device modules. The contacts are formed by a selective deposition process to reduce parasitic resistance. The metal contact plugs are formed without voids per deposition-etch process to reduce contact resistance.

[0045] While the forgoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope of the disclosure, the scope of which is determined by the following claims.

Claims

1. 1. A method of forming a contact trench structure in a semiconductor device, comprising: performing a first selective deposition process to form contacts on sidewalls of trenches, each of the sidewalls of the trenches including a first cross-section of a first material and a second cross-section of a second material, the first selective deposition process comprising: epitaxially growing a third material on the sidewalls of the trench; and performing a first selective deposition process, the first selective deposition process including etching a portion of the third material formed on the first cross section of the first material to selectively form the contact on the second cross section of the second material in the trench; performing a second selective deposition process to form a metal silicide layer on the contact, the second selective deposition process comprising: growing a metal suicide material in the trench, on the contact and on the first cross section of the first material; and performing a second selective deposition process including etching portions of the metal silicide material formed on the first cross section of the first material to form the metal silicide layer selectively on the contact; performing a first metal fill process to form a contact plug in the trench, the first metal fill process including depositing a contact plug metal material in the trench; performing an etching process to form an opening in the trench, the etching process including partially etching the contact plug metal material in the trench; performing a second metal fill process, the second metal fill process including depositing the contact plug metal material in the opening.

2. the first material comprises silicon dioxide or silicon nitride; The method of claim 1 , wherein the second material comprises a silicon-containing material.

3. The method of claim 1 , wherein the third material comprises a material selected from the group consisting of silicon (Si), silicon carbide (SiC), and silicon germanium (SiGe).

4. 2. The method of claim 1, wherein the contact plug metal material comprises a material selected from the group consisting of tungsten (W), cobalt (Co), ruthenium (Ru), and molybdenum (Mo).

5. 2. The method of claim 1, wherein the metal silicide material comprises a material selected from the group consisting of titanium silicide (Ti), cobalt silicide (Co), nickel silicide (Ni), molybdenum silicide (Mo), or tantalum silicide (Ta).

6. performing a conformal deposition process prior to the first metal filling process, the conformal deposition process comprising: The method of claim 1 , further comprising performing a conformal deposition process comprising depositing a barrier metal material on exposed surfaces of the trench.

7. 7. The method of claim 6, wherein the barrier metal material comprises a material selected from the group consisting of titanium nitride (TiN) and tantalum nitride (TaN).

8. 1. A method for forming a void-free trench contact plug in a semiconductor device, comprising: performing a first metal fill process to form a contact plug in a trench, the first metal fill process including depositing a contact plug metal material in the trench, a sidewall of the trench including a first cross section of a first material in which an epitaxially grown contact is formed, and a second cross section of a second material; performing an etching process to form an opening in the trench, the etching process including partially etching the contact plug metal material in the trench; performing a second metal fill process, the second metal fill process including depositing the contact plug metal material in the opening.

9. the first material comprises silicon dioxide or silicon nitride; The method of claim 8 , wherein the second material comprises a silicon-containing material.

10. 9. The method of claim 8, wherein the epitaxially grown contact comprises a material selected from the group consisting of silicon (Si), silicon carbide (SiC), and silicon germanium (SiGe).

11. 9. The method of claim 8, wherein the contact plug metal material comprises a material selected from the group consisting of tungsten (W), cobalt (Co), ruthenium (Ru), and molybdenum (Mo).

12. The method of claim 8 further comprising conformally depositing a barrier metal layer on the exposed surfaces of the trench.

13. The method of claim 12, wherein the barrier metal layer comprises a material selected from the group consisting of titanium nitride (TiN) and tantalum nitride (TaN).

14. a stack of a first semiconductor layer and a second semiconductor layer, a trench being formed through the stack; a spacer formed at each end of the first semiconductor layer facing the trench; a contact epitaxially grown in each of the first cross sections of the second semiconductor layer within the trench; a metal silicide layer grown on said contact; a barrier metal layer over the metal silicide layer in the trench; a void-free metal contact plug in said trench.

15. the first semiconductor layer comprises silicon germanium; 15. The semiconductor structure of claim 14 wherein said second semiconductor layer comprises silicon.

16. 15. The semiconductor structure of claim 14 wherein said spacers comprise silicon dioxide or silicon nitride.

17. 15. The semiconductor structure of claim 14 wherein said contact comprises a material selected from the group consisting of silicon (Si), silicon carbide (SiC), and silicon germanium (SiGe).

18. 15. The semiconductor structure of claim 14, wherein said void-free metal contact plug comprises a material selected from the group consisting of tungsten (W), cobalt (Co), ruthenium (Ru), and molybdenum (Mo).

19. 15. The semiconductor structure of claim 14 wherein said metal suicide layer comprises a material selected from the group consisting of titanium suicide (Ti), cobalt suicide (Co), nickel suicide (Ni), molybdenum suicide (Mo), or tantalum suicide (Ta).

20. The semiconductor structure of claim 14, wherein the barrier metal layer comprises a material selected from the group consisting of titanium nitride (TiN) and tantalum nitride (TaN).

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