Package containing integrated devices coupled through bridges - Patents.com

Abstract

1. A package comprising: a first integrated device comprising a first plurality of under bump metallization interconnects; a second integrated device comprising a second plurality of under bump metallization interconnects; a bridge coupled to the first integrated device and the second integrated device; an encapsulation layer at least partially encapsulating the first integrated device, the second integrated device, and the bridge; a metallization portion located on the first integrated device, the second integrated device, the bridge, and the encapsulation layer, the metallization portion including at least one dielectric layer and a plurality of metallization interconnects; a first plurality of pillar interconnects coupled to the first plurality of under bump metallization interconnects, the first plurality of pillar interconnects being located in the encapsulation layer; and a second plurality of pillar interconnects coupled to the second plurality of under bump metallization interconnects, the second plurality of pillar interconnects being located in the encapsulation layer.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to and the benefit of nonprovisional application Ser. No. 17 / 328,666, filed in the United States Patent Office on May 24, 2021, the entire contents of which are incorporated herein by reference for all applicable purposes as if fully set forth herein below.

[0002] Various features relate to a package that contains the integrated device. [Background technology]

[0003] A package may include a substrate and several integrated devices mounted on the substrate. The integrated devices may be configured to communicate with each other through the substrate. There is a continuing need to provide packages having integrated devices with improved communication capabilities between the integrated devices. These packages may have a smaller footprint and a lower profile. Summary of the Invention [Means for solving the problem]

[0004] Various features relate to a package that contains the integrated device.

[0005] One example provides a package including a first integrated device comprising a first plurality of under bump metallization interconnects, a second integrated device comprising a second plurality of under bump metallization interconnects, a bridge coupled to the first integrated device and the second integrated device, an encapsulation layer at least partially encapsulating the first integrated device, the second integrated device, and the bridge, a metallization portion located on the first integrated device, the second integrated device, the bridge, and the encapsulation layer, the metallization portion including at least one dielectric layer and a plurality of metallization interconnects, a first plurality of pillar interconnects coupled to the first plurality of under bump metallization interconnects and the metallization portion, the first plurality of pillar interconnects being located in the encapsulation layer, and a second plurality of pillar interconnects coupled to the second plurality of under bump metallization interconnects and the metallization portion, the second plurality of pillar interconnects being located in the encapsulation layer.

[0006] Another example includes a first integrated device comprising a first plurality of under-bump metallization interconnects, a second integrated device comprising a second plurality of under-bump metallization interconnects, a means for bridging interconnection coupled to the first integrated device and the second integrated device, a means for encapsulation at least partially encapsulating the first integrated device, the second integrated device, and the means for bridging interconnection, and a metallization portion overlying the first integrated device, the second integrated device, the means for bridging interconnection, and the means for encapsulation. the metallization portion including at least one dielectric layer and a plurality of metallization interconnects; a first plurality of pillar interconnects coupled to the first plurality of under-bump metallization interconnects and the metallization portion, the first plurality of pillar interconnects being located on the means for encapsulation; and a second plurality of pillar interconnects coupled to the second plurality of under-bump metallization interconnects and the metallization portion, the second plurality of pillar interconnects being located on the means for encapsulation.

[0007] Another example provides a method for manufacturing a package. The method couples a bridge to a first integrated device and a second integrated device. The first integrated device comprises a first plurality of under-bump metallization interconnects. The second integrated device comprises a second plurality of under-bump metallization interconnects. The method forms a first plurality of pillar interconnects over the first plurality of under-bump metallization interconnects. The method forms a second plurality of pillar interconnects over the second plurality of under-bump metallization interconnects. The method forms an encapsulation layer that at least partially encapsulates the first integrated device, the second integrated device, the bridge, the first plurality of pillar interconnects, and the second plurality of pillar interconnects. The method forms a metallization portion over the first integrated device, the second integrated device, the bridge, and the encapsulation layer, and forming the metallization portion includes forming at least one dielectric layer and forming the plurality of metallization interconnects.

[0008] Various features, nature and advantages may become apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters refer to the same correspondingly throughout. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 illustrates a package including integrated devices coupled through a bridge. [Diagram 2] FIG. 1 illustrates a package including integrated devices coupled through a bridge. [Diagram 3] FIG. 1 illustrates a package-on-package (PoP) diagram with a package containing an integrated device coupled through a bridge. [Figure 4] FIG. 1 illustrates a package including integrated devices coupled through multiple bridges. [Figure 5A]1A-1C illustrate an exemplary sequence for manufacturing a package including integrated devices coupled through a bridge. [Figure 5B] 1A-1C illustrate an exemplary sequence for manufacturing a package including integrated devices coupled through a bridge. [Figure 5C] 1A-1C illustrate an exemplary sequence for manufacturing a package including integrated devices coupled through a bridge. [Figure 5D] 1A-1C illustrate an exemplary sequence for manufacturing a package including integrated devices coupled through a bridge. [Figure 6] 1 illustrates an example flow diagram of a method for manufacturing a package including integrated devices coupled through a bridge. [Figure 7A] 1A-1C illustrate an exemplary sequence for manufacturing a package including integrated devices coupled through a bridge. [Figure 7B] 1A-1C illustrate an exemplary sequence for manufacturing a package including integrated devices coupled through a bridge. [Figure 7C] 1A-1C illustrate an exemplary sequence for manufacturing a package including integrated devices coupled through a bridge. [Figure 8] 1 illustrates an example flow diagram of a method for manufacturing a package including integrated devices coupled through a bridge. [Figure 9] 1 illustrates various electronic devices that may integrate a die, integrated device, integrated passive device (IPD), device package, package, integrated circuit, and / or PCB as described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] In the following description, specific details are given to enable a thorough understanding of various aspects of the present disclosure. However, it will be understood by those skilled in the art that aspects may be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring the aspects in unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail to avoid obscuring aspects of the present disclosure.

[0011] The present disclosure describes a package including a first integrated device comprising a first plurality of under bump metallization interconnects, a second integrated device comprising a second plurality of under bump metallization interconnects, a bridge coupled to the first integrated device and the second integrated device, an encapsulation layer at least partially encapsulating the first integrated device, the second integrated device, and the bridge, a metallization portion located on the first integrated device, the second integrated device, the bridge, and the encapsulation layer, the metallization portion including at least one dielectric layer and a plurality of metallization interconnects, a first plurality of pillar interconnects coupled to the first plurality of under bump metallization interconnects and the metallization portion, the first plurality of pillar interconnects being located in the encapsulation layer, and a second plurality of pillar interconnects coupled to the second plurality of under bump metallization interconnects and the metallization portion, the second plurality of pillar interconnects being located in the encapsulation layer. The use of bridges can help provide shorter electrical paths between integrated devices, which can help improve the performance of the integrated devices and packages.

[0012] Exemplary Package Including Integrated Devices Coupled Through Bridges 1 shows an example of a package 100 including integrated devices coupled through a bridge. The package 100 is coupled to a board 190 (e.g., a printed circuit board) through a number of solder interconnects 170. The package 100 includes an integrated device 102, an integrated device 104, a metallization portion 106, a bridge 108, and an encapsulation layer 110.

[0013] The metallization portion 106 includes at least one dielectric layer 160 and a plurality of metallization interconnects 162. A back side of the bridge 108 faces the metallization portion 106. The back side of the bridge 108 may be bonded to the metallization portion 106. The metallization portion 106 is bonded to an encapsulation layer 110. The encapsulation layer 110 may at least partially encapsulate the bridge 108. The encapsulation layer 110 may be a means for encapsulation. The integrated device 102 and the integrated device 104 may be bonded to the bridge 108. A front side of the integrated device 102 may face a front side of the bridge 108. The front side of the integrated device 102 may also face the metallization portion 106. The metallization portion 106 may be a first metallization portion. The integrated device 102 may be coupled (e.g., mechanically coupled, electrically coupled) to the metallization portion 106 through pillar interconnects 112. The pillar interconnects 112 may be through mold vias (e.g., TMV) and / or through mold interconnects.

[0014] Similarly, the front side of the integrated device 104 may face the front side of the bridge 108. The front side of the integrated device 104 may also face the metallization portion 106. The integrated device 104 may be coupled (e.g., mechanically coupled, electrically coupled) to the metallization portion 106 through a plurality of pillar interconnects 114. The plurality of pillar interconnects 114 may be a plurality of through mold vias (e.g., TMV) and / or a plurality of through mold interconnects. The integrated device 102 and the integrated device 104 may be part of a back side of the package 100.

[0015] Metallization portion 106 may at least partially encapsulate bridge 108, multiple pillar interconnects 112, multiple pillar interconnects 114, integrated device 102, and / or integrated device 104. Metallization portion 106 may be part of and / or located on a front surface of package 100.

[0016] The integrated device 102 may be configured to be electrically coupled to the integrated device 104 through the bridge 108. One advantage of the bridge 108 is that the bridge 108 provides a shorter electrical path for currents (e.g., electrical signals, input / output signals) between the integrated device 102 and the integrated device 104, which helps improve the overall performance of the package 100 and the performance of the integrated device 102 and the integrated device 104. The currents between the integrated device 102 and the integrated device 104 that travel through the bridge 108 do not have to travel through the plurality of pillar interconnects 112, the plurality of pillar interconnects 114, and the metallization portion 106. Additionally, as described further below, the bridge 108 may be configured to include a plurality of bridge interconnects that include a width of 1 micrometer or less (e.g., 0.5 to 1 micrometer). The bridge interconnects of the bridge 108 may have a width that is smaller than the width of the plurality of metallization interconnects 162 of the metallization portion 106. The smaller width of the bridge interconnect can help provide more electrical paths in a given area between integrated device 102 and integrated device 104, which can help enable faster communication and more communication paths between integrated device 102 and integrated device 104.

[0017] The integrated device 102 (e.g., a first integrated device) may include a die (e.g., a bare semiconductor die). The integrated device 102 includes a die substrate 120, a passivation layer 122, and a plurality of pads 124. The integrated device 102 may include a plurality of under-bump metallization interconnects 126. The die substrate 120 may include silicon. The die substrate 120 may include a plurality of active devices (e.g., transistors). A front end of line (FEOL) process may be used to fabricate the die substrate 120. The plurality of pads 124 may be located on the die substrate 120. The plurality of pads 124 may be a top layer of the integrated device 102. The plurality of pads 124 may be configured to be electrically coupled to the active devices (e.g., transistors). The passivation layer 122 may be located on the plurality of pads 124 and the die substrate 120. The integrated device 102 may include a frontside and a backside. The front side of the integrated device 102 may include a side of the integrated device 102 that includes the under-bump metallization interconnects 126, the pads 124, and / or the passivation layer 122. The back side of the integrated device 102 may include a side facing away from the pads 124. The back side of the integrated device 102 may include a side that includes the die substrate 120. The under-bump metallization interconnects 126 are coupled to the pads 124.

[0018] The integrated device 104 (e.g., a second integrated device) may include a die (e.g., a bare semiconductor die). The integrated device 104 includes a die substrate 140, a passivation layer 142, and a plurality of pads 144. The integrated device 104 may include a plurality of under-bump metallization interconnects 146. The die substrate 140 may include silicon. The die substrate 140 may include a plurality of active devices (e.g., transistors). A front-end-of-line (FEOL) process may be used to fabricate the die substrate 140. The plurality of pads 144 may be located on the die substrate 140. The plurality of pads 144 may be a top layer of the integrated device 104. The plurality of pads 144 may be configured to be electrically coupled to the active devices (e.g., transistors). The passivation layer 142 may be located on the plurality of pads 144 and the die substrate 140. The integrated device 104 may include a front surface and a back surface. The front side of the integrated device 104 may include a side of the integrated device 104 that includes the plurality of under bump metallization interconnects 146, the plurality of pads 144, and / or the passivation layer 142. The back side of the integrated device 104 may include a side that faces away from the plurality of pads 144. The back side of the integrated device 104 may include a side that includes the die substrate 140. The plurality of under bump metallization interconnects 146 are coupled to the plurality of pads 144.

[0019] In some implementations, the integrated device 102 and / or the integrated device 104 may include one or more interconnects and one or more dielectric layers located on a die substrate (e.g., 120, 140). The one or more interconnects and one or more dielectric layers may be located between the die substrate (e.g., 120, 140) and a passivation layer (e.g., 122, 142). In such cases, the pads (e.g., 124, 144) may be coupled to one or more interconnects. The one or more interconnects may be coupled to one or more active devices (e.g., transistors). A back end of line (BEOL) process may be used to fabricate the one or more interconnects and one or more dielectric layers.

[0020] The bridge 108 includes a substrate 180 (e.g., a die substrate), a passivation layer 182, a plurality of bridge interconnects 185, a plurality of bridge interconnects 184, and a plurality of bridge interconnects 186. The bridge 108 may be a means for bridge interconnection. The bridge 108 may be a bridge die. The bridge 108 may be a passive die. The substrate 180 may include silicon. The plurality of bridge interconnects 185 are formed and located on the substrate 180. The passivation layer 182 may be located on the plurality of bridge interconnects 185. The plurality of bridge interconnects 184 are coupled to the plurality of bridge interconnects 185. The plurality of bridge interconnects 186 are coupled to the plurality of bridge interconnects 185. The plurality of bridge interconnects 184 and / or the plurality of bridge interconnects 186 may include a plurality of bridge under bump metallization interconnects and / or a plurality of bridge post interconnects. The plurality of bridge interconnects 185 may be arranged in a row of bridge interconnects. In some implementations, one or more bridge interconnects from the plurality of bridge interconnects 185 may have a width of 1 micrometer or less (e.g., 0.5 to 1 micrometer). In some implementations, one or more bridge interconnects from the plurality of bridge interconnects 185 may have a minimum width of 0.5 micrometers. In some implementations, two adjacent bridge interconnects from the plurality of bridge interconnects 185 may be 1 micrometer or less (e.g., 0.5 to 1 micrometer). In some implementations, the minimum spacing between two adjacent bridge interconnects from the plurality of bridge interconnects 185 may be 0.5 micrometers.

[0021] The bridge 108 is coupled to the integrated device 102 such that the plurality of under bump metallization interconnects 126 are coupled to the plurality of bridge interconnects 184. There may or may not be an interface between the plurality of under bump metallization interconnects 126 and the plurality of bridge interconnects 184. The bridge 108 is coupled to the integrated device 104 such that the plurality of under bump metallization interconnects 146 are coupled to the plurality of bridge interconnects 186. There may or may not be an interface between the plurality of under bump metallization interconnects 146 and the plurality of bridge interconnects 186.

[0022] An electrical path between the integrated device 102 and the integrated device 104 may include the pad 124a, the under bump metallization interconnect 126a, a bridge interconnect from the plurality of bridge interconnects 184, a bridge interconnect from the plurality of bridge interconnects 185, a bridge interconnect from the plurality of bridge interconnects 186, the under bump metallization interconnect 146a, and the pad 144a. The bridge 108 may include several electrical paths that may be arranged in rows of bridge interconnects. The electrical paths may be configured to allow electrical current (e.g., input / output signals) between the integrated device 102 and the integrated device 104.

[0023] FIG. 1 illustrates an interface between the under bump metallization interconnect 126a and a bridge interconnect from the plurality of bridge interconnects 184. However, in some implementations, there may be no interface between the under bump metallization interconnect 126a and a bridge interconnect from the plurality of bridge interconnects 184. In some implementations, a front surface of the under bump metallization interconnect 126a is bonded to a bridge interconnect from the plurality of bridge interconnects 184. The front surface of the under bump metallization interconnect may be the surface that is the widest portion of the under bump metallization interconnect. A metal-to-metal oxide bonding process and / or a hybrid bonding process may be used to bond the front surface of the under bump metallization interconnect 126a to the bridge interconnect from the plurality of bridge interconnects 184.

[0024] 1 also illustrates an interface between the under bump metallization interconnect 146a and a bridge interconnect from the plurality of bridge interconnects 186. However, in some implementations, there may be no interface between the under bump metallization interconnect 146a and a bridge interconnect from the plurality of bridge interconnects 186. In some implementations, a front side of the under bump metallization interconnect 146a is bonded to a bridge interconnect from the plurality of bridge interconnects 186. An intermetallic oxide bonding process and / or a hybrid bonding process may be used to bond the front side of the under bump metallization interconnect 146a to a bridge interconnect from the plurality of bridge interconnects 186.

[0025] Different components of the package 100 may have different sizes and / or shapes. For example, the integrated devices (e.g., 102, 104) may have a thickness of about 140 micrometers. The passivation layers (e.g., 122, 142) may have a thickness of about 5 micrometers. The under-bump metallization interconnects (e.g., 126, 146) may have a width of about 50 micrometers. The bridge 108 may have a thickness of about 25 micrometers. The bridge interconnects (e.g., 184, 186) may have a width of about 30 micrometers. Each of the metal layers of the metallization interconnects 162 may have a thickness of about 4-5 micrometers. Different implementations may couple the bridge 108 to the integrated devices 102 and 104.

[0026] 2 illustrates an example of a package 200 including an integrated device coupled through a bridge. The package 200 is coupled to a board 190 (e.g., a printed circuit board) through a number of solder interconnects 170. The package 200 is similar to the package 100 and therefore includes similar components as the package 100. The package 200 includes an integrated device 102, an integrated device 104, a metallization portion 106, a bridge 108, and an encapsulation layer 110.

[0027] 2 shows that the bridge 108 is coupled to the integrated device 102 through a plurality of solder interconnects 284. FIG 2 also shows that the bridge 108 is coupled to the integrated device 104 through a plurality of solder interconnects 286. The plurality of solder interconnects 284 is coupled to at least one under bump metallization interconnect (e.g., 126a) from the plurality of under bump metallization interconnects 126 and to the plurality of bridge interconnects 184. The plurality of solder interconnects 286 is coupled to at least one under bump metallization interconnect (e.g., 146a) from the plurality of under bump metallization interconnects 146 and to the plurality of bridge interconnects 186.

[0028] An electrical path between the integrated device 102 and the integrated device 104 may include the pad 124a, the under bump metallization interconnect 126a, a solder interconnect from the plurality of solder interconnects 284, a bridge interconnect from the plurality of bridge interconnects 184, a bridge interconnect from the plurality of bridge interconnects 185, a bridge interconnect from the plurality of bridge interconnects 186, a solder interconnect from the plurality of solder interconnects 286, the under bump metallization interconnect 146a, and the pad 144a. The bridge 108 may include several electrical paths that may be arranged in rows of bridge interconnects. The electrical paths may be configured to allow electrical current (e.g., input / output signals) between the integrated device 102 and the integrated device 104.

[0029] In some implementations, the packages of FIGS. 1 and 2 may be implemented as part of a package-on-package (PoP). FIG. 3 shows a package 300 including an integrated device coupled through a bridge. The package 300 is coupled to a board 190 (e.g., a printed circuit board) through a number of solder interconnects 170. The package 300 is similar to the package 100 and may therefore include similar components as the package 100. The package 300 may also include additional components. The package 300 includes an integrated device 102, an integrated device 104, a metallization portion 106, a bridge 108, an encapsulation layer 110, and a metallization portion 306. The integrated device 302 and the integrated device 304 are coupled to the package 300. The package 300, the integrated device 302, and the integrated device 304 may be implemented as a package-on-package (PoP). In some implementations, metallization portion 106 may be a first metallization portion 106 and metallization portion 306 may be a second metallization portion.

[0030] The integrated device 102, the integrated device 104, the metallization portion 106, the bridge 108, and the encapsulation layer 110 may be coupled to each other in a similar manner as described for the package 100. The integrated device 102 may be configured to be coupled to the integrated device 104 through the bridge 108 in a similar manner as described for the package 100 of FIG. 1 and / or the package 200 of FIG. 2. The metallization portion 306 may be coupled to the encapsulation layer 110, the back side of the integrated device 102, and the back side of the integrated device 104. In some implementations, one or more adhesives (not shown) may be used to couple the back side of the integrated device 102 and / or the back side of the integrated device 104 to the metallization portion 306. The use of adhesives is described below in at least FIGS. 7A-7C. The metallization portion 306 may be considered to be part of the back side of the package 300. The metallization portion 306 includes at least one dielectric layer 360 (e.g., at least one second dielectric layer) and a plurality of interconnects 362. The plurality of interconnects 362 may include a plurality of metallization interconnects (e.g., a second plurality of metallization interconnects). The metallization portion 306 may be configured to be electrically coupled to the metallization portion 106 through a plurality of pillar interconnects 312. The plurality of pillar interconnects 312 may be coupled to the plurality of metallization interconnects 162 and the plurality of interconnects 362. The plurality of pillar interconnects 312 may be located in the encapsulation layer 110. The plurality of pillar interconnects 312 may be a plurality of through mold vias (e.g., TMV) and / or a plurality of through mold interconnects. The encapsulation layer 110 may include a mold, a resin, an epoxy, and / or a polymer. The encapsulation layer 110 may be a means for encapsulation.

[0031] The integrated device 302 is coupled to the metallization portion 306 through a plurality of pillar interconnects 322 and / or a plurality of solder interconnects 320. For example, the integrated device 302 is coupled to a plurality of interconnects 362 through a plurality of pillar interconnects 322 and / or a plurality of solder interconnects 320. The integrated device 304 is coupled to the metallization portion 306 through a plurality of pillar interconnects 342 and / or a plurality of solder interconnects 340. For example, the integrated device 304 is coupled to a plurality of interconnects 362 through a plurality of pillar interconnects 342 and / or a plurality of solder interconnects 340. The integrated device 302 and / or the integrated device 304 may be similar to the integrated device 102 and / or the integrated device 104.

[0032] In some implementations, the integrated device 302 may be configured to be electrically coupled to the integrated device 102 through the plurality of pillar interconnects 322, the plurality of solder interconnects 320, the plurality of interconnects 362 of the metallization portion 306, the plurality of pillar interconnects 312, the plurality of metallization interconnects 162 of the metallization portion 106, and the plurality of pillar interconnects 112.

[0033] In some implementations, the integrated device 304 may be configured to be electrically coupled to the integrated device 104 through the plurality of pillar interconnects 342, the plurality of solder interconnects 340, the plurality of interconnects 362 of the metallization portion 306, the plurality of pillar interconnects 312, the plurality of metallization interconnects 162 of the metallization portion 106, and the plurality of pillar interconnects 114.

[0034] The plurality of metallization interconnects 162 may be a means for metallization interconnection. The plurality of metallization interconnects 362 may be a means for metallization interconnection. The plurality of metallization interconnects 162 and / or 362 may include at least one redistribution layer (RDL) interconnect (e.g., a redistribution interconnect). The redistribution layer interconnect may include a U-shape or a V-shape. The terms "U-shape" and "V-shape" are interchangeable. The terms "U-shape" and "V-shape" may refer to the side shape of the interconnect and / or the redistribution layer interconnect. U-shaped interconnects (e.g., U-shaped side shape interconnects) and V-shaped interconnects (e.g., V-shaped side shape interconnects) may have a top portion and a bottom portion. The bottom portion of a U-shaped interconnect (or V-shaped interconnect) may be bonded to the top portion of another U-shaped interconnect (or V-shaped interconnect).

[0035] It should be noted that a package may include more than two integrated devices and more than one bridge. Figure 4 shows a plan view of a package 400 including several integrated devices coupled through bridges. The package 400 includes an integrated device 102, an integrated device 104, an integrated device 402, an integrated device 404, a bridge 108, a bridge 408, a bridge 420, and a bridge 440. In some implementations, the packages 100, 200, and / or 300 may be represented by the package 400.

[0036] As shown in FIG. 4 , the integrated device 102 is coupled to the integrated device 104 through a bridge 108. The integrated device 102 may communicate with the integrated device 104 through the bridge 108. The integrated device 102 is coupled to the integrated device 402 through a bridge 420. The integrated device 102 may communicate with the integrated device 402 through the bridge 420. The integrated device 402 is coupled to the integrated device 404 through a bridge 408. The integrated device 402 may communicate with the integrated device 404 through the bridge 408. The integrated device 404 is coupled to the integrated device 104 through a bridge 440. The integrated device 404 may communicate with the integrated device 104 through the bridge 440. The bridge 408 includes a plurality of bridge interconnects 485. The bridge 420 includes a plurality of bridge interconnects 422. The bridge 440 includes a plurality of bridge interconnects 442. Bridge 408, bridge 420, and / or bridge 440 may be similar to bridge 108. However, bridge 408, bridge 420, and / or bridge 440 may have different sizes, shapes, and / or different numbers of bridge interconnects.

[0037] The integrated devices (e.g., 102, 104, 302, 304, 402, 404) may include a die (e.g., a bare die). Any of the integrated devices described in this disclosure may have a structure similar to that described for integrated devices 102 and / or 104. The integrated devices may include radio frequency (RF) devices, analog devices, passive devices, filters, capacitors, inductors, antennas, transmitters, receivers, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, light emitting diode (LED) integrated devices, silicon (Si)-based integrated devices, silicon carbide (SiC)-based integrated devices, GaAs-based integrated devices, GaN-based integrated devices, memories, power management processors, and / or combinations thereof.

[0038] Having described various packages, the sequence and process for manufacturing the packages is described below.

[0039] Exemplary sequence for manufacturing a package including integrated devices bonded through a bridge In some implementations, manufacturing a package includes several processes. Figures 5A-5D show an example sequence for providing or manufacturing a package. In some implementations, the sequence of Figures 5A-5D can be used to provide or manufacture the package 100 of Figure 1 and / or other packages described in this disclosure.

[0040] 5A-5D may combine one or more stages to simplify and / or clarify the sequence for providing or manufacturing a package. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the spirit of the disclosure.

[0041] Stage 1 shown in FIG. 5A illustrates a state after integrated device 102 (e.g., a first integrated device) and integrated device 104 (e.g., a second integrated device) are bonded to carrier 500. The integrated devices (e.g., 102, 104) may include a die substrate (e.g., 120, 140), a number of pads (e.g., 124, 144), and a passivation layer (e.g., 122, 142). The integrated devices (e.g., 102, 104) may also include a number of under-bump metallization interconnects (e.g., 126, 146). The integrated devices (e.g., 102, 104) may include a die (e.g., a bare die, a first die). In some implementations, a front-end-of-line (FEOL) process may be used to fabricate the integrated devices or portions of the integrated devices.

[0042] Stage 2 shows the state after the bridge 108 is bonded to the integrated device 102 and the integrated device 104. The bridge 108 may be bonded to the integrated device 102 and the integrated device 104 such that the front side of the bridge 108 faces the front side of the integrated device 102 and the front side of the integrated device 104. In some implementations, a metal-metal oxide bonding process and / or a hybrid bonding process may be used to bond the bridge 108 to the integrated devices 102 and 104. This may result in the bridge 108 being bonded to the integrated devices 102 and 104 in a similar manner as described for the package 100 of FIG. 1. In some implementations, the bridge 108 may be bonded to the integrated device 102 and the integrated device 104 through multiple solder interconnects by a solder reflow process. This may result in the bridge 108 being bonded to the integrated devices 102 and 104 in a similar manner as described for the package 200 of FIG. 2.

[0043] Stage 3 shows a state after a plurality of pillar interconnects 112 are formed on the integrated device 102. The plurality of pillar interconnects 112 (e.g., a first plurality of pillar interconnects) may be considered part of the integrated device 102. The plurality of pillar interconnects 112 may be formed on a plurality of pads 124. A plating process may be used to form the plurality of pillar interconnects 112. Stage 2 also shows a state after a plurality of pillar interconnects 114 are formed on the integrated device 104. The plurality of pillar interconnects 114 (e.g., a second plurality of pillar interconnects) may be considered part of the integrated device 104. The plurality of pillar interconnects 114 may be formed on a plurality of pads 144. A plating process may be used to form the plurality of pillar interconnects 114.

[0044] Stage 4 shows the state after the encapsulation layer 110 is formed over the carrier 500, the integrated device 102, the integrated device 104, the bridge 108, the plurality of pillar interconnects 112, and the plurality of pillar interconnects 114. The encapsulation layer 110 may include a mold, a resin, an epoxy, and / or a polymer. The encapsulation layer 110 may be a means for encapsulation. The process of forming and / or disposing the encapsulation layer 110 may include using a compression and transfer molding process, a sheet molding process, or a liquid molding process.

[0045] Stage 5, shown in FIG. 5B, illustrates a state after a portion of the encapsulation layer 110, a portion of the bridge 108, a portion of the plurality of pillar interconnects 112, and / or a portion of the plurality of pillar interconnects 114 have been removed. A grinding and / or polishing process may be used to remove a portion of the encapsulation layer 110, a portion of the bridge 108, a portion of the plurality of pillar interconnects 112, and / or a portion of the plurality of pillar interconnects 114. After the grinding and / or polishing process, a surface (e.g., a top surface) of the encapsulation layer 110 may be planar with a surface (e.g., a top surface) of the plurality of pillar interconnects 112, a surface of the plurality of pillar interconnects 114, and / or a surface of the back surface of the bridge 108. The grinding and / or polishing process may help reduce the overall thickness of the package.

[0046] Stage 6 illustrates a state after a plurality of metallization interconnects 503 are formed on the plurality of pillar interconnects 112, the plurality of pillar interconnects 114, and the encapsulation layer 110. The metallization interconnects 503 may include a plurality of redistribution layer interconnects. The plurality of metallization interconnects 503 may include a redistribution interconnect including a U-shaped interconnect or a V-shaped interconnect. A deposition process (e.g., a plating process) may be used to form the plurality of metallization interconnects 503. Forming the metallization interconnects 503 may include forming a seed layer, performing a lithography process, a plating process, a stripping process, and / or an etching process.

[0047] Stage 7 shows the state after a dielectric layer 510 has been formed over the metallization interconnects 503. To form the dielectric layer 510, a deposition process may be used.

[0048] Stage 8 shows the state after an opening 511 has been formed in the dielectric layer 510. To form the opening 511, an etching process may be used.

[0049] 5C depicts a state after a plurality of metallization interconnects 513 are formed in and on the dielectric layer 510. Some of the plurality of metallization interconnects 513 may be formed in cavities (e.g., 511) of the dielectric layer 510. The plurality of metallization interconnects 513 may be coupled to the plurality of metallization interconnects 503. Forming the plurality of metallization interconnects 513 may include forming a seed layer, performing a lithography process, a plating process, a stripping process, and / or an etching process.

[0050] Stage 10 illustrates a state after a dielectric layer 520 and a plurality of metallization interconnects 523 are formed over the dielectric layer 510 and the plurality of metallization interconnects 513. The plurality of metallization interconnects 523 may be bonded to the plurality of metallization interconnects 513. A deposition process may be used to form the dielectric layer 520. Forming the plurality of metallization interconnects 523 may include forming a seed layer, performing a lithography process, a plating process, a stripping process, and / or an etching process.

[0051] Stage 11 shows a state after a dielectric layer 530, a plurality of metallization interconnects 533, and a dielectric layer 540 are formed over the dielectric layer 520 and the plurality of metallization interconnects 523. The plurality of metallization interconnects 533 may be coupled to the plurality of metallization interconnects 523. A deposition process may be used to form the dielectric layer 530. Forming the plurality of metallization interconnects 533 may include forming a seed layer, performing a lithography process, a plating process, a stripping process, and / or an etching process. A deposition process and an etching process may be used to form the dielectric layer 540. Stage 11 may show the metallization portion 106 including at least one dielectric layer 160 and a plurality of metallization interconnects 162. The at least one dielectric layer 160 may represent the dielectric layer 510, the dielectric layer 520, the dielectric layer 530, and / or the dielectric layer 540. The plurality of metallization interconnects 162 may represent the plurality of metallization interconnects 503 , 513 , 523 , and / or 533 .

[0052] 5D depicts stage 12 after the carrier 500 has been removed. Removing the carrier 500 may include separating the carrier 500 from the backside of the integrated device 102 and the backside of the integrated device 104. The carrier 500 may be removed, ground, and / or peeled away from the integrated device 102, the integrated device 104, and the encapsulation layer 110.

[0053] Stage 13 shows the state after the plurality of solder interconnects 170 are bonded to the plurality of metallization interconnects 162. Stage 13 may show the package 100 including the integrated device 102, the integrated device 104, the bridge 108, the encapsulation layer 110, and the metallization portion 106.

[0054] 1 is an exemplary flow diagram of a method for manufacturing a package including integrated devices bonded through a bridge; In some implementations, manufacturing the package includes several processes. Figure 6 shows an example flow diagram of a method 600 for providing or manufacturing a package. In some implementations, the method 600 of Figure 6 can be used to provide or manufacture the package of Figures 1-2 and / or other packages described in this disclosure.

[0055] It should be noted that the method 600 of Figure 6 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing the package. In some implementations, the order of the processes may be changed or modified.

[0056] The method includes (at 605) bonding an integrated device 102 (e.g., a first integrated device) and an integrated device 104 (e.g., a second integrated device) to a carrier (e.g., 500). The integrated devices (e.g., 102, 104) may include a die substrate (e.g., 120, 140), a number of pads (e.g., 124, 144), and a passivation layer (e.g., 122, 142). The integrated devices (e.g., 102, 104) may also include a number of under-bump metallization interconnects (e.g., 126, 146). The integrated devices (e.g., 102, 104) may include a die (e.g., a bare die, a first die). In some implementations, a front-end-of-line (FEOL) process may be used to fabricate the integrated devices or portions of the integrated devices. Stage 1 of FIG. 5A illustrates and describes an example of bonding an integrated device to a carrier.

[0057] The method includes (at 610) bonding a bridge (e.g., 108) to an integrated device (e.g., 102, 104). The bridge 108 may be bonded to the integrated device 102 and the integrated device 104 such that a front side of the bridge 108 faces the front side of the integrated device 102 and the front side of the integrated device 104. In some implementations, a metal-metal oxide bonding process and / or a hybrid bonding process may be used to bond the bridge 108 to the integrated devices 102 and 104. This may result in the bridge 108 being bonded to the integrated devices 102 and 104 in a similar manner as described for the package 100 of FIG. 1. In some implementations, the bridge 108 may be bonded to the integrated devices 102 and 104 through a plurality of solder interconnects by a solder reflow process. This may result in the bridge 108 being bonded to the integrated devices 102 and 104 in a similar manner as described for the package 200 of FIG. 2. Stage 2 of FIG. 5A illustrates and describes an example of a bridge being bonded to an integrated device.

[0058] The method bonds (at 615) the pillar interconnects (e.g., 112, 114) to the integrated device (e.g., 102, 104). For example, the method may form the pillar interconnects 112 over the under bump metallization interconnects 126 of the integrated device 102 and the pillar interconnects 114 over the under bump metallization interconnects 146 of the integrated device 104. A plating process may be used to form the pillar interconnects 112 and 114. Stage 3 of FIG. 5A illustrates an example of forming pillar interconnects over an integrated device.

[0059] The method forms (at 620) an encapsulation layer 110 over the carrier 500, the integrated device 102, the integrated device 104, the bridge 108, the plurality of pillar interconnects 112, and the plurality of pillar interconnects 114. The encapsulation layer 110 may include a mold, a resin, an epoxy, and / or a polymer. The encapsulation layer 110 may be a means for encapsulation. The process of forming and / or disposing the encapsulation layer 110 may include using a compression and transfer molding process, a sheet molding process, or a liquid molding process. Stage 4 of FIG. 5A illustrates and describes an example of forming the encapsulation layer.

[0060] The method removes (at 625) a portion of the encapsulation layer 110, a portion of the bridge 108, a portion of the plurality of pillar interconnects 112, and / or a portion of the plurality of pillar interconnects 114. A grinding and / or polishing process may be used to remove the portion of the encapsulation layer 110, the portion of the bridge 108, the portion of the plurality of pillar interconnects 112, and / or a portion of the plurality of pillar interconnects 114. After the grinding and / or polishing process, a surface (e.g., a top surface) of the encapsulation layer 110 may be planar with a surface (e.g., a top surface) of the plurality of pillar interconnects 112, a surface of the plurality of pillar interconnects 114, and / or a surface of a back surface of the bridge 108. Stage 5 of FIG. 5B illustrates and describes an example of removing a portion of the encapsulation layer, a portion of the bridge, and a portion of the plurality of pillar interconnects.

[0061] The method forms (at 630) a metallization portion (e.g., 106). The metallization portion 106 may be a first metallization portion. Forming the metallization portion 106 may include forming at least one dielectric layer (e.g., 160) and forming a plurality of metallization interconnects (e.g., 162). Forming the at least one dielectric layer may include a deposition process. Forming the plurality of metallization interconnects may include forming a seed layer, performing a lithography process, a plating process, a stripping process, and / or an etching process. In some implementations, forming the metallization portion may include repeatedly forming a plurality of metallization interconnects and forming a dielectric layer. Stage 6 of FIG. 5B to Stage 11 of FIG. 5C show and describe an example of forming a metallization portion.

[0062] The method includes (at 635) separating the carrier (e.g., 500) from the backside of the integrated device. Separating the carrier 500 may include separating the carrier 500 from the backside of the integrated device 102 and the backside of the integrated device 104. The carrier 500 may be removed, ground, and / or peeled away from the integrated device 102, the integrated device 104, and the encapsulation layer 110. Stage 12 of FIG. 5D illustrates and describes one example of a separated carrier.

[0063] The method includes (at 640) bonding a plurality of solder interconnects (e.g., 170) to a metallization portion (e.g., 106). A solder reflow process may be used to bond the plurality of solder interconnects 170 to the plurality of metallization interconnects 162. Stage 13 of Figure 5D illustrates and describes an example of bonding a plurality of solder interconnects to a plurality of metallization interconnects of a metallization portion of a package.

[0064] Exemplary sequence for manufacturing a package including integrated devices bonded through a bridge In some implementations, manufacturing a package includes several processes. Figures 7A-7C show an example sequence for providing or manufacturing a package. In some implementations, the sequence of Figures 7A-7C can be used to provide or manufacture package 300 of Figure 3 and / or other packages described in this disclosure.

[0065] It should be noted that the sequences of Figures 7A-7C may combine one or more stages to simplify and / or clarify the sequence for providing or manufacturing a package. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the spirit of the disclosure.

[0066] Stage 1 shown in FIG. 7A shows a metallization portion 306 formed on a carrier 700. The metallization portion 306 includes at least one dielectric layer 360 and a plurality of metallization interconnects 362. The metallization portion 306 may be a second metallization portion. A deposition process may be used to form the at least one dielectric layer 360. Forming the plurality of metallization interconnects 362 may include forming a seed layer, performing a lithography process, a plating process, a stripping process, and / or an etching process. Processes similar to those of stage 6 of FIG. 5B to stage 11 of FIG. 5C may be used to form the metallization portion 306.

[0067] Stage 2 illustrates a state after the integrated device 102 (e.g., a first integrated device) and the integrated device 104 (e.g., a second integrated device) are bonded to the metallization portion 306. In some implementations, an adhesive (e.g., 702, 704) may be used to bond the integrated devices to the metallization portion 306. For example, (i) an adhesive 702 may be bonded to a backside and the metallization portion 306 of the integrated device 102, and an adhesive 704 may be bonded to a backside and the metallization portion 306 of the integrated device 104. The integrated devices (e.g., 102, 104) may include a die substrate (e.g., 120, 140), a number of pads (e.g., 124, 144), a number of under bump metallization interconnects (e.g., 126, 146), and a passivation layer (e.g., 122, 142). The integrated device (e.g., 102, 104) may include a die (e.g., a bare die, a first die). In some implementations, a front-end-of-line (FEOL) process may be used to fabricate the integrated device or a portion of the integrated device.

[0068] Stage 3 shows a state after a plurality of pillar interconnects 112 are formed on the integrated device 102. The plurality of pillar interconnects 112 (e.g., a first plurality of pillar interconnects) may be considered part of the integrated device 102. The plurality of pillar interconnects 112 may be formed on a plurality of under bump metallization interconnects 126. A plating process may be used to form the plurality of pillar interconnects 112. Stage 3 also shows a state after a plurality of pillar interconnects 114 are formed on the integrated device 104. The plurality of pillar interconnects 114 (e.g., a second plurality of pillar interconnects) may be considered part of the integrated device 104. The plurality of pillar interconnects 114 may be formed on a plurality of under bump metallization interconnects 146. A plating process may be used to form the plurality of pillar interconnects 114.

[0069] Stage 4 shows the state after the bridge 108 is bonded to the integrated device 102 and the integrated device 104. The bridge 108 may be bonded to the integrated device 102 and the integrated device 104 such that the front side of the bridge 108 faces the front side of the integrated device 102 and the front side of the integrated device 104. In some implementations, a metal-metal oxide bonding process and / or a hybrid bonding process may be used to bond the bridge 108 to the integrated devices 102 and 104. This may result in the bridge 108 being bonded to the integrated devices 102 and 104 in a similar manner as described for the package 100 of FIG. 1. In some implementations, the bridge 108 may be bonded to the integrated device 102 and the integrated device 104 through a plurality of solder interconnects by a solder reflow process. This may result in the bridge 108 being bonded to the integrated devices 102 and 104 in a similar manner as described for the package 200 of FIG. 2.

[0070] Stage 5 shown in FIG. 7B illustrates a state after an encapsulation layer 110 is formed over the metallization portion 306, the integrated device 102, the integrated device 104, the bridge 108, the plurality of pillar interconnects 112, and the plurality of pillar interconnects 114. The encapsulation layer 110 may include a mold, a resin, an epoxy, and / or a polymer. The encapsulation layer 110 may be a means for encapsulation. The process of forming and / or disposing the encapsulation layer 110 may include using a compression and transfer molding process, a sheet molding process, or a liquid molding process.

[0071] Stage 6 illustrates the state after a portion of encapsulation layer 110, a portion of bridge 108, a portion of multiple pillar interconnects 112, and / or a portion of multiple pillar interconnects 114 have been removed. A grinding and / or polishing process may be used to remove a portion of encapsulation layer 110, a portion of bridge 108, a portion of multiple pillar interconnects 112, and / or a portion of multiple pillar interconnects 114. After the grinding and / or polishing process, a surface (e.g., a top surface) of encapsulation layer 110 may be planar with a surface (e.g., a top surface) of multiple pillar interconnects 112, a surface of multiple pillar interconnects 114, and / or a surface of a back surface of bridge 108.

[0072] Stage 7 shows the state after cavities 710 have been formed in encapsulation layer 110. A laser process (e.g., laser ablation) may be used to form cavities 710 in encapsulation layer 110. Cavities 710 may expose portions of interconnects 362.

[0073] Stage 8 shows the state after the pillar interconnects 312 are formed in the cavities 710 of the encapsulation layer 110. A plating process may be used to form the pillar interconnects 312. The pillar interconnects 312 may be coupled to the metallization interconnects 362.

[0074] Stage 9 shown in FIG. 7C shows a metallization portion 106 formed on the back surface of the encapsulation layer 110, the plurality of pillar interconnects 312, the plurality of pillar interconnects 112, the plurality of pillar interconnects 114, and the bridge 108. The metallization portion 106 includes at least one dielectric layer 160 and a plurality of metallization interconnects 162. A deposition process may be used to form the at least one dielectric layer 160. Forming the plurality of metallization interconnects 162 may include forming a seed layer, performing a lithography process, a plating process, a stripping process, and / or an etching process. Processes similar to those of stage 6 of FIG. 5B through stage 11 of FIG. 5C may be used to form the metallization portion 106.

[0075] Stage 10 shows the condition after the carrier 700 has been removed. Removing the carrier 700 may include separating the carrier 700 from the metallization interconnects 306. The carrier 700 may be removed, ground, and / or stripped from the metallization interconnects 306.

[0076] Stage 11 shows a state after the plurality of solder interconnects 170 are bonded to the plurality of metallization interconnects 162 of the metallization portion 106. Stage 13 may show a package 300 including the integrated device 102, the integrated device 104, the bridge 108, the encapsulation layer 110, the metallization portion 106 (e.g., a first metallization portion), and the metallization portion 306 (e.g., a second metallization portion). Stage 11 may show the package 300. In some implementations, the integrated device 302 and / or the integrated device 304 may be bonded to the metallization portion 306 of the package 300 to form a package-on-package (PoP).

[0077] 1 is an exemplary flow diagram of a method for manufacturing a package including integrated devices bonded through a bridge; In some implementations, manufacturing the package includes several processes. Figure 8 shows an example flow diagram of a method 800 for providing or manufacturing a package. In some implementations, the method 800 of Figure 8 can be used to provide or manufacture the package 300 of Figure 3 and / or other packages described in this disclosure.

[0078] It should be noted that the method 800 of Figure 8 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing the package. In some implementations, the order of the processes may be changed or modified.

[0079] The method includes (at 805) forming a metallization portion (e.g., 306) on the carrier (e.g., 700). The metallization portion 306 may be a second metallization portion. Forming the metallization portion 306 may include forming at least one dielectric layer (e.g., 360) and forming a plurality of metallization interconnects (e.g., 362). Forming the at least one dielectric layer may include a deposition process. Forming the plurality of metallization interconnects may include forming a seed layer, performing a lithography process, a plating process, a stripping process, and / or an etching process. In some implementations, forming the metallization portion may include repeatedly forming a plurality of metallization interconnects and forming a dielectric layer. Stage 1 of FIG. 7A illustrates and describes an example of forming a metallization portion.

[0080] The method includes (at 810) bonding an integrated device 102 (e.g., a first integrated device) and an integrated device 104 (e.g., a second integrated device) to a metallization portion (e.g., 306). An adhesive (e.g., 702, 704) may be used to bond a backside of the integrated device 102 and a backside of the integrated device 104 to the metallization portion 306. The integrated device (e.g., 102, 104) may include a die substrate (e.g., 120, 140), a number of pads (e.g., 124, 144), a number of under-bump metallization interconnects (e.g., 126, 146), and a passivation layer (e.g., 122, 142). The integrated device (e.g., 102, 104) may include a die (e.g., a bare die, a first die). In some implementations, a front-end-of-line (FEOL) process may be used to fabricate the integrated device or a portion of the integrated device. Stage 2 of FIG. 7A illustrates an example of bonding an integrated device to a metallization portion.

[0081] The method bonds (at 815) the pillar interconnects (e.g., 112, 114) to the integrated device (e.g., 102, 104). For example, the method may form the pillar interconnects 112 over the under bump metallization interconnects 126 of the integrated device 102 and the pillar interconnects 114 over the under bump metallization interconnects 146 of the integrated device 104. A plating process may be used to form the pillar interconnects 112 and 114. Stage 3 of FIG. 7A illustrates an example of forming pillar interconnects over an integrated device.

[0082] The method includes (at 820) bonding a bridge (e.g., 108) to the integrated device (e.g., 102, 104). The bridge 108 may be bonded to the integrated device 102 and the integrated device 104 such that a front side of the bridge 108 faces the front side of the integrated device 102 and the front side of the integrated device 104. In some implementations, a metal-metal oxide bonding process and / or a hybrid bonding process may be used to bond the bridge 108 to the integrated devices 102 and 104. This may result in the bridge 108 being bonded to the integrated devices 102 and 104 in a similar manner as described for the package 100 of FIG. 1. In some implementations, the bridge 108 may be bonded to the integrated device 102 and the integrated device 104 through a plurality of solder interconnects by a solder reflow process. This may result in the bridge 108 being bonded to the integrated devices 102 and 104 in a similar manner as described for the package 200 of FIG. 2. Stage 4 of FIG. 7A illustrates and describes an example of a bridge being bonded to an integrated device.

[0083] The method forms (at 825) an encapsulation layer 110 over the metallization portion 306, the integrated device 102, the integrated device 104, the bridge 108, the plurality of pillar interconnects 112, and the plurality of pillar interconnects 114. The encapsulation layer 110 may include a mold, a resin, an epoxy, and / or a polymer. The encapsulation layer 110 may be a means for encapsulation. The process of forming and / or disposing the encapsulation layer 110 may include using a compression and transfer molding process, a sheet molding process, or a liquid molding process. Stage 5 of FIG. 7B illustrates and describes an example of forming the encapsulation layer.

[0084] The method removes (at 830) a portion of the encapsulation layer 110, a portion of the bridge 108, a portion of the plurality of pillar interconnects 112, and / or a portion of the plurality of pillar interconnects 114. A grinding and / or polishing process may be used to remove the portion of the encapsulation layer 110, the portion of the bridge 108, the portion of the plurality of pillar interconnects 112, and / or a portion of the plurality of pillar interconnects 114. After the grinding and / or polishing process, a surface (e.g., a top surface) of the encapsulation layer 110 may be planar with a surface (e.g., a top surface) of the plurality of pillar interconnects 112, a surface of the plurality of pillar interconnects 114, and / or a surface of a back surface of the bridge 108. Stage 6 of FIG. 7B illustrates and describes an example of removing a portion of the encapsulation layer, a portion of the bridge, and a portion of the plurality of pillar interconnects.

[0085] The method includes forming (at 835) a plurality of pillar interconnects (e.g., 312) in the encapsulation layer 110. Forming (at 835) the plurality of pillar interconnects 312 may include forming a cavity (e.g., 710) in the encapsulation layer 110 and forming the plurality of pillar interconnects 312 in the cavity 710 of the encapsulation layer 110. A laser process (e.g., laser ablation) may be used to form the cavity 710. A plating process may be used to form the plurality of pillar interconnects 312 in the cavity 710 of the encapsulation layer 110. Stages 7-8 of FIG. 7B illustrate an example of forming a cavity and interconnects in the encapsulation layer.

[0086] The method forms (at 840) a metallization portion (e.g., 106). The metallization portion 106 may be a first metallization portion. Forming the metallization portion 106 may include forming at least one dielectric layer (e.g., 160) and forming a plurality of metallization interconnects (e.g., 162). Forming the at least one dielectric layer may include a deposition process. Forming the plurality of metallization interconnects may include forming a seed layer, performing a lithography process, a plating process, a stripping process, and / or an etching process. In some implementations, forming the metallization portion may include repeatedly forming a plurality of metallization interconnects and forming a dielectric layer. Stage 9 of FIG. 7C illustrates and describes an example of forming a metallization portion.

[0087] The method continues (at 845) by separating the carrier (e.g., 700) from the metallization portion 306. Separating the carrier 700 may include removing the carrier 700 from the metallization portion 306. The carrier 700 may be removed, ground, and / or stripped from the metallization portion 306. Stage 10 of Figure 7C illustrates and describes one example of a package after the carrier has been separated.

[0088] The method includes (at 850) bonding a plurality of solder interconnects (e.g., 170) to a metallization portion (e.g., 106). A solder reflow process may be used to bond the plurality of solder interconnects 170 to the plurality of metallization interconnects 162. Stage 11 of Figure 7C illustrates and describes one example of a plurality of solder interconnects bonded to a plurality of metallization interconnects of a metallization portion.

[0089] Exemplary Electronic Devices FIG. 9 illustrates various electronic devices that may be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, package-on-package (PoP), system-in-package (SiP), or system-on-chip (SoC). For example, a mobile phone device 902, a laptop computer device 904, a fixed location terminal device 906, a wearable device 908, or an automobile 910 may include a device 900 as described herein. The device 900 may be, for example, any of the devices and / or integrated circuit (IC) packages described herein. The devices 902, 904, 906, and 908 and the vehicle 910 illustrated in FIG. 9 are merely examples. Other electronic devices may also feature device 900, including, but not limited to, a group of devices (e.g., electronic devices) including mobile devices, handheld personal communications system (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in automotive vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0090] One or more of the components, processes, features, and / or functions shown in Figures 1-4, 5A-5D, 6, 7A-7C, and 8-9 may be rearranged and / or combined into a single component, process, feature, or function, or may be combined into several components, processes, or functions. Additional elements, components, processes, and / or functions may be added without departing from this disclosure. It is also noted that Figures 1-4, 5A-5D, 6, 7A-7C, and 8-9 and their corresponding descriptions in this disclosure are not limited to dies and / or ICs. In some implementations, Figures 1-4, 5A-5D, 6, 7A-7C, and 8-9 and their corresponding descriptions may be used to manufacture, fabricate, provide, and / or produce devices and / or integrated devices. In some implementations, a device may include a die (e.g., a logic die), an integrated device, an integrated passive device (IPD) (e.g., a passive die), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, and / or an interposer.

[0091] It should be noted that the figures in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some examples, the figures may not be to scale. In some examples, for clarity, not all components and / or parts are shown. In some examples, the positions, locations, sizes and / or shapes of various parts and / or components in the figures may be exemplary. In some implementations, various components and / or parts in the figures may be optional.

[0092] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" should not necessarily be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the described feature, advantage, or mode of operation. The term "coupled" is used herein to refer to a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically contacts object B, and object B contacts object C, object A and object C may still be considered to be coupled to each other even if they do not directly physically contact each other. The term "electrically coupled" may mean that two objects are directly or indirectly coupled together such that an electric current (e.g., signal, power, ground) can travel between the two objects. Two objects that are electrically coupled may or may not have an electric current traveling between the two objects. The use of the terms "first", "second", "third" and "fourth" (and / or any above fourth) is arbitrary. Any of the components described may be the first, second, third or fourth components. For example, a component referred to as the second component may be the first, second, third or fourth component. The term "encapsulate" means that an object may partially or completely encapsulate another object. The terms "top" and "bottom" are arbitrary. A component located at the top may be located above a component located at the bottom. A top component may be considered a bottom component and vice versa. As described in this disclosure, a first component located "above" a second component may mean that the first component is located above or below the second component, depending on how bottom or top is arbitrarily defined.In another example, a first component may be located over (e.g., above) a first surface of a second component, and a third component may be located over (e.g., below) a second surface of the second component, the second surface being opposite the first surface. It is further noted that the term "over" as used in this application in the context of one component being located over another component may be used to mean a component on and / or within (e.g., on a surface of or embedded in) the other component. Thus, for example, a first component over a second component may mean (1) that the first component is over but not directly contacting the second component, (2) that the first component is on (e.g., on a surface of) the second component, and / or (3) that the first component is within (e.g., embedded in) the second component. A first component that is located "in" a second component may be partially located within the second component or completely located within the second component. As used in this disclosure, the term "about "the value of X"" or "approximately the value of X" means within 10 percent of the "value of X." For example, a value of about 1 or approximately 1 means a value in the range of 0.9 to 1.1.

[0093] In some implementations, an interconnect is an element or component of a device or package that enables or facilitates an electrical connection between two points, elements, and / or components. In some implementations, an interconnect may include a trace, a via, a pad, a pillar, a metallization layer, a redistribution layer, and / or an under bump metallization (UBM) layer / interconnect. In some implementations, an interconnect may include a conductive material that may be configured to provide an electrical path for a signal (e.g., a data signal), ground, and / or power. An interconnect may include two or more elements or components. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Various implementations may use different processes and / or sequences to form an interconnect. In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating process, and / or a plating process may be used to form the interconnects.

[0094] It should also be noted that various disclosures contained herein may be described as a process, which is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe operations as a sequential process, many of the operations may be performed in parallel or simultaneously. Additionally, the order of operations may be rearranged. A process is terminated when its operations are completed.

[0095] The following provides a summary of aspects of the disclosure.

[0096] Aspect 1: A package including: a first integrated device comprising a first plurality of under bump metallization interconnects; a second integrated device comprising a second plurality of under bump metallization interconnects; a bridge coupled to the first integrated device and the second integrated device; an encapsulation layer at least partially encapsulating the first integrated device, the second integrated device, and the bridge; a metallization portion located on the first integrated device, the second integrated device, the bridge, and the encapsulation layer, the metallization portion including at least one dielectric layer and a plurality of metallization interconnects; a first plurality of pillar interconnects coupled to the first plurality of under bump metallization interconnects and the metallization portion, the first plurality of pillar interconnects being located in the encapsulation layer; and a second plurality of pillar interconnects coupled to the second plurality of under bump metallization interconnects and the metallization portion, the second plurality of pillar interconnects being located in the encapsulation layer.

[0097] Example 2: The package of example 1, wherein the bridge comprises a plurality of bridge interconnects coupled to the first integrated device and the second integrated device.

[0098] Aspect 3: The package of aspect 2, wherein a plurality of bridge interconnects are coupled to at least one under bump metallization interconnect from a first integrated device and to at least one under bump metallization interconnect from a second integrated device.

[0099] Example 4: The package of Examples 2-3, wherein the plurality of bridge interconnects comprises a plurality of bridge under bump metallization interconnects.

[0100] Aspect 5: The package of aspect 4, wherein a plurality of bridge under bump metallization interconnects are coupled to at least one under bump metallization interconnect from a first integrated device and to at least one under bump metallization interconnect from a second integrated device.

[0101] Example 6: The package of Examples 2-5, wherein the plurality of bridge interconnects are coupled to the first plurality of under bump metallization interconnects and the second plurality of under bump metallization interconnects by hybrid bonding.

[0102] Aspect 7: The package of aspects 2-5, wherein the plurality of bridge interconnects are coupled to the first plurality of under bump metallization interconnects and the second plurality of under bump metallization interconnects through at least one solder interconnect.

[0103] Example 8: The package of Examples 2-7, wherein the plurality of bridge interconnects have a minimum width of 0.5 micrometers.

[0104] Example 9: The package of Examples 2-8, wherein the plurality of bridge interconnects have a width in the range of about 0.5 to 1 micrometers.

[0105] Example 10: The package of Examples 1 to 9, further comprising a second metallization portion located on a back surface of the first integrated device and a back surface of the second integrated device, the second metallization portion including at least a second dielectric layer and a second plurality of metallization interconnects.

[0106] Example 11: The package of Example 10, further comprising a third plurality of pillar interconnects coupled to the metallization portion and the second metallization portion, the third plurality of pillar interconnects being located in the encapsulation layer.

[0107] Aspect 12: an integrated circuit having a first integrated device and a second integrated device; a bridge interconnect coupled to the first integrated device and the second integrated device; an encapsulation means for at least partially encapsulating the first integrated device, the second integrated device, and the bridge interconnect; a metallization portion overlying the first integrated device, the second integrated device, the bridge interconnect, and the encapsulation means, the metallization portion including at least one dielectric layer and the plurality of metallization interconnects; a first plurality of pillar interconnects coupled to the first plurality of under bump metallization interconnects and the metallization portion, the first plurality of pillar interconnects being located on the encapsulation means; and a second plurality of pillar interconnects coupled to the second plurality of under bump metallization interconnects and the metallization portion, the second plurality of pillar interconnects being located on the encapsulation means.

[0108] Example 13: The apparatus of example 12, wherein the means for bridge interconnection comprises a plurality of bridge interconnects coupled to the first integrated device and the second integrated device.

[0109] Example 14: The apparatus of example 13, wherein the plurality of bridge interconnects are coupled to at least one under bump metallization interconnect from a first integrated device and to at least one under bump metallization interconnect from a second integrated device.

[0110] Example 15: The apparatus of Examples 13-14, wherein the plurality of bridge interconnects comprises a plurality of bridge under bump metallization interconnects.

[0111] Example 16: The apparatus of example 15, wherein a plurality of bridge under bump metallization interconnects are coupled to at least one under bump metallization interconnect from a first integrated device and to at least one under bump metallization interconnect from a second integrated device.

[0112] Example 17: The apparatus of Examples 13-16, wherein the plurality of bridge interconnects are coupled to the first plurality of under bump metallization interconnects and the second plurality of under bump metallization interconnects by hybrid bonding.

[0113] Example 18: The device of Examples 13-16, wherein the plurality of bridge interconnects are coupled to the first plurality of under bump metallization interconnects and the second plurality of under bump metallization interconnects through at least one solder interconnect.

[0114] Example 19: The apparatus of Examples 13 to 18, wherein the plurality of bridge interconnects comprises a minimum width of 0.5 micrometers.

[0115] Example 20: The device of Examples 13 to 19, wherein the plurality of bridge interconnects have a width in the range of about 0.5 to 1 micrometers.

[0116] Example 21: The apparatus of Examples 12 to 20, further comprising a second metallization portion located on a back surface of the first integrated device and a back surface of the second integrated device, the second metallization portion including at least one second dielectric layer and a means for a second metallization interconnection.

[0117] Example 22: The device of example 21, further comprising a third plurality of pillar interconnects coupled to the metallization portion and the second metallization portion, the third plurality of pillar interconnects being located in the means for encapsulation.

[0118] Aspect 23: The apparatus of aspects 12 to 22, wherein the apparatus comprises a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and a device in a motor vehicle.

[0119] Aspect 24: A method for manufacturing a package. The method includes coupling a bridge to a first integrated device and a second integrated device. The first integrated device includes a first plurality of under-bump metallization interconnects. The second integrated device includes a second plurality of under-bump metallization interconnects. The method includes forming a first plurality of interconnects over the first plurality of under-bump metallization interconnects. The method includes forming a second plurality of interconnects over the second plurality of under-bump metallization interconnects. The method includes forming an encapsulation layer that at least partially encapsulates the first integrated device, the second integrated device, the bridge, the first plurality of interconnects, and the second plurality of interconnects. The method includes forming a metallization portion over the first integrated device, the second integrated device, the bridge, and the encapsulation layer. Forming the metallization portion includes forming at least one dielectric layer and forming a plurality of metallization interconnects.

[0120] Example 25: The method of example 24, further comprising forming a second metallization portion, comprising forming at least one second dielectric layer and forming a second plurality of metallization interconnects.

[0121] Example 26: The method of Example 25, further comprising bonding a back side of the first integrated device and a back side of the second integrated device to a second metallization portion.

[0122] Example 27: The method of Example 26, wherein the back side of the first integrated device and the back side of the second integrated device are coupled to the second metallization portion by an adhesive.

[0123] Example 28: The method of Examples 24-27, wherein the bridge comprises a plurality of bridge interconnects coupled to the first integrated device and the second integrated device.

[0124] Example 29: The method of example 28, wherein the plurality of bridge interconnects comprises a minimum width of 0.5 micrometers.

[0125] Example 30: The method of examples 28 to 29, wherein the plurality of bridge interconnects have a width in the range of about 0.5 to 1 micrometers.

[0126] Various features of the present disclosure described herein may be implemented in different systems without departing from the present disclosure. It should be noted that the above aspects of the present disclosure are merely examples and should not be construed as limiting the present disclosure. The description of the aspects of the present disclosure is intended to be illustrative and is not intended to limit the scope of the claims. Thus, the present teachings can be easily applied to other types of devices, and many alternatives, modifications, and variations will be apparent to those skilled in the art. [Explanation of symbols]

[0127] 100 packages 102 Integrated Devices 104 Integrated Devices 106 Metallization part 108 Bridge 110 Encapsulation Layer 112 Pillar Interconnect 114 Pillar Interconnect 120 Die Substrate 122 Passivation Layer 124 Pad 126 Under Bump Metallization Interconnect 140 Die Substrate 142 Passivation Layer 144 Pad 146 Under Bump Metallization Interconnect 160 Dielectric layer 162 Metallization Interconnects 170 Solder Interconnects 180 Substrate 184 Bridge Interconnect 185 Bridge Interconnect 186 Bridge Interconnect 190 Board 200 packages 284 Solder Interconnects 286 Solder Interconnects 300 packages 302 Integrated Devices 304 Integrated Devices 306 Metallization part 312 Pillar Interconnect 320 Solder Interconnects 322 Pillar Interconnect 340 Solder Interconnects 342 Pillar Interconnect 360 Dielectric layer 362 Metallization Interconnects 400 packages 402 Integrated Devices 404 Integrated Devices 408 Bridge 420 Bridge 422 Bridge Interconnect 440 Bridge 442 Bridge Interconnect 485 Bridge Interconnect 500 Careers 503 Metallization Interconnects 510 Dielectric layer 511 Aperture 513 Metallization Interconnects 520 Dielectric layer 523 Metallization Interconnects 530 Dielectric layer 533 Metallization Interconnects 540 Dielectric Layer 700 Carriers 900 devices 902 Mobile Phone Devices 904 Laptop Computer Devices 906 Fixed Location Terminal Devices 908 Wearable Devices 910 Automobiles 1006 Fixed Location Terminal Device

Claims

1. A package comprising: a first integrated device comprising a first plurality of under bump metallization interconnects; a second integrated device comprising a second plurality of under bump metallization interconnects; a bridge coupled to the first integrated device and the second integrated device; an encapsulation layer at least partially encapsulating the first integrated device, the second integrated device, and the bridge; a first metallization portion overlying the first integrated device, the second integrated device, the bridge, and the encapsulation layer, the first metallization portion including at least one dielectric layer and a plurality of metallization interconnects; a first plurality of pillar interconnects coupled to the first plurality of under bump metallization interconnects and the first metallization portion, the first plurality of pillar interconnects being located in the encapsulation layer; a second plurality of pillar interconnects coupled to the second plurality of under bump metallization interconnects and the first metallization portion, the second plurality of pillar interconnects being located in the encapsulation layer; Equipped with the bridge comprises a plurality of bridge interconnects directly bonded to the first plurality of under bump metallization interconnects or directly bonded to the second plurality of under bump metallization interconnects.

2. 2. The package of claim 1 , wherein the plurality of bridge interconnects are directly bonded to at least one under bump metallization interconnect of the first plurality of under bump metallization interconnects and directly bonded to at least one under bump metallization interconnect of the second plurality of under bump metallization interconnects.

3. The package of claim 1 , wherein the plurality of bridge interconnects comprises a plurality of bridge under bump metallization interconnects.

4. 4. The package of claim 3, wherein the plurality of bridge underbump metallization interconnects are directly bonded to at least one underbump metallization interconnect of the first plurality of underbump metallization interconnects and are directly bonded to at least one underbump metallization interconnect of the second plurality of underbump metallization interconnects.

5. 2. The package of claim 1, wherein the plurality of bridge interconnects are directly bonded to the first plurality of under bump metallization interconnects and directly bonded to the second plurality of under bump metallization interconnects by hybrid bonds.

6. 2. The package of claim 1 , wherein the plurality of bridge interconnects are directly coupled to the first plurality of under bump metallization interconnects and directly coupled to the second plurality of under bump metallization interconnects through at least one solder interconnect.

7. 10. The package of claim 1, wherein the plurality of bridge interconnects have a minimum width of 0.5 micrometers.

8. 10. The package of claim 1, wherein the plurality of bridge interconnects have a width in a range of approximately 0.5 to 1 micrometers.

9. 10. The package of claim 1, further comprising a second metallization portion located on a back surface of the first integrated device and a back surface of the second integrated device, the second metallization portion including at least a second dielectric layer and a second plurality of metallization interconnects.

10. 10. The package of claim 9, further comprising a third plurality of pillar interconnects coupled to the first metallization portion and the second metallization portion, the third plurality of pillar interconnects being located in the encapsulation layer.

11. An apparatus comprising a package described in any one of claims 1 to 10.

12. 12. The apparatus of claim 11, wherein the apparatus comprises a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and a device in a motor vehicle.

13. A method for producing a package according to any one of claims 1 to 10, comprising the steps of: directly coupling the bridge comprising the plurality of bridge interconnects to the first integrated device and the second integrated device by directly coupling the plurality of bridge interconnects to the first plurality of under bump metallization interconnects and to the second plurality of under bump metallization interconnects; forming the first plurality of pillar interconnects over the first plurality of under bump metallization interconnects; forming the second plurality of pillar interconnects over the second plurality of under bump metallization interconnects; forming the encapsulation layer at least partially encapsulating the first integrated device, the second integrated device, the bridge, the first plurality of pillar interconnects, and the second plurality of pillar interconnects; forming the first metallization portion over the first integrated device, the second integrated device, the bridge, and the encapsulation layer, the first metallization portion including forming at least one dielectric layer and forming a plurality of metallization interconnects; A method comprising:

14. The method of claim 13, further comprising the steps of: removing a portion of the encapsulation layer, a portion of the bridge, a portion of the first plurality of pillar interconnects, and a portion of the second plurality of pillar interconnects. The method of claim 13 further comprising:

15. forming a second metallization portion, the second metallization portion including forming at least one second dielectric layer and forming a second plurality of metallization interconnects. The method of claim 13 further comprising:

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