Repeated plasma treatment

Abstract

A method for processing a substrate includes performing a repetitive plasma process including a plurality of cycles, each cycle of the plurality of cycles including purging a plasma processing chamber including the substrate with a first deposition gas including carbon. The substrate includes a first layer including silicon and a second layer including a metal oxide. The method further includes exposing the substrate to a first plasma generated from the first deposition gas to selectively deposit a first polymer film on the first layer relative to the second layer, purging the plasma processing chamber with an etching gas including fluorine, and exposing the substrate to a second plasma generated from the etching gas to etch the second layer.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Non-provisional Patent Application No. 17 / 339,495, filed June 4, 2021, which is incorporated by reference in its entirety.

[0002] The present invention relates generally to systems and methods for processing semiconductor devices, and in particular embodiments, to systems and methods for repetitive plasma processing. [Background technology]

[0003] Generally, semiconductor devices, such as integrated circuits (ICs), are fabricated by sequentially depositing and patterning layers of dielectric, conductive, and semiconducting materials on a substrate to form a network of electronic components and interconnect elements (e.g., transistors, resistors, capacitors, metal lines, contacts, and vias) integrated in a monolithic structure. The process flows used to form the constituent structures of semiconductor devices include the deposition and removal of various materials. For these purposes, various plasma processes are often used in the fabrication of semiconductor devices.

[0004] Plasma etching, a type of plasma process, is a common technique for etching a material by exposing it to a plasma of a gas containing charged species, neutral species, or a combination thereof. In plasma etching, the selectivity and directionality (anisotropic or isotropic) of the etch are important key properties that determine the process performance. As innovations in the semiconductor industry continue to introduce new materials and device architectures, further developments in plasma etching processes, particularly to improve selectivity and directionality, are desired to meet the increasing requirements in semiconductor device manufacturing. Summary of the Invention [Means for solving the problem]

[0005] According to a preferred embodiment of the present invention, there is provided a method for processing a substrate comprising performing a repetitive plasma process comprising a plurality of cycles, each cycle of the plurality of cycles comprising: purging a plasma processing chamber containing a substrate with a first deposition gas comprising carbon, the substrate comprising a first layer comprising silicon and a second layer comprising a metal oxide; exposing the substrate to a first plasma generated from the first deposition gas to selectively deposit a first polymer film on the first layer relative to the second layer; purging the plasma processing chamber with an etching gas comprising fluorine; and exposing the substrate to a second plasma generated from the etching gas to etch the second layer.

[0006] According to a preferred embodiment of the present invention, a method of processing a substrate includes performing a repetitive plasma process including a plurality of cycles, one of the plurality of cycles including: applying a first source power to a source electrode of a plasma processing chamber, applying a first bias power to a bias electrode of the plasma processing chamber, and flowing a deposition gas comprising carbon into the plasma processing chamber to selectively deposit a polymer film on a silicon-containing layer relative to a metal oxide layer during a first time interval; purging the plasma processing chamber with an etching gas comprising fluorine during a second time interval; and applying a second source power to the source electrode, applying a second bias power to the bias electrode, and flowing an etching gas into the plasma processing chamber to etch the metal oxide layer during a third time interval, wherein the first layer is covered under the polymer film during the third interval.

[0007] In accordance with a preferred embodiment of the present invention, a method for processing a substrate includes performing a repetitive plasma process including a plurality of cycles, each cycle of the plurality of cycles including: purging a plasma processing chamber including a substrate with a deposition gas including carbon, the substrate including a patterned interlayer dielectric (ILD) layer and a hard mask on a metal oxide etch stop layer (ESL) covering metal lines, the hard mask, the ILD layer, and the metal oxide ESL including an outer exposed surface; performing an area-selective plasma deposition process by exposing the substrate to a first plasma generated from a deposition gas to preferentially deposit a polymer film on the hard mask and the ILD layer relative to the metal oxide ESL; purging the plasma processing chamber with an etching gas including fluorine; and performing an etching process by exposing the substrate to a second plasma generated from an etching gas to preferentially etch the metal oxide ESL relative to the hard mask and the ILD layer.

[0008] For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: [Brief description of the drawings]

[0009] [Fig. 1A-1M] 1A-1I show cross-sectional views of a substrate at various intermediate stages of fabrication in a dual damascene interconnect (BEOL) processing flow undergoing repeated plasma processes (FIGS. 1G-1I) according to various embodiments. FIG. 1A shows the incoming substrate. FIG. 1B shows after trench etch. FIG. 1C shows after trench refill. FIG. 1D shows after photoresist patterning. FIG. 1E shows after via etch. FIG. 1F shows after top blocking layer removal. FIG. 1G shows after an area selective plasma deposition process. FIG. 1H shows after an etch stop layer (ESL) etch. FIG. 1I shows after completion of repeated plasma processes. FIG. 1J shows after bottom blocking layer removal. FIG. 1K shows after diffusion barrier layer deposition. FIG. 1L shows after metallization. FIG. 1M shows after planarization. [Figures 2A-2E]2A-2E show cross-sectional views of a substrate at various intermediate stages of fabrication in a dual damascene BEOL processing flow undergoing repeated plasma processes according to an alternative embodiment: Fig. 2A shows the incoming substrate; Fig. 2B shows after via etch; Fig. 2C shows after via refill; Fig. 2D shows after photoresist patterning; and Fig. 2E shows after trench etch. [Figure 3A-3C] 3A and 3B show cross-sectional views of a substrate undergoing repeated plasma processes according to different embodiments, in which FIG. 3A shows the substrate after a first area-selective plasma deposition process, FIG. 3B shows the substrate after a second area-selective plasma deposition process, and FIG. 3C shows the substrate after etching an etch stop layer (ESL). [Figure 4A] 4A-4I show flow diagrams of a cyclic plasma process according to various embodiments: Figure 4A illustrates a cyclic plasma process according to the embodiment described in Figures 1G-1I; [Figure 4B] FIG. 4B illustrates a dual damascene BEOL process including a repeated plasma process (trench first) according to the exemplary embodiment described in FIGS. 1A-1M. [Figure 4C] FIG. 4C illustrates another dual damascene BEOL process including a repeated plasma process (via first) according to the alternative embodiment described in FIGS. 2A-2E and 1F-1M. [Figure 4D] FIG. 4D illustrates a cyclic plasma process according to another alternative embodiment described in FIGS. 3A-3C. [Figure 5A] 5A-5C illustrate an embodiment method of a cyclic plasma process in a plasma processing tool: FIG 5A shows a timing diagram of one cycle of a time-multiplexed embodiment of a cyclic plasma process; [Figure 5B] FIG. 5B shows a flow diagram of a cyclic plasma process according to the embodiment of FIG. 5A. [Figure 6] 4A-4D and 5A-5B show cross-sectional views of a plasma system for carrying out a time-multiplexed embodiment of the repetitive plasma etching process shown in the flow diagrams of FIGS. [Figure 7A] 7A shows a plasma system for carrying out spatially separated embodiments of the cyclic plasma process shown in the flow diagrams of Figures 4A-4D and 5A-5B. Figure 7A shows a top view. [Figure 7B] FIG 7B shows a cross-sectional view of a plasma system for carrying out spatially separated embodiments of the cyclic plasma process shown in the flow diagrams of FIG 4A-4D and FIG 5A-5B. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] This disclosure describes embodiments of a cyclic plasma process method for selectively removing metal oxide materials over silicon-containing or other materials using fluorine-containing etching gases without causing corrosion of the metal as observed with corrosive etching gases. As described further below, the cyclic plasma process may be used to selectively remove etch stop layers (ESLs) containing metal oxides, such as aluminum oxide, as part of a damascene back-end of line (BEOL) process in semiconductor device manufacturing. The embodiments described herein provide the advantage of efficiently removing metal oxide materials while reducing the loss of other materials, such as silicon-containing hardmask materials and interlayer dielectric (ILD) materials, and avoiding metal corrosion. The innovative method achieves this advantage by combining area-selective plasma deposition that forms a protective layer over the silicon-containing material, such as silicon-containing materials, with a subsequent etch using a fluorine-containing non-corrosive gas that selectively removes the target metal oxide material with little or no protective layer, as described in further detail below. Although described in this disclosure in the context of a copper dual damascene process, the cyclic plasma process may be applied to other process flows in other structures, as known to those skilled in the art.

[0011] In general, the dual damascene BEOL process is a key step in integrated circuit fabrication for forming copper (Cu) interconnects. In the dual damascene BEOL process, a first recess, such as a via or trench, is formed and the first recess is filled with a temporary fill material. A second recess is then formed, and then the entire recess is filled with copper metal, followed by planarization. The process of forming the vias and trenches may include the removal of an etch stop layer (ESL). The ESL may be disposed between two blocking layers to separate different metal layers. Although these multiple layer stacks are sometimes collectively referred to as an etch stop layer, in this disclosure, the layers are individually referred to as the top blocking layer, the etch stop layer (ESL), and the bottom blocking layer. Although silicon carbide and silicon nitride have been used as conventional ESL materials, aluminum oxide (Al2O3) may be preferred for the ESL due to its low dielectric constant (k value of about 4-6 as a thin film) and high density. However, removal of aluminum oxide ESL is a challenge, and conventional methods for etching aluminum oxide ESL are not satisfactory. For example, wet etching processes tend to be isotropic, which increases the bottom critical dimension and results in the risk of shorts between vias or between vias and trenches. Dry plasma etching using chlorine-(Cl) or bromine-(Br) containing gases, such as BCl3, HBr, and Cl2, can cause corrosion of metal lines. On the other hand, non-corrosive gases such as fluorocarbons may be used in plasma etching processes, but may have low selectivity of ESL etching to hard mask (HM) and interlayer dielectric (ILD) materials. In various embodiments of the present disclosure, the method is based on a cyclic plasma process including an area-selective plasma deposition process and a plasma etching process using one or more fluorine-containing etching gases, which can advantageously provide better etch selectivity of ESL materials. Such advantages can lead to improved precise control of the critical dimensions of semiconductor devices during fabrication.

[0012] In various embodiments, the cyclic plasma process for selectively removing metal oxide layers is performed as part of a dual damascene back-end of line (BEOL) process in semiconductor manufacturing. Although the cyclic plasma process of the present disclosure is sometimes described as a step in a dual damascene BEOL process, the cyclic plasma process may also be applied to a single damascene BEOL process or other manufacturing processes.

[0013] First, in FIGS. 1A-1M, a dual damascene BEOL process flow (trench first) undergoing a repetitive plasma process for ESL removal is shown according to various embodiments. In FIGS. 2A-2E, an alternative embodiment of a dual damascene BEOL process flow (via first) is shown. Furthermore, in FIGS. 3A-3C, a repetitive plasma process having two area-selective plasma deposition process steps is shown according to another alternative embodiment. Several process flows of the repetitive plasma process are further described with reference to FIGS. 4A-4D for different embodiments. The steps of the repetitive plasma process may be separated in time or space. To illustrate the temporal / spatial separation, FIG. 5A shows a timing diagram of one cycle of a time-multiplexed implementation of the repetitive plasma process, and FIG. 5B shows a corresponding process flow chart. FIG. 6 shows an exemplary plasma processing system. In FIGS. 7A and 7B, an alternative plasma processing system and corresponding spatial separation method are shown.

[0014] 1A shows a cross-sectional view of an incoming substrate 90. In various embodiments, the substrate 90 may be part of a semiconductor device and may have undergone several processing steps following conventional processing, for example. Thus, the substrate 90 may include layers of semiconductors useful in various microelectronic technologies. For example, a semiconductor structure may include the substrate 90 upon which various device regions are formed.

[0015] In one or more embodiments, the substrate 90 may be a silicon wafer or a silicon-on-insulator (SOI) wafer. In certain embodiments, the substrate 90 may include a silicon germanium wafer, a silicon carbide wafer, a gallium arsenide wafer, a gallium nitride wafer, or other compound semiconductors. In other embodiments, the substrate 90 includes heterogeneous layers, such as silicon germanium-on-silicon, gallium nitride-on-silicon, silicon carbon-on-silicon, as well as layers of silicon-on-silicon or SOI substrates. In various embodiments, the substrate 90 is patterned or embedded with other components of a semiconductor device.

[0016] As shown in FIG. 1A, the substrate 90 may further include a metal layer 100 thereon. In some embodiments, there may be one or more layers between the substrate 90 and the metal layer 100, such as a dielectric layer. In various embodiments, the metal layer 100 may be formed as part of a patterned metal interconnect on the substrate 90. In various embodiments, the metal layer 100 may include copper (Cu), aluminum (Al), doped polycrystalline silicon, tungsten, titanium nitride, tantalum nitride, ruthenium, and other metals. The metal layer 100 may be formed by deposition using, for example, physical vapor deposition (PVD).

[0017] A dielectric layer may be deposited on the metal layer 100 as a bottom barrier layer 115. In certain embodiments, the bottom barrier layer 115 may include silicon-based dielectric materials such as silicon nitride and silicon carbonitride (SiCN). The bottom barrier layer 115 may be deposited using deposition techniques such as vapor deposition, including chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD), as well as other plasma processes, such as plasma enhanced chemical vapor deposition (PECVD), sputtering, and other processes.

[0018] Another dielectric layer may be further deposited as an etch stop layer (ESL) 120 on the bottom barrier layer 115. In various embodiments, the ESL 120 may include aluminum oxide, aluminum nitride, or zirconium oxide. The ESL 120 may be deposited using deposition techniques such as vapor deposition, including chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD), as well as other plasma processes, such as plasma enhanced chemical vapor deposition (PECVD), sputtering, and other processes. In certain embodiments, the thickness of the ESL 120 may be between 2 nm and 5 nm.

[0019] 1A , a top blocking layer 125 may be formed on the ESL 120. In certain embodiments, the top blocking layer 125 may include a silicon-based dielectric material, such as silicon nitride and silicon carbonitride (SiCN). The top blocking layer 125 may generally be the same material as the bottom blocking layer 115. The top blocking layer 125 may be deposited using deposition techniques such as vapor deposition, including chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD), as well as other plasma processes, such as plasma enhanced chemical vapor deposition (PECVD), sputtering, and other processes.

[0020] Another dielectric layer may be formed on top of the top blocking layer 125 as an interlevel dielectric (ILD) layer 130. The ILD layer 130 may include a silicon-based dielectric material having a low dielectric constant (i.e., low k value), such as organosilicate glass (SiCOH), dense SiCOH, porous SiCOH, and other porous dielectric materials. The ILD layer 130 may be deposited using deposition techniques such as vapor deposition, including chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD), as well as other plasma processes, such as plasma enhanced chemical vapor deposition (PECVD), sputtering, and other processes.

[0021] As further shown in FIG. 1A, a first hard mask 140 may be formed on the interlayer dielectric (ILD) layer 130. In certain embodiments, the first hard mask 140 may include silicon nitride. In alternative embodiments, the first hard mask 140 may include silicon dioxide (SiO2) or titanium nitride. Additionally, the first hard mask 140 may be a stacked hard mask including two or more layers using two different materials, for example. A first layer of the first hard mask 140 may include a metal-based layer, such as titanium nitride, titanium, tantalum nitride, tantalum, tungsten-based compounds, ruthenium-based compounds, or aluminum-based compounds, and a second layer of the first hard mask 140 may include a dielectric layer, such as silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, amorphous silicon, or polycrystalline silicon. The first hard mask 140 may be deposited using deposition techniques such as vapor deposition, including chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD), as well as other plasma processes, such as plasma enhanced chemical vapor deposition (PECVD), sputtering, and other processes.

[0022] A first photoresist 150 may be deposited on the first hard mask 140, for example, using a coating process or a spin-on process. In various embodiments, the first photoresist 150 may include a photosensitive organic material and may be applied onto the first hard mask 140 from a solution, for example, by a conventional spin-coating technique. As shown in FIG. 1A, the first photoresist 150 may be patterned in a pattern using conventional photolithography techniques. In various embodiments, the pattern of the first photoresist 150 may be used for first recess formation. In certain embodiments, the first pattern may be used for trench formation, as shown in FIG. 1B.

[0023] FIG. 1B shows the substrate 90 after trench etching to form trench features. The first photoresist 150 of FIG. 1A acts as a mask layer, and the pattern of the first photoresist 150 is transferred. The trench etch anisotropically removes the portions of the first hard mask 140 and the interlayer dielectric (ILD) layer 130 that were not masked by the first photoresist 150. As shown in FIG. 1B, the trench etch may be stopped before the top blocking layer 125 is exposed to leave a space for forming a via in a later step. An etch stop layer may be used to stop the trench etch, although in some embodiments, a timed etch may be used. In certain embodiments, the trench etch includes one or more wet etch processes, plasma etch processes, reactive ion etch (RIE) processes, or a combination of these or other etch processes. The first photoresist 150 remaining after the trench etch may be removed from the substrate 90, for example, by conventional plasma ashing techniques.

[0024] 1C shows the substrate 90 after trench refill and deposition of the second hard mask 142 and the second photoresist 152. In trench refill, after removing the remaining first hard mask 140, a fill material 160, also called a gap fill material or organic bottom antireflective coating (BARC), fills the trench features formed in the previous step. The fill material 160 may be spun on from a solution of an organic solvent. In some embodiments, the fill material 160 may be deposited using other deposition techniques, including evaporation. A planarization process, such as a chemical mechanical planarization process, may be used to ensure that the surface of the fill material 160 is coplanar with the major surface of the ILD layer 130.

[0025] Further, still referring to FIG. 1C, a second hard mask 142 and a second photoresist 152 are applied for the next step of patterning. The second hard mask 142 may be similar to the first hard mask 140 previously described, but may have a different composition in some embodiments. The second hard mask 142 may be deposited using deposition techniques such as deposition, including chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD), as well as other plasma processes, such as plasma enhanced chemical vapor deposition (PECVD), sputtering, and other processes. The second photoresist 152 may be similar to the first photoresist 150 previously described, but may have a different composition in some embodiments. The second photoresist 152 is applied onto the second hard mask 142 from a solution, for example, by a conventional spin coating technique.

[0026] 1D shows the substrate 90 after one or more lithography processes have defined a pattern of second photoresist 152. In various embodiments, the pattern of second photoresist 152 may be used for second recess formation. In certain embodiments, as shown in FIG. 1E, the pattern of second photoresist 152 may be used for via formation.

[0027] FIG. 1E shows the substrate 90 after removing the fill material 160 after the via etch. The second photoresist 152 in FIG. 1D acts as a mask layer to transfer the pattern of the second photoresist 152. The via etch anisotropically removes the portions of the second hard mask 142, the fill material 160, and the interlayer dielectric (ILD) layer 130 that were not masked by the second photoresist 152. The remaining second photoresist 152 and the fill material 160 may be removed, for example, by conventional plasma ashing techniques. This removal step may also remove the portions of the second hard mask 142 that are isolated above the fill material 160. In certain embodiments, the via etch process includes one or more wet etch processes, plasma etch processes, reactive ion etch (RIE) processes, or a combination of these or other etch processes.

[0028] FIG. 1F illustrates the substrate 90 after removing the top blocking layer 125 at the bottom of the formed via. In various embodiments, the removal of the top blocking layer may be performed by an etching process to expose a portion of the etch stop layer (ESL) 120 prior to a subsequent repeated plasma process (e.g., FIGS. 1G-1I). In certain embodiments, the etching of the top blocking layer 125 includes one or more wet etching processes, plasma etching processes, reactive ion etching (RIE) processes, or a combination of these or other etching processes. In certain embodiments, the via etching and the etching of the top blocking layer 125 may be performed as a single etching step. In certain embodiments, the repeated plasma processes described below may be performed in a manner to achieve at least a portion of the objectives of the via etching or the etching of the top blocking layer 125.

[0029] In certain embodiments, before performing the repeated plasma process, an optional pretreatment may be performed to chemically or physically modify the composition of surface termination groups of layers overlying the substrate 90 (e.g., the second hard mask 142 and the interlayer dielectric (ILD) layer 130 of FIG. 1F) to enhance the selectivity of subsequent repeated plasma processes. For example, the optional pretreatment may be a plasma treatment using a hydrogen-containing reducing agent. In one embodiment, a plasma treatment using molecular hydrogen (H2) may be performed.

[0030] FIG. 1G illustrates the substrate 90 after an area-selective plasma deposition process to form a polymer film 165. The formation of the polymer film 165 is the first plasma step of a cyclic plasma process in various embodiments. In various embodiments, the polymer film 165 may be selectively formed on the second hard mask 142 and the interlayer dielectric (ILD) layer 130 relative to the ESL 120 by exposing the substrate 90 to a plasma of a deposition gas. In various embodiments, the deposition rate on the second hard mask 142 or the interlayer dielectric (ILD) layer 130 relative to the ESL 120 may be between 5:1 and 1000:1, resulting in little or no polymer film being formed on the ESL 120. Thus, the polymer film 165 is much thicker on the second hard mask 142 or the interlayer dielectric (ILD) layer 130 than on the ESL 120.

[0031] In various embodiments, the deposition gas includes a mixture of a carbon-containing polymer film precursor and a diluent. For example, in various embodiments, the polymer film precursor is an alkane. In certain embodiments, the deposition gas is a mixture of methane (CH4) and argon (Ar) in any ratio. In some embodiments, the deposition gas may further include hydrogen (H2) or nitrogen (N2). In some embodiments, the deposition gas may further include ethane, ethylene, and other hydrocarbons.

[0032] In one embodiment, the area-selective plasma deposition process may be performed using a mixture of CH4 and Ar gas at a process temperature between 20° C. and 120° C., and the polymer film 165 is preferentially formed on the interlayer dielectric (ILD) layer 130 and the second hard mask 142, which include silicon-containing materials such as silicon nitride, silicon oxide, and organosilicate glass (SiCOH), compared to the etch stop layer (ESL) 120, which includes aluminum oxide. The silicon oxide may be prepared by plasma-enhanced CVD or flowable CVD, for example, using tetraethyl orthosilicate (TEOS) as a precursor. In a different embodiment, the polymer film 165 may be preferentially formed on the second hard mask 142, which includes titanium nitride, compared to the ESL 120, which includes aluminum oxide.

[0033] FIG. 1H shows the substrate 90 after etching of the ESL 120 using a fluorine-containing gas in the second plasma step of the cyclic plasma process. The polymer film 165 formed by the first plasma step (area-selective plasma deposition process) in the steps before FIG. 1G above acts as a protective layer to protect the second hard mask 142 and the ILD layer 130 while the exposed portion of the ESL 120 is anisotropically etched. A thicker polymer film 165 formed on the second hard mask 142 or the interlayer dielectric (ILD) layer 130 protects the underlying material from etching and allows the use of non-selective or even less selective etchants. If a polymer film 165 is present on the ESL 120, it will be etched first, since it is thinner, and then the exposed ESL 120 will be etched.

[0034] In various embodiments, the fluorine-containing etch gas may include gases that are not corrosive to metals, including copper. In various embodiments, the fluorine-containing gas does not contain chlorine or bromine and may not cause metal corrosion of metal lines over an extended period of time. This is different from chlorine or bromine-containing gases that may cause copper corrosion during product life, resulting in product failure.

[0035] In various embodiments, the fluorine-containing etch gas includes tetrafluoromethane (CF4), nitrogen trifluoride (NF3), fluoroform (CHF3), difluoromethane (CH2F2), fluoromethane (CH3F), and combinations thereof. The fluorine-containing etch gas may be selected to be free of sulfur, which may cause metal corrosion of metal lines, similar to chlorine or bromine as described above. In certain embodiments, the etch gas further includes oxygen (O2) in any ratio. In one or more embodiments, the etch gas further includes oxygen at 0.1% to 10% by volume. The etch gas may further include a diluent, such as argon (Ar) and nitrogen (N2), in any ratio. In various embodiments, the area-selective plasma deposition (first plasma step) and subsequent etch plasma process (second plasma step) are repeated to achieve a target amount of selective ESL removal. Various embodiments of the repeated plasma process are further described with reference to FIGS. 4A-4D.

[0036] In a particular embodiment, the etch plasma process (second plasma step) preferentially removes the ESL 120 comprising aluminum oxide compared to the second hard mask 142 protected by a polymer film and the interlevel dielectric (ILD) layer 130 comprising silicon-containing materials such as silicon nitride, silicon oxide, and organosilicate glass (SiCOH) using a plasma of tetrafluoromethane (CF4) at a process temperature between 60° C. and 120° C. In a different embodiment, the ESL 120 comprising aluminum oxide may be preferentially etched compared to the second hard mask 142 protected by a polymer film comprising titanium nitride.

[0037] FIGURE 1I illustrates substrate 90 after completion of the cyclic plasma process. According to various embodiments, portions of ESL 120 corresponding to the pattern of second photoresist 152 defined in FIGURE 1D are removed to extend the via down to bottom barrier layer 115. In the embodiment illustrated in FIGURE 1I, the process parameters of the cyclic plasma process may be optimized to completely remove not only ESL 120, but also polymer film 165 from second hard mask 142 and ILD layer 130.

[0038] In various embodiments, after the repetitive plasma process, further steps of a dual damascene back-end wiring (BEOL) process may be performed to form metal interconnects. FIG. 1J shows the substrate 90 after etching to remove a portion of the bottom blocking layer 115, exposing a portion of the metal layer 100 according to the pattern of vias formed. In certain embodiments, the etching of the bottom blocking layer 115 includes one or more wet etching processes, plasma etching processes, reactive ion etching (RIE) processes, or a combination of these or other etching processes. In certain embodiments, at least a portion of the etching of the bottom blocking layer 115, or any other subsequent steps of the dual damascene BEOL process, may be integrated as part of the repetitive plasma process described above.

[0039] 1K shows the substrate 90 after deposition of a diffusion barrier layer 170. In certain embodiments, the diffusion barrier layer 170 may include tantalum, tantalum nitride, titanium, or titanium nitride. The diffusion barrier layer is intended to prevent the metal in the metal layer 100 from diffusing into other components during fabrication. The diffusion barrier layer 170 may be deposited using deposition techniques such as vapor deposition, including sputtering, chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD), as well as other plasma processes, such as plasma enhanced chemical vapor deposition (PECVD) and other processes.

[0040] FIG. 1L shows the substrate 90 after metal deposition. Metal deposition may be performed by deposition of a seed layer of metal (e.g., copper) using sputtering or physical vapor deposition (PVD) techniques, followed by electroplating. In this step of metal deposition, the vias and trenches are filled with metal. As shown in FIG. 1L, in various embodiments, the same metal may be used for metal deposition, typically as metal layer 100.

[0041] Finally, FIG. 1M shows substrate 90 after planarization, where excess metal has been removed, for example by chemical mechanical planarization (CMP).

[0042] In the exemplary embodiment shown in Figures 1A-1M, the trench etch (Figure 1B) is performed before the via etch (Figure 1E). This sequence is called trench first. However, in other embodiments, the via etch may be performed before the trench etch (via first), as shown in Figures 2A-2E below.

[0043] In FIG. 2A, an incoming substrate 90 has a structure similar to the previous (trench-first) embodiment described above, with a layer stack including a metal layer 100, a bottom blocking layer 115, an etch stop layer (ESL) 120, a top blocking layer 125, and an interlayer dielectric (ILD) layer 130. A first hard mask 240 is formed on top of the ILD layer 130. A first photoresist 250 may be formed on the first hard mask 240 with a pattern for a via etch similar to that of FIG. 1D. The first hard mask 240 and the first photoresist 250 may be similar to the first hard mask 140 and the first photoresist 150 of FIG. 1A, respectively, although in some embodiments they may have different compositions.

[0044] Figure 2B shows the substrate 90 after the via etch. The first photoresist 250 of Figure 2A acts as a mask layer to which the pattern of the first photoresist 250 is transferred. As previously described with the previous embodiments, the via etch may be performed using a suitable etching process to anisotropically remove the portions of the first hard mask 240 and the interlayer dielectric (ILD) layer 130 that were not masked by the first photoresist 250 and expose the top blocking layer 125 at the bottom of the formed via.

[0045] FIG. 2C shows substrate 90 after via refill and deposition of second hard mask 242 and second photoresist 252. In via refill, the remaining first hard mask 240 is removed, followed by filling material 260 filling the via feature formed in the previous step. Fill material 260 may be similar to fill material 160, but in some embodiments may have a different composition. Fill material 260 may be spun on from a solution of an organic solvent. In some embodiments, fill material 260 may be deposited using other deposition techniques, including evaporation. A planarization process, such as a chemical mechanical planarization process, may be used to ensure that the surface of fill material 260 is flush with the major surface of ILD layer 130.

[0046] 2C, a second hard mask 242 and a second photoresist 252 are formed on the ILD layer 130 and the fill material 260, similar to FIG. 1C. The second hard mask 242 and the second photoresist 252 may be similar to the first hard mask 240 and the first photoresist 250, respectively, although they may have different compositions. The second hard mask 242 may be deposited using a suitable deposition technique, similar to the second hard mask 142 of FIG. 1C. The second photoresist 252 may be applied onto the second hard mask 242 from a solution, for example, by a conventional spin-coating technique.

[0047] 2D shows the substrate 90 after one or more lithography processes have defined a pattern in a second photoresist 252. The pattern in the second photoresist 252 may be used for trench formation.

[0048] FIG. 2E shows the substrate 90 after trench etching. The patterned second photoresist 252 of FIG. 2D acts as a mask layer to transfer the pattern of the second photoresist 252. As previously described with the previous embodiments, the trench etch may be performed using a suitable etching process to anisotropically remove the second hard mask 242, the fill material 260, and the portions of the interlayer dielectric (ILD) layer 130 that were not masked by the second photoresist 252. As shown in FIG. 2E, the trench etch may be performed to completely remove the fill material 260 to expose the top blocking layer at the bottom of the via, but may be stopped before the portions of the ILD layer 130 that were not masked by the second photoresist 252 are completely removed. An etch stop layer may be used to stop the trench etch, but in some embodiments, a timed etch may be used. The remaining second photoresist 252 may be removed, for example, by conventional plasma ashing techniques. At this stage, substrate 90 has a structure with trench and via features similar to that shown in FIG. 1E formed according to the trench-first embodiment.

[0049] Subsequently, removal of the top blocking layer 125, repeated plasma processes, and subsequent processes may be performed as in the previous embodiments (eg, as in Figures 1F, 1G-1I, and 1J-1M, respectively).

[0050] Although the previous embodiment is described as part of a dual damascene interconnect (BEOL) process, the repeated plasma process of the present disclosure is not limited to the dual damascene BEOL process and may be applied to other manufacturing processes to selectively remove certain materials (e.g., aluminum oxide) by using one or more protective layers selectively formed on other materials (e.g., silicon-containing materials). In one embodiment, the repeated plasma process may be applied to a single damascene BEOL process. In one cycle of the single damascene BEOL process, only one recess, such as a trench or a via, may be formed instead of two recesses in the dual damascene BEOL process. For example, the repeated plasma etching may be performed after the via formation (e.g., FIG. 2B).

[0051] In various embodiments, the repeated plasma process may include two separate area-selective plasma deposition process steps. The method of this embodiment may improve selective etching of target material from a surface containing more than two materials. The formation of trenches and vias prior to the repeated plasma process may be performed by a trench-first method (e.g., FIGS. 1A-1E) or a via-first method (e.g., FIGS. 2A-2E), resulting in the same structure as shown in FIG. 1F. Subsequent repeated plasma process steps according to these embodiments are shown in FIGS. 3A-3C.

[0052] FIG. 3A shows the substrate 90 after a first area-selective plasma deposition process (first plasma step) using a first deposition gas. The first deposition gas may be similar to the deposition gas previously described with reference to FIG. 1G. As shown, a first polymer film 360 may be preferentially formed on the second hard mask 142 relative to the interlayer dielectric (ILD) layer 130 and the etch stop layer (ESL) 120. The first polymer film 360 may be similar in composition to and formed similarly to the polymer film 165 described above. At this stage, for example, the composition of the first deposition gas and other process parameters may be selected to achieve a high deposition rate and / or selectivity with respect to the second hard mask 142.

[0053] Next, FIG. 3B shows the substrate 90 after a second area-selective plasma deposition process (second plasma step) using a second deposition gas. A second polymer film 362, which is compositionally different from the first polymer film 360, may be preferentially formed on the ILD layer 130 compared to the second hard mask 142 and the ESL 120. The first polymer film 360, the second polymer film 362, or both may be compositionally similar to the polymer film 165. In one embodiment, the first and second polymer films 360 and 362 may be compositionally the same, but may be formed at different rates by selecting different process parameters for the first and second plasma steps. The second deposition gas may be similar to the deposition gas previously described with reference to FIG. 1G. For example, the second deposition gas includes a mixture of a carbon-containing second polymer film precursor and a diluent. In a particular embodiment, the second polymer film precursor is an alkane. In a particular embodiment, the deposition gas is a mixture of methane (CH4) and argon (Ar) in any ratio. In some embodiments, the deposition gas may further include hydrogen (H2) or nitrogen (N2). The second deposition gas may or may not be the same as the first deposition gas of the first area-selective plasma deposition process. The composition of the second deposition gas and other process parameters may be selected to achieve a high deposition rate and / or selectivity with respect to the inter-layer dielectric (ILD) layer 130.

[0054] In one embodiment, the process parameters of the first plasma step may be optimized toward forming a first polymer film 360 on a silicon-containing hardmask, while the process parameters of the second plasma step may be optimized toward forming a second polymer film 362 on an ILD layer 130 comprising a low-k dielectric such as SiCOH, while both conditions are still selective relative to an etch stop layer (ESL) 120 comprising aluminum oxide.

[0055] 3C shows substrate 90 after etching of ESL 120 using a fluorine-containing gas in a third plasma step of the cyclic plasma process. The exposed portions of ESL 120 are anisotropically etched as previously described in FIG. 1H. The first and second polymer films 360 and 362 formed by the above first and second area-selective plasma deposition process steps (first and second plasma steps) act as protective layers to protect second hard mask 142 and ILD layer 130, respectively.

[0056] Although the embodiments described above (e.g., Figures 3A-3C) include two area-selective plasma deposition process steps, in alternative embodiments, the repeated plasma process may include any number of area-selective plasma deposition process steps and one or more etching processes.

[0057] In the following, Figures 4A to 4D show process flow charts of a repetitive plasma process corresponding to the above-mentioned embodiments, where Figure 4A corresponds to Figures 1G to 1I, Figure 4B corresponds to Figures 1A to 1M, Figure 4C corresponds to Figures 2A to 2E and Figures 1F to 1M, and Figure 4D corresponds to Figures 3A to 3C, respectively.

[0058] In various embodiments, all steps of the repetitive plasma process, eg, corresponding to FIGS. 1G-1I, may be performed inside a plasma processing tool.

[0059] FIG. 4A illustrates a process flow of a repetitive plasma process according to various embodiments. The repetitive plasma process (block 450A) includes four main steps: purging a plasma processing chamber of a plasma processing tool with a carbon-containing deposition gas (block 451), exposing a substrate to a plasma generated from the deposition gas (block 452) (e.g., FIG. 1G), purging the plasma processing chamber with a fluorine-containing etching gas (block 455), and exposing a substrate to a plasma of an etching gas (block 456) (e.g., FIG. 1H). Each step of the repetitive plasma process may be separated in time or space. In certain embodiments, the repetitive plasma process may be performed in a single compartment of a plasma processing chamber by a time multiplexing process as detailed in FIG. 5 and FIG. 6. In other embodiments, the repetitive plasma process may be performed in separate compartments of a plasma processing chamber, and the substrate may be transported from one compartment to another to proceed to the next step, as shown with reference to FIG. 7A and FIG. 7B.

[0060] In block 451, as a first step of a cyclic plasma process, the plasma processing chamber may be purged with a carbon-containing deposition gas, such as methane (CH4), and the substrate temperature may be equilibrated at a process temperature. In various embodiments, the substrate temperature may be elevated, for example, by a heater and cooled by water cooling or liquid helium cooling, which are controlled by a temperature controller.

[0061] Secondly, in block 452, a first plasma step (area-selective plasma deposition) of the cyclic plasma process is performed by a plasma deposition tool, such as a plasma enhanced chemical vapor deposition (PECVD) tool (e.g., FIG. 1G). By providing plasma source energy from one or more plasma power sources, a plasma of a deposition gas is generated in the plasma processing chamber, and the substrate is exposed to the plasma of the deposition gas. Precursor species of the polymer film 165 can be energized by the plasma to form radicals. These radicals can be adsorbed on the surface and react randomly with each other in a plasma polymerization process to form the polymer film 165 (e.g., FIG. 1G). The difference in the amount of adsorption between different materials can result in different rates of plasma polymerization, thereby resulting in different film growth rates. Therefore, the process parameters, such as source power, bias power, gas flow rate, process pressure, process temperature, process time, and gas composition, can be optimized to achieve the area-selective formation of the polymer film.

[0062] Next, in block 235, the first plasma step is terminated by turning off the plasma source power, and the plasma processing chamber is purged with an etching gas containing fluorine. In various embodiments, the substrate temperature may be kept the same as the first plasma step, or may be equilibrated at another process temperature. In various embodiments, the substrate temperature may be raised, for example, by a heater and cooled by water cooling or liquid helium cooling, which are controlled by a temperature controller.

[0063] In block 456, a second plasma step is performed to etch the metal oxide (e.g., ESL 120 of FIG. 1H). As shown in FIG. 1H, the polymer film 165 may also be partially or completely removed during this step. A plasma of an etching gas is generated in the plasma processing chamber and the substrate is exposed to the plasma of the etching gas. In certain embodiments, the polymer film 165 and ESL 120, which includes aluminum oxide, are anisotropically etched while other materials (e.g., second hard mask 142 and interlayer dielectric (ILD) layer 130 of FIG. 1H) are protected.

[0064] In some conventional methods, plasma etching using non-corrosive gases tends to lead to non-selective etching. The common conditions for removing metal oxide materials such as aluminum oxide often damage other materials such as silicon-containing materials that may be used as hard masks and interlayer dielectric (ILD) layers. However, in the method of the disclosed embodiment, such damage may be advantageously minimized or completely eliminated thanks to the presence of a polymer film formed on such materials during area-selective deposition in the first plasma step. Process parameters such as source power, bias power, gas flow rate, process pressure, process temperature, process time, and gas composition may be optimized to effectively etch the target metal oxide material, and at the same time, removal of the polymer film may also be achieved.

[0065] In certain embodiments, the plasma processing chamber may be evacuated to a vacuum prior to any of the purging steps (e.g., blocks 451 and 455). Additionally, in some embodiments, one or more additional treatment steps may be inserted between the steps. The additional treatments may be thermal treatments under vacuum, wet processes, plasma treatments similar to the pre-treatment (block 445), or other processes.

[0066] In various embodiments, this cycle of four steps (blocks 451, 452, 455, and 456) may be repeated to achieve the desired process performance. The cycle may begin with any of these four steps.

[0067] In FIG. 4B, according to certain embodiments, a repetitive plasma process may be used to selectively remove an etch stop layer (ESL) from a substrate as part of a dual damascene interconnect (BEOL) process using a trench-first approach (e.g., FIGS. 1A-1M).

[0068] The substrate may have undergone various manufacturing steps and may have a layer stack including a first hard mask 140 and a first photoresist 150 (block 400) (e.g., FIG. 1A). First, a trench etch (block 410) (e.g., FIG. 1B) is performed to form a trench feature as described above. Then, trench refill, deposition of a second hard mask 142 and a second photoresist 152, and patterning of the second photoresist 152 are performed (block 420) (e.g., FIGS. 1C and 1D). This is followed by a via etch (block 430) (e.g., FIG. 1E). Next, the top blocking layer 125 may be optionally removed (block 440) (e.g., FIG. 1F). In some embodiments, this step of removing the top blocking layer 125 may be integrated into a subsequent repeated plasma process (block 450B) (e.g., FIGS. 1G-1I). Additionally, to enhance the selectivity of subsequent repeated plasma processes, an optional pretreatment (block 445) may be performed to chemically or physically modify the composition of surface termination groups of layers present on the substrate 90 (e.g., second hard mask 142 and interlayer dielectric (ILD) layer 130 of FIG. 1F). A repeated plasma process (block 450B) (e.g., FIGS. 1G-1I) may then be performed as described above with reference to block 450A of FIG. 4A.

[0069] Still referring to FIG. 4B, after completion of the repeated plasma process (block 450B), the bottom insulating layer 115 may be optionally removed (block 460) (e.g., FIG. 1J). In some embodiments, this step of removing the bottom insulating layer 115 may be integrated into the previous repeated plasma process (block 450B) (e.g., FIGS. 1G-1I). Subsequently, deposition of a diffusion barrier layer 170, metal deposition, and planarization are performed to complete the metal interconnect formation cycle (block 470) (e.g., FIGS. 1K-1M).

[0070] FIG. 4C illustrates an exemplary process flow diagram of a dual damascene interconnect (BEOL) process using a via-first method according to an alternative embodiment (eg, FIGS. 2A-2E and 1F-1M).

[0071] As with previous embodiments using the trench-first method, the substrate may have undergone various manufacturing steps and may have a layer stack including a first hard mask 240 and a first photoresist 250 (block 402) (e.g., FIG. 2A). First, a via etch (block 402) (e.g., FIG. 2B) is performed to form a via feature as previously described. Next, via refill, deposition of a second hard mask 242 and a second photoresist 252, and patterning of the second photoresist 252 are performed (block 422) (e.g., FIGS. 2C and 2D). Then, a trench etch is performed (block 432) (e.g., FIG. 2E). Subsequent processes may be similar to the process flows of previously described trench-first embodiments (e.g., FIGS. 1F-1M and 4B). The top blocking layer 125 may be optionally removed (block 442) (e.g., FIG. 1F), although in some embodiments, this step of removing the top blocking layer 125 may be integrated into a subsequent repeated plasma process (block 450B) (e.g., FIG. 1G-FIG. 1I). Furthermore, to enhance the selectivity of the subsequent repeated plasma process, an optional pretreatment (block 447) may be performed to chemically or physically modify the composition of the surface termination groups of the layers present on the substrate 90 (e.g., the second hard mask 142 and the interlayer dielectric (ILD) layer 130 of FIG. 1F). The repeated plasma process (block 450C) and subsequent processes may be similar to the previous embodiments described above (e.g., blocks 450B, 460, and 470 of FIG. 4B). After completion of the repeated plasma process (block 450C), the bottom insulating layer 115 may be optionally removed (block 462) (e.g., FIG. 1J), although in some embodiments this step of removing the bottom insulating layer 115 may be integrated into the previous repeated plasma process (block 450C) (e.g., FIGS. 1G-1I). Finally, deposition of a diffusion barrier layer 170, metal deposition, and planarization are performed (block 472) (e.g., FIGS. 1K-1M).

[0072] 4D shows an example process flow chart of a repetitive plasma process including two area-selective plasma deposition process steps and an etch process according to different embodiments (e.g., FIGS. 3A-3C). As mentioned above, in certain embodiments, a repetitive plasma process including two area-selective plasma deposition process steps may be used to enable two optimized conditions for plasma depositing two polymer films on two different materials compared to a target etch material.

[0073] In these embodiments, the repeated plasma process may include six steps: in addition to the four steps previously described (e.g., blocks 451, 452, 455, and 456 in Figures 4A-4C), a first area-selective plasma deposition step (block 452) is followed by a purge step with a second deposition gas (block 453), and an area-selective plasma deposition process with the second deposition gas (block 454).

[0074] In this disclosure, details of the cyclic plasma process and alternative embodiments are described with a focus on four main steps: two purge steps and area-selective plasma deposition and etching (e.g., block 450A of FIG. 4A ). However, it is contemplated that such details may be applicable to cyclic plasma processes including any number of plasma deposition and etching processes (e.g., example block 450D having two deposition process steps and one etching process).

[0075] FIG. 5A shows a timing diagram of four steps in one cycle of a time-multiplexed embodiment of a repetitive plasma process, such as that shown in the flow diagram of FIG. 4A. The six horizontal axes of FIG. 5A represent the progression of time. Four time intervals T1, T2, T3, and T4 for the four steps of one cycle of the repetitive plasma etching process 230 are shown diagrammatically by four double arrows adjacent to a time axis. With reference to FIG. 4A, T1, T2, T3, and T4 correspond to a purge with a deposition gas (block 451), an area-selective plasma deposition process (block 452), a purge with an etching gas (block 455), and a plasma etch (block 456), respectively. Four vertical dotted lines intersecting the time axis demarcate the boundaries of the non-overlapping time intervals T1, T2, T3, and T4. In a particular embodiment, T1 may be about 5 to about 60 seconds, T2 may be about 1 to about 5 seconds, T3 may be about 5 to about 60 seconds, and T4 may be about 1 to about 5 seconds. The durations of the time intervals T1, T2, T3, and T4 may not be equal according to the respective process recipes. Six time axes are used to generally illustrate plots of six process parameters versus time for one of multiple cycles of an exemplary repeating plasma etch process 450A as shown in FIG. 4A. The six process parameters plotted in FIG. 5A are source power, bias power, process pressure, gas flow rate of deposition gas, gas flow rate of etching gas, and gas flow rate of dilution gas.

[0076] 5A, any other process parameters, such as temperature, may be independently controlled at each step of the repeated plasma process according to the respective process recipe. In a particular embodiment, time intervals T1 and T3 may be adjusted to stabilize the process temperature during T2 and T4, respectively.

[0077] In various embodiments, the substrate is kept at a temperature between 5° C. and 120° C. In some embodiments, the temperature may be changed at each step of the repeated plasma process, and a purge step is used to stabilize the system before generating the plasma. In alternative embodiments, the temperature may be programmed to increase or cool during the plasma steps, i.e., time intervals T2 and T4.

[0078] During time interval T1 shown in FIG. 5A, while the source power and bias power are turned off, a deposition gas is introduced to purge the plasma processing chamber. In certain embodiments, a dilution gas is also optionally used. In various embodiments, the total gas flow rate may be between 20-1000 sccm. The process pressure may be between 5-100 mTorr. In some embodiments, the CH4 / Ar gas flow rate is 30 / 150 sccm and the process pressure is 10 mTorr.

[0079] The switch from the time interval T1 for area selective plasma deposition to the next time interval T2 is performed by turning on the source power and bias power. In this step, radical rich conditions are desired to form the polymer film. A sufficiently high source power may be applied to achieve a radical rich environment. In various embodiments, the source power may be between 50W and 1000W and the bias power may be between 0W and 200W. The total gas flow rate may be between 20 and 1000sccm. The process pressure may be between 5 and 100mTorr. In some embodiments, the source power is 500W and the bias power is 100W. The CH4 / Ar gas flow rate is 30 / 150sccm. The process pressure is 10mTorr. In certain embodiments, the gas flow rate of the dilution gas may vary between T1 and T2.

[0080] Time interval T3 is then initiated by turning off the source power and bias power. At the same time, the gas flow is also switched from deposition gas to etching gas to purge the plasma processing chamber. The gas flow rates are selected independently of the conditions at T1 and T2. In various embodiments, the total gas flow rate may be between 20-1000 sccm. The process pressure may be between 5-100 mTorr. In some embodiments, the CF4 / CHF3 / Ar gas flow rates are 60 / 60 / 520 sccm and the process pressure is 10 mTorr.

[0081] After completion of purging the plasma processing chamber with the etching gas, a time interval T4 is initiated by turning on the source power and bias power to release the etching gas and generate the plasma. In this etching step, it is important to achieve conditions to etch anisotropically while sufficiently etching the material at the bottom of the via while causing little or no damage to the sidewalls. For anisotropic etching conditions, a relatively high bias power is desired compared to the deposition step. In various embodiments, the source power may be between 10-1000 W and the bias power may be between 50-500 W. The total gas flow rate may be between 20-1000 sccm. The process pressure may be between 5-100 mTorr. In some embodiments, the source power is 50 W and the bias power is 600 W. The CF4 / CHF3 / Ar gas flow rate is 60 / 60 / 520 sccm and the process pressure is 10 mTorr.

[0082] After time interval T4, another cycle of four time intervals may be performed. This cycle may be repeated any number of times to achieve the desired process performance. Although FIG. 5A shows a single set of conditions for one cycle of the repeating plasma process, in various embodiments, each cycle may have different conditions for process parameters from the first cycle, including any of the time intervals (T1, T2, T3, and T4), gas flow rates, gas composition, process pressure, process temperature, source power, and bias power.

[0083] Furthermore, it should be noted that the plots in Figure 5A are for illustrative purposes only. For example, these plots show how the process parameters are changed as step functions, but it is understood that instantaneous changes in the process parameters are not feasible and that finite response times for the physical parameters to stabilize should be taken into account. Furthermore, as described above, one or more additional treatment steps may be inserted after any of the time intervals (T1, T2, T3, and T4), such as evacuation, thermal treatment under vacuum, wet process, plasma treatment, etc.

[0084] FIG. 5B shows a flow diagram of a repeating plasma process according to the embodiment of FIG. 5A. In a first time interval (T1) (block 510), the source power and bias power are turned off if they are on, a deposition gas including carbon and a dilution gas is introduced into the plasma processing chamber containing the substrate at a first gas flow rate, and the plasma processing chamber is purged. In a second time interval (T2) (block 520), the source power is applied at a first level to form a plasma of the deposition gas, and the substrate is exposed to the plasma of the deposition gas. In a third time interval (T3) (block 530), the source power, the first bias power, and the deposition gas are turned off, and an etching gas including tetrafluoromethane (CF4), nitrogen trifluoride (NF3), fluoroform (CHF3), difluoromethane (CH2F2), or fluoromethane (CH3F) and a dilution gas is introduced into the plasma chamber at a second gas flow rate, and the plasma processing chamber is purged. Finally, during a fourth time interval (T4) (block 540), the source power is applied at a second level to form a plasma of the etching gas and the substrate is exposed to the plasma of the etching gas.

[0085] FIG. 6 illustrates a plasma system 600 for performing a time-multiplexed embodiment of a repetitive plasma etch process, for example, as illustrated in the flow diagrams of FIGS. 4A-4C. The plasma system 600 includes a plasma processing chamber 650 configured to maintain a plasma directly above a substrate 602 loaded on a substrate holder 610. Process gases may be introduced into the plasma processing chamber 650 through a gas inlet 622 and pumped out of the plasma processing chamber 650 through a gas outlet 624. The gas inlet 622 and the gas outlet 624 may each include a set of multiple gas inlets and gas outlets. Gas flow rates and chamber pressure may be controlled by a gas flow control system 620 coupled to the gas inlet 622 and the gas outlet 624. The gas flow control system 620 may include various components such as a high pressure gas canister, valves (e.g., throttle valves), pressure sensors, gas flow sensors, vacuum pumps, piping, and an electronically programmable controller. An RF bias power supply 634 and an RF source power supply 630 may be coupled to respective electrodes of the plasma processing chamber 650. The substrate holder 610 may also be an electrode coupled to an RF bias power supply 634. The RF source power supply 630 is shown coupled to a spiral electrode 632 wrapped around the dielectric sidewall 616. In Figure 6, the gas inlet 622 is an opening in the top plate 612 and the gas outlet 624 is an opening in the bottom plate 614. The top plate 612 and bottom plate 614 may be conductive and may be electrically connected to the system ground (reference potential).

[0086] Plasma system 600 is merely an example. In various alternative embodiments, plasma system 600 may be configured to sustain an inductively coupled plasma (ICP) with RF source power coupled to a planar coil on a top dielectric cover, or a capacitively coupled plasma (CCP) maintained using a disk-shaped top electrode within plasma processing chamber 650. Gas inlets and gas outlets may be coupled to the sidewalls of the plasma processing chamber, and in some embodiments, pulsed RF and pulsed DC power sources may also be used.

[0087] 7A and 7B show a plasma system 700 for performing a spatially separated embodiment of a repetitive plasma process, with FIG. 7A being a top view and FIG. 7B being a cross-sectional view. In the plasma system 700, the four components of each cycle may be performed in four spatially separated sections of a spatial plasma processing chamber 740. The four components of each cycle of the repetitive plasma etch process may be performed by moving the substrate through the four spatially separated sections of the spatial plasma processing chamber 740, for example, using a rotatable stage 710.

[0088] In the top view shown in FIG. 7A, the rotatable stage 710 is separated into four compartments: a first purge compartment 745, a first plasma compartment 750, a second purge compartment 755, and a second plasma compartment 760. These four compartments may be separated, for example, by an inert gas curtain 730. Each compartment may have one or more gas inlets and gas outlets. In FIG. 7A, the first plasma compartment 750 has a gas inlet 752 and a gas outlet 724, the second plasma compartment 760 has a gas inlet 723 and a gas outlet 725, and the two purge compartments 745 and 755 have a gas inlet 720 and a gas outlet 726. Purging using a deposition gas (block 451 in Figures 4A-4D) may be performed in a first purge compartment 745, area-selective plasma deposition (block 452 in Figures 4A-4D) may be performed in a first plasma compartment 750, purging using an etching gas (block 455 in Figures 4A-4D) may be performed in a second purge compartment 755, and plasma etching (block 456 in Figures 4A-4D) may be performed in a second plasma compartment 760.

[0089] For example, as shown in FIG. 7A, multiple substrates may be loaded onto the rotatable stage 710. A first substrate 702 shown loaded onto the rotatable stage 710 in a first plasma compartment 750 may undergo a deposition step of one cycle of multiple cycles of a repetitive plasma etching process, and then moved to a second purge compartment 755, followed by a next plasma etching step. At the same time, another substrate 704 may return to the first purge compartment 745 after the plasma etching step, followed by a plasma deposition step of the next cycle. Thus, multiple substrates may undergo different steps of a repetitive plasma process at the same time. One rotation of the rotatable stage 710 is equivalent to performing one cycle of a repetitive plasma etching process.

[0090] In the cross-sectional view shown in FIG. 7B, plasma compartments 750 and 760 are visible. In the exemplary spatial plasma processing chamber 740, the plasma compartments 750 and 760 are configured to maintain a capacitively coupled plasma (CCP) using a top electrode 712 coupled to an RF power source 714. In the exemplary embodiment shown in FIG. 7B, the rotatable stage 710 is electrically coupled to ground. The grounded rotatable stage 710 may function as a bottom electrode. The gas outlets 724, 725, and 726 may be connected to vacuum pumps of a gas flow system and controlled to maintain a desired pressure and gas flow rate in the corresponding compartment. One of the inert gas curtains 730 is shown diagrammatically in dashed lines. The inert curtain 730 may be a flow of inert gas (e.g., argon or helium) introduced through one of the gas inlets 720.

[0091] Illustrative embodiments of the present invention are summarized herein, with other embodiments being apparent from the entire specification and claims appended hereto. EXAMPLES

[0092] Example 1. A method for processing a substrate comprising performing a repetitive plasma process comprising a plurality of cycles, each cycle of the plurality of cycles comprising: purging a plasma processing chamber containing a substrate with a first deposition gas comprising carbon, the substrate comprising a first layer comprising silicon and a second layer comprising a metal oxide; exposing the substrate to a first plasma generated from the first deposition gas to selectively deposit a first polymer film on the first layer relative to the second layer; purging the plasma processing chamber with an etching gas comprising fluorine; and exposing the substrate to a second plasma generated from the etching gas to etch the second layer.

[0093] Example 2. The method of example 1, wherein the substrate comprises a third layer comprising silicon and oxygen, the third layer being a different material than the first layer, and a first polymer film is selectively deposited on the third layer relative to the second layer while exposing the substrate to a first plasma.

[0094] Example 3. The method of any one of Examples 1 or 2, further comprising exposing the substrate to a third plasma generated from a second deposition gas comprising carbon to selectively deposit a second polymer film on the third layer relative to the second layer.

[0095] Example 4. The method of any one of Examples 1-3, further comprising performing a pretreatment step prior to the repeated plasma process to modify the composition of the surface termination groups of the first layer or the second layer.

[0096] Example 5. The method of any one of Examples 1-4, wherein exposing the substrate to a plasma of the deposition gas and exposing the substrate to a plasma of the etching gas are separated in time by time-multiplexed processing in a fixed zone of the plasma processing chamber.

[0097] Example 6. The method of any one of Examples 1-5, wherein exposing the substrate to the plasma of the deposition gas and exposing the substrate to the plasma of the etching gas are spatially separated within a plurality of separated compartments of the plasma processing chamber.

[0098] Example 7. The method of any one of Examples 1-6, wherein the first layer comprises silicon nitride or silicon dioxide and the second layer comprises aluminum oxide.

[0099] Example 8. The method of any one of Examples 1-7, further comprising: maintaining the substrate at a first temperature during exposure to the first plasma; and maintaining the substrate at a second temperature during exposure to the second plasma, the second temperature being different from the first temperature.

[0100] Example 9. The method of any one of Examples 1-8, wherein the first deposition gas comprises methane (CH4) and the etching gas comprises tetrafluoromethane (CF4), nitrogen trifluoride (NF3), fluoroform (CHF3), difluoromethane (CH2F2), or fluoromethane (CH3F).

[0101] Example 10. The method of any one of Examples 1-9, wherein the first deposition gas further comprises a mixture comprising hydrogen (H2), argon (Ar), or nitrogen (N2).

[0102] Example 11. A method for processing a substrate, comprising: performing a repetitive plasma process comprising a plurality of cycles, one of the plurality of cycles comprising: applying a first source power to a source electrode of a plasma processing chamber, applying a first bias power to a bias electrode of the plasma processing chamber, and flowing a deposition gas comprising carbon into the plasma processing chamber to selectively deposit a polymer film on the silicon-containing layer relative to the metal oxide layer during a first time interval; purging the plasma processing chamber with an etching gas comprising fluorine during a second time interval; and applying a second source power to the source electrode, applying a second bias power to the bias electrode, and flowing an etching gas into the plasma processing chamber to etch the metal oxide layer during a third time interval, wherein the first layer is covered under the polymer film during the third interval.

[0103] Example 12. The method of example 11, wherein the cycle of the plurality of cycles further comprises purging the plasma processing chamber with a deposition gas during a fourth time interval.

[0104] Example 13. The method of any one of Examples 11 or 12, wherein the first source power is higher than the second source power and the second bias power is higher than the first bias power.

[0105] Example 14. The method of any one of Examples 11-13, wherein a cycle of the plurality of cycles further includes flowing a dilution gas into the plasma processing chamber for first, second, and third time intervals, the flow rate of the dilution gas being higher during the second interval than during the first interval.

[0106] Example 15. The method of any one of Examples 11-14, wherein the deposition gas comprises a hydrocarbon, the dilution gas comprises argon, and the etching gas comprises tetrafluoromethane (CF4), nitrogen trifluoride (NF3), fluoroform (CHF3), difluoromethane (CH2F2), or fluoromethane (CH3F).

[0107] Example 16. The method of any one of Examples 11-15, wherein the metal oxide layer comprises aluminum oxide.

[0108] Example 17. The method of any one of Examples 11-16, wherein the third time interval is selected to completely remove the polymer film.

[0109] Example 18. A method for processing a substrate, comprising performing a repetitive plasma process comprising a plurality of cycles, each cycle of the plurality of cycles comprising: purging a plasma processing chamber containing a substrate with a deposition gas comprising carbon, the substrate comprising a patterned interlayer dielectric (ILD) layer and a hardmask on a metal oxide etch stop layer (ESL) covering metal lines, the hardmask, the ILD layer, and the metal oxide ESL comprising an outer exposed surface; performing an area-selective plasma deposition process by exposing the substrate to a first plasma generated from a deposition gas to preferentially deposit a polymer film on the hardmask and the ILD layer relative to the metal oxide ESL; purging the plasma processing chamber with an etching gas comprising fluorine; and performing an etching process by exposing the substrate to a second plasma generated from an etching gas to preferentially etch the metal oxide ESL relative to the hardmask and the ILD layer.

[0110] Example 19. The method of example 18, wherein the metal oxide ESL comprises aluminum oxide, the deposition gas comprises methane, and the etching gas comprises tetrafluoromethane (CF4), nitrogen trifluoride (NF3), fluoroform (CHF3), difluoromethane (CH2F2), or fluoromethane (CH3F).

[0111] Example 20. The method of any one of examples 18 or 19, wherein the repeated plasma process is part of a dual damascene process.

[0112] Although the present invention has been described with reference to exemplary embodiments, this specification is not intended to be construed in a limiting sense. Various modifications and combinations of those exemplary embodiments, as well as other embodiments of the present invention, will be apparent to those skilled in the art upon reference to this specification. It is therefore intended that the appended claims cover any such modifications or embodiments.

Claims

1. 1. A method for processing a substrate, comprising: The method includes performing a repetitive plasma process comprising a plurality of cycles; Each cycle of the plurality of cycles comprises: purging a plasma processing chamber containing the substrate with a first deposition gas comprising methane, ethane, or ethylene, the substrate comprising a silicon-containing hardmask layer and a metal oxide layer, the silicon-containing hardmask layer having a first outer surface and the metal oxide layer having a second outer surface; exposing the first and second exterior surfaces to a first plasma generated from the first deposition gas to selectively deposit a first polymer film over the silicon-containing hardmask layer relative to the metal oxide layer; ceasing the first plasma exposure step and purging the plasma processing chamber with an etching gas comprising fluorine; exposing the substrate to a second plasma generated from the etching gas to etch the metal oxide layer, the first polymer film protecting the silicon-containing hard mask layer from being etched by the second plasma; The method comprising:

2. the substrate has a third layer comprising silicon and oxygen, the third layer having a third outer surface exposed to the first plasma, the third layer being a different material than the silicon-containing hard mask layer; The method of claim 1 , wherein the first polymer film is selectively deposited onto the third layer with respect to the metal oxide layer during the step of exposing the substrate to the first plasma.

3. 3. The method of claim 2, further comprising exposing the substrate to a third plasma generated from a second deposition gas comprising carbon to selectively deposit a second polymer film on the third layer relative to the metal oxide layer.

4. 10. The method of claim 1, further comprising performing a pretreatment step prior to the cyclic plasma process to modify a composition of surface termination groups of the silicon-containing hardmask layer or the metal oxide layer.

5. 2. The method of claim 1 , wherein the steps of exposing the substrate to the first plasma of the deposition gas and the second plasma of the etching gas are performed in a fixed zone of the plasma processing chamber and are separated in time.

6. 10. The method of claim 1, wherein the steps of exposing the substrate to the plasma of the deposition gas and exposing the substrate to the plasma of the etching gas are spatially separated in isolated sections of the plasma processing chamber.

7. 10. The method of claim 1, wherein the silicon-containing hardmask layer comprises silicon nitride or silicon dioxide and the metal oxide layer comprises aluminum oxide.

8. moreover, maintaining the substrate at a first temperature during the step of exposing the substrate to the first plasma; maintaining the substrate at a second temperature during the step of exposing the substrate to the second plasma, the second temperature being different from the first temperature; 2. The method of claim 1, comprising:

9. the first deposition gas comprises methane (CH4); 2. The method of claim 1, wherein the etching gas comprises tetrafluoromethane (CF4), nitrogen trifluoride (NF3), fluoroform (CHF3), difluoromethane (CH2F2), or fluoromethane (CH3F).

10. 10. The method of claim 1, wherein the first deposition gas further comprises a mixture including hydrogen (H2), argon (Ar), or nitrogen (N2).

11. 1. A method for processing a substrate, comprising: The method includes performing a cyclic plasma process that selectively etches a metal oxide layer of the substrate, the substrate having a silicon-containing layer, the cyclic plasma process including a plurality of cycles; One cycle of the plurality of cycles comprises: applying a first source power to a source electrode of a plasma processing chamber for a first time interval, applying a first bias power to a bias electrode of the plasma processing chamber, and flowing a deposition gas comprising methane, ethane, or ethylene into the plasma processing chamber to selectively deposit a polymer film on the silicon-containing layer with respect to the metal oxide layer; stopping the flowing of the deposition gas and the application of the first source power and the first bias power for a second time interval and purging the plasma processing chamber with an etching gas comprising fluorine; applying a second source power to the source electrode, applying a second bias power to the bias electrode, and flowing the etching gas into the plasma processing chamber for a third time interval to etch the metal oxide layer, wherein the silicon-containing layer is covered under the polymer film during the third interval; The method comprising:

12. 12. The method of claim 11, wherein the first source power is higher than the second source power and the second bias power is higher than the first bias power.

13. a cycle of the plurality of cycles further comprising flowing a dilution gas through the plasma processing chamber for the first, second, and third time intervals; The method of claim 11 , wherein the flow rate of the dilution gas is made higher during the second interval than during the first interval.

14. 12. The method of claim 11, wherein the deposition gas comprises argon and the etching gas comprises tetrafluoromethane (CF4), nitrogen trifluoride (NF3), fluoroform (CHF3), difluoromethane (CH2F2), or fluoromethane (CH3F).

15. The method of claim 11 , wherein the metal oxide layer comprises aluminum oxide.

16. The method of claim 11 , wherein the third time interval is selected to completely remove the polymer film.

17. 1. A method for processing a substrate, comprising: The method includes performing a repetitive plasma process comprising a plurality of cycles; Each cycle of the plurality of cycles comprises: purging a plasma processing chamber containing the substrate with a fluorine-free hydrocarbon containing deposition gas, the substrate having a hard mask and an interlayer dielectric (ILD) layer patterned on top of a metal oxide etch stop layer (ESL) covering metal lines, the hard mask, the ILD layer, and the metal oxide ESL including an outer exposed surface; performing an area selective plasma deposition process by exposing the substrate to a first plasma generated from the deposition gas to preferentially deposit a polymer film on top of the hard mask and the ILD layer relative to the metal oxide ESL; purging the plasma processing chamber with an etching gas comprising fluorine after performing the area-selective plasma deposition process; performing an etching process by exposing the substrate to a second plasma generated from the etching gas after purging the plasma processing chamber to preferentially etch the metal oxide ESL relative to the hard mask and the ILD layer; The method comprising:

18. 20. The method of claim 17, wherein the metal oxide ESL comprises aluminum oxide, the deposition gas comprises methane, and the etching gas comprises tetrafluoromethane (CF4), nitrogen trifluoride (NF3), fluoroform (CHF3), difluoromethane (CH2F2), or fluoromethane (CH3F).

19. The method of claim 1, wherein the first and second outer surfaces are parallel to each other.

20. The cycle of the plurality of cycles further comprising: The method of claim 11 , further comprising purging the plasma processing chamber with the deposition gas for a fourth time interval.

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