Device packaging substrate, method for manufacturing same, and device packaging including same

Abstract

An electronic device packaging substrate and a method for manufacturing the same are provided. The substrate has a finer wire width, transmits signals with low resistance, and provides a compact electronic device package. The substrate can be driven with high efficiency even when high frequency power is applied.

Description

[Technical field]

[0001] [CROSS REFERENCE TO RELATED APPLICATIONS] This application claims priority to U.S. Provisional Patent Application No. 63 / 230,118, filed August 6, 2021, the entire disclosure of which is incorporated herein by reference for all purposes.

[0002] The present disclosure relates to device packaging substrates, methods for making same, and device packaging including same. [Background technology]

[0003] Semiconductor technology, semiconductor packaging technology, semiconductor manufacturing technology, and software technology are considered to be the four core technologies in the semiconductor industry that have enabled the rapid development of electronic products in recent years. Semiconductor technology has made advances in various fields such as sub-micron nanoscale line widths, over 10 million cells, high-speed operation, and heat dissipation, but they are often supported by complete packaging technology. Therefore, the electrical performance of semiconductors is often determined by the packaging technology and the resulting electrical connections rather than the performance of the semiconductor itself.

[0004] A dielectric material may be introduced into the redistribution lines of the packaging substrate to distinguish different conductive layers from each other, and holes may be formed in the dielectric layer to provide multiple blind vias to connect two or more conductive layers arranged one above the other.

[0005] In order to improve the adhesion between the dielectric layer and the conductive layer, methods have been used that increase the surface roughness of the conductive layer. Summary of the Invention

[0006] This Summary is provided to introduce some concepts in a simplified form that are described later in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0007] In one aspect, the present invention provides a semiconductor device comprising: a glass substrate having a through hole disposed therein; and an upper redistribution layer disposed on one side of the glass substrate, the upper redistribution layer including a wire disposed in an insulating material of the upper redistribution layer, the upper redistribution layer including a first upper redistribution layer and a second upper redistribution layer, the first upper redistribution layer including a first wire having a predetermined first pattern and a first thickness, and a first blind via configured to connect the wires disposed above and below each other, the second upper redistribution layer including a second wire having a predetermined second pattern and a second thickness, and a first blind via configured to connect the wires disposed above and below each other, the first thickness being smaller than the second thickness, and w1p being a length from a roughness peak on one side of the first wire to a roughness peak on the other side of the first wire in a cross section thereof, Provided is an electronic element packaging substrate, characterized in that when w1v is the length from a roughness valley on one side of the first wire to a roughness valley on the other side in a cross section of the first wire, the ratio of the length w1v to the length w1p is 0.8 to 1.0.

[0008] the first wire has a first surface roughness value; On one side of the first wire, the first surface roughness value is less than or equal to 200 nm.

[0009] A ratio of the first thickness to the second thickness is less than or equal to 0.7.

[0010] The first thickness is a width of a first upper redistribution layer, and the second thickness is a width of a second upper redistribution layer, the first thickness is smaller than the second thickness, and the first thickness is less than 5 μm.

[0011] The first wire has a cross-sectional surface roughness value, and on one side of the first wire, the cross-sectional surface roughness value is 20 nm or less.

[0012] The adhesive strength between the insulating material and one of the wires disposed within the insulating material is 200 gf to 800 gf.

[0013] The first wire comprises copper having a particulate grain, the copper having a grain size of 40 nm or less.

[0014] A primer layer is disposed between the insulating material and the wire disposed within the insulating material.

[0015] The insulating material includes a polymer resin and inorganic particles, and a polysilane layer is disposed between the insulating material and the wire disposed within the insulating material, and the polysilane layer connects the surface of the wire disposed within the insulating material to the polymer resin or the inorganic particles by chemical bonds.

[0016] The first wire is not subjected to a surface etching process.

[0017] In another aspect, the present invention provides a method for manufacturing a semiconductor device, comprising: a first step of preparing a glass substrate in which a through hole is to be disposed; a second step of forming a second upper redistribution layer on the glass substrate; and a third step of forming a first upper redistribution layer on the second upper redistribution layer, the first upper redistribution layer including a first wire having a first predetermined pattern and a first thickness, and the second upper redistribution layer including a second wire having a second predetermined pattern and a second thickness, the first step including a first sub-step of forming the first wire having the first predetermined pattern and the first thickness by plating, and a second sub-step of performing a primer treatment on a surface of the first wire, and a third sub-step of filling an insulating material into a space between the wires (253a), wherein the first thickness is smaller than the second thickness, and where w1p is a length from a roughness peak on one side of the first wire to a roughness peak on the other side in a cross section of the first wire, and w1v is a length from a roughness valley on one side of the first wire to a roughness valley on the other side in a cross section of the first wire, a ratio of the length w1v to the length w1p is 0.8 to 1.0.

[0018] No surface etching step is applied to the surface so as to increase the surface roughness of the wire.

[0019] The first wire is a columnar grain copper-free copper wire.

[0020] The primer treatment in the second sub-stage is carried out with an imidazole compound or a silane compound.

[0021] The present invention provides an electronic device package including the above-described substrate and a device mounted on the packaging substrate.

[0022] Other features and aspects will become apparent from the following detailed description, the drawings, and the claims. [Brief description of the drawings]

[0023] [Figure 1]FIG. 1 illustrates a perspective view of an example electronic device package in accordance with one or more embodiments. [Diagram 2] FIG. 1 is a perspective view of a substrate for an electronic device package in accordance with one or more embodiments. [Diagram 3] 3 is a cross-sectional view showing a part of a cross section taken along line AA' in FIG. 2. [Figure 4] 3. A detailed view of region "∪" in FIG. 3 (the upper left "A." is an image of an example sample with a surface roughness Ry of 200 nm or less, and the lower left "B." is an image of a comparative example sample with an Ry of 2000 to 3000 nm). [Figure 5A] FIG. 5 is an enlarged view of region “G” in FIG. 4, showing a schematic cross-section of a wire with low surface roughness. [Figure 5B] FIG. 5 is an enlarged view of region “G” in FIG. 4, showing a schematic cross-section of a wire with high surface roughness. [Figure 6A] 1A-1D are schematic cross-sectional views illustrating the manufacturing process of a wire having particle-type grains. [Figure 6B] FIG. 1 is a schematic diagram showing a cross-section of a wire having column-type grain. In the drawings and the detailed description, like numbers refer to like elements. The drawings may not be to scale, and the relative scale, proportions, and descriptions of elements in the drawings may be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] The following detailed description is provided to assist the reader in a comprehensive understanding of the method, device, and / or system described herein. However, various changes, modifications, and equivalents of the method, device, and / or system described herein will become apparent upon understanding the present disclosure. For example, the order of operations described herein is merely illustrative and is not limited to those described herein, and may be changed as becomes apparent upon understanding the present disclosure, except that the operations are necessarily performed in a certain order. It should also be noted that the description of features that are well known to those skilled in the art may be omitted for clarity and conciseness, but the omission of features and their description are not intended to acknowledge their general knowledge.

[0025] The features described herein may be embodied in different forms and should not be construed as being limited to the examples described herein. Rather, the examples described herein are provided merely to illustrate some of the many possible ways of implementing the methods, apparatus, and / or systems described herein that will become apparent after understanding the present disclosure.

[0026] In this specification, terms such as "first," "second," and "third" are used to describe various members, components, regions, layers, or sections, but are not intended to limit these members, components, regions, layers, or sections. Rather, these terms are used only to distinguish one member, component, region, layer, or section from another member, component, region, layer, or section. Thus, a first member, component, region, layer, or section referred to in an embodiment described herein may also be referred to as a second member, component, region, layer, or section without departing from the teachings of the embodiment.

[0027] In the specification, when an element, such as a layer, region, or substrate, is described as being "on" or "connected" or "coupled" to another element, it is directly "on," "connected" or "coupled" to the other element, or there are one or more other elements between them. In contrast, when an element is described as being "directly on," "directly connected to," or "directly coupled" to another element, there are no other intervening elements between them. Similarly, expressions such as "between," "just between," "adjacent to," and "directly adjacent to" can be interpreted as above.

[0028] The terms used herein are intended to describe particular examples only and are not used to limit the disclosure. As used herein, the singular form is intended to include the plural form unless the context clearly dictates otherwise. As used herein, the term "and / or" includes any one and any two or more of the associated listed items in any combination. As used herein, the terms "including," "comprising," and "having" specify the presence of stated features, numbers, operations, elements, components, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, operations, elements, components, and / or combinations thereof. As used herein, the term "may" in an example or embodiment (e.g., with respect to what an example or embodiment may include or may perform) means that there is at least one example or embodiment in which such feature is included or performed. However, not all examples are limited to this.

[0029] In this specification, "B is disposed on A" means that B is disposed on A in direct contact therewith, or B is disposed on A with another layer interposed therebetween, and should not be interpreted as being limited to B being disposed in direct contact with A, unless otherwise clearly explained in the specification.

[0030] Unless otherwise defined, all terms, including technical and scientific terms, used herein have the same meaning as commonly understood by a person of ordinary skill in the art to which this disclosure belongs, consistent with the understanding of this disclosure. Terms as defined in commonly used dictionaries are interpreted to have a meaning consistent with the meaning in the context of the relevant technology and this disclosure, and should not be interpreted in an idealized or overly formal sense unless expressly defined in this specification.

[0031] In one or more embodiments, the term "radio frequency" refers to frequencies between about 1 GHz and about 300 GHz, specifically frequencies between about 1 GHz and about 30 GHz, or frequencies between about 1 GHz and about 15 GHz.

[0032] In one or more embodiments, unless otherwise specified, a "fine line" refers to a line having a width of 5 μm or less, such as a line having a width of 1-4 μm or less.

[0033] One or more embodiments of the present invention relate to an electronic element packaging substrate or a device packaging substrate that can realize finer wiring widths, transmit signals with low resistance, and provide a compact package, and a method for manufacturing the same.

[0034] There is growing interest in utilizing high frequency power to increase the transmission speed and capacity of signals. The development of high frequency semiconductor devices inevitably increases the market demand for packaging substrates that can accommodate high frequencies.

[0035] When applying high-frequency power to a package, it is difficult to use a substrate with semiconductor properties, such as a silicon substrate (which may result in power loss due to the generation of parasitic elements, etc.), and a strong skin effect occurs in the wires.

[0036] The redistribution lines may be disposed within a packaging substrate. As semiconductors and / or semiconductor packages become smaller and thinner, the size of the wires (or conductive layers, e.g., copper wires) and the spacing between them in the packaging substrate become smaller.

[0037] The redistribution layer is manufactured by repeating a series of steps of forming and removing an insulating layer and a conductive layer, respectively. As a result, the redistribution layer may be formed in a structure in which wiring (conductive layer) is embedded in an insulating material in a predetermined pattern.

[0038] In general, sufficient adhesion to insulating materials in rewiring can be ensured by increasing the surface roughness of the conductive layer. Increasing the surface roughness increases the contact area due to the anchor effect and improves the adhesion between the conductive layer and the insulating material. For example, the roughness of a copper wire can be improved by etching the surface of the copper wire.

[0039] In a typical wire with a sufficiently large cross section, the rough and irregular shape of the cross-sectional end formed by the surface roughness causes only a slight increase in resistance and effectively improves the adhesive strength at the interface. In contrast, in a fine wire, the resistance increase is excessive, which may adversely affect or hinder the flow of current. In addition, when high frequency is applied, the effect of the resistance due to the surface roughness is an important factor in determining the resistance of the rewiring.

[0040] One or more embodiments relate to an electronic device packaging substrate that substantially reduces power loss even when high frequency power is applied, employs fine lines, and avoids the use of a two-layer structure consisting of a support substrate and an interposer.

[0041] One or more embodiments are described in more detail below.

[0042] Electronic device packaging substrate

[0043] Fig. 2 is a perspective view showing a substrate for an electronic device package according to one or more embodiments, Fig. 3 is a cross-sectional view showing a portion of the cross-section taken along line A-A' in Fig. 2, and Fig. 4 is a detailed view of region "∪" in Fig. 3 (the upper left "A." is an image of an example sample having a surface roughness Ry of 200 nm or less, and the lower left "B." is an image of a comparative example sample having an Ry of 2000-3000 nm). An example packaging substrate 200 will be described with reference to Figs. 2-4.

[0044] The packaging substrate 200 includes a glass substrate 21 having a through hole 23 disposed therein, and an upper redistribution layer 250 disposed on one surface 213 of the glass substrate.

[0045] The glass substrate 21 may be any suitable substrate for use in the semiconductor industry. Non-limiting examples include, but are not limited to, borosilicate glass substrates or alkali-free glass substrates. By way of example, the glass substrate may be selected from commercially available products from Corning, Schott, AGC, or other manufacturers.

[0046] The through holes 23 are through glass vias (TGVs) that penetrate the first surface 213 and the second surface 215 of the glass substrate, and may be formed at predetermined positions of the glass substrate by a method such as etching. The through holes efficiently connect elements provided on the first surface and the second surface while the glass substrate maintains its role of supporting the elements. This connection may be an electrical connection realized by a wire.

[0047] Optionally, the device may further include a cavity (not shown) at a predetermined location, in one example, in which a passive element may be located.

[0048] The upper redistribution layer 250 includes wires 24 having a predetermined pattern and an insulating material 22. The wires 24 may be disposed within the insulating material 22.

[0049] The upper redistribution layer 250 includes a first upper redistribution layer 253 and a second upper redistribution layer 257 disposed one above the other.

[0050] In a non-limiting example, the first upper redistribution layer 253 and the second upper redistribution layer 257 may have wires of different sizes and blind vias of different diameters, and the like.

[0051] A ratio of the thickness of the second upper redistribution layer 257 to the thickness of the first upper redistribution layer 253 may be about 0.8 to about 5, or about 1 to about 3. In this case, the redistribution layer can be manufactured more efficiently.

[0052] The first upper redistribution layer 253 includes first wires 253a having a predetermined pattern and a thickness d1u, and first blind vias 253b connecting wires disposed above and below the first blind vias 253b to each other.

[0053] The second upper redistribution layer 257 includes second wires having a predetermined pattern and a thickness d2u, and second blind vias 257b that connect the wires disposed above and below the second blind vias 257b to each other.

[0054] The portions other than the wires in the first redistribution layer 253 and the second upper redistribution layer 257 may be filled with an insulating material. In this case, the insulating materials may not be clearly distinguishable from each other in a cross section because they appear to be connected together.

[0055] In one example, the thickness d1u may be less than the thickness d2u.

[0056] In one example, the ratio of the thickness d1u to the thickness d2u may be less than or equal to about 0.7.

[0057] d1u is the width of the first upper redistribution layer 253 and the width of the second upper redistribution layer 257.

[0058] In one example, the width d1u may be smaller than the width d2u.

[0059] In one example, the first wire 253a may be a thin wire.

[0060] In one example, the width d1u may be less than about 5 μm.

[0061] In one example, the d1u may be about 1 μm to about 5 μm.

[0062] The first wire 253a may have a characteristic of having a low surface roughness. In particular, the surface roughness of both side surfaces and / or the top surface may be controlled to a low level.

[0063] FIG. 5A is a conceptual diagram showing a cross section of a wire having a small surface roughness, and FIG. 5B is a conceptual diagram showing a cross section of a wire having a large surface roughness.

[0064] 5A and 5B, the first wire 253a may have a surface with substantially different heights (i.e., an uneven surface). The wire may be conceptually represented as straight, but in practice, it is not strictly speaking completely smooth or flat. In one example, the first wire shown in FIG. 5B may have a surface roughness Ry of about 2,000 nm to about 3,000 nm.

[0065] Surface roughness R parameters include Ra, Rp, Rv, and Ry, depending on the measurement standard. Usually, surface roughness refers to the arithmetic mean roughness Ra. Within the reference length, the maximum valley depth from the mean line to the valley bottom line, the maximum peak height from the mean line to the peak line, and the maximum height roughness from the lowest point to the highest point are called Rv, Rp, and Ry, respectively. Ry is the sum of Rv and Rp.

[0066] The surface roughness of a wire can be measured by a method other than the general roughness measurement method. The surface roughness of a wire can be easily measured using a roughness meter during its manufacture, but it is actually difficult to measure the surface roughness of a wire embedded in an insulating material using a roughness meter. It is also difficult to set the reference length. Therefore, the cross section of the wire used in the packaging substrate is observed, and the roughness peak and valley values ​​are obtained along the boundary between the insulating material and the wire.

[0067] The length from the peak of the roughness on one side of the first wire 253a to the peak of the roughness on the opposite side in the cross section of the first wire 253a is defined as w1p, and the length from the valley of the roughness on one side of the first wire 253a to the valley of the roughness on the opposite side in the cross section of the first wire 253a is defined as w1v (Figures 5A and 5B).

[0068] In one example, the one side and the opposite side may be opposite each other.

[0069] The element located between the imaginary line tangent to w1p and the imaginary line tangent to w1v is an element where a peak or valley is formed on the wire surface in a direction substantially perpendicular to the current flow direction. The movement of charge in this element may not cause the current to flow. Therefore, inside the wire, the current flows substantially based on the imaginary line tangent to w1v.

[0070] As the wire becomes finer, the proportion of the portion where roughness is formed in the cross section of the wire increases. When the surface roughness of the wire, which has a smaller cross-sectional area as the wire becomes finer, increases, the area through which the current actually flows decreases. This is a serious problem, unlike a relatively wide wire. In order to form a mechanical fastening site, it may be beneficial to adjust the surface roughness Ry to about 2 μm to about 3 μm. For example, assume that the width of the wire is about 6 μm. When the surface roughness Ry of about 2 μm to about 3 μm is formed on each of the two side surfaces of the wire, the width of the wire through which the current can actually flow is about 0 μm to about 2 μm, except for the portion where the valley portion is formed on the two side surfaces. This causes the resistance of the wire to become excessively high.

[0071] When applying AC power, the current density is observed to be highest at the skin of the wire, which corresponds to the edges when the wire is viewed in cross section. This is called the skin effect, and the higher the frequency applied, the greater the skin effect becomes.

[0072] When a wire having a mechanically fixed portion is used on a packaging substrate to which high frequency power is applied, the skin effect becomes large, resulting in high resistance, and problems such as reduced efficiency of signal transmission and reduced durability occur.

[0073] Therefore, for wires, particularly thin wires, the height (size) from the peak to the valley of the roughness on both sides of the wire is an important parameter.

[0074] In one or more embodiments, the ratio of the length w1v to w1p of the first wire 253a is about 0.8 to about 1.0. Specifically, the ratio may be about 0.85 to about 1.0, about 0.9 to about 1.0, or about 0.94 to about 1.0. A wire ratio in the above range allows for smoother current flow and achieves more efficient signal transmission, especially when high frequency power is applied.

[0075] In one or more embodiments, the features on both sides may be applied equally to the upper and lower surfaces of the first wire 253a when viewed in cross section. Specifically, the length from the roughness peak on the upper surface to the roughness peak on the lower surface in the cross section of the first wire 253a is defined as w1p', and the length from the roughness valley on the upper surface to the roughness valley on the lower surface in the cross section of the first wire 253a is defined as w1v'.

[0076] The ratio of the length of w1v' to w1p' in the first wiring 253a is about 0.8 to about 1.0. Specifically, the ratio of the length of w1v' to w1p' may be about 0.85 to about 1.0, about 0.9 to about 1.0, or about 0.94 to about 1.0. When the wire ratio is in the above range, the current flows more smoothly and more efficient signal transmission is achieved, especially when high frequency power is applied.

[0077] For reference, the underside of the measurement sample in FIG. 5A is shown as having bumps (high roughness) because the surface roughness is not controlled to be smooth, but it should be understood that samples with smooth surfaces can also be manufactured.

[0078] The first wire 253a may have a surface roughness Ry1 value observed in a cross section thereof.

[0079] In one aspect, the first wire 253a may have an Ry1 value of about 200 nm or less.

[0080] The first wire 253a may have an Ry1 value of about 200 nm or less on at least two sides.

[0081] The first wire 253a may have an Ry1 value of about 200 nm or less on all four sides.

[0082] The Ry1 value may be greater than about 0 nm and not greater than 180 nm, about 2 nm to about 150 nm, or about 5 nm to about 100 nm.

[0083] The first wire 253a may have a Ra1 value, which is the surface roughness Ra observed on a cross section of the first wire 253a.

[0084] In one aspect, the first wire 253a may have a Ra1 value of about 20 nm or less.

[0085] The first wire 253a may have an Ra1 value of about 20 nm or less on at least two sides.

[0086] The first wire 253a may have an Ra1 value of about 20 nm or less on all four sides.

[0087] The Ra1 value may be greater than about 0 nm and equal to or less than about 20 nm, from about 1 nm to about 18 nm, or from about 2 nm to about 15 nm.

[0088] It is preferable that the surface of the first wire 253a is not substantially etched.

[0089] In this embodiment, the wire may be substantially smooth across its entire surface.

[0090] The surface properties of the wire may be obtained by methods such as controlling the grain size during the plating process, or without performing a surface etching step on the wire. The detailed manufacturing method will be described later.

[0091] Other wires, such as second wire 257a, may have the same surface characteristics as described for first wire 253a.

[0092] Because wires having the above surface roughness characteristics may not have mechanical fastening sites as in typical applications, a primer layer (not shown) may be formed between each wire 24 and the insulating material 22 that surrounds them to ensure sufficient adhesion.

[0093] The primer layer may be a silane or polysilane layer. The primer layer may be substantially indistinguishable as a separate layer when viewed under a microscope.

[0094] The insulating material 22 may include polymer resins and inorganic particles.

[0095] The inorganic particles may include, but are not limited to, silica particles. For example, the average particle size of each inorganic particle may be 100 nm or less, or 80 nm or less. The average particle size of the inorganic particles may be 20 nm or more. A mixture of inorganic particles with different diameters may be used.

[0096] The polymer resin may be, but is not limited to, an ultraviolet-curable epoxy resin, for example, an epoxy resin may be used in combination with a phenol-based hardener, a cyanate ester, or a phenol ester-based hardener.

[0097] The insulating material may be an inorganic particle dispersed in an uncured or semi-cured polymer resin. A sufficient insulating effect can be obtained by the presence of inorganic particles of various diameters in the insulating material at a predetermined ratio. The insulating material penetrates into gaps due to its high fluidity, substantially preventing the formation of voids in the redistribution layer, and is fixed by the curing of the polymer resin.

[0098] The insulating material may be Ajinomoto Build-up Film (ABF), but is not particularly limited as long as it can form a rewiring layer.

[0099] The method of applying the insulating material includes, but is not limited to, a method of placing a build-up film on the wire and then laminating it with pressure sensitive material.

[0100] The polysilane layer connects the surface of the wire to the insulating material through chemical bonds. In one example, if the wire contains copper, the copper is chemically bonded to the silane, or oxygen on the copper surface is chemically bonded to the silane (-Cu-O-Si). Therefore, even if no mechanical fastening site is formed on the wire surface, sufficient adhesion can be ensured to prevent peeling even when the electronic device is driven.

[0101] The polysilane layer connects the surface of the wire with the functional groups of the polymer, or the surface of the wire with the surfaces of the inorganic particles, through chemical bonds.

[0102] The adhesion between one of the wires 24 and the insulating material 22 may be approximately 200 gf or greater.

[0103] The adhesion between one of the wires 24 and the insulating material 22 may be from about 200 gf to about 800 gf.

[0104] The adhesive strength is a value measured when a primer is used, and may be at least about 2 times, or about 2 to about 8 times, the adhesive strength measured when the wire is directly adhered to the insulating material without using a primer.

[0105] The thermal expansion coefficient may differ depending on the type of material. When operating an electronic device, the temperature of the package inevitably rises and falls repeatedly. Due to this difference in thermal expansion coefficient, forces in substantially different directions may act on the interface between the insulating material and the conductive layer. Repeated application of such forces may cause peeling at the interface, which may lead to defects such as increased resistance during signal transmission and peeling.

[0106] In one or more embodiments, the wire and the insulating material may have substantially similar coefficients of thermal expansion.

[0107] The ratio of the thermal expansion coefficients of wire 24 and insulating material 22 may be about 0.7 to about 1.2 based on the thermal expansion coefficient of wire 24. The ratio may be 0.8 to 1.1 based on the thermal expansion coefficient of wire 24. The ratio may be 0.95 to 1.05 based on the thermal expansion coefficient of wire 24. When the ratio of the thermal expansion coefficients is in such a narrow range, the occurrence of defects in the electronic device package can be significantly reduced.

[0108] The wire 24 may have a thermal expansion coefficient at 25°C of 15 to 19 ppm / °C, or may have a thermal expansion coefficient of 16 to 18.5 ppm / °C.

[0109] The insulating material 22 may have a thermal expansion coefficient at 25°C of 1 to 30 ppm / °C.

[0110] The first wire 253a may include copper having a grain type grain.

[0111] The first wire 253a may include a copper wire.

[0112] The copper wire may be a metal comprising copper having particulate grains.

[0113] The copper wire may be metallic copper or a copper-containing alloy.

[0114] The copper may have a grain size of about 40 nm or less, or from about 20 nm to about 30 nm.

[0115] The wires 24 may be made of copper foil if required to be large in size. When the wires 24 are fine wires, they are often manufactured by electroplating.

[0116] FIG. 6A is a schematic diagram illustrating a cross-section of a wire having particle-type grains during the manufacturing process.

[0117] 6A, to illustrate the copper applied wire, a sample having an insulating material, a wire material, and a seed layer 243 is placed in an electrolyte, and then a plating process is performed. The seed layer may be, for example, but is not limited to, a titanium sputtered layer. The wire material 241 (e.g., copper) grows in a grain shape, filling the voids in the insulating material, and has a grain-type grain as a whole, although the grain size varies more or less.

[0118] 6B is a schematic diagram showing a cross section of a wire having columnar grains. For example, when a wire 24 is manufactured using copper foil, the structure of the wire 24 embedded in the insulating material 22 may be similar to that of FIG. 6A, except that the grain morphology is columnar rather than particulate.

[0119] Wire with granular grains can be finer than wire with columnar grains.

[0120] The surface of the wire may be etched to form mechanical anchoring sites. Etching is performed with an acid composition. The morphology of the etched surface varies depending on the type of acid. For example, when the acid is formic acid, the grain boundaries are etched, resulting in a high surface roughness.

[0121] In one or more embodiments, the wire 24, particularly the fine wire, may be manufactured by forming a primer layer in a manner similar to that described above, except that no such surface treatment is performed. The detailed manufacturing process will be described later.

[0122] The packaging substrate 200 may further include a bottom layer 290 (FIG. 3) below the other side 215 (FIG. 3).

[0123] The lower layer 290 may include a lower redistribution layer (not shown).

[0124] The lower redistribution layer includes lower wires (not shown) having a predetermined pattern and a predetermined thickness, and lower blind vias (not shown) connecting the wires disposed above and below each other.

[0125] The packaging substrate 200 may include an upper insulating layer disposed on an upper surface of the upper redistribution layer. The upper insulating layer may have bumps (not shown) for transmitting signals to the elements 30.

[0126] The packaging substrate 200 may include a lower insulating layer disposed under the lower layer. The lower insulating layer may have bumps (not shown) for receiving signals from a main substrate or the like and transmitting signals from elements.

[0127] The packaging substrate 200 may further include a lid 70 (FIG. 1) disposed on an upper surface of the upper redistribution layer. The lid 70 may help release heat from the device or substrate to the outside and protect the glass substrate 21 from external impact. In addition, one side of the lid 70 may be formed with a hole or a recess to which a pin can be coupled. These may improve the convenience of fixing the packaging substrate during or after the manufacturing process.

[0128] The packaging substrate 200 may include a power transfer element 35 disposed on or within the packaging substrate 200. The power transfer element may be, for example, but is not limited to, a passive element. The power transfer element may be, for example, but is not limited to, a capacitor, such as an aluminum capacitor or a multi-layer ceramic capacitor (MLCC).

[0129] The power transfer element may be disposed on an upper redistribution layer. The power transfer element may be disposed in a cavity formed in a glass substrate. The power transfer element may be disposed in a cavity formed in an upper redistribution layer.

[0130] Electronic Device Package

[0131] FIG. 1 is a perspective view of an example electronic device package in accordance with one or more embodiments.

[0132] According to one or more embodiments, an electronic device package 900 includes an electronic device packaging substrate 200 and a device 30 mounted on the packaging substrate.

[0133] The description of the electronic device packaging substrate 200 is omitted since it has been described above.

[0134] The element 30 may be, for example, but is not limited to, a computing element such as a CPU or GPU, or a storage element such as a memory chip. The element 30 may be arranged in parallel or stacked with one or more other elements.

[0135] The element 30 may be a high-frequency semiconductor element. When the high-frequency semiconductor element is applied in combination with a package substrate, unlike when it is applied in combination with a silicon substrate or the like, parasitic elements are substantially not generated in a high-frequency environment, and high efficiency can be achieved, and, unlike when it is applied in combination with a prepreg substrate, rewiring can be realized in a compact size.

[0136] Method for manufacturing electronic device packaging substrate

[0137] In one or more embodiments, a method for manufacturing an electronic element packaging substrate having a patterned metal layer includes a first step of preparing a glass substrate 21 in which a through hole 23 is disposed, a second step of forming a second upper redistribution layer 257 on the glass substrate 21, and a third step of forming a first upper redistribution layer 253 on the second upper redistribution layer 257.

[0138] The first upper redistribution layer 253 includes first wires 253a having a predetermined pattern and a thickness d1u.

[0139] The second upper redistribution layer 257 includes second wires 257a having a predetermined pattern and a thickness d2u.

[0140] The first step includes a 1-1 step (first sub-step) of forming a first wire 253a (including an example of forming at least one element) having a predetermined pattern and thickness d1u by plating, a 1-2 step (second sub-step) of treating the surface of the first wire 253a with a primer, and a 1-3 step (third sub-step) of filling an insulating material in the space between each of the first wires 253a.

[0141] A detailed description of the electronic element packaging substrate and the glass substrate, through holes, wires, etc. included therein will be omitted since they overlap with the above description.

[0142] The first wire 253a may be a copper wire that is substantially free of columnar grain copper.

[0143] The primer treatment in the 1-2nd stage may be carried out using a silane compound or an imidazole compound.

[0144] The silane compounds may be applied as silane coupling agents or those with added functional groups.

[0145] For example, the silane compound may have a hydrolyzable functional group such as a methoxy group and / or an ethoxy group at one end, and may have an amino group, a vinyl group, an epoxy group, a methacryloxy group, an acryloxy group, a ureido group, a mercapto group, a sulfide group, or an isocyanate group at the other end.

[0146] In one example, the compound used in the priming process may include imidazole, 3-glycidoxypropyltrimethoxysilane, or tetramethylorthosilicate.

[0147] Specifically, the primer treatment may be performed by coating and curing.

[0148] The silane compound is bonded to the surfaces of metals and insulating materials (for example, polymer compounds and inorganic particles) through a chemical reaction, and can improve the adhesive strength at the interface.

[0149] A detailed explanation of this will be omitted since it overlaps with the above.

[0150] An electronic device packaging substrate, a manufacturing method thereof, and an electronic device package including the same according to one or more embodiments may implement finer line widths and transmit signals with low resistance.

[0151] The electronic device packaging according to one or more embodiments, the manufacturing method thereof, and the electronic device package including the same can provide an electronic device package with a compact size and can be operated with high efficiency even when high frequency power is applied.

[0152] Although the present disclosure includes specific embodiments, it will be apparent to those skilled in the art after reading the disclosure of this application that various changes in form and details can be made in these embodiments without departing from the spirit and scope of the claims and their equivalents. The embodiments described herein should be considered in an illustrative sense only and not for the purpose of limitation. The description of a feature or aspect in each embodiment shall be deemed applicable to the same feature or aspect in other embodiments. Appropriate results may be achieved when the described techniques are performed in different orders and / or when the components in the described systems, architectures, devices, or circuits are combined in different ways and / or when other components or their equivalents are substituted or supplemented.

[0153] Therefore, the scope of the disclosure is defined by the claims and their equivalents, rather than the detailed description, and all changes that come within the scope of the claims and their equivalents are intended to be embraced by the disclosure.

Claims

1. 1. An electronic device packaging substrate, comprising: The electronic device packaging substrate includes a glass substrate having a through hole disposed therein, and an upper redistribution layer disposed on one surface of the glass substrate, the upper redistribution layer includes wires disposed within an insulating material of the upper redistribution layer, the upper redistribution layer including a first upper redistribution layer and a second upper redistribution layer; the first upper redistribution layer includes first wires having a first predetermined pattern and a first thickness, and first blind vias configured to connect wires disposed above and below each other; the second upper redistribution layer includes second wires having a second predetermined pattern and a second thickness, and second blind vias configured to connect the wires disposed above and below each other; the first thickness is less than the second thickness; the first wire includes four sides; w1p is the length from the roughness peak on one side of the first wire to the roughness peak on the other side of the first wire in a cross section of the first wire, When w1v is defined as the length from the roughness valley of one side surface of the first wire to the roughness valley of the other side surface of the first wire in the cross section of the first wire, An electronic device packaging substrate, wherein a ratio of the length w1v to the length w1p is 0.8 to 1.

0.

2. The first wire has a surface roughness Ry of Ry1; The electronic device packaging substrate of claim 1 , wherein the Ry1 value on one side of the first wire is 200 nm or less.

3. 2 . The electronic component packaging substrate of claim 1 , wherein a ratio of the first thickness to the second thickness is less than or equal to 0.

7.

4. the first thickness is a width of a first upper redistribution layer; the second thickness is a width of the second upper redistribution layer; the first thickness is less than the second thickness; The electronic device packaging substrate of claim 1 , wherein the first thickness is less than 5 μm.

5. The first wire has a surface roughness Ra of Ra1, The electronic device packaging substrate of claim 1 , wherein the Ra1 value on one side of the first wire is 20 nm or less.

6. 2. The electronic device packaging substrate of claim 1, wherein the adhesive strength between the insulating material and one of the wires disposed within the insulating material is 200 gf to 800 gf.

7. the first wire comprises copper having a grain type grain; 2. The electronic device packaging substrate of claim 1, wherein the copper has a grain size of 40 nm or less.

8. 2. The electronic device packaging substrate of claim 1, wherein a primer layer is disposed between the insulating material and the wire disposed within the insulating material.

9. the insulating material includes a polymer resin and inorganic particles; a polysilane layer disposed between the insulating material and the wire disposed within the insulating material; 2. The electronic device packaging substrate according to claim 1, wherein the polysilane layer connects the surface of the wire disposed in the insulating material with the polymer resin or the inorganic particles through chemical bonds.

10. The electronic component packaging substrate according to claim 1 , wherein the first wire is formed without performing a surface etching process.

11. 1. A method for manufacturing an electronic device packaging substrate having a patterned metal layer, comprising: The manufacturing method includes: A first step of preparing a glass substrate in which a through hole is to be disposed; a second step of forming a second upper redistribution layer on the glass substrate; and a third step of forming a first upper redistribution layer on the second upper redistribution layer; the first upper redistribution layer includes first wires having a first predetermined pattern and a first thickness; the second upper redistribution layer includes second wires having a second predetermined pattern and a second thickness; The first stage comprises: a first sub-step of forming a first wire having the first predetermined pattern and the first thickness by plating; a second sub-step of priming the surface of the first wire; and a third sub-step of filling spaces between each of the first wires with an insulating material; the first thickness is less than the second thickness; the first wire includes four sides; w1p is the length from the roughness peak on one side of the first wire to the roughness peak on the other side of the first wire in a cross section of the first wire, When w1v is defined as the length from the roughness valley of one side surface of the first wire to the roughness valley of the other side surface of the first wire in the cross section of the first wire, A method for manufacturing an electronic component packaging substrate, wherein a ratio of the length w1v to the length w1p is 0.8 to 1.

0.

12. 12. The method of claim 11, wherein a surface etching process is applied to the surface such that a surface roughness of the first wire is not increased.

13. The method of claim 11, wherein the first wire is a copper wire having a grain type grain.

14. 12. The method of claim 11, wherein the primer treatment in the second sub-step is performed with an imidazole compound or a silane compound.

15. An electronic device package comprising the electronic device packaging substrate of claim 1 and a device mounted on the electronic device packaging substrate.

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